[llvm] [RISCV] Add register bank and instruction selection support for FP G_SELECT. (PR #72726)

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git-clang-format --diff 813aaf39f94609a46f38f1e3a15a763a2cc0d2cf a4478ef19edfed35eb196fbff2486347157cf58f -- llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 2586390e85..8a524b4c89 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -821,7 +821,8 @@ bool RISCVInstructionSelector::selectSelect(MachineInstr &MI,
   unsigned Opc = RISCV::Select_GPR_Using_CC_GPR;
   if (RBI.getRegBank(DstReg, MRI, TRI)->getID() == RISCV::FPRBRegBankID) {
     unsigned Size = MRI.getType(DstReg).getSizeInBits();
-    Opc = Size == 32 ? RISCV::Select_FPR32_Using_CC_GPR : RISCV::Select_FPR64_Using_CC_GPR;
+    Opc = Size == 32 ? RISCV::Select_FPR32_Using_CC_GPR
+                     : RISCV::Select_FPR64_Using_CC_GPR;
   }
 
   MachineInstr *Result = MIB.buildInstr(Opc)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 5721bd9609..b516bd41be 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -338,7 +338,9 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     // %z = G_SELECT %cond %x %y
     // fpr = G_FOO %z ...
     if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
-               [&](const MachineInstr &UseMI) { return onlyUsesFP(UseMI, MRI, TRI); }))
+               [&](const MachineInstr &UseMI) {
+                 return onlyUsesFP(UseMI, MRI, TRI);
+               }))
       ++NumFP;
 
     // Check if the defs of the source values always produce floating point

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https://github.com/llvm/llvm-project/pull/72726