[llvm] [RISCV] Add Zbs Write classes to SiFive7AnyToGPRBypass. (PR #72560)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/72560

None

>From 2b3714e359a4a34a41b59ef7df368fe2ea5ef0d7 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 16 Nov 2023 11:30:33 -0800
Subject: [PATCH] [RISCV] Add Zbs Write classes to SiFive7AnyToGPRBypass.

---
 llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 9da68dc9a139d32..53ef9d1baf7b59a 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -182,6 +182,8 @@ class SiFive7AnyToGPRBypass<SchedRead read, int cycles = 2>
                                  WriteSHXADD, WriteSHXADD32,
                                  WriteRotateImm, WriteRotateImm32,
                                  WriteRotateReg, WriteRotateReg32,
+                                 WriteSingleBit, WriteSingleBitImm,
+                                 WriteBEXT, WriteBEXTI,
                                  WriteCLZ, WriteCLZ32, WriteCTZ, WriteCTZ32,
                                  WriteCPOP, WriteCPOP32,
                                  WriteREV8, WriteORCB, WriteSFB,