[llvm] 2fbd088 - [InstCombine] Queue Xor for deletion after replacing its uses in freelyInvertAllUsersOf. (#72445)

[via llvm-commits]

Author: Craig Topper
Date: 2023-11-16T09:46:34-08:00
New Revision: 2fbd0885246cf687f388620318d6954b0984fcba

URL: https://github.com/llvm/llvm-project/commit/2fbd0885246cf687f388620318d6954b0984fcba
DIFF: https://github.com/llvm/llvm-project/commit/2fbd0885246cf687f388620318d6954b0984fcba.diff

LOG: [InstCombine] Queue Xor for deletion after replacing its uses in freelyInvertAllUsersOf. (#72445)

Fixes #72433

Added: 
    llvm/test/Transforms/InstCombine/pr72433.ll

Modified: 
    llvm/lib/Transforms/InstCombine/InstructionCombining.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index 16de4e3ffe1f51a..463a7b5bb1bb588 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -1185,6 +1185,8 @@ void InstCombinerImpl::freelyInvertAllUsersOf(Value *I, Value *IgnoredUser) {
       break;
     case Instruction::Xor:
       replaceInstUsesWith(cast<Instruction>(*U), I);
+      // Add to worklist for DCE.
+      addToWorklist(cast<Instruction>(U));
       break;
     default:
       llvm_unreachable("Got unexpected user - out of sync with "

diff  --git a/llvm/test/Transforms/InstCombine/pr72433.ll b/llvm/test/Transforms/InstCombine/pr72433.ll
new file mode 100644
index 000000000000000..ec3fcfcfea46fcf
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/pr72433.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -passes=instcombine -S < %s | FileCheck %s
+
+define i32 @widget(i32 %arg, i32 %arg1) {
+; CHECK-LABEL: define i32 @widget(
+; CHECK-SAME: i32 [[ARG:%.*]], i32 [[ARG1:%.*]]) {
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne i32 [[ARG]], 0
+; CHECK-NEXT:    [[TMP0:%.*]] = zext i1 [[ICMP]] to i32
+; CHECK-NEXT:    [[MUL:%.*]] = shl nuw nsw i32 20, [[TMP0]]
+; CHECK-NEXT:    [[XOR:%.*]] = zext i1 [[ICMP]] to i32
+; CHECK-NEXT:    [[ADD9:%.*]] = or i32 [[MUL]], [[XOR]]
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i1 [[ICMP]] to i32
+; CHECK-NEXT:    [[MUL2:%.*]] = shl nuw nsw i32 [[ADD9]], [[TMP1]]
+; CHECK-NEXT:    ret i32 [[MUL2]]
+;
+bb:
+  %icmp = icmp eq i32 %arg, 0
+  %zext = zext i1 %icmp to i32
+  %sub = sub i32 2, %zext
+  %mul = mul i32 20, %sub
+  %zext8 = zext i1 %icmp to i32
+  %xor = xor i32 %zext8, 1
+  %add9 = add i32 %mul, %xor
+  %mul2 = mul i32 %add9, %sub
+  ret i32 %mul2
+}