[llvm] 1b781ee - [RISCV] Refactor isAllOnesMask. NFC

[Luke Lau via llvm-commits]

Author: Luke Lau
Date: 2023-11-15T17:14:18+08:00
New Revision: 1b781ee9284ded54aabd88690a726b615c29cc2d

URL: https://github.com/llvm/llvm-project/commit/1b781ee9284ded54aabd88690a726b615c29cc2d
DIFF: https://github.com/llvm/llvm-project/commit/1b781ee9284ded54aabd88690a726b615c29cc2d.diff

LOG: [RISCV] Refactor isAllOnesMask. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVFoldMasks.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp b/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp
index d1c77a6cc7756df..63849238f9ec7c2 100644
--- a/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp
@@ -50,7 +50,7 @@ class RISCVFoldMasks : public MachineFunctionPass {
 private:
   bool convertVMergeToVMv(MachineInstr &MI, MachineInstr *MaskDef);
 
-  bool isAllOnesMask(MachineInstr *MaskCopy);
+  bool isAllOnesMask(MachineInstr *MaskDef);
 };
 
 } // namespace
@@ -59,22 +59,21 @@ char RISCVFoldMasks::ID = 0;
 
 INITIALIZE_PASS(RISCVFoldMasks, DEBUG_TYPE, "RISC-V Fold Masks", false, false)
 
-bool RISCVFoldMasks::isAllOnesMask(MachineInstr *MaskCopy) {
-  if (!MaskCopy)
+bool RISCVFoldMasks::isAllOnesMask(MachineInstr *MaskDef) {
+  if (!MaskDef)
     return false;
-  assert(MaskCopy->isCopy() && MaskCopy->getOperand(0).getReg() == RISCV::V0);
-  Register SrcReg =
-      TRI->lookThruCopyLike(MaskCopy->getOperand(1).getReg(), MRI);
+  assert(MaskDef->isCopy() && MaskDef->getOperand(0).getReg() == RISCV::V0);
+  Register SrcReg = TRI->lookThruCopyLike(MaskDef->getOperand(1).getReg(), MRI);
   if (!SrcReg.isVirtual())
     return false;
-  MachineInstr *SrcDef = MRI->getVRegDef(SrcReg);
-  if (!SrcDef)
+  MaskDef = MRI->getVRegDef(SrcReg);
+  if (!MaskDef)
     return false;
 
   // TODO: Check that the VMSET is the expected bitwidth? The pseudo has
   // undefined behaviour if it's the wrong bitwidth, so we could choose to
   // assume that it's all-ones? Same applies to its VL.
-  switch (SrcDef->getOpcode()) {
+  switch (MaskDef->getOpcode()) {
   case RISCV::PseudoVMSET_M_B1:
   case RISCV::PseudoVMSET_M_B2:
   case RISCV::PseudoVMSET_M_B4: