[llvm] [RISCV] postpone removal in initundef pass (PR #71661)
Piyou Chen via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 15 00:07:05 PST 2023
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/71661
>From 6f2f47bec1ba542a6211ef315112efc3370567ee Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 8 Nov 2023 03:07:37 -0800
Subject: [PATCH 1/3] [RISCV][NFC] precommit testcase
---
.../rvv/handle-noreg-with-implicit-def.mir | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir
diff --git a/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir b/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir
new file mode 100644
index 000000000000000..3a8a1170c90ed2f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir
@@ -0,0 +1,19 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -run-pass=riscv-init-undef -o - %s | FileCheck %s --check-prefix=MIR
+...
+---
+name: vrgather_all_undef
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; MIR-LABEL: name: vrgather_all_undef
+ ; MIR: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
+ ; MIR-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 $noreg, killed [[PseudoRVVInitUndefM1_]], 0, 0, 5 /* e32 */, 0 /* tu, mu */
+ ; MIR-NEXT: $v8 = COPY %1
+ ; MIR-NEXT: PseudoRET implicit $v8
+ %2:vr = IMPLICIT_DEF
+ early-clobber %1:vr = PseudoVRGATHER_VI_M1 $noreg, killed undef %2, 0, 0, 5 /* e32 */, 0 /* tu, mu */
+ $v8 = COPY %1
+ PseudoRET implicit $v8
+
+...
>From 96ebdc99b5240528f3ad113d6976d1a9c99bfa79 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 8 Nov 2023 03:15:50 -0800
Subject: [PATCH 2/3] [RISCV] Postpone earse DeadMI in InitUndef pass
InitUndef pass need replace the implicit def with InitUndef pseudo, but current remove method will make noreg2implicit borken.
This patch postpone the removal until all basicblock be processed.
---
llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp | 9 ++++++++-
.../RISCV/regalloc-last-chance-recoloring-failure.ll | 8 ++++----
.../CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir | 3 ++-
3 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp b/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
index 9d7660ba9a4b103..85a894f481af962 100644
--- a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
@@ -42,6 +42,7 @@
#include "RISCV.h"
#include "RISCVSubtarget.h"
#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/DetectDeadLanes.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
using namespace llvm;
@@ -59,6 +60,8 @@ class RISCVInitUndef : public MachineFunctionPass {
// Newly added vregs, assumed to be fully rewritten
SmallSet<Register, 8> NewRegs;
+ SmallVector<MachineInstr *, 8> DeadInsts;
+
public:
static char ID;
@@ -174,7 +177,7 @@ bool RISCVInitUndef::handleImplicitDef(MachineBasicBlock &MBB,
BuildMI(MBB, Inst, Inst->getDebugLoc(), TII->get(Opcode), NewDest);
if (!HasOtherUse)
- Inst = MBB.erase(Inst);
+ DeadInsts.push_back(&(*Inst));
for (auto MO : UseMOs) {
MO->setReg(NewDest);
@@ -290,6 +293,7 @@ bool RISCVInitUndef::runOnMachineFunction(MachineFunction &MF) {
MRI = &MF.getRegInfo();
TII = ST->getInstrInfo();
TRI = MRI->getTargetRegisterInfo();
+ DeadInsts.clear();
bool Changed = false;
DeadLaneDetector DLD(MRI, TRI);
@@ -298,6 +302,9 @@ bool RISCVInitUndef::runOnMachineFunction(MachineFunction &MF) {
for (MachineBasicBlock &BB : MF)
Changed |= processBasicBlock(MF, BB, DLD);
+ for (auto *DeadMI : DeadInsts)
+ DeadMI->eraseFromParent();
+
return Changed;
}
diff --git a/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll b/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
index 84ff1bf646280ef..f017d8dff2bde31 100644
--- a/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
+++ b/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
@@ -36,7 +36,7 @@ define void @last_chance_recoloring_failure() {
; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: li s0, 36
; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
-; CHECK-NEXT: vfwadd.vv v16, v8, v8, v0.t
+; CHECK-NEXT: vfwadd.vv v16, v8, v12, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
@@ -45,7 +45,7 @@ define void @last_chance_recoloring_failure() {
; CHECK-NEXT: call func at plt
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vrgather.vv v16, v8, v8, v0.t
+; CHECK-NEXT: vrgather.vv v16, v8, v12, v0.t
; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: csrr a2, vlenb
@@ -105,13 +105,13 @@ define void @last_chance_recoloring_failure() {
; SUBREGLIVENESS-NEXT: vmclr.m v0
; SUBREGLIVENESS-NEXT: li s0, 36
; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma
-; SUBREGLIVENESS-NEXT: vfwadd.vv v16, v8, v8, v0.t
+; SUBREGLIVENESS-NEXT: vfwadd.vv v16, v8, v12, v0.t
; SUBREGLIVENESS-NEXT: addi a0, sp, 16
; SUBREGLIVENESS-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; SUBREGLIVENESS-NEXT: call func at plt
; SUBREGLIVENESS-NEXT: li a0, 32
; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; SUBREGLIVENESS-NEXT: vrgather.vv v16, v8, v8, v0.t
+; SUBREGLIVENESS-NEXT: vrgather.vv v16, v8, v12, v0.t
; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma
; SUBREGLIVENESS-NEXT: csrr a1, vlenb
; SUBREGLIVENESS-NEXT: slli a1, a1, 3
diff --git a/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir b/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir
index 3a8a1170c90ed2f..9ed3de951d03a0d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir
@@ -8,7 +8,8 @@ body: |
bb.0.entry:
; MIR-LABEL: name: vrgather_all_undef
; MIR: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
- ; MIR-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 $noreg, killed [[PseudoRVVInitUndefM1_]], 0, 0, 5 /* e32 */, 0 /* tu, mu */
+ ; MIR-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; MIR-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 [[DEF]], killed [[PseudoRVVInitUndefM1_]], 0, 0, 5 /* e32 */, 0 /* tu, mu */
; MIR-NEXT: $v8 = COPY %1
; MIR-NEXT: PseudoRET implicit $v8
%2:vr = IMPLICIT_DEF
>From 73174a30810bc4974b2647bf327d6006a3521f74 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 15 Nov 2023 00:06:45 -0800
Subject: [PATCH 3/3] Clear DeadInsts after removal
---
llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp b/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
index 85a894f481af962..f519e3b2fd3b111 100644
--- a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
@@ -293,7 +293,6 @@ bool RISCVInitUndef::runOnMachineFunction(MachineFunction &MF) {
MRI = &MF.getRegInfo();
TII = ST->getInstrInfo();
TRI = MRI->getTargetRegisterInfo();
- DeadInsts.clear();
bool Changed = false;
DeadLaneDetector DLD(MRI, TRI);
@@ -304,6 +303,7 @@ bool RISCVInitUndef::runOnMachineFunction(MachineFunction &MF) {
for (auto *DeadMI : DeadInsts)
DeadMI->eraseFromParent();
+ DeadInsts.clear();
return Changed;
}
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