[llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension (PR #72340)

via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 14 19:48:46 PST 2023


https://github.com/sun-jacobi edited https://github.com/llvm/llvm-project/pull/72340


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