[llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 14 19:09:59 PST 2023

Previous message: [llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)
Next message: [llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

https://github.com/topperc approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/71541

Previous message: [llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)
Next message: [llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list