[llvm] [RISCV] Remove vmv.s.x and vmv.x.s lmul pseudo variants (PR #71501)

[Craig Topper via llvm-commits]

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@@ -8,7 +8,7 @@
 define signext i8 @extractelt_nxv1i8_0(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
+; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
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topperc wrote:

The vmv.x.s instruction doesn't really use the VL or the LMUL. It doesn't require the vector register to be naturally aligned to the LMUL. It only uses SEW to know how many bits to extract and where to sign extend in the scalar register. This makes it different than other instructions so it's hard to know for sure.

https://github.com/llvm/llvm-project/pull/71501