[llvm] [RISCV][GISel] Support G_UMIN/UMAX/SMIN/SMAX legal with Zbb. (PR #72182)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 13 16:58:30 PST 2023
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/72182
>From 601b8018e41ad61e81326be90b84f7fd0633f6da Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 13 Nov 2023 16:15:12 -0800
Subject: [PATCH] [RISCV][GISel] Support G_UMIN/UMAX/SMIN/SMAX legal with Zbb.
---
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 6 +-
.../RISCV/GISel/RISCVRegisterBankInfo.cpp | 4 +
.../instruction-select/minmax-rv32.mir | 85 +++++++++++++++++++
.../instruction-select/minmax-rv64.mir | 82 ++++++++++++++++++
.../legalizer/rv32/legalize-smax.mir | 54 ++++++++++++
.../legalizer/rv32/legalize-smin.mir | 54 ++++++++++++
.../legalizer/rv32/legalize-umax.mir | 44 ++++++++++
.../legalizer/rv32/legalize-umin.mir | 44 ++++++++++
.../legalizer/rv64/legalize-smax.mir | 51 +++++++++++
.../legalizer/rv64/legalize-smin.mir | 51 +++++++++++
.../legalizer/rv64/legalize-umax.mir | 42 +++++++++
.../legalizer/rv64/legalize-umin.mir | 42 +++++++++
.../GlobalISel/regbankselect/minmax-rv32.mir | 77 +++++++++++++++++
.../GlobalISel/regbankselect/minmax-rv64.mir | 77 +++++++++++++++++
14 files changed, 712 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv32.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv64.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index c6654873118f98f..c0ae84287082ab8 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -200,7 +200,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
}
getActionDefinitionsBuilder(G_ABS).lower();
- getActionDefinitionsBuilder({G_UMAX, G_UMIN, G_SMAX, G_SMIN}).lower();
+
+ auto &MinMax = getActionDefinitionsBuilder({G_UMAX, G_UMIN, G_SMAX, G_SMIN});
+ if (ST.hasStdExtZbb())
+ MinMax.legalFor({sXLen}).minScalar(0, sXLen);
+ MinMax.lower();
getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index f81ff3e27131bf5..cb1da8ff11c08cb 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -199,9 +199,13 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_SDIV:
case TargetOpcode::G_SREM:
case TargetOpcode::G_SMULH:
+ case TargetOpcode::G_SMAX:
+ case TargetOpcode::G_SMIN:
case TargetOpcode::G_UDIV:
case TargetOpcode::G_UREM:
case TargetOpcode::G_UMULH:
+ case TargetOpcode::G_UMAX:
+ case TargetOpcode::G_UMIN:
case TargetOpcode::G_PTR_ADD:
case TargetOpcode::G_PTRTOINT:
case TargetOpcode::G_INTTOPTR:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv32.mir
new file mode 100644
index 000000000000000..b0d387fd640906e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv32.mir
@@ -0,0 +1,85 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: | FileCheck -check-prefix=RV32I %s
+
+---
+name: smax_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+body: |
+ bb.0.entry:
+ ; RV32I-LABEL: name: smax_i32
+ ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; RV32I-NEXT: [[MAX:%[0-9]+]]:gpr = MAX [[COPY]], [[COPY1]]
+ ; RV32I-NEXT: $x10 = COPY [[MAX]]
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = COPY $x10
+ %1:gprb(s32) = COPY $x11
+ %2:gprb(s32) = G_SMAX %0, %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: smin_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+body: |
+ bb.0.entry:
+ ; RV32I-LABEL: name: smin_i32
+ ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; RV32I-NEXT: [[MIN:%[0-9]+]]:gpr = MIN [[COPY]], [[COPY1]]
+ ; RV32I-NEXT: $x10 = COPY [[MIN]]
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = COPY $x10
+ %1:gprb(s32) = COPY $x11
+ %2:gprb(s32) = G_SMIN %0, %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: umax_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+body: |
+ bb.0.entry:
+ ; RV32I-LABEL: name: umax_i32
+ ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; RV32I-NEXT: [[MAXU:%[0-9]+]]:gpr = MAXU [[COPY]], [[COPY1]]
+ ; RV32I-NEXT: $x10 = COPY [[MAXU]]
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = COPY $x10
+ %1:gprb(s32) = COPY $x11
+ %2:gprb(s32) = G_UMAX %0, %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: umin_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+body: |
+ bb.0.entry:
+ ; RV32I-LABEL: name: umin_i32
+ ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; RV32I-NEXT: [[MINU:%[0-9]+]]:gpr = MINU [[COPY]], [[COPY1]]
+ ; RV32I-NEXT: $x10 = COPY [[MINU]]
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = COPY $x10
+ %1:gprb(s32) = COPY $x11
+ %2:gprb(s32) = G_UMIN %0, %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv64.mir
new file mode 100644
index 000000000000000..4bbe93a4133f651
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/minmax-rv64.mir
@@ -0,0 +1,82 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: | FileCheck -check-prefix=RV64I %s
+
+---
+name: smax_i64
+legalized: true
+regBankSelected: true
+body: |
+ bb.0.entry:
+ ; RV64I-LABEL: name: smax_i64
+ ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; RV64I-NEXT: [[MAX:%[0-9]+]]:gpr = MAX [[COPY]], [[COPY1]]
+ ; RV64I-NEXT: $x10 = COPY [[MAX]]
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ %0:gprb(s64) = COPY $x10
+ %1:gprb(s64) = COPY $x11
+ %2:gprb(s64) = G_SMAX %0, %1
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: smin_i64
+legalized: true
+regBankSelected: true
+body: |
+ bb.0.entry:
+ ; RV64I-LABEL: name: smin_i64
+ ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; RV64I-NEXT: [[MIN:%[0-9]+]]:gpr = MIN [[COPY]], [[COPY1]]
+ ; RV64I-NEXT: $x10 = COPY [[MIN]]
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ %0:gprb(s64) = COPY $x10
+ %1:gprb(s64) = COPY $x11
+ %2:gprb(s64) = G_SMIN %0, %1
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: umax_i64
+legalized: true
+regBankSelected: true
+body: |
+ bb.0.entry:
+ ; RV64I-LABEL: name: umax_i64
+ ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; RV64I-NEXT: [[MAXU:%[0-9]+]]:gpr = MAXU [[COPY]], [[COPY1]]
+ ; RV64I-NEXT: $x10 = COPY [[MAXU]]
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ %0:gprb(s64) = COPY $x10
+ %1:gprb(s64) = COPY $x11
+ %2:gprb(s64) = G_UMAX %0, %1
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: umin_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+body: |
+ bb.0.entry:
+ ; RV64I-LABEL: name: umin_i64
+ ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; RV64I-NEXT: [[MINU:%[0-9]+]]:gpr = MINU [[COPY]], [[COPY1]]
+ ; RV64I-NEXT: $x10 = COPY [[MINU]]
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ %0:gprb(s64) = COPY $x10
+ %1:gprb(s64) = COPY $x11
+ %2:gprb(s64) = G_UMIN %0, %1
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smax.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smax.mir
index a0833a4b7b550a7..5fcb531567c9099 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smax.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smax.mir
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s --check-prefix=ZBB
---
name: smax_i8
@@ -21,6 +23,22 @@ body: |
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
; CHECK-NEXT: $x10 = COPY [[ASHR2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smax_i8
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; ZBB-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
+ ; ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+ ; ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]]
+ ; ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SMAX]], [[C2]](s32)
+ ; ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
+ ; ZBB-NEXT: $x10 = COPY [[ASHR2]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s8) = G_TRUNC %0(s32)
@@ -51,6 +69,22 @@ body: |
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
; CHECK-NEXT: $x10 = COPY [[ASHR2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smax_i16
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; ZBB-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
+ ; ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+ ; ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]]
+ ; ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SMAX]], [[C2]](s32)
+ ; ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
+ ; ZBB-NEXT: $x10 = COPY [[ASHR2]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s16) = G_TRUNC %0(s32)
@@ -72,6 +106,13 @@ body: |
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smax_i32
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[COPY1]]
+ ; ZBB-NEXT: $x10 = COPY [[SMAX]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = G_SMAX %0, %1
@@ -95,6 +136,19 @@ body: |
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smax_i64
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; ZBB-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]
+ ; ZBB-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; ZBB-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+ ; ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; ZBB-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
+ ; ZBB-NEXT: $x10 = COPY [[SELECT1]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = COPY $x12
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smin.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smin.mir
index e6091ec68b6b269..6622558b7472266 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smin.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-smin.mir
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s --check-prefix=ZBB
---
name: smin_i8
@@ -21,6 +23,22 @@ body: |
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
; CHECK-NEXT: $x10 = COPY [[ASHR2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smin_i8
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; ZBB-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
+ ; ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+ ; ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]]
+ ; ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SMIN]], [[C2]](s32)
+ ; ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
+ ; ZBB-NEXT: $x10 = COPY [[ASHR2]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s8) = G_TRUNC %0(s32)
@@ -51,6 +69,22 @@ body: |
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
; CHECK-NEXT: $x10 = COPY [[ASHR2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smin_i16
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; ZBB-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
+ ; ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+ ; ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]]
+ ; ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SMIN]], [[C2]](s32)
+ ; ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
+ ; ZBB-NEXT: $x10 = COPY [[ASHR2]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s16) = G_TRUNC %0(s32)
@@ -72,6 +106,13 @@ body: |
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smin_i32
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[COPY1]]
+ ; ZBB-NEXT: $x10 = COPY [[SMIN]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = G_SMIN %0, %1
@@ -95,6 +136,19 @@ body: |
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smin_i64
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; ZBB-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]]
+ ; ZBB-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; ZBB-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+ ; ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; ZBB-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
+ ; ZBB-NEXT: $x10 = COPY [[SELECT1]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = COPY $x12
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umax.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umax.mir
index a05dd43ce0aa3da..d3e4f2332fa58de 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umax.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umax.mir
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s --check-prefix=ZBB
---
name: umax_i8
@@ -18,6 +20,17 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
; CHECK-NEXT: $x10 = COPY [[AND2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umax_i8
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; ZBB-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
+ ; ZBB-NEXT: $x10 = COPY [[UMAX]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s8) = G_TRUNC %0(s32)
@@ -45,6 +58,17 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
; CHECK-NEXT: $x10 = COPY [[AND2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umax_i16
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; ZBB-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
+ ; ZBB-NEXT: $x10 = COPY [[UMAX]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s16) = G_TRUNC %0(s32)
@@ -66,6 +90,13 @@ body: |
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umax_i32
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[COPY]], [[COPY1]]
+ ; ZBB-NEXT: $x10 = COPY [[UMAX]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = G_UMAX %0, %1
@@ -89,6 +120,19 @@ body: |
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umax_i64
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; ZBB-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]
+ ; ZBB-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; ZBB-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+ ; ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; ZBB-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
+ ; ZBB-NEXT: $x10 = COPY [[SELECT1]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = COPY $x12
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umin.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umin.mir
index d9282d84455bcfa..683f9703a0c5d02 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umin.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-umin.mir
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s --check-prefix=ZBB
---
name: umin_i8
@@ -18,6 +20,17 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
; CHECK-NEXT: $x10 = COPY [[AND2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umin_i8
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; ZBB-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
+ ; ZBB-NEXT: $x10 = COPY [[UMIN]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s8) = G_TRUNC %0(s32)
@@ -45,6 +58,17 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
; CHECK-NEXT: $x10 = COPY [[AND2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umin_i16
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; ZBB-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
+ ; ZBB-NEXT: $x10 = COPY [[UMIN]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s16) = G_TRUNC %0(s32)
@@ -66,6 +90,13 @@ body: |
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umin_i32
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]]
+ ; ZBB-NEXT: $x10 = COPY [[UMIN]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = G_UMIN %0, %1
@@ -89,6 +120,19 @@ body: |
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umin_i64
+ ; ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; ZBB-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+ ; ZBB-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+ ; ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
+ ; ZBB-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; ZBB-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+ ; ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; ZBB-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[COPY]], [[COPY2]]
+ ; ZBB-NEXT: $x10 = COPY [[SELECT1]](s32)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = COPY $x12
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-smax.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-smax.mir
index 93cd1b6290e7ec4..df62c2f3bee936f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-smax.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-smax.mir
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s --check-prefix=ZBB
---
name: smax_i8
@@ -21,6 +23,22 @@ body: |
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
; CHECK-NEXT: $x10 = COPY [[ASHR2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smax_i8
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+ ; ZBB-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+ ; ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
+ ; ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
+ ; ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[ASHR]], [[ASHR1]]
+ ; ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+ ; ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SMAX]], [[C2]](s64)
+ ; ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
+ ; ZBB-NEXT: $x10 = COPY [[ASHR2]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s8) = G_TRUNC %0(s64)
@@ -51,6 +69,22 @@ body: |
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
; CHECK-NEXT: $x10 = COPY [[ASHR2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smax_i16
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
+ ; ZBB-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
+ ; ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
+ ; ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
+ ; ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[ASHR]], [[ASHR1]]
+ ; ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
+ ; ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SMAX]], [[C2]](s64)
+ ; ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
+ ; ZBB-NEXT: $x10 = COPY [[ASHR2]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s16) = G_TRUNC %0(s64)
@@ -75,6 +109,16 @@ body: |
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SELECT]], 32
; CHECK-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smax_i32
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
+ ; ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
+ ; ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
+ ; ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMAX]], 32
+ ; ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64)
@@ -96,6 +140,13 @@ body: |
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smax_i64
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[COPY]], [[COPY1]]
+ ; ZBB-NEXT: $x10 = COPY [[SMAX]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s64) = G_SMAX %0, %1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-smin.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-smin.mir
index 322d61a9d08fac5..36ed433ae930bbc 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-smin.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-smin.mir
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s --check-prefix=ZBB
---
name: smin_i8
@@ -21,6 +23,22 @@ body: |
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
; CHECK-NEXT: $x10 = COPY [[ASHR2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smin_i8
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+ ; ZBB-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+ ; ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
+ ; ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
+ ; ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[ASHR]], [[ASHR1]]
+ ; ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+ ; ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SMIN]], [[C2]](s64)
+ ; ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
+ ; ZBB-NEXT: $x10 = COPY [[ASHR2]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s8) = G_TRUNC %0(s64)
@@ -51,6 +69,22 @@ body: |
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
; CHECK-NEXT: $x10 = COPY [[ASHR2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smin_i16
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
+ ; ZBB-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+ ; ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
+ ; ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
+ ; ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
+ ; ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[ASHR]], [[ASHR1]]
+ ; ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
+ ; ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SMIN]], [[C2]](s64)
+ ; ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
+ ; ZBB-NEXT: $x10 = COPY [[ASHR2]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s16) = G_TRUNC %0(s64)
@@ -75,6 +109,16 @@ body: |
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SELECT]], 32
; CHECK-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smin_i32
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
+ ; ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
+ ; ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
+ ; ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMIN]], 32
+ ; ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64)
@@ -96,6 +140,13 @@ body: |
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: smin_i64
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[COPY]], [[COPY1]]
+ ; ZBB-NEXT: $x10 = COPY [[SMIN]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s64) = G_SMIN %0, %1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-umax.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-umax.mir
index e07aa9978fb4591..ed28153b8260aa5 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-umax.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-umax.mir
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s --check-prefix=ZBB
---
name: umax_i8
@@ -18,6 +20,17 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SELECT]], [[C2]]
; CHECK-NEXT: $x10 = COPY [[AND2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umax_i8
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; ZBB-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
+ ; ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[AND]], [[AND1]]
+ ; ZBB-NEXT: $x10 = COPY [[UMAX]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s8) = G_TRUNC %0(s64)
@@ -45,6 +58,17 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SELECT]], [[C2]]
; CHECK-NEXT: $x10 = COPY [[AND2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umax_i16
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; ZBB-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
+ ; ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[AND]], [[AND1]]
+ ; ZBB-NEXT: $x10 = COPY [[UMAX]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s16) = G_TRUNC %0(s64)
@@ -72,6 +96,17 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SELECT]], [[C2]]
; CHECK-NEXT: $x10 = COPY [[AND2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umax_i32
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; ZBB-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
+ ; ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[AND]], [[AND1]]
+ ; ZBB-NEXT: $x10 = COPY [[UMAX]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64)
@@ -93,6 +128,13 @@ body: |
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umax_i64
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[COPY]], [[COPY1]]
+ ; ZBB-NEXT: $x10 = COPY [[UMAX]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s64) = G_UMAX %0, %1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-umin.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-umin.mir
index 23c6a26bec57a07..4c5b7efad3edb22 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-umin.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-umin.mir
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s --check-prefix=ZBB
---
name: umin_i8
@@ -18,6 +20,17 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SELECT]], [[C2]]
; CHECK-NEXT: $x10 = COPY [[AND2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umin_i8
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; ZBB-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
+ ; ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[AND]], [[AND1]]
+ ; ZBB-NEXT: $x10 = COPY [[UMIN]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s8) = G_TRUNC %0(s64)
@@ -45,6 +58,17 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SELECT]], [[C2]]
; CHECK-NEXT: $x10 = COPY [[AND2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umin_i16
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; ZBB-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
+ ; ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[AND]], [[AND1]]
+ ; ZBB-NEXT: $x10 = COPY [[UMIN]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s16) = G_TRUNC %0(s64)
@@ -72,6 +96,17 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SELECT]], [[C2]]
; CHECK-NEXT: $x10 = COPY [[AND2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umin_i32
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; ZBB-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
+ ; ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[AND]], [[AND1]]
+ ; ZBB-NEXT: $x10 = COPY [[UMIN]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64)
@@ -93,6 +128,13 @@ body: |
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
+ ;
+ ; ZBB-LABEL: name: umin_i64
+ ; ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[COPY]], [[COPY1]]
+ ; ZBB-NEXT: $x10 = COPY [[UMIN]](s64)
+ ; ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s64) = G_UMIN %0, %1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir
new file mode 100644
index 000000000000000..123b6b9649837b5
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir
@@ -0,0 +1,77 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=regbankselect \
+# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck -check-prefix=RV32I %s
+
+---
+name: smax_i32
+legalized: true
+body: |
+ bb.0.entry:
+ ; RV32I-LABEL: name: smax_i32
+ ; RV32I: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+ ; RV32I-NEXT: [[SMAX:%[0-9]+]]:gprb(s32) = G_SMAX [[COPY]], [[COPY1]]
+ ; RV32I-NEXT: $x10 = COPY [[SMAX]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s32) = G_SMAX %0, %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: smin_i32
+legalized: true
+body: |
+ bb.0.entry:
+ ; RV32I-LABEL: name: smin_i32
+ ; RV32I: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+ ; RV32I-NEXT: [[SMIN:%[0-9]+]]:gprb(s32) = G_SMIN [[COPY]], [[COPY1]]
+ ; RV32I-NEXT: $x10 = COPY [[SMIN]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s32) = G_SMIN %0, %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: umax_i32
+legalized: true
+body: |
+ bb.0.entry:
+ ; RV32I-LABEL: name: umax_i32
+ ; RV32I: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+ ; RV32I-NEXT: [[UMAX:%[0-9]+]]:gprb(s32) = G_UMAX [[COPY]], [[COPY1]]
+ ; RV32I-NEXT: $x10 = COPY [[UMAX]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s32) = G_UMAX %0, %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: umin_i32
+legalized: true
+body: |
+ bb.0.entry:
+ ; RV32I-LABEL: name: umin_i32
+ ; RV32I: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+ ; RV32I-NEXT: [[UMIN:%[0-9]+]]:gprb(s32) = G_UMIN [[COPY]], [[COPY1]]
+ ; RV32I-NEXT: $x10 = COPY [[UMIN]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s32) = G_UMIN %0, %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir
new file mode 100644
index 000000000000000..661f1ed61df6037
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir
@@ -0,0 +1,77 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=regbankselect \
+# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck -check-prefix=RV64I %s
+
+---
+name: smax_i64
+legalized: true
+body: |
+ bb.0.entry:
+ ; RV64I-LABEL: name: smax_i64
+ ; RV64I: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+ ; RV64I-NEXT: [[SMAX:%[0-9]+]]:gprb(s64) = G_SMAX [[COPY]], [[COPY1]]
+ ; RV64I-NEXT: $x10 = COPY [[SMAX]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s64) = G_SMAX %0, %1
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: smin_i64
+legalized: true
+body: |
+ bb.0.entry:
+ ; RV64I-LABEL: name: smin_i64
+ ; RV64I: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+ ; RV64I-NEXT: [[SMIN:%[0-9]+]]:gprb(s64) = G_SMIN [[COPY]], [[COPY1]]
+ ; RV64I-NEXT: $x10 = COPY [[SMIN]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s64) = G_SMIN %0, %1
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: umax_i64
+legalized: true
+body: |
+ bb.0.entry:
+ ; RV64I-LABEL: name: umax_i64
+ ; RV64I: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+ ; RV64I-NEXT: [[UMAX:%[0-9]+]]:gprb(s64) = G_UMAX [[COPY]], [[COPY1]]
+ ; RV64I-NEXT: $x10 = COPY [[UMAX]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s64) = G_UMAX %0, %1
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: umin_i64
+legalized: true
+body: |
+ bb.0.entry:
+ ; RV64I-LABEL: name: umin_i64
+ ; RV64I: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+ ; RV64I-NEXT: [[UMIN:%[0-9]+]]:gprb(s64) = G_UMIN [[COPY]], [[COPY1]]
+ ; RV64I-NEXT: $x10 = COPY [[UMIN]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s64) = G_UMIN %0, %1
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
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