[llvm] [RISCV][GISel] Legalizer and register bank selection for G_JUMP_TABLE and G_BRJT (PR #71970)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 10 12:32:15 PST 2023
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/71970
>From 9081368fbbacc2322288485b1c32c56dbcbe0dad Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 10 Nov 2023 09:48:10 -0800
Subject: [PATCH 1/4] [RISCV][GISel] Legalizer support for G_BRJT and
G_JUMP_TABLE.
---
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 5 +-
.../rv32/legalize-jump-table-brjt.mir | 153 +++++++++++++++++
.../rv64/legalize-jump-table-brjt.mir | 159 ++++++++++++++++++
3 files changed, 315 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-jump-table-brjt.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-jump-table-brjt.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 1aba6b78d8a9d9b..2baaadd8ae00af0 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -131,13 +131,14 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
getActionDefinitionsBuilder(G_BRCOND).legalFor({sXLen}).minScalar(0, sXLen);
+ getActionDefinitionsBuilder(G_BRJT).legalFor({{p0, sXLen}});
+
getActionDefinitionsBuilder(G_PHI)
.legalFor({p0, sXLen})
.widenScalarToNextPow2(0)
.clampScalar(0, sXLen, sXLen);
- getActionDefinitionsBuilder(G_GLOBAL_VALUE)
- .legalFor({p0});
+ getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE}).legalFor({p0});
if (ST.hasStdExtM() || ST.hasStdExtZmmul()) {
getActionDefinitionsBuilder(G_MUL)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-jump-table-brjt.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-jump-table-brjt.mir
new file mode 100644
index 000000000000000..a7fd7da77261f84
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-jump-table-brjt.mir
@@ -0,0 +1,153 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+
+--- |
+ define i32 @jt_test(i32 signext %in) {
+ entry:
+ switch i32 %in, label %default [
+ i32 1, label %bb1
+ i32 2, label %bb2
+ i32 3, label %bb3
+ i32 4, label %bb4
+ i32 5, label %bb5
+ i32 6, label %bb6
+ ]
+
+ bb1: ; preds = %entry
+ ret i32 4
+
+ bb2: ; preds = %entry
+ ret i32 3
+
+ bb3: ; preds = %entry
+ ret i32 2
+
+ bb4: ; preds = %entry
+ ret i32 1
+
+ bb5: ; preds = %entry
+ ret i32 100
+
+ bb6: ; preds = %entry
+ ret i32 200
+
+ default: ; preds = %entry
+ ret i32 1000
+ }
+
+...
+---
+name: jt_test
+tracksRegLiveness: true
+jumpTable:
+ kind: block-address
+ entries:
+ - id: 0
+ blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ]
+body: |
+ ; CHECK-LABEL: name: jt_test
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 200
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 100
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1000
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C8]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[SUB]](s32), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.entry:
+ ; CHECK-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0
+ ; CHECK-NEXT: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[SUB]](s32)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.bb1:
+ ; CHECK-NEXT: $x10 = COPY [[C6]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.bb2:
+ ; CHECK-NEXT: $x10 = COPY [[C5]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.bb3:
+ ; CHECK-NEXT: $x10 = COPY [[C4]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.bb4:
+ ; CHECK-NEXT: $x10 = COPY [[C3]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.bb5:
+ ; CHECK-NEXT: $x10 = COPY [[C2]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7.bb6:
+ ; CHECK-NEXT: $x10 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.8.default:
+ ; CHECK-NEXT: $x10 = COPY [[C7]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ bb.1.entry:
+ successors: %bb.8, %bb.9
+ liveins: $x10
+
+ %0:_(s32) = COPY $x10
+ %4:_(s32) = G_CONSTANT i32 5
+ %8:_(s32) = G_CONSTANT i32 200
+ %9:_(s32) = G_CONSTANT i32 100
+ %10:_(s32) = G_CONSTANT i32 1
+ %11:_(s32) = G_CONSTANT i32 2
+ %12:_(s32) = G_CONSTANT i32 3
+ %13:_(s32) = G_CONSTANT i32 4
+ %14:_(s32) = G_CONSTANT i32 1000
+ %1:_(s32) = G_CONSTANT i32 1
+ %2:_(s32) = G_SUB %0, %1
+ %6:_(s1) = G_ICMP intpred(ugt), %2(s32), %4
+ G_BRCOND %6(s1), %bb.8
+
+ bb.9.entry:
+ successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7
+
+ %7:_(p0) = G_JUMP_TABLE %jump-table.0
+ G_BRJT %7(p0), %jump-table.0, %2(s32)
+
+ bb.2.bb1:
+ $x10 = COPY %13(s32)
+ PseudoRET implicit $x10
+
+ bb.3.bb2:
+ $x10 = COPY %12(s32)
+ PseudoRET implicit $x10
+
+ bb.4.bb3:
+ $x10 = COPY %11(s32)
+ PseudoRET implicit $x10
+
+ bb.5.bb4:
+ $x10 = COPY %10(s32)
+ PseudoRET implicit $x10
+
+ bb.6.bb5:
+ $x10 = COPY %9(s32)
+ PseudoRET implicit $x10
+
+ bb.7.bb6:
+ $x10 = COPY %8(s32)
+ PseudoRET implicit $x10
+
+ bb.8.default:
+ $x10 = COPY %14(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-jump-table-brjt.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-jump-table-brjt.mir
new file mode 100644
index 000000000000000..9293959c8f39dd5
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-jump-table-brjt.mir
@@ -0,0 +1,159 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+
+--- |
+ define i32 @jt_test(i32 signext %in) {
+ entry:
+ %0 = sext i32 %in to i64
+ switch i64 %0, label %default [
+ i64 1, label %bb1
+ i64 2, label %bb2
+ i64 3, label %bb3
+ i64 4, label %bb4
+ i64 5, label %bb5
+ i64 6, label %bb6
+ ]
+
+ bb1:
+ ret i32 4
+
+ bb2:
+ ret i32 3
+
+ bb3:
+ ret i32 2
+
+ bb4:
+ ret i32 1
+
+ bb5:
+ ret i32 100
+
+ bb6:
+ ret i32 200
+
+ default:
+ ret i32 1000
+ }
+
+...
+---
+name: jt_test
+tracksRegLiveness: true
+jumpTable:
+ kind: custom32
+ entries:
+ - id: 0
+ blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ]
+body: |
+ ; CHECK-LABEL: name: jt_test
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ASSERT_SEXT]], 32
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SEXT_INREG]], [[C1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[SUB]](s64), [[C]]
+ ; CHECK-NEXT: G_BRCOND [[ICMP]](s64), %bb.8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.entry:
+ ; CHECK-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0
+ ; CHECK-NEXT: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[SUB]](s64)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.bb1:
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: $x10 = COPY [[C2]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.bb2:
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: $x10 = COPY [[C3]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.bb3:
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK-NEXT: $x10 = COPY [[C4]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.bb4:
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: $x10 = COPY [[C5]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.bb5:
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 100
+ ; CHECK-NEXT: $x10 = COPY [[C6]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7.bb6:
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 200
+ ; CHECK-NEXT: $x10 = COPY [[C7]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.8.default:
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 1000
+ ; CHECK-NEXT: $x10 = COPY [[C8]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ bb.1.entry:
+ successors: %bb.8, %bb.9
+ liveins: $x10
+
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = G_ASSERT_SEXT %1, 32
+ %0:_(s32) = G_TRUNC %2(s64)
+ %7:_(s64) = G_CONSTANT i64 5
+ %3:_(s64) = G_SEXT %0(s32)
+ %4:_(s64) = G_CONSTANT i64 1
+ %5:_(s64) = G_SUB %3, %4
+ %9:_(s1) = G_ICMP intpred(ugt), %5(s64), %7
+ G_BRCOND %9(s1), %bb.8
+
+ bb.9.entry:
+ successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7
+
+ %10:_(p0) = G_JUMP_TABLE %jump-table.0
+ G_BRJT %10(p0), %jump-table.0, %5(s64)
+
+ bb.2.bb1:
+ %22:_(s64) = G_CONSTANT i64 4
+ $x10 = COPY %22(s64)
+ PseudoRET implicit $x10
+
+ bb.3.bb2:
+ %20:_(s64) = G_CONSTANT i64 3
+ $x10 = COPY %20(s64)
+ PseudoRET implicit $x10
+
+ bb.4.bb3:
+ %18:_(s64) = G_CONSTANT i64 2
+ $x10 = COPY %18(s64)
+ PseudoRET implicit $x10
+
+ bb.5.bb4:
+ %16:_(s64) = G_CONSTANT i64 1
+ $x10 = COPY %16(s64)
+ PseudoRET implicit $x10
+
+ bb.6.bb5:
+ %14:_(s64) = G_CONSTANT i64 100
+ $x10 = COPY %14(s64)
+ PseudoRET implicit $x10
+
+ bb.7.bb6:
+ %12:_(s64) = G_CONSTANT i64 200
+ $x10 = COPY %12(s64)
+ PseudoRET implicit $x10
+
+ bb.8.default:
+ %24:_(s64) = G_CONSTANT i64 1000
+ $x10 = COPY %24(s64)
+ PseudoRET implicit $x10
+
+...
>From b95806f192d73a6f93a3c1d51efe3e711103ea80 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 10 Nov 2023 10:18:49 -0800
Subject: [PATCH 2/4] [RISCV][GISel] Register bank selection for G_JUMP_TABLE
and G_BRJT.
---
.../RISCV/GISel/RISCVRegisterBankInfo.cpp | 5 +
.../regbankselect/jump-table-brjt-rv32.mir | 154 +++++++++++++++++
.../regbankselect/jump-table-brjt-rv64.mir | 159 ++++++++++++++++++
3 files changed, 318 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 60b6de0a760dcbb..3cdee17be8d1d88 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -166,12 +166,17 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_CONSTANT:
case TargetOpcode::G_FRAME_INDEX:
case TargetOpcode::G_GLOBAL_VALUE:
+ case TargetOpcode::G_JUMP_TABLE:
case TargetOpcode::G_BRCOND:
OperandsMapping = getOperandsMapping({GPRValueMapping, nullptr});
break;
case TargetOpcode::G_BR:
OperandsMapping = getOperandsMapping({nullptr});
break;
+ case TargetOpcode::G_BRJT:
+ OperandsMapping =
+ getOperandsMapping({GPRValueMapping, nullptr, GPRValueMapping});
+ break;
case TargetOpcode::G_ICMP:
OperandsMapping = getOperandsMapping(
{GPRValueMapping, nullptr, GPRValueMapping, GPRValueMapping});
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir
new file mode 100644
index 000000000000000..f53a939d7f88231
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir
@@ -0,0 +1,154 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck -check-prefix=RV32I %s
+
+--- |
+ define i32 @jt_test(i32 signext %in) {
+ entry:
+ switch i32 %in, label %default [
+ i32 1, label %bb1
+ i32 2, label %bb2
+ i32 3, label %bb3
+ i32 4, label %bb4
+ i32 5, label %bb5
+ i32 6, label %bb6
+ ]
+
+ bb1: ; preds = %entry
+ ret i32 4
+
+ bb2: ; preds = %entry
+ ret i32 3
+
+ bb3: ; preds = %entry
+ ret i32 2
+
+ bb4: ; preds = %entry
+ ret i32 1
+
+ bb5: ; preds = %entry
+ ret i32 100
+
+ bb6: ; preds = %entry
+ ret i32 200
+
+ default: ; preds = %entry
+ ret i32 1000
+ }
+
+...
+---
+name: jt_test
+legalized: true
+tracksRegLiveness: true
+jumpTable:
+ kind: block-address
+ entries:
+ - id: 0
+ blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ]
+body: |
+ ; RV32I-LABEL: name: jt_test
+ ; RV32I: bb.0.entry:
+ ; RV32I-NEXT: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 5
+ ; RV32I-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 200
+ ; RV32I-NEXT: [[C2:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 100
+ ; RV32I-NEXT: [[C3:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+ ; RV32I-NEXT: [[C4:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 2
+ ; RV32I-NEXT: [[C5:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
+ ; RV32I-NEXT: [[C6:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 4
+ ; RV32I-NEXT: [[C7:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1000
+ ; RV32I-NEXT: [[C8:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+ ; RV32I-NEXT: [[SUB:%[0-9]+]]:gprb(s32) = G_SUB [[COPY]], [[C8]]
+ ; RV32I-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ugt), [[SUB]](s32), [[C]]
+ ; RV32I-NEXT: G_BRCOND [[ICMP]](s32), %bb.8
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: bb.1.entry:
+ ; RV32I-NEXT: successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[JUMP_TABLE:%[0-9]+]]:gprb(p0) = G_JUMP_TABLE %jump-table.0
+ ; RV32I-NEXT: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[SUB]](s32)
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: bb.2.bb1:
+ ; RV32I-NEXT: $x10 = COPY [[C6]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: bb.3.bb2:
+ ; RV32I-NEXT: $x10 = COPY [[C5]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: bb.4.bb3:
+ ; RV32I-NEXT: $x10 = COPY [[C4]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: bb.5.bb4:
+ ; RV32I-NEXT: $x10 = COPY [[C3]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: bb.6.bb5:
+ ; RV32I-NEXT: $x10 = COPY [[C2]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: bb.7.bb6:
+ ; RV32I-NEXT: $x10 = COPY [[C1]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: bb.8.default:
+ ; RV32I-NEXT: $x10 = COPY [[C7]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ bb.1.entry:
+ successors: %bb.8, %bb.9
+ liveins: $x10
+
+ %0:_(s32) = COPY $x10
+ %4:_(s32) = G_CONSTANT i32 5
+ %8:_(s32) = G_CONSTANT i32 200
+ %9:_(s32) = G_CONSTANT i32 100
+ %10:_(s32) = G_CONSTANT i32 1
+ %11:_(s32) = G_CONSTANT i32 2
+ %12:_(s32) = G_CONSTANT i32 3
+ %13:_(s32) = G_CONSTANT i32 4
+ %14:_(s32) = G_CONSTANT i32 1000
+ %1:_(s32) = G_CONSTANT i32 1
+ %2:_(s32) = G_SUB %0, %1
+ %16:_(s32) = G_ICMP intpred(ugt), %2(s32), %4
+ G_BRCOND %16(s32), %bb.8
+
+ bb.9.entry:
+ successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7
+
+ %7:_(p0) = G_JUMP_TABLE %jump-table.0
+ G_BRJT %7(p0), %jump-table.0, %2(s32)
+
+ bb.2.bb1:
+ $x10 = COPY %13(s32)
+ PseudoRET implicit $x10
+
+ bb.3.bb2:
+ $x10 = COPY %12(s32)
+ PseudoRET implicit $x10
+
+ bb.4.bb3:
+ $x10 = COPY %11(s32)
+ PseudoRET implicit $x10
+
+ bb.5.bb4:
+ $x10 = COPY %10(s32)
+ PseudoRET implicit $x10
+
+ bb.6.bb5:
+ $x10 = COPY %9(s32)
+ PseudoRET implicit $x10
+
+ bb.7.bb6:
+ $x10 = COPY %8(s32)
+ PseudoRET implicit $x10
+
+ bb.8.default:
+ $x10 = COPY %14(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir
new file mode 100644
index 000000000000000..e36d2418ae06286
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir
@@ -0,0 +1,159 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck -check-prefix=RV64I %s
+
+--- |
+ define i32 @jt_test(i32 signext %in) {
+ entry:
+ %0 = sext i32 %in to i64
+ switch i64 %0, label %default [
+ i64 1, label %bb1
+ i64 2, label %bb2
+ i64 3, label %bb3
+ i64 4, label %bb4
+ i64 5, label %bb5
+ i64 6, label %bb6
+ ]
+
+ bb1: ; preds = %entry
+ ret i32 4
+
+ bb2: ; preds = %entry
+ ret i32 3
+
+ bb3: ; preds = %entry
+ ret i32 2
+
+ bb4: ; preds = %entry
+ ret i32 1
+
+ bb5: ; preds = %entry
+ ret i32 100
+
+ bb6: ; preds = %entry
+ ret i32 200
+
+ default: ; preds = %entry
+ ret i32 1000
+ }
+
+...
+---
+name: jt_test
+legalized: true
+tracksRegLiveness: true
+jumpTable:
+ kind: custom32
+ entries:
+ - id: 0
+ blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ]
+body: |
+ ; RV64I-LABEL: name: jt_test
+ ; RV64I: bb.0.entry:
+ ; RV64I-NEXT: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:gprb(s64) = G_ASSERT_SEXT [[COPY]], 32
+ ; RV64I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 5
+ ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:gprb(s64) = G_SEXT_INREG [[ASSERT_SEXT]], 32
+ ; RV64I-NEXT: [[C1:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+ ; RV64I-NEXT: [[SUB:%[0-9]+]]:gprb(s64) = G_SUB [[SEXT_INREG]], [[C1]]
+ ; RV64I-NEXT: [[ICMP:%[0-9]+]]:gprb(s64) = G_ICMP intpred(ugt), [[SUB]](s64), [[C]]
+ ; RV64I-NEXT: G_BRCOND [[ICMP]](s64), %bb.8
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: bb.1.entry:
+ ; RV64I-NEXT: successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[JUMP_TABLE:%[0-9]+]]:gprb(p0) = G_JUMP_TABLE %jump-table.0
+ ; RV64I-NEXT: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[SUB]](s64)
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: bb.2.bb1:
+ ; RV64I-NEXT: [[C2:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 4
+ ; RV64I-NEXT: $x10 = COPY [[C2]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: bb.3.bb2:
+ ; RV64I-NEXT: [[C3:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 3
+ ; RV64I-NEXT: $x10 = COPY [[C3]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: bb.4.bb3:
+ ; RV64I-NEXT: [[C4:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 2
+ ; RV64I-NEXT: $x10 = COPY [[C4]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: bb.5.bb4:
+ ; RV64I-NEXT: [[C5:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+ ; RV64I-NEXT: $x10 = COPY [[C5]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: bb.6.bb5:
+ ; RV64I-NEXT: [[C6:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 100
+ ; RV64I-NEXT: $x10 = COPY [[C6]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: bb.7.bb6:
+ ; RV64I-NEXT: [[C7:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 200
+ ; RV64I-NEXT: $x10 = COPY [[C7]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: bb.8.default:
+ ; RV64I-NEXT: [[C8:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1000
+ ; RV64I-NEXT: $x10 = COPY [[C8]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ bb.1.entry:
+ successors: %bb.8, %bb.9
+ liveins: $x10
+
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = G_ASSERT_SEXT %1, 32
+ %7:_(s64) = G_CONSTANT i64 5
+ %3:_(s64) = G_SEXT_INREG %2, 32
+ %4:_(s64) = G_CONSTANT i64 1
+ %5:_(s64) = G_SUB %3, %4
+ %26:_(s64) = G_ICMP intpred(ugt), %5(s64), %7
+ G_BRCOND %26(s64), %bb.8
+
+ bb.9.entry:
+ successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7
+
+ %10:_(p0) = G_JUMP_TABLE %jump-table.0
+ G_BRJT %10(p0), %jump-table.0, %5(s64)
+
+ bb.2.bb1:
+ %22:_(s64) = G_CONSTANT i64 4
+ $x10 = COPY %22(s64)
+ PseudoRET implicit $x10
+
+ bb.3.bb2:
+ %20:_(s64) = G_CONSTANT i64 3
+ $x10 = COPY %20(s64)
+ PseudoRET implicit $x10
+
+ bb.4.bb3:
+ %18:_(s64) = G_CONSTANT i64 2
+ $x10 = COPY %18(s64)
+ PseudoRET implicit $x10
+
+ bb.5.bb4:
+ %16:_(s64) = G_CONSTANT i64 1
+ $x10 = COPY %16(s64)
+ PseudoRET implicit $x10
+
+ bb.6.bb5:
+ %14:_(s64) = G_CONSTANT i64 100
+ $x10 = COPY %14(s64)
+ PseudoRET implicit $x10
+
+ bb.7.bb6:
+ %12:_(s64) = G_CONSTANT i64 200
+ $x10 = COPY %12(s64)
+ PseudoRET implicit $x10
+
+ bb.8.default:
+ %24:_(s64) = G_CONSTANT i64 1000
+ $x10 = COPY %24(s64)
+ PseudoRET implicit $x10
+
+...
>From 799d884bc28498dc4046bffe60f2ec94d8a379c1 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 10 Nov 2023 12:31:12 -0800
Subject: [PATCH 3/4] Remove unneeded command line flag from tests.
---
.../RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir | 2 +-
.../RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir
index f53a939d7f88231..b7fd2a3ce01aad6 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv32.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir
index e36d2418ae06286..56cac99a2b411fe 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/jump-table-brjt-rv64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
--- |
>From c48ba95a8a408a6d3218db3e2cfc10c25d08d113 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 10 Nov 2023 12:32:01 -0800
Subject: [PATCH 4/4] Drop +m from test.
---
.../GlobalISel/legalizer/rv64/legalize-jump-table-brjt.mir | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-jump-table-brjt.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-jump-table-brjt.mir
index 9293959c8f39dd5..9910e98a3e8200f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-jump-table-brjt.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-jump-table-brjt.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=legalizer %s -o - \
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
--- |
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