[llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)

[Michael Maitland via llvm-commits]

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@@ -14,3 +14,15 @@ def GPRRegBank : RegisterBank<"GPRB", [GPR]>;
 
 /// Floating Point Registers: F.
 def FPRRegBank : RegisterBank<"FPRB", [FPR64]>;
+
+/// Vector Register Banks:
+def VRRegBank : RegisterBank<"VRB", [VR]>;
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michaelmaitland wrote:

>From the [regbankinfo api](https://releases.llvm.org/9.0.0/docs/GlobalISel.html#api-registerbankinfo) and [gmir-regbank](https://llvm.org/docs/GlobalISel/GMIR.html#gmir-regbank) docs:
```
* Banks: addRegBankCoverage — which register bank covers each register class.
* Register Banks are a means to constrain the register allocator to use a particular register file for a virtual register.
```

The current approach in this patch creates reg bank covers which try to be as small as they can be. For example, if we know that it has a VRM2 class, we choose a VRM2 bank instead of the more broad VR bank. My aim was that we'd constrain the register allocator to only use register that work for M2.

The approach you suggest creates reg bank covers that include the entire register file (the vector registers). What does this achieve if we cannot use every register in the register file anyway?

On a separate, but related note, do you think should VR and VM registers have different banks?

https://github.com/llvm/llvm-project/pull/71541