[clang] [llvm] [AArch64] Add quadword gather load/scatter store intrinsics with unscaled vector offset (PR #71290)

[Momchil Velikov via llvm-commits]

================
@@ -1457,6 +1457,24 @@ class AdvSIMD_GatherLoad_VS_Intrinsic
                 ],
                 [IntrReadMem]>;
 
+class AdvSIMD_GatherLoadQ_VS_Intrinsic
+    : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+                [
+                  llvm_nxv1i1_ty,
+                  llvm_anyvector_ty,
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momchil-velikov wrote:

> So, why do we have the predicated vector as llvm_nxv1i1_ty? I was exception something like LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, because I don't see any cast for the predicate under EmitSVEGatherLoad. This line Ops[0] = EmitSVEPredicateCast( Ops[0], castllvm::ScalableVectorType(F->getArg(0)->getType())); would map to whatever is the type in the position 0.

Yes, that's the idea: https://github.com/llvm/llvm-project/pull/71289

As for the `<vscale x 1 x i1>` it's the correct type to use as justified here: https://github.com/llvm/llvm-project/pull/71290/commits/a3b7e136e2f045a1c9948b679da89ec9a406516e


> Second, does it works if we replace the second llvm_anyvector_ty by llvm_nxv2i64_ty? I do think the vector will always be 64 bits

Yes, that better be `llvm_nxv2i64_ty`. I will fix it.


https://github.com/llvm/llvm-project/pull/71290