[llvm] [AMDGPU] Folding imm offset in more cases for scratch access (PR #70634)

[via llvm-commits]

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@@ -1146,13 +1146,61 @@ bool AMDGPUDAGToDAGISel::isDSOffset2Legal(SDValue Base, unsigned Offset0,
   return CurDAG->SignBitIsZero(Base);
 }
 
-bool AMDGPUDAGToDAGISel::isFlatScratchBaseLegal(SDValue Base,
+// Check that the address value of flat scratch load/store being put into
+// SGPR/VGPR is legal with respect to hardware's requirement that address in
+// SGPR/VGPR should be unsigned. When \p CheckTwoInstrs is set, we will check
+// against the instruction that defines \p Addr as well as the instruction that
+// defines the base address. When \p CheckTwoOperands is set, we will check both
+// operands (In case of two instructions, they are the operands from the
+// instruction that defines the base address).
+bool AMDGPUDAGToDAGISel::isFlatScratchBaseLegal(SDValue Addr,
+                                                bool CheckTwoInstrs,
+                                                bool CheckTwoOperands,
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ruiling wrote:

Thanks for pointing out this! I think the major confusion comes from the code to handle SGPR+VGPR+Imm case. I have moved it to a separate function. So I still keep one boolean flag `CheckBothOperands` which means check both operands instead of only checking the first operand. I think it is not necessary to split again.

https://github.com/llvm/llvm-project/pull/70634