[llvm] 0d48a46 - [ConstraintElim] Add test for mis-compile with adjacent loops.

[Florian Hahn via llvm-commits]

Author: Florian Hahn
Date: 2023-11-08T14:01:25Z
New Revision: 0d48a4645d9a3e9f188a0c9503df3f82ca5759e3

URL: https://github.com/llvm/llvm-project/commit/0d48a4645d9a3e9f188a0c9503df3f82ca5759e3
DIFF: https://github.com/llvm/llvm-project/commit/0d48a4645d9a3e9f188a0c9503df3f82ca5759e3.diff

LOG: [ConstraintElim] Add test for mis-compile with adjacent loops.

In the added test case, the AddRec from the first loop is used
incorrectly in the second loop.

Added: 
    llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-adjacent-loops.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-adjacent-loops.ll b/llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-adjacent-loops.ll
new file mode 100644
index 000000000000000..2df668a22050a3e
--- /dev/null
+++ b/llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-adjacent-loops.ll
@@ -0,0 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=constraint-elimination -S %s | FileCheck %s
+
+target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+
+declare void @use(i16)
+
+define void @test_loop_add_rec_used_in_adjacent_loop(i8 %len.n, i16 %a) {
+; CHECK-LABEL: @test_loop_add_rec_used_in_adjacent_loop(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LEN:%.*]] = zext i8 [[LEN_N:%.*]] to i16
+; CHECK-NEXT:    [[LEN_NEG:%.*]] = icmp uge i16 [[LEN]], [[A:%.*]]
+; CHECK-NEXT:    br i1 [[LEN_NEG]], label [[EXIT:%.*]], label [[LOOP_1_PH:%.*]]
+; CHECK:       loop.1.ph:
+; CHECK-NEXT:    br label [[LOOP_1:%.*]]
+; CHECK:       loop.1:
+; CHECK-NEXT:    [[IV:%.*]] = phi i16 [ 0, [[LOOP_1_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_1]] ]
+; CHECK-NEXT:    [[C_0:%.*]] = icmp eq i16 [[IV]], [[A]]
+; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i16 [[IV]], 1
+; CHECK-NEXT:    br i1 [[C_0]], label [[LOOP_2_HEADER:%.*]], label [[LOOP_1]]
+; CHECK:       loop.2.header:
+; CHECK-NEXT:    [[IV_2:%.*]] = phi i16 [ [[IV]], [[LOOP_1]] ], [ [[IV]], [[LOOP_2_LATCH:%.*]] ]
+; CHECK-NEXT:    [[C:%.*]] = icmp eq i16 [[IV_2]], [[LEN]]
+; CHECK-NEXT:    br i1 [[C]], label [[EXIT]], label [[FOR_BODY:%.*]]
+; CHECK:       for.body:
+; CHECK-NEXT:    [[AND:%.*]] = and i1 true, true
+; CHECK-NEXT:    br i1 [[AND]], label [[LOOP_2_LATCH]], label [[EXIT]]
+; CHECK:       loop.2.latch:
+; CHECK-NEXT:    call void @use(i16 [[IV_2]])
+; CHECK-NEXT:    br label [[LOOP_2_HEADER]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  %len = zext i8 %len.n to i16
+  %len.neg = icmp uge i16 %len, %a
+  br i1 %len.neg, label %exit, label %loop.1.ph
+
+loop.1.ph:
+  br label %loop.1
+
+loop.1:
+  %iv = phi i16 [ 0, %loop.1.ph ], [ %iv.next, %loop.1 ]
+  %c.0 = icmp eq i16 %iv, %a
+  %iv.next = add nuw nsw i16 %iv, 1
+  br i1 %c.0, label %loop.2.header, label %loop.1
+
+loop.2.header:
+  %iv.2 = phi i16 [ %iv, %loop.1 ], [ %iv, %loop.2.latch ]
+  %c = icmp eq i16 %iv.2, %len
+  br i1 %c, label %exit, label %for.body
+
+for.body:
+  %t.1 = icmp uge i16 %iv.2, 0
+  %t.2 = icmp ult i16 %iv.2, %a
+  %and = and i1 %t.1, %t.2
+  br i1 %and, label %loop.2.latch, label %exit
+
+loop.2.latch:
+  call void @use(i16 %iv.2)
+  br label %loop.2.header
+
+exit:
+  ret void
+}