[llvm] [RISCV][GlobalISel] Vector Extension vadd Legalizer (PR #71400)

Michael Maitland via llvm-commits llvm-commits at lists.llvm.org
Mon Nov 6 08:45:22 PST 2023


michaelmaitland wrote:

Thanks for working on this. I added myself as a reviewer in the top right -- you can click on reviewers and add names. I also added the llvm:globalisel and backend:RISCV-V labels for more visibility. We should add some more reviewers to this once we figure out the problem you are having and once we clean up the commits a bit.

It looks like the test is failing because of the following assertion failure:

```
llc: llvm-project/llvm/include/llvm/CodeGen/MachineRegisterInfo.h:665: const llvm::TargetRegisterClass *llvm::MachineRegisterInfo::getRegClass(llvm::Register) const: Assertion `isa<const TargetRegisterClass *>(VRegInfo[Reg.id()].first) && "Register class not set, wrong accessor"' failed.
```

I touched this function in one of my PRs: https://github.com/llvm/llvm-project/pull/70881. Maybe you can investigate why we're failing this assertion as a result of this test case? Were we supposed to assign a register a regclass? Maybe we need to do some work in RegBankSelection to avoid this failure?

https://github.com/llvm/llvm-project/pull/71400


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