[llvm] [AMDGPU] Move WWM register pre-allocation to during regalloc (PR #70618)

[Christudasan Devadasan via llvm-commits]

cdevadas wrote:

> The decision to use a physical register is made during SGPR spill lowering based on whether the function is an entry function or not.
One correction. I always wanted the SGPR spill lowering to use virtual VGPR here so that RA can allocate them efficiently. Currently, we use physical registers for CSR SGPR spills inserted at the prolog/epilog and virtual for the rest of the spills (the one introduced during SGPR-regalloc). This is to ensure that the CSR spills get VGPRs that won't be reused by RA for any other liveranges in the function. This is a fixup to ensure the CSR spills get static CFI entries. We earlier encountered an issue in the rocgdb during frame unwinding that the CFI entries for the CSR spills are broken.

Skipping AMDGPU::SI_SPILL_S32_TO_VGPR & AMDGPU::SI_RESTORE_S32_FROM_VGPR here is the right thing. Because they are meant to be allocated during RA.
BTW, why SI_RESTORE_S32_FROM_VGPR isn't included here?


https://github.com/llvm/llvm-project/pull/70618