[llvm] TableGen support for RegisterBankInfo (PR #71357)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 5 22:05:31 PST 2023
https://github.com/CBSears updated https://github.com/llvm/llvm-project/pull/71357
>From d6f25b08833463b4caa4148dee629c8e9f900a12 Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Sun, 5 Nov 2023 16:41:38 -0800
Subject: [PATCH 1/4] renamed emitRBIIMPL and other small changes
---
llvm/utils/TableGen/RegisterBankEmitter.cpp | 102 ++++++++++++++++++--
1 file changed, 94 insertions(+), 8 deletions(-)
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index f851d9a79870b45..ad87c9a4d06bb30 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
//
// This tablegen backend is responsible for emitting a description of a target
-// register bank for a code generator.
+// register bank and register bank info for a code generator.
//
//===----------------------------------------------------------------------===//
@@ -112,7 +112,11 @@ class RegisterBankEmitter {
void emitBaseClassDefinition(raw_ostream &OS, const StringRef TargetName,
const std::vector<RegisterBank> &Banks);
void emitBaseClassImplementation(raw_ostream &OS, const StringRef TargetName,
- std::vector<RegisterBank> &Banks);
+ const std::vector<RegisterBank> &Banks);
+ void emitRBIHeader(raw_ostream &OS, const StringRef TargetName,
+ const std::vector<RegisterBank> &Banks);
+ void emitRBIImplementation(raw_ostream &OS, const StringRef TargetName,
+ const std::vector<RegisterBank> &Banks);
public:
RegisterBankEmitter(RecordKeeper &R) : Target(R), Records(R) {}
@@ -213,7 +217,7 @@ static void visitRegisterBankClasses(
void RegisterBankEmitter::emitBaseClassImplementation(
raw_ostream &OS, StringRef TargetName,
- std::vector<RegisterBank> &Banks) {
+ const std::vector<RegisterBank> &Banks) {
const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
const CodeGenHwModes &CGH = Target.getHwModes();
@@ -231,7 +235,9 @@ void RegisterBankEmitter::emitBaseClassImplementation(
for (const auto &RCs : RCsGroupedByWord) {
OS << " // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31) << "\n";
for (const auto &RC : RCs) {
- OS << " (1u << (" << RC->getQualifiedIdName() << " - "
+ std::string QualifiedRegClassID =
+ (Twine(RC->Namespace) + "::" + RC->getName() + "RegClassID").str();
+ OS << " (1u << (" << QualifiedRegClassID << " - "
<< LowestIdxInWord << ")) |\n";
}
OS << " 0,\n";
@@ -244,7 +250,7 @@ void RegisterBankEmitter::emitBaseClassImplementation(
for (const auto &Bank : Banks) {
std::string QualifiedBankID =
(TargetName + "::" + Bank.getEnumeratorName()).str();
- OS << "constexpr RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ "
+ OS << "const RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ "
<< QualifiedBankID << ", /* Name */ \"" << Bank.getName() << "\", "
<< "/* CoveredRegClasses */ " << Bank.getCoverageArrayName()
<< ", /* NumRegClasses */ "
@@ -289,6 +295,76 @@ void RegisterBankEmitter::emitBaseClassImplementation(
<< "} // end namespace llvm\n";
}
+void RegisterBankEmitter::emitRBIHeader(
+ raw_ostream &OS, const StringRef TargetName,
+ const std::vector<RegisterBank> &Banks) {
+ const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
+
+ OS << "namespace llvm {\n"
+ << "namespace " << TargetName << " {\n"
+ << "enum PartialMappingIdx {\n"
+ << " PMI_None = -1,\n";
+
+ // Banks and Register Classes are *not* emitted in their original text order
+ int ID = 0;
+ for (const auto &Bank : Banks) {
+ for (const CodeGenRegisterClass *RC :
+ Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+ OS << " PMI_" << RC->getName() << " = " << ID++ << ",\n";
+ }
+ }
+ OS << "};\n";
+ OS << "} // end namespace " << TargetName << "\n"
+ << "} // end namespace llvm\n";
+}
+
+void RegisterBankEmitter::emitRBIImplementation(raw_ostream &OS,
+ const StringRef TargetName,
+ const std::vector<RegisterBank> &Banks) {
+ const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
+
+ OS << "namespace llvm {\n"
+ << "namespace " << TargetName << " {\n"
+ << "RegisterBankInfo::PartialMapping PartMappings[] = {\n";
+ for (const auto &Bank : Banks) {
+ for (const CodeGenRegisterClass *RC :
+ Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
+ if (RC->RSI.isSimple()) {
+ // StartIdx is currently 0 in all of the in-tree backends
+ OS << " { 0, " << RC->RSI.getSimple().RegSize << ", "
+ << Bank.getInstanceVarName() << " },\n";
+ } else {
+ // FIXME: dumb workaround for RISCV assert() for now
+ OS << " // non-Simple() RegisterClass " << RC->getName() << "\n";
+ }
+ }
+ }
+ OS << "};\n\n";
+
+ // emit PartialMappingIdx of the first Register Class of each Register Bank
+ OS << "PartialMappingIdx BankIDToFirstRegisterClassIdx[] = {\n";
+ for (const auto &Bank : Banks) {
+ OS << " PMI_"
+ << Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)[0]
+ ->getName()
+ << ",\n";
+ }
+ OS << "};\n\n";
+
+ // emit count of Register Classes of each Register Bank
+ OS << "int BankIDToRegisterClassCount[] = {\n";
+ for (const auto &Bank : Banks) {
+ OS << " "
+ << Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)
+ .size()
+ << ",\n";
+ }
+ OS << "};\n\n";
+
+ OS << "} // end namespace " << TargetName << "\n"
+ << "} // end namespace llvm\n";
+}
+
void RegisterBankEmitter::run(raw_ostream &OS) {
StringRef TargetName = Target.getName();
const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
@@ -330,7 +406,8 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
}
Records.startTimer("Emit output");
- emitSourceFileHeader("Register Bank Source Fragments", OS);
+ emitSourceFileHeader("Register Bank And Register Bank Info Source Fragments",
+ OS);
OS << "#ifdef GET_REGBANK_DECLARATIONS\n"
<< "#undef GET_REGBANK_DECLARATIONS\n";
emitHeader(OS, TargetName, Banks);
@@ -342,8 +419,17 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
<< "#ifdef GET_TARGET_REGBANK_IMPL\n"
<< "#undef GET_TARGET_REGBANK_IMPL\n";
emitBaseClassImplementation(OS, TargetName, Banks);
- OS << "#endif // GET_TARGET_REGBANK_IMPL\n";
+ OS << "#endif // GET_TARGET_REGBANK_IMPL\n\n"
+ << "#ifdef GET_REGBANKINFO_DECLARATIONS\n"
+ << "#undef GET_REGBANKINFO_DECLARATIONS\n";
+ emitRBIHeader(OS, TargetName, Banks);
+ OS << "#endif // GET_REGBANKINFO_DECLARATIONS\n\n"
+ << "#ifdef GET_REGBANKINFO_IMPL\n"
+ << "#undef GET_REGBANKINFO_IMPL\n";
+ emitRBIImplementation(OS, TargetName, Banks);
+ OS << "#endif // GET_REGBANKINFO_IMPL\n";
}
static TableGen::Emitter::OptClass<RegisterBankEmitter>
- X("gen-register-bank", "Generate registers bank descriptions");
+ X("gen-register-bank",
+ "Generate register bank and register bank info descriptions");
>From 7bee10e30a2ba0262df3a4fde72bec533ed94f60 Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Sun, 5 Nov 2023 18:44:37 -0800
Subject: [PATCH 2/4] added const keyword to emitted arrays
---
llvm/utils/TableGen/RegisterBankEmitter.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index ad87c9a4d06bb30..545647d8fe4cacf 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -325,7 +325,7 @@ void RegisterBankEmitter::emitRBIImplementation(raw_ostream &OS,
OS << "namespace llvm {\n"
<< "namespace " << TargetName << " {\n"
- << "RegisterBankInfo::PartialMapping PartMappings[] = {\n";
+ << "const RegisterBankInfo::PartialMapping PartMappings[] = {\n";
for (const auto &Bank : Banks) {
for (const CodeGenRegisterClass *RC :
Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
@@ -342,7 +342,7 @@ void RegisterBankEmitter::emitRBIImplementation(raw_ostream &OS,
OS << "};\n\n";
// emit PartialMappingIdx of the first Register Class of each Register Bank
- OS << "PartialMappingIdx BankIDToFirstRegisterClassIdx[] = {\n";
+ OS << "const PartialMappingIdx BankIDToFirstRegisterClassIdx[] = {\n";
for (const auto &Bank : Banks) {
OS << " PMI_"
<< Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)[0]
@@ -352,7 +352,7 @@ void RegisterBankEmitter::emitRBIImplementation(raw_ostream &OS,
OS << "};\n\n";
// emit count of Register Classes of each Register Bank
- OS << "int BankIDToRegisterClassCount[] = {\n";
+ OS << "const int BankIDToRegisterClassCount[] = {\n";
for (const auto &Bank : Banks) {
OS << " "
<< Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)
>From e74d92530b75ec4d653a35dc7ec82ba96fd339f9 Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Sun, 5 Nov 2023 19:04:37 -0800
Subject: [PATCH 3/4] clang-format formatting
---
llvm/utils/TableGen/RegisterBankEmitter.cpp | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index 545647d8fe4cacf..2e0b282f324366b 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -116,7 +116,7 @@ class RegisterBankEmitter {
void emitRBIHeader(raw_ostream &OS, const StringRef TargetName,
const std::vector<RegisterBank> &Banks);
void emitRBIImplementation(raw_ostream &OS, const StringRef TargetName,
- const std::vector<RegisterBank> &Banks);
+ const std::vector<RegisterBank> &Banks);
public:
RegisterBankEmitter(RecordKeeper &R) : Target(R), Records(R) {}
@@ -237,8 +237,8 @@ void RegisterBankEmitter::emitBaseClassImplementation(
for (const auto &RC : RCs) {
std::string QualifiedRegClassID =
(Twine(RC->Namespace) + "::" + RC->getName() + "RegClassID").str();
- OS << " (1u << (" << QualifiedRegClassID << " - "
- << LowestIdxInWord << ")) |\n";
+ OS << " (1u << (" << QualifiedRegClassID << " - " << LowestIdxInWord
+ << ")) |\n";
}
OS << " 0,\n";
LowestIdxInWord += 32;
@@ -318,9 +318,10 @@ void RegisterBankEmitter::emitRBIHeader(
<< "} // end namespace llvm\n";
}
-void RegisterBankEmitter::emitRBIImplementation(raw_ostream &OS,
- const StringRef TargetName,
- const std::vector<RegisterBank> &Banks) {
+void RegisterBankEmitter::emitRBIImplementation(
+ raw_ostream &OS,
+ const StringRef TargetName,
+ const std::vector<RegisterBank> &Banks) {
const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
OS << "namespace llvm {\n"
>From 241919d4e107fab3be71406858d19967a42718cf Mon Sep 17 00:00:00 2001
From: Chris Sears <chris at doublewide.io>
Date: Sun, 5 Nov 2023 22:04:20 -0800
Subject: [PATCH 4/4] fixing clang-format complaint
---
llvm/utils/TableGen/RegisterBankEmitter.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index 2e0b282f324366b..37b9c0fc92d927b 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -319,8 +319,7 @@ void RegisterBankEmitter::emitRBIHeader(
}
void RegisterBankEmitter::emitRBIImplementation(
- raw_ostream &OS,
- const StringRef TargetName,
+ raw_ostream &OS, const StringRef TargetName,
const std::vector<RegisterBank> &Banks) {
const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
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