[llvm] 7fe4025 - Autogenerate a indvars test for ease of update in future change
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 31 09:57:22 PDT 2023
Author: Philip Reames
Date: 2023-10-31T09:57:11-07:00
New Revision: 7fe4025c16be8148f88091b201c29492aaa1ccd0
URL: https://github.com/llvm/llvm-project/commit/7fe4025c16be8148f88091b201c29492aaa1ccd0
DIFF: https://github.com/llvm/llvm-project/commit/7fe4025c16be8148f88091b201c29492aaa1ccd0.diff
LOG: Autogenerate a indvars test for ease of update in future change
Added:
Modified:
llvm/test/Transforms/IndVarSimplify/ada-loops.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/IndVarSimplify/ada-loops.ll b/llvm/test/Transforms/IndVarSimplify/ada-loops.ll
index 26d4219b347f157..b4725f8ce774e76 100644
--- a/llvm/test/Transforms/IndVarSimplify/ada-loops.ll
+++ b/llvm/test/Transforms/IndVarSimplify/ada-loops.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
; RUN: opt < %s -passes=indvars -S | FileCheck %s
;
; PR1301
@@ -15,85 +16,142 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32"
target triple = "i686-pc-linux-gnu"
-; CHECK-LABEL: @kinds__sbytezero
-; CHECK: bb.thread:
-; CHECK: sext
-; CHECK: bb:
-; CHECK-NOT: {{sext i8|zext i8|add i8|trunc}}
-
define void @kinds__sbytezero(ptr nocapture %a) nounwind {
+; CHECK-LABEL: define void @kinds__sbytezero(
+; CHECK-SAME: ptr nocapture [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: bb.thread:
+; CHECK-NEXT: [[TMP46:%.*]] = getelementptr [256 x i32], ptr [[A]], i32 0, i32 0
+; CHECK-NEXT: store i32 0, ptr [[TMP46]], align 4
+; CHECK-NEXT: [[SEXT:%.*]] = sext i8 127 to i32
+; CHECK-NEXT: br label [[BB:%.*]]
+; CHECK: bb:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ [[INDVARS_IV_NEXT:%.*]], [[BB]] ], [ -128, [[BB_THREAD:%.*]] ]
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i32 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = add nsw i32 [[INDVARS_IV_NEXT]], 128
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr [256 x i32], ptr [[A]], i32 0, i32 [[TMP3]]
+; CHECK-NEXT: store i32 0, ptr [[TMP4]], align 4
+; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[INDVARS_IV_NEXT]], [[SEXT]]
+; CHECK-NEXT: br i1 [[TMP0]], label [[RETURN:%.*]], label [[BB]]
+; CHECK: return:
+; CHECK-NEXT: ret void
+;
bb.thread:
- %tmp46 = getelementptr [256 x i32], ptr %a, i32 0, i32 0 ; <ptr> [#uses=1]
- store i32 0, ptr %tmp46
- br label %bb
+ %tmp46 = getelementptr [256 x i32], ptr %a, i32 0, i32 0 ; <ptr> [#uses=1]
+ store i32 0, ptr %tmp46
+ br label %bb
bb: ; preds = %bb, %bb.thread
- %i.0.reg2mem.0 = phi i8 [ -128, %bb.thread ], [ %tmp8, %bb ] ; <i8> [#uses=1]
- %tmp8 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=3]
- %tmp1 = sext i8 %tmp8 to i32 ; <i32> [#uses=1]
- %tmp3 = add i32 %tmp1, 128 ; <i32> [#uses=1]
- %tmp4 = getelementptr [256 x i32], ptr %a, i32 0, i32 %tmp3 ; <ptr> [#uses=1]
- store i32 0, ptr %tmp4
- %0 = icmp eq i8 %tmp8, 127 ; <i1> [#uses=1]
- br i1 %0, label %return, label %bb
+ %i.0.reg2mem.0 = phi i8 [ -128, %bb.thread ], [ %tmp8, %bb ] ; <i8> [#uses=1]
+ %tmp8 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=3]
+ %tmp1 = sext i8 %tmp8 to i32 ; <i32> [#uses=1]
+ %tmp3 = add i32 %tmp1, 128 ; <i32> [#uses=1]
+ %tmp4 = getelementptr [256 x i32], ptr %a, i32 0, i32 %tmp3 ; <ptr> [#uses=1]
+ store i32 0, ptr %tmp4
+ %0 = icmp eq i8 %tmp8, 127 ; <i1> [#uses=1]
+ br i1 %0, label %return, label %bb
return: ; preds = %bb
- ret void
+ ret void
}
-; CHECK-LABEL: @kinds__ubytezero
define void @kinds__ubytezero(ptr nocapture %a) nounwind {
+; CHECK-LABEL: define void @kinds__ubytezero(
+; CHECK-SAME: ptr nocapture [[A:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: bb.thread:
+; CHECK-NEXT: [[TMP35:%.*]] = getelementptr [256 x i32], ptr [[A]], i32 0, i32 0
+; CHECK-NEXT: store i32 0, ptr [[TMP35]], align 4
+; CHECK-NEXT: br label [[BB:%.*]]
+; CHECK: bb:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ [[INDVARS_IV_NEXT:%.*]], [[BB]] ], [ 0, [[BB_THREAD:%.*]] ]
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i32 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr [256 x i32], ptr [[A]], i32 0, i32 [[INDVARS_IV_NEXT]]
+; CHECK-NEXT: store i32 0, ptr [[TMP3]], align 4
+; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[INDVARS_IV_NEXT]], 255
+; CHECK-NEXT: br i1 [[TMP0]], label [[RETURN:%.*]], label [[BB]]
+; CHECK: return:
+; CHECK-NEXT: ret void
+;
bb.thread:
- %tmp35 = getelementptr [256 x i32], ptr %a, i32 0, i32 0 ; <ptr> [#uses=1]
- store i32 0, ptr %tmp35
- br label %bb
+ %tmp35 = getelementptr [256 x i32], ptr %a, i32 0, i32 0 ; <ptr> [#uses=1]
+ store i32 0, ptr %tmp35
+ br label %bb
bb: ; preds = %bb, %bb.thread
- %i.0.reg2mem.0 = phi i8 [ 0, %bb.thread ], [ %tmp7, %bb ] ; <i8> [#uses=1]
- %tmp7 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=3]
- %tmp1 = zext i8 %tmp7 to i32 ; <i32> [#uses=1]
- %tmp3 = getelementptr [256 x i32], ptr %a, i32 0, i32 %tmp1 ; <ptr> [#uses=1]
- store i32 0, ptr %tmp3
- %0 = icmp eq i8 %tmp7, -1 ; <i1> [#uses=1]
- br i1 %0, label %return, label %bb
+ %i.0.reg2mem.0 = phi i8 [ 0, %bb.thread ], [ %tmp7, %bb ] ; <i8> [#uses=1]
+ %tmp7 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=3]
+ %tmp1 = zext i8 %tmp7 to i32 ; <i32> [#uses=1]
+ %tmp3 = getelementptr [256 x i32], ptr %a, i32 0, i32 %tmp1 ; <ptr> [#uses=1]
+ store i32 0, ptr %tmp3
+ %0 = icmp eq i8 %tmp7, -1 ; <i1> [#uses=1]
+ br i1 %0, label %return, label %bb
return: ; preds = %bb
- ret void
+ ret void
}
define void @kinds__srangezero(ptr nocapture %a) nounwind {
+; CHECK-LABEL: define void @kinds__srangezero(
+; CHECK-SAME: ptr nocapture [[A:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: bb.thread:
+; CHECK-NEXT: br label [[BB:%.*]]
+; CHECK: bb:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ [[INDVARS_IV_NEXT:%.*]], [[BB]] ], [ -10, [[BB_THREAD:%.*]] ]
+; CHECK-NEXT: [[TMP4:%.*]] = add nsw i32 [[INDVARS_IV]], 10
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr [21 x i32], ptr [[A]], i32 0, i32 [[TMP4]]
+; CHECK-NEXT: store i32 0, ptr [[TMP5]], align 4
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i32 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INDVARS_IV_NEXT]], 11
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[RETURN:%.*]], label [[BB]]
+; CHECK: return:
+; CHECK-NEXT: ret void
+;
bb.thread:
- br label %bb
+ br label %bb
bb: ; preds = %bb, %bb.thread
- %i.0.reg2mem.0 = phi i8 [ -10, %bb.thread ], [ %tmp7, %bb ] ; <i8> [#uses=2]
- %tmp12 = sext i8 %i.0.reg2mem.0 to i32 ; <i32> [#uses=1]
- %tmp4 = add i32 %tmp12, 10 ; <i32> [#uses=1]
- %tmp5 = getelementptr [21 x i32], ptr %a, i32 0, i32 %tmp4 ; <ptr> [#uses=1]
- store i32 0, ptr %tmp5
- %tmp7 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=2]
- %0 = icmp sgt i8 %tmp7, 10 ; <i1> [#uses=1]
- br i1 %0, label %return, label %bb
+ %i.0.reg2mem.0 = phi i8 [ -10, %bb.thread ], [ %tmp7, %bb ] ; <i8> [#uses=2]
+ %tmp12 = sext i8 %i.0.reg2mem.0 to i32 ; <i32> [#uses=1]
+ %tmp4 = add i32 %tmp12, 10 ; <i32> [#uses=1]
+ %tmp5 = getelementptr [21 x i32], ptr %a, i32 0, i32 %tmp4 ; <ptr> [#uses=1]
+ store i32 0, ptr %tmp5
+ %tmp7 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=2]
+ %0 = icmp sgt i8 %tmp7, 10 ; <i1> [#uses=1]
+ br i1 %0, label %return, label %bb
return: ; preds = %bb
- ret void
+ ret void
}
define void @kinds__urangezero(ptr nocapture %a) nounwind {
+; CHECK-LABEL: define void @kinds__urangezero(
+; CHECK-SAME: ptr nocapture [[A:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: bb.thread:
+; CHECK-NEXT: br label [[BB:%.*]]
+; CHECK: bb:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ [[INDVARS_IV_NEXT:%.*]], [[BB]] ], [ 10, [[BB_THREAD:%.*]] ]
+; CHECK-NEXT: [[TMP4:%.*]] = add nsw i32 [[INDVARS_IV]], -10
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr [21 x i32], ptr [[A]], i32 0, i32 [[TMP4]]
+; CHECK-NEXT: store i32 0, ptr [[TMP5]], align 4
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i32 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INDVARS_IV_NEXT]], 31
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[RETURN:%.*]], label [[BB]]
+; CHECK: return:
+; CHECK-NEXT: ret void
+;
bb.thread:
- br label %bb
+ br label %bb
bb: ; preds = %bb, %bb.thread
- %i.0.reg2mem.0 = phi i8 [ 10, %bb.thread ], [ %tmp7, %bb ] ; <i8> [#uses=2]
- %tmp12 = sext i8 %i.0.reg2mem.0 to i32 ; <i32> [#uses=1]
- %tmp4 = add i32 %tmp12, -10 ; <i32> [#uses=1]
- %tmp5 = getelementptr [21 x i32], ptr %a, i32 0, i32 %tmp4 ; <ptr> [#uses=1]
- store i32 0, ptr %tmp5
- %tmp7 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=2]
- %0 = icmp sgt i8 %tmp7, 30 ; <i1> [#uses=1]
- br i1 %0, label %return, label %bb
+ %i.0.reg2mem.0 = phi i8 [ 10, %bb.thread ], [ %tmp7, %bb ] ; <i8> [#uses=2]
+ %tmp12 = sext i8 %i.0.reg2mem.0 to i32 ; <i32> [#uses=1]
+ %tmp4 = add i32 %tmp12, -10 ; <i32> [#uses=1]
+ %tmp5 = getelementptr [21 x i32], ptr %a, i32 0, i32 %tmp4 ; <ptr> [#uses=1]
+ store i32 0, ptr %tmp5
+ %tmp7 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=2]
+ %0 = icmp sgt i8 %tmp7, 30 ; <i1> [#uses=1]
+ br i1 %0, label %return, label %bb
return: ; preds = %bb
- ret void
+ ret void
}
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