[llvm] [AMDGPU] Correct assert that incorrectly chained multiple == operators. (PR #70291)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/70291

I believe this assert was trying to check that 3 variables were equal to 0.

I think it instead got interpreted as ((DSWCount == DSWWithPermCount) == DSWWithSharedVMEMCount) == 0 I guess (DSWCount == DSWWithPermCount) was true because both counts were 0. Then true got compared to DSWWithSharedVMEMCount, and since DSWWithSharedVMEMCount is 0, that compare was false. And then that false compared equal to the final 0.

>From 7c47ef9cad48a411c1eead043c1c6781450007f0 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 25 Oct 2023 21:48:25 -0700
Subject: [PATCH] [AMDGPU] Correct assert that incorrectly chained multiple ==
 operators.

I believe this assert was trying to check that 3 variables were
equal to 0.

I think it instead got interpreted as ((DSWCount == DSWWithPermCount) == DSWWithSharedVMEMCount) == 0
I guess (DSWCount == DSWWithPermCount) was true because both counts
were 0. Then true got compared to DSWWithSharedVMEMCount, and since
DSWWithSharedVMEMCount is 0, that compare was false. And then that
false compared equal to the final 0.
---
 llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index c67a21c639fc029..0b2bb98738be2aa 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -1121,8 +1121,8 @@ void MFMASmallGemmSingleWaveOpt::applyIGLPStrategy(
   unsigned MFMACount = 0;
   unsigned DSRCount = 0;
 
-  assert((IsPostRA ||
-          DSWCount == DSWWithPermCount == DSWWithSharedVMEMCount == 0) &&
+  assert((IsPostRA || (DSWCount == 0 && DSWWithPermCount == 0 &&
+                       DSWWithSharedVMEMCount == 0)) &&
          "DSWCounters should be zero in pre-RA scheduling!");
   SmallVector<SUnit *, 6> DSWithPerms;
   for (auto &SU : DAG->SUnits) {