[llvm] [llvm][AArch64][Assembly]: Add FP8FMA assembly and disassembly. (PR #70237)

via llvm-commits llvm-commits at lists.llvm.org
Wed Oct 25 11:07:21 PDT 2023


github-actions[bot] wrote:


<!--LLVM CODE FORMAT COMMENT: {clang-format}-->

:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff 8715600435c7650addabcf2a8337bdfd3297c58d 92dd4217280833703abc12d7f8c52f697db45629 -- llvm/include/llvm/TargetParser/AArch64TargetParser.h llvm/include/llvm/TargetParser/SubtargetFeature.h llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp llvm/unittests/TargetParser/TargetParserTest.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index c6bc6f8dc7d4..4cdc792039e2 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2598,32 +2598,31 @@ static std::optional<std::pair<int, int>> parseVectorKind(StringRef Suffix,
 
   switch (VectorKind) {
   case RegKind::NeonVector:
-    Res =
-        StringSwitch<std::pair<int, int>>(Suffix.lower())
-            .Case("", {0, 0})
-            .Case(".1d", {1, 64})
-            .Case(".1q", {1, 128})
-            .Case(".2b", {2, 8})
-            // '.2h' needed for fp16 scalar pairwise reductions
-            .Case(".2h", {2, 16})
-            .Case(".2s", {2, 32})
-            .Case(".2d", {2, 64})
-            // '.4b' is another special case for the ARMv8.2a dot product
-            // operand
-            .Case(".4b", {4, 8})
-            .Case(".4h", {4, 16})
-            .Case(".4s", {4, 32})
-            .Case(".8b", {8, 8})
-            .Case(".8h", {8, 16})
-            .Case(".16b", {16, 8})
-            // Accept the width neutral ones, too, for verbose syntax. If those
-            // aren't used in the right places, the token operand won't match so
-            // all will work out.
-            .Case(".b", {0, 8})
-            .Case(".h", {0, 16})
-            .Case(".s", {0, 32})
-            .Case(".d", {0, 64})
-            .Default({-1, -1});
+    Res = StringSwitch<std::pair<int, int>>(Suffix.lower())
+              .Case("", {0, 0})
+              .Case(".1d", {1, 64})
+              .Case(".1q", {1, 128})
+              .Case(".2b", {2, 8})
+              // '.2h' needed for fp16 scalar pairwise reductions
+              .Case(".2h", {2, 16})
+              .Case(".2s", {2, 32})
+              .Case(".2d", {2, 64})
+              // '.4b' is another special case for the ARMv8.2a dot product
+              // operand
+              .Case(".4b", {4, 8})
+              .Case(".4h", {4, 16})
+              .Case(".4s", {4, 32})
+              .Case(".8b", {8, 8})
+              .Case(".8h", {8, 16})
+              .Case(".16b", {16, 8})
+              // Accept the width neutral ones, too, for verbose syntax. If
+              // those aren't used in the right places, the token operand won't
+              // match so all will work out.
+              .Case(".b", {0, 8})
+              .Case(".h", {0, 16})
+              .Case(".s", {0, 32})
+              .Case(".d", {0, 64})
+              .Default({-1, -1});
     break;
   case RegKind::SVEPredicateAsCounter:
   case RegKind::SVEPredicateVector:
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 4e7b4b4ef997..af7df2f58973 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1713,27 +1713,37 @@ TEST(TargetParserTest, testAArch64Extension) {
 
 TEST(TargetParserTest, AArch64ExtensionFeatures) {
   std::vector<uint64_t> Extensions = {
-      AArch64::AEK_CRC,     AArch64::AEK_LSE,       AArch64::AEK_RDM,
-      AArch64::AEK_CRYPTO,  AArch64::AEK_SM4,       AArch64::AEK_SHA3,
-      AArch64::AEK_SHA2,    AArch64::AEK_AES,       AArch64::AEK_DOTPROD,
-      AArch64::AEK_FP,      AArch64::AEK_SIMD,      AArch64::AEK_FP16,
-      AArch64::AEK_FP16FML, AArch64::AEK_PROFILE,   AArch64::AEK_RAS,
-      AArch64::AEK_SVE,     AArch64::AEK_SVE2,      AArch64::AEK_SVE2AES,
-      AArch64::AEK_SVE2SM4, AArch64::AEK_SVE2SHA3,  AArch64::AEK_SVE2BITPERM,
-      AArch64::AEK_RCPC,    AArch64::AEK_RAND,      AArch64::AEK_MTE,
-      AArch64::AEK_SSBS,    AArch64::AEK_SB,        AArch64::AEK_PREDRES,
-      AArch64::AEK_BF16,    AArch64::AEK_I8MM,      AArch64::AEK_F32MM,
-      AArch64::AEK_F64MM,   AArch64::AEK_TME,       AArch64::AEK_LS64,
-      AArch64::AEK_BRBE,    AArch64::AEK_PAUTH,     AArch64::AEK_FLAGM,
-      AArch64::AEK_SME,     AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
-      AArch64::AEK_SME2,    AArch64::AEK_HBC,       AArch64::AEK_MOPS,
-      AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1,    AArch64::AEK_SME2p1,
-      AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
-      AArch64::AEK_RCPC3,   AArch64::AEK_THE,       AArch64::AEK_D128,
-      AArch64::AEK_LSE128,  AArch64::AEK_SPECRES2,  AArch64::AEK_RASv2,
-      AArch64::AEK_ITE,     AArch64::AEK_GCS,       AArch64::AEK_FPMR,
-      AArch64::AEK_FP8DOT2, AArch64::AEK_SSVE_FP8DOT2,
-      AArch64::AEK_FP8DOT4, AArch64::AEK_SSVE_FP8DOT4};
+      AArch64::AEK_CRC,          AArch64::AEK_LSE,
+      AArch64::AEK_RDM,          AArch64::AEK_CRYPTO,
+      AArch64::AEK_SM4,          AArch64::AEK_SHA3,
+      AArch64::AEK_SHA2,         AArch64::AEK_AES,
+      AArch64::AEK_DOTPROD,      AArch64::AEK_FP,
+      AArch64::AEK_SIMD,         AArch64::AEK_FP16,
+      AArch64::AEK_FP16FML,      AArch64::AEK_PROFILE,
+      AArch64::AEK_RAS,          AArch64::AEK_SVE,
+      AArch64::AEK_SVE2,         AArch64::AEK_SVE2AES,
+      AArch64::AEK_SVE2SM4,      AArch64::AEK_SVE2SHA3,
+      AArch64::AEK_SVE2BITPERM,  AArch64::AEK_RCPC,
+      AArch64::AEK_RAND,         AArch64::AEK_MTE,
+      AArch64::AEK_SSBS,         AArch64::AEK_SB,
+      AArch64::AEK_PREDRES,      AArch64::AEK_BF16,
+      AArch64::AEK_I8MM,         AArch64::AEK_F32MM,
+      AArch64::AEK_F64MM,        AArch64::AEK_TME,
+      AArch64::AEK_LS64,         AArch64::AEK_BRBE,
+      AArch64::AEK_PAUTH,        AArch64::AEK_FLAGM,
+      AArch64::AEK_SME,          AArch64::AEK_SMEF64F64,
+      AArch64::AEK_SMEI16I64,    AArch64::AEK_SME2,
+      AArch64::AEK_HBC,          AArch64::AEK_MOPS,
+      AArch64::AEK_PERFMON,      AArch64::AEK_SVE2p1,
+      AArch64::AEK_SME2p1,       AArch64::AEK_B16B16,
+      AArch64::AEK_SMEF16F16,    AArch64::AEK_CSSC,
+      AArch64::AEK_RCPC3,        AArch64::AEK_THE,
+      AArch64::AEK_D128,         AArch64::AEK_LSE128,
+      AArch64::AEK_SPECRES2,     AArch64::AEK_RASv2,
+      AArch64::AEK_ITE,          AArch64::AEK_GCS,
+      AArch64::AEK_FPMR,         AArch64::AEK_FP8DOT2,
+      AArch64::AEK_SSVE_FP8DOT2, AArch64::AEK_FP8DOT4,
+      AArch64::AEK_SSVE_FP8DOT4};
 
   std::vector<StringRef> Features;
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/70237


More information about the llvm-commits mailing list