[llvm] Reapply inline spiller subranges (PR #70194)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 25 04:00:15 PDT 2023
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/70194
Stack of patches to show the diff from the revert
>From 95e8f070f68aff9c43b9bbd975e5f17a2c60d1f7 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 3 Oct 2023 13:42:31 +0300
Subject: [PATCH 1/3] AMDGPU: Add infinite looping testcase after subrange
spilling change
This infinite looped after d8127b2ba8a87a610851b9a462f2fc2526c36e37
---
.../identical-subrange-spill-infloop.ll | 405 ++++++++++++++++++
.../CodeGen/AMDGPU/infloop-subrange-spill.mir | 143 +++++++
2 files changed, 548 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
diff --git a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
new file mode 100644
index 000000000000000..27fa6712f9eb429
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
@@ -0,0 +1,405 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck %s
+
+define void @main(i1 %arg) #0 {
+; CHECK-LABEL: main:
+; CHECK: ; %bb.0: ; %bb
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; CHECK-NEXT: s_mov_b64 exec, s[4:5]
+; CHECK-NEXT: v_writelane_b32 v1, s30, 0
+; CHECK-NEXT: v_writelane_b32 v1, s31, 1
+; CHECK-NEXT: v_writelane_b32 v1, s36, 2
+; CHECK-NEXT: v_writelane_b32 v1, s37, 3
+; CHECK-NEXT: v_writelane_b32 v1, s38, 4
+; CHECK-NEXT: v_writelane_b32 v1, s39, 5
+; CHECK-NEXT: v_writelane_b32 v1, s40, 6
+; CHECK-NEXT: v_writelane_b32 v1, s41, 7
+; CHECK-NEXT: v_writelane_b32 v1, s42, 8
+; CHECK-NEXT: v_writelane_b32 v1, s43, 9
+; CHECK-NEXT: v_writelane_b32 v1, s44, 10
+; CHECK-NEXT: v_writelane_b32 v1, s45, 11
+; CHECK-NEXT: v_writelane_b32 v1, s46, 12
+; CHECK-NEXT: v_writelane_b32 v1, s47, 13
+; CHECK-NEXT: v_writelane_b32 v1, s48, 14
+; CHECK-NEXT: v_writelane_b32 v1, s49, 15
+; CHECK-NEXT: s_getpc_b64 s[24:25]
+; CHECK-NEXT: v_writelane_b32 v1, s50, 16
+; CHECK-NEXT: s_movk_i32 s4, 0xf0
+; CHECK-NEXT: s_mov_b32 s5, s24
+; CHECK-NEXT: v_writelane_b32 v1, s51, 17
+; CHECK-NEXT: s_load_dwordx16 s[36:51], s[4:5], 0x0
+; CHECK-NEXT: ; implicit-def: $vgpr4 : SGPR spill to VGPR lane
+; CHECK-NEXT: s_mov_b64 s[4:5], 0
+; CHECK-NEXT: s_load_dwordx4 s[28:31], s[4:5], 0x0
+; CHECK-NEXT: s_movk_i32 s4, 0x130
+; CHECK-NEXT: s_mov_b32 s5, s24
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: v_writelane_b32 v4, s36, 0
+; CHECK-NEXT: v_writelane_b32 v4, s37, 1
+; CHECK-NEXT: v_writelane_b32 v4, s38, 2
+; CHECK-NEXT: v_writelane_b32 v4, s39, 3
+; CHECK-NEXT: v_writelane_b32 v4, s40, 4
+; CHECK-NEXT: v_writelane_b32 v4, s41, 5
+; CHECK-NEXT: v_writelane_b32 v4, s42, 6
+; CHECK-NEXT: v_writelane_b32 v4, s43, 7
+; CHECK-NEXT: v_writelane_b32 v4, s44, 8
+; CHECK-NEXT: v_writelane_b32 v4, s45, 9
+; CHECK-NEXT: v_writelane_b32 v4, s46, 10
+; CHECK-NEXT: s_load_dwordx16 s[4:19], s[4:5], 0x0
+; CHECK-NEXT: v_writelane_b32 v4, s47, 11
+; CHECK-NEXT: v_writelane_b32 v4, s48, 12
+; CHECK-NEXT: v_writelane_b32 v4, s49, 13
+; CHECK-NEXT: s_mov_b32 s20, 0
+; CHECK-NEXT: v_mov_b32_e32 v2, 0
+; CHECK-NEXT: v_writelane_b32 v4, s50, 14
+; CHECK-NEXT: v_mov_b32_e32 v5, s28
+; CHECK-NEXT: v_mov_b32_e32 v6, v2
+; CHECK-NEXT: s_mov_b32 s21, s20
+; CHECK-NEXT: s_mov_b32 s22, s20
+; CHECK-NEXT: s_mov_b32 s23, s20
+; CHECK-NEXT: v_writelane_b32 v4, s51, 15
+; CHECK-NEXT: v_mov_b32_e32 v3, v2
+; CHECK-NEXT: image_sample_lz v5, v[5:6], s[44:51], s[20:23] dmask:0x1
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: v_writelane_b32 v4, s4, 16
+; CHECK-NEXT: v_writelane_b32 v1, s52, 18
+; CHECK-NEXT: v_writelane_b32 v4, s5, 17
+; CHECK-NEXT: v_writelane_b32 v1, s53, 19
+; CHECK-NEXT: v_writelane_b32 v4, s6, 18
+; CHECK-NEXT: v_writelane_b32 v1, s54, 20
+; CHECK-NEXT: image_sample_lz v6, v[2:3], s[4:11], s[20:23] dmask:0x1
+; CHECK-NEXT: v_writelane_b32 v4, s7, 19
+; CHECK-NEXT: v_writelane_b32 v1, s55, 21
+; CHECK-NEXT: v_writelane_b32 v4, s8, 20
+; CHECK-NEXT: v_writelane_b32 v1, s56, 22
+; CHECK-NEXT: v_writelane_b32 v4, s9, 21
+; CHECK-NEXT: v_writelane_b32 v1, s57, 23
+; CHECK-NEXT: v_writelane_b32 v4, s10, 22
+; CHECK-NEXT: v_writelane_b32 v1, s58, 24
+; CHECK-NEXT: v_writelane_b32 v4, s11, 23
+; CHECK-NEXT: v_writelane_b32 v1, s59, 25
+; CHECK-NEXT: v_writelane_b32 v4, s12, 24
+; CHECK-NEXT: v_writelane_b32 v1, s60, 26
+; CHECK-NEXT: v_writelane_b32 v4, s13, 25
+; CHECK-NEXT: v_writelane_b32 v1, s61, 27
+; CHECK-NEXT: v_writelane_b32 v4, s14, 26
+; CHECK-NEXT: v_writelane_b32 v1, s62, 28
+; CHECK-NEXT: v_writelane_b32 v4, s15, 27
+; CHECK-NEXT: v_writelane_b32 v1, s63, 29
+; CHECK-NEXT: v_writelane_b32 v4, s16, 28
+; CHECK-NEXT: v_writelane_b32 v1, s64, 30
+; CHECK-NEXT: v_writelane_b32 v4, s17, 29
+; CHECK-NEXT: v_writelane_b32 v1, s65, 31
+; CHECK-NEXT: v_writelane_b32 v4, s18, 30
+; CHECK-NEXT: v_writelane_b32 v1, s66, 32
+; CHECK-NEXT: v_writelane_b32 v4, s19, 31
+; CHECK-NEXT: s_mov_b32 s4, 48
+; CHECK-NEXT: s_movk_i32 s28, 0x2f0
+; CHECK-NEXT: s_mov_b32 s5, s24
+; CHECK-NEXT: s_mov_b32 s29, s24
+; CHECK-NEXT: v_writelane_b32 v1, s67, 33
+; CHECK-NEXT: s_movk_i32 s26, 0x1f0
+; CHECK-NEXT: s_mov_b32 s27, s24
+; CHECK-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_load_dwordx16 s[36:51], s[26:27], 0x0
+; CHECK-NEXT: s_load_dwordx16 s[52:67], s[28:29], 0x0
+; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
+; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; CHECK-NEXT: s_xor_b64 s[24:25], vcc, -1
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_mul_f32_e32 v0, v6, v5
+; CHECK-NEXT: s_and_saveexec_b64 s[26:27], s[24:25]
+; CHECK-NEXT: s_xor_b64 s[26:27], exec, s[26:27]
+; CHECK-NEXT: s_cbranch_execz .LBB0_3
+; CHECK-NEXT: ; %bb.1: ; %bb48
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: v_writelane_b32 v4, s36, 32
+; CHECK-NEXT: v_writelane_b32 v4, s37, 33
+; CHECK-NEXT: v_writelane_b32 v4, s38, 34
+; CHECK-NEXT: v_writelane_b32 v4, s39, 35
+; CHECK-NEXT: v_writelane_b32 v4, s40, 36
+; CHECK-NEXT: v_writelane_b32 v4, s41, 37
+; CHECK-NEXT: v_writelane_b32 v4, s42, 38
+; CHECK-NEXT: v_writelane_b32 v4, s43, 39
+; CHECK-NEXT: v_writelane_b32 v4, s44, 40
+; CHECK-NEXT: v_writelane_b32 v4, s45, 41
+; CHECK-NEXT: v_writelane_b32 v4, s46, 42
+; CHECK-NEXT: v_writelane_b32 v4, s47, 43
+; CHECK-NEXT: v_writelane_b32 v4, s48, 44
+; CHECK-NEXT: v_writelane_b32 v4, s49, 45
+; CHECK-NEXT: v_writelane_b32 v4, s50, 46
+; CHECK-NEXT: v_writelane_b32 v4, s51, 47
+; CHECK-NEXT: v_readlane_b32 s36, v4, 0
+; CHECK-NEXT: v_readlane_b32 s44, v4, 8
+; CHECK-NEXT: v_readlane_b32 s45, v4, 9
+; CHECK-NEXT: v_readlane_b32 s46, v4, 10
+; CHECK-NEXT: v_readlane_b32 s47, v4, 11
+; CHECK-NEXT: v_readlane_b32 s48, v4, 12
+; CHECK-NEXT: v_readlane_b32 s49, v4, 13
+; CHECK-NEXT: v_readlane_b32 s50, v4, 14
+; CHECK-NEXT: v_readlane_b32 s51, v4, 15
+; CHECK-NEXT: v_readlane_b32 s37, v4, 1
+; CHECK-NEXT: v_readlane_b32 s38, v4, 2
+; CHECK-NEXT: v_readlane_b32 s39, v4, 3
+; CHECK-NEXT: v_readlane_b32 s40, v4, 4
+; CHECK-NEXT: v_readlane_b32 s41, v4, 5
+; CHECK-NEXT: image_sample_lz v5, v[2:3], s[44:51], s[20:23] dmask:0x1
+; CHECK-NEXT: v_readlane_b32 s42, v4, 6
+; CHECK-NEXT: v_readlane_b32 s43, v4, 7
+; CHECK-NEXT: v_readlane_b32 s36, v4, 32
+; CHECK-NEXT: v_readlane_b32 s37, v4, 33
+; CHECK-NEXT: v_readlane_b32 s38, v4, 34
+; CHECK-NEXT: v_readlane_b32 s39, v4, 35
+; CHECK-NEXT: v_readlane_b32 s40, v4, 36
+; CHECK-NEXT: v_readlane_b32 s41, v4, 37
+; CHECK-NEXT: v_readlane_b32 s42, v4, 38
+; CHECK-NEXT: v_readlane_b32 s43, v4, 39
+; CHECK-NEXT: v_readlane_b32 s44, v4, 40
+; CHECK-NEXT: v_readlane_b32 s45, v4, 41
+; CHECK-NEXT: v_readlane_b32 s46, v4, 42
+; CHECK-NEXT: v_readlane_b32 s47, v4, 43
+; CHECK-NEXT: v_readlane_b32 s48, v4, 44
+; CHECK-NEXT: v_readlane_b32 s49, v4, 45
+; CHECK-NEXT: v_readlane_b32 s50, v4, 46
+; CHECK-NEXT: v_readlane_b32 s51, v4, 47
+; CHECK-NEXT: v_mov_b32_e32 v3, 0
+; CHECK-NEXT: s_and_b64 vcc, exec, -1
+; CHECK-NEXT: .LBB0_2: ; %bb50
+; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: s_mov_b32 s21, s20
+; CHECK-NEXT: s_mov_b32 s22, s20
+; CHECK-NEXT: s_mov_b32 s23, s20
+; CHECK-NEXT: image_sample_lz v6, v[2:3], s[44:51], s[8:11] dmask:0x1
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: image_sample_lz v2, v[2:3], s[60:67], s[20:23] dmask:0x1
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_sub_f32_e32 v2, v2, v6
+; CHECK-NEXT: v_mul_f32_e32 v2, v2, v0
+; CHECK-NEXT: v_mul_f32_e32 v2, v2, v5
+; CHECK-NEXT: s_mov_b64 vcc, vcc
+; CHECK-NEXT: s_cbranch_vccnz .LBB0_2
+; CHECK-NEXT: .LBB0_3: ; %Flow14
+; CHECK-NEXT: s_andn2_saveexec_b64 s[28:29], s[26:27]
+; CHECK-NEXT: s_cbranch_execz .LBB0_10
+; CHECK-NEXT: ; %bb.4: ; %bb32
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: s_and_saveexec_b64 s[8:9], s[24:25]
+; CHECK-NEXT: s_xor_b64 vcc, exec, s[8:9]
+; CHECK-NEXT: s_cbranch_execz .LBB0_6
+; CHECK-NEXT: ; %bb.5: ; %bb43
+; CHECK-NEXT: s_mov_b32 s8, 0
+; CHECK-NEXT: s_mov_b64 s[12:13], s[36:37]
+; CHECK-NEXT: s_mov_b32 s9, s8
+; CHECK-NEXT: v_mov_b32_e32 v2, s8
+; CHECK-NEXT: s_mov_b64 s[14:15], s[38:39]
+; CHECK-NEXT: s_mov_b64 s[16:17], s[40:41]
+; CHECK-NEXT: s_mov_b64 s[18:19], s[42:43]
+; CHECK-NEXT: v_readlane_b32 s36, v4, 0
+; CHECK-NEXT: v_mov_b32_e32 v3, s9
+; CHECK-NEXT: s_mov_b32 s10, s8
+; CHECK-NEXT: s_mov_b32 s11, s8
+; CHECK-NEXT: v_readlane_b32 s37, v4, 1
+; CHECK-NEXT: v_readlane_b32 s38, v4, 2
+; CHECK-NEXT: v_readlane_b32 s39, v4, 3
+; CHECK-NEXT: v_readlane_b32 s40, v4, 4
+; CHECK-NEXT: v_readlane_b32 s41, v4, 5
+; CHECK-NEXT: v_readlane_b32 s42, v4, 6
+; CHECK-NEXT: v_readlane_b32 s43, v4, 7
+; CHECK-NEXT: v_mov_b32_e32 v6, 0
+; CHECK-NEXT: v_mov_b32_e32 v7, v6
+; CHECK-NEXT: v_readlane_b32 s44, v4, 8
+; CHECK-NEXT: v_readlane_b32 s45, v4, 9
+; CHECK-NEXT: v_readlane_b32 s46, v4, 10
+; CHECK-NEXT: image_sample_lz v5, v[2:3], s[36:43], s[8:11] dmask:0x1
+; CHECK-NEXT: s_mov_b64 s[42:43], s[18:19]
+; CHECK-NEXT: s_mov_b64 s[40:41], s[16:17]
+; CHECK-NEXT: s_mov_b64 s[38:39], s[14:15]
+; CHECK-NEXT: s_mov_b64 s[36:37], s[12:13]
+; CHECK-NEXT: v_readlane_b32 s12, v4, 16
+; CHECK-NEXT: v_readlane_b32 s20, v4, 24
+; CHECK-NEXT: v_readlane_b32 s21, v4, 25
+; CHECK-NEXT: v_readlane_b32 s22, v4, 26
+; CHECK-NEXT: v_readlane_b32 s23, v4, 27
+; CHECK-NEXT: v_readlane_b32 s24, v4, 28
+; CHECK-NEXT: v_readlane_b32 s25, v4, 29
+; CHECK-NEXT: v_readlane_b32 s26, v4, 30
+; CHECK-NEXT: v_readlane_b32 s27, v4, 31
+; CHECK-NEXT: v_readlane_b32 s47, v4, 11
+; CHECK-NEXT: v_readlane_b32 s48, v4, 12
+; CHECK-NEXT: v_readlane_b32 s49, v4, 13
+; CHECK-NEXT: v_readlane_b32 s50, v4, 14
+; CHECK-NEXT: v_readlane_b32 s51, v4, 15
+; CHECK-NEXT: image_sample_lz v2, v[2:3], s[20:27], s[4:7] dmask:0x1
+; CHECK-NEXT: v_readlane_b32 s13, v4, 17
+; CHECK-NEXT: v_readlane_b32 s14, v4, 18
+; CHECK-NEXT: v_readlane_b32 s15, v4, 19
+; CHECK-NEXT: v_readlane_b32 s16, v4, 20
+; CHECK-NEXT: v_readlane_b32 s17, v4, 21
+; CHECK-NEXT: v_readlane_b32 s18, v4, 22
+; CHECK-NEXT: v_readlane_b32 s19, v4, 23
+; CHECK-NEXT: ; implicit-def: $vgpr0
+; CHECK-NEXT: s_waitcnt vmcnt(1)
+; CHECK-NEXT: buffer_store_dwordx3 v[5:7], off, s[8:11], 0
+; CHECK-NEXT: s_waitcnt vmcnt(1)
+; CHECK-NEXT: buffer_store_dwordx4 v[2:5], off, s[8:11], 0
+; CHECK-NEXT: .LBB0_6: ; %Flow12
+; CHECK-NEXT: s_andn2_saveexec_b64 s[4:5], vcc
+; CHECK-NEXT: s_cbranch_execz .LBB0_9
+; CHECK-NEXT: ; %bb.7: ; %bb33.preheader
+; CHECK-NEXT: s_mov_b32 s8, 0
+; CHECK-NEXT: s_mov_b32 s6, s8
+; CHECK-NEXT: s_mov_b32 s7, s8
+; CHECK-NEXT: v_mov_b32_e32 v2, s6
+; CHECK-NEXT: s_mov_b32 s9, s8
+; CHECK-NEXT: s_mov_b32 s10, s8
+; CHECK-NEXT: s_mov_b32 s11, s8
+; CHECK-NEXT: v_mov_b32_e32 v3, s7
+; CHECK-NEXT: image_sample_lz v5, v[2:3], s[36:43], s[8:11] dmask:0x1
+; CHECK-NEXT: image_sample_lz v6, v[2:3], s[52:59], s[8:11] dmask:0x1
+; CHECK-NEXT: s_and_b64 vcc, exec, 0
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_sub_f32_e32 v2, v6, v5
+; CHECK-NEXT: v_mul_f32_e32 v0, v2, v0
+; CHECK-NEXT: v_mov_b32_e32 v2, 0
+; CHECK-NEXT: .LBB0_8: ; %bb33
+; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: v_add_f32_e32 v3, v2, v0
+; CHECK-NEXT: v_sub_f32_e32 v2, v2, v3
+; CHECK-NEXT: s_mov_b64 vcc, vcc
+; CHECK-NEXT: s_cbranch_vccz .LBB0_8
+; CHECK-NEXT: .LBB0_9: ; %Flow13
+; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
+; CHECK-NEXT: .LBB0_10: ; %UnifiedReturnBlock
+; CHECK-NEXT: s_or_b64 exec, exec, s[28:29]
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: v_readlane_b32 s67, v1, 33
+; CHECK-NEXT: v_readlane_b32 s66, v1, 32
+; CHECK-NEXT: v_readlane_b32 s65, v1, 31
+; CHECK-NEXT: v_readlane_b32 s64, v1, 30
+; CHECK-NEXT: v_readlane_b32 s63, v1, 29
+; CHECK-NEXT: v_readlane_b32 s62, v1, 28
+; CHECK-NEXT: v_readlane_b32 s61, v1, 27
+; CHECK-NEXT: v_readlane_b32 s60, v1, 26
+; CHECK-NEXT: v_readlane_b32 s59, v1, 25
+; CHECK-NEXT: v_readlane_b32 s58, v1, 24
+; CHECK-NEXT: v_readlane_b32 s57, v1, 23
+; CHECK-NEXT: v_readlane_b32 s56, v1, 22
+; CHECK-NEXT: v_readlane_b32 s55, v1, 21
+; CHECK-NEXT: v_readlane_b32 s54, v1, 20
+; CHECK-NEXT: v_readlane_b32 s53, v1, 19
+; CHECK-NEXT: v_readlane_b32 s52, v1, 18
+; CHECK-NEXT: v_readlane_b32 s51, v1, 17
+; CHECK-NEXT: v_readlane_b32 s50, v1, 16
+; CHECK-NEXT: v_readlane_b32 s49, v1, 15
+; CHECK-NEXT: v_readlane_b32 s48, v1, 14
+; CHECK-NEXT: v_readlane_b32 s47, v1, 13
+; CHECK-NEXT: v_readlane_b32 s46, v1, 12
+; CHECK-NEXT: v_readlane_b32 s45, v1, 11
+; CHECK-NEXT: v_readlane_b32 s44, v1, 10
+; CHECK-NEXT: v_readlane_b32 s43, v1, 9
+; CHECK-NEXT: v_readlane_b32 s42, v1, 8
+; CHECK-NEXT: v_readlane_b32 s41, v1, 7
+; CHECK-NEXT: v_readlane_b32 s40, v1, 6
+; CHECK-NEXT: v_readlane_b32 s39, v1, 5
+; CHECK-NEXT: v_readlane_b32 s38, v1, 4
+; CHECK-NEXT: v_readlane_b32 s37, v1, 3
+; CHECK-NEXT: v_readlane_b32 s36, v1, 2
+; CHECK-NEXT: v_readlane_b32 s31, v1, 1
+; CHECK-NEXT: v_readlane_b32 s30, v1, 0
+; CHECK-NEXT: ; kill: killed $vgpr4
+; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; CHECK-NEXT: s_mov_b64 exec, s[4:5]
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+bb:
+ %i = call i64 @llvm.amdgcn.s.getpc()
+ %i1 = trunc i64 %i to i32
+ %i2 = insertelement <2 x i32> zeroinitializer, i32 %i1, i64 1
+ %i3 = bitcast <2 x i32> %i2 to i64
+ %i4 = inttoptr i64 %i3 to ptr addrspace(4)
+ %i5 = getelementptr i8, ptr addrspace(4) %i4, i64 48
+ %i6 = load <4 x i32>, ptr addrspace(4) %i5, align 16
+ %i7 = getelementptr i8, ptr addrspace(4) %i4, i64 64
+ %i8 = load <4 x i32>, ptr addrspace(4) %i7, align 16
+ %i9 = getelementptr i8, ptr addrspace(4) %i4, i64 240
+ %i10 = load <8 x i32>, ptr addrspace(4) %i9, align 32
+ %i11 = getelementptr i8, ptr addrspace(4) %i4, i64 272
+ %i12 = load <8 x i32>, ptr addrspace(4) %i11, align 32
+ %i13 = getelementptr i8, ptr addrspace(4) %i4, i64 304
+ %i14 = load <8 x i32>, ptr addrspace(4) %i13, align 32
+ %i15 = getelementptr i8, ptr addrspace(4) %i4, i64 336
+ %i16 = load <8 x i32>, ptr addrspace(4) %i15, align 32
+ %i17 = getelementptr i8, ptr addrspace(4) %i4, i64 496
+ %i18 = load <8 x i32>, ptr addrspace(4) %i17, align 32
+ %i19 = getelementptr i8, ptr addrspace(4) %i4, i64 528
+ %i20 = load <8 x i32>, ptr addrspace(4) %i19, align 32
+ %i21 = getelementptr i8, ptr addrspace(4) %i4, i64 752
+ %i22 = load <8 x i32>, ptr addrspace(4) %i21, align 32
+ %i23 = getelementptr i8, ptr addrspace(4) %i4, i64 784
+ %i24 = load <8 x i32>, ptr addrspace(4) %i23, align 32
+ %i25 = load <4 x float>, ptr addrspace(4) null, align 16
+ %i26 = extractelement <4 x float> %i25, i64 0
+ %i27 = call float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32 1, float %i26, float 0.000000e+00, <8 x i32> %i12, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
+ %i28 = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i14, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
+ %i29 = extractelement <4 x float> %i28, i64 0
+ %i30 = fmul float %i29, %i27
+ %i31 = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i16, <4 x i32> %i6, i1 false, i32 0, i32 0)
+ br i1 %arg, label %bb32, label %bb48
+
+bb32: ; preds = %bb
+ br i1 %arg, label %bb33, label %bb43
+
+bb33: ; preds = %bb33, %bb32
+ %i34 = phi float [ %i42, %bb33 ], [ 0.000000e+00, %bb32 ]
+ %i35 = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i18, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
+ %i36 = extractelement <2 x float> %i35, i64 0
+ %i37 = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i22, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
+ %i38 = extractelement <2 x float> %i37, i64 0
+ %i39 = fsub float %i38, %i36
+ %i40 = fmul float %i39, %i30
+ %i41 = fadd float %i34, %i40
+ %i42 = fsub float %i34, %i41
+ br label %bb33
+
+bb43: ; preds = %bb32
+ %i44 = call float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i10, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
+ %i45 = bitcast float %i44 to i32
+ %i46 = insertelement <3 x i32> zeroinitializer, i32 %i45, i64 0
+ call void @llvm.amdgcn.raw.buffer.store.v3i32(<3 x i32> %i46, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0)
+ %i47 = bitcast <4 x float> %i31 to <4 x i32>
+ call void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32> %i47, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0)
+ ret void
+
+bb48: ; preds = %bb
+ %i49 = call float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i12, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
+ br label %bb50
+
+bb50: ; preds = %bb50, %bb48
+ %i51 = phi float [ 0.000000e+00, %bb48 ], [ %i58, %bb50 ]
+ %i52 = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 1, float %i51, float 0.000000e+00, <8 x i32> %i20, <4 x i32> %i8, i1 false, i32 0, i32 0)
+ %i53 = extractelement <2 x float> %i52, i64 0
+ %i54 = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 1, float %i51, float 0.000000e+00, <8 x i32> %i24, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
+ %i55 = extractelement <2 x float> %i54, i64 0
+ %i56 = fsub float %i55, %i53
+ %i57 = fmul float %i56, %i30
+ %i58 = fmul float %i57, %i49
+ br label %bb50
+}
+
+declare i64 @llvm.amdgcn.s.getpc() #1
+declare <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #2
+declare float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #2
+declare <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #2
+declare void @llvm.amdgcn.raw.buffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32 immarg) #3
+declare void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32 immarg) #3
+
+attributes #0 = { "amdgpu-waves-per-eu"="10,10" }
+attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+attributes #2 = { nocallback nofree nosync nounwind willreturn memory(read) }
+attributes #3 = { nocallback nofree nosync nounwind willreturn memory(write) }
diff --git a/llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir b/llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
new file mode 100644
index 000000000000000..88d08146e91b013
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
@@ -0,0 +1,143 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-before=greedy,0 -stop-after=virtregrewriter,0 -simplify-mir -o - %s | FileCheck %s
+--- |
+ define void @main() #0 {
+ ret void
+ }
+
+ attributes #0 = { "amdgpu-waves-per-eu"="10,10" }
+
+...
+---
+name: main
+tracksRegLiveness: true
+machineFunctionInfo:
+ scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
+ frameOffsetReg: '$sgpr33'
+ stackPtrOffsetReg: '$sgpr32'
+ sgprForEXECCopy: '$sgpr58_sgpr59'
+body: |
+ ; CHECK-LABEL: name: main
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: dead renamable $sgpr5 = IMPLICIT_DEF
+ ; CHECK-NEXT: dead undef [[DEF:%[0-9]+]].sub0:vreg_64 = IMPLICIT_DEF
+ ; CHECK-NEXT: dead renamable $sgpr5 = IMPLICIT_DEF
+ ; CHECK-NEXT: dead [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: dead undef [[DEF2:%[0-9]+]].sub0:vreg_64 = IMPLICIT_DEF
+ ; CHECK-NEXT: dead renamable $sgpr5 = IMPLICIT_DEF
+ ; CHECK-NEXT: dead undef [[DEF3:%[0-9]+]].sub1:vreg_64 = IMPLICIT_DEF
+ ; CHECK-NEXT: dead renamable $sgpr5 = IMPLICIT_DEF
+ ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = S_LOAD_DWORDX16_IMM undef renamable $sgpr4_sgpr5, 0, 0 :: (invariant load (s512), align 32, addrspace 4)
+ ; CHECK-NEXT: renamable $sgpr24 = IMPLICIT_DEF
+ ; CHECK-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = S_LOAD_DWORDX16_IMM undef renamable $sgpr4_sgpr5, 0, 0 :: (invariant load (s512), align 32, addrspace 4)
+ ; CHECK-NEXT: $exec = S_MOV_B64_term undef renamable $sgpr4_sgpr5
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x000000000000FFFF
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_MOV_B64_term undef renamable $sgpr4_sgpr5
+ ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.3, implicit $exec
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x000000000000FFFF
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: dead [[IMAGE_SAMPLE_LZ_V1_V2_:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF3]], killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43, undef renamable $sgpr24_sgpr25_sgpr26_sgpr27, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
+ ; CHECK-NEXT: dead [[IMAGE_SAMPLE_LZ_V1_V2_1:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF3]], killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, renamable $sgpr24_sgpr25_sgpr26_sgpr27, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
+ ; CHECK-NEXT: SI_RETURN
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x000000000000FFFF
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr12 = IMPLICIT_DEF
+ ; CHECK-NEXT: SI_SPILL_S512_SAVE renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s512) into %stack.0, align 4, addrspace 5)
+ ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = IMPLICIT_DEF
+ ; CHECK-NEXT: dead undef [[IMAGE_SAMPLE_LZ_V1_V2_2:%[0-9]+]].sub0:vreg_96 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF3]], killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43, renamable $sgpr12_sgpr13_sgpr14_sgpr15, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
+ ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = SI_SPILL_S512_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s512) from %stack.0, align 4, addrspace 5)
+ ; CHECK-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = IMPLICIT_DEF
+ ; CHECK-NEXT: dead undef [[IMAGE_SAMPLE_LZ_V1_V2_3:%[0-9]+]].sub0:vreg_128 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF3]], undef renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, killed renamable $sgpr12_sgpr13_sgpr14_sgpr15, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
+ ; CHECK-NEXT: S_BRANCH %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4:
+ ; CHECK-NEXT: liveins: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x00000000FFFFFFFF
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 = COPY killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
+ ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = IMPLICIT_DEF
+ ; CHECK-NEXT: dead [[IMAGE_SAMPLE_LZ_V1_V2_4:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF]], killed renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, undef renamable $sgpr24_sgpr25_sgpr26_sgpr27, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
+ ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = COPY killed renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27
+ ; CHECK-NEXT: S_BRANCH %bb.6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5:
+ ; CHECK-NEXT: liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x000000000000FFFF
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, undef renamable $sgpr4_sgpr5, implicit-def $scc
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.7, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6:
+ ; CHECK-NEXT: liveins: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x00000000FFFFFFFF
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: dead [[IMAGE_SAMPLE_LZ_V1_V2_5:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF]], renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, undef renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
+ ; CHECK-NEXT: renamable $sgpr25 = COPY undef renamable $sgpr24
+ ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.6, implicit undef $vcc
+ ; CHECK-NEXT: S_BRANCH %bb.5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7:
+ ; CHECK-NEXT: SI_RETURN
+ bb.0:
+ liveins: $vgpr0
+
+ undef %0.sub1:sreg_64 = IMPLICIT_DEF
+ %1:sgpr_512 = IMPLICIT_DEF
+ undef %2.sub0:vreg_64 = IMPLICIT_DEF
+ %3:sgpr_256 = IMPLICIT_DEF
+ undef %4.sub1:sgpr_64 = IMPLICIT_DEF
+ %5:vgpr_32 = IMPLICIT_DEF
+ undef %6.sub0:vreg_64 = IMPLICIT_DEF
+ undef %7.sub1:sreg_64 = IMPLICIT_DEF
+ undef %8.sub1:vreg_64 = IMPLICIT_DEF
+ undef %9.sub1:sreg_64 = IMPLICIT_DEF
+ %10:sgpr_512 = S_LOAD_DWORDX16_IMM undef %0, 0, 0 :: (invariant load (s512), align 32, addrspace 4)
+ undef %11.sub0:sgpr_128 = IMPLICIT_DEF
+ %12:sgpr_512 = S_LOAD_DWORDX16_IMM undef %7, 0, 0 :: (invariant load (s512), align 32, addrspace 4)
+ $exec = S_MOV_B64_term undef %9
+ S_CBRANCH_EXECZ %bb.5, implicit $exec
+ S_BRANCH %bb.4
+
+ bb.1:
+ $exec = S_MOV_B64_term undef %9
+ S_CBRANCH_EXECNZ %bb.3, implicit $exec
+
+ bb.2:
+ %13:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %8, %10.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, undef %11, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
+ %14:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %8, %12.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, %11, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
+ SI_RETURN
+
+ bb.3:
+ undef %15.sub0:sgpr_128 = IMPLICIT_DEF
+ undef %16.sub0:vreg_96 = IMAGE_SAMPLE_LZ_V1_V2 undef %8, %1.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, %15, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
+ undef %17.sub0:vreg_128 = IMAGE_SAMPLE_LZ_V1_V2 undef %8, undef %10.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, %3.sub0_sub1_sub2_sub3, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
+ S_BRANCH %bb.2
+
+ bb.4:
+ %18:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %2, %1.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, undef %11, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
+ S_BRANCH %bb.6
+
+ bb.5:
+ $exec = S_XOR_B64_term $exec, undef %9, implicit-def $scc
+ S_CBRANCH_EXECZ %bb.7, implicit $exec
+ S_BRANCH %bb.1
+
+ bb.6:
+ %19:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %2, %10.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, undef %3.sub4_sub5_sub6_sub7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)
+ undef %11.sub1:sgpr_128 = COPY undef %11.sub0
+ S_CBRANCH_VCCNZ %bb.6, implicit undef $vcc
+ S_BRANCH %bb.5
+
+ bb.7:
+ SI_RETURN
+
+...
>From f1a735754d2e93036a13ffc1145494c01eaeeeaf Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Mon, 2 Oct 2023 15:17:17 +0300
Subject: [PATCH 2/3] Reapply "InlineSpiller: Consider if all subranges are the
same when avoiding redundant spills"
This reverts commit e816c89c8406670e516c1b20af586358748bf77e.
---
llvm/lib/CodeGen/InlineSpiller.cpp | 33 +-
.../AMDGPU/av_spill_cross_bb_usage.mir | 16 +-
.../CodeGen/AMDGPU/spill-scavenge-offset.ll | 392 ++++++++----------
llvm/test/CodeGen/AMDGPU/swdev380865.ll | 97 ++---
.../CodeGen/Hexagon/regalloc-bad-undef.mir | 4 +-
llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll | 42 +-
llvm/test/CodeGen/Thumb2/mve-vst3.ll | 57 ++-
7 files changed, 299 insertions(+), 342 deletions(-)
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index 46fcc62e09e8a8c..da80addcc31331c 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -495,6 +495,31 @@ bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI,
return true;
}
+/// Check if all subranges in \p LI and \p SLI have the same value number at \p
+/// Idx.
+static bool allSubRangeValNoSame(const LiveInterval &LI,
+ const LiveInterval &SLI,
+ const MachineInstr &MI,
+ const MachineRegisterInfo &MRI,
+ const TargetRegisterInfo &TRI, SlotIndex Idx) {
+ for (auto &SR : SLI.subranges()) {
+ VNInfo *SubVNI = SR.getVNInfoAt(Idx);
+
+ for (auto &SubLI : LI.subranges()) {
+ if (SubLI.LaneMask == SR.LaneMask) {
+ if (SubVNI != SubLI.getVNInfoAt(Idx))
+ return false;
+ } else if ((SubLI.LaneMask & SR.LaneMask).any()) {
+ // TODO: Check non-exact, overlapping subranges if they share the same
+ // def instruction
+ return false;
+ }
+ }
+ }
+
+ return true;
+}
+
/// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any
/// redundant spills of this value in SLI.reg and sibling copies.
void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
@@ -524,7 +549,13 @@ void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
if (!MI.mayStore() && !TII.isCopyInstr(MI))
continue;
SlotIndex Idx = LIS.getInstructionIndex(MI);
- if (LI->getVNInfoAt(Idx) != VNI)
+
+ // The main range value numbers will differ if multiple instructions are
+ // used to define its various subregisters. Check the subregister value
+ // numbers as a fallback.
+ if (LI->getVNInfoAt(Idx) != VNI &&
+ (!SLI.hasSubRanges() ||
+ !allSubRangeValNoSame(*LI, SLI, MI, MRI, TRI, Idx)))
continue;
// Follow sibling copies down the dominator tree.
diff --git a/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir b/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
index 7209d160e6c8a7a..857784282528bc7 100644
--- a/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
+++ b/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
@@ -47,7 +47,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.2(0x80000000)
- ; GCN-NEXT: liveins: $exec:0x000000000000000F, $sgpr30, $sgpr31, $vgpr0:0x0000000000000003, $vgpr1:0x0000000000000003, $vgpr2:0x0000000000000003, $vgpr3:0x0000000000000003, $vgpr4:0x0000000000000003, $vgpr5:0x0000000000000003, $vgpr6:0x0000000000000003, $vgpr7:0x0000000000000003, $vgpr8:0x0000000000000003, $vgpr9:0x0000000000000003, $vgpr40, $sgpr30_sgpr31, $vgpr10_vgpr11:0x000000000000000F, $vgpr14_vgpr15:0x000000000000000F, $vgpr41_vgpr42:0x000000000000000F, $vgpr43_vgpr44:0x000000000000000F, $vgpr45_vgpr46:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F
+ ; GCN-NEXT: liveins: $exec:0x000000000000000F, $sgpr30, $sgpr31, $vgpr0:0x0000000000000003, $vgpr1:0x0000000000000003, $vgpr2:0x0000000000000003, $vgpr3:0x0000000000000003, $vgpr4:0x0000000000000003, $vgpr5:0x0000000000000003, $vgpr6:0x0000000000000003, $vgpr7:0x0000000000000003, $vgpr8:0x0000000000000003, $vgpr9:0x0000000000000003, $vgpr40, $sgpr30_sgpr31, $vgpr10_vgpr11:0x000000000000000F, $vgpr41_vgpr42:0x000000000000000F, $vgpr43_vgpr44:0x000000000000000F, $vgpr45_vgpr46:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x000000000000000F, $vgpr60_vgpr61:0x000000000000000F
; GCN-NEXT: {{ $}}
; GCN-NEXT: renamable $vgpr57 = COPY $vgpr9, implicit $exec
; GCN-NEXT: renamable $vgpr56 = COPY $vgpr8, implicit $exec
@@ -62,17 +62,15 @@ body: |
; GCN-NEXT: renamable $sgpr16_sgpr17 = IMPLICIT_DEF
; GCN-NEXT: $vgpr40 = V_WRITELANE_B32 $sgpr30, 0, $vgpr40, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
; GCN-NEXT: $vgpr40 = V_WRITELANE_B32 $sgpr31, 1, $vgpr40, implicit $sgpr30_sgpr31
- ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec, implicit-def $vgpr14_vgpr15, implicit $vgpr14_vgpr15 :: (store (s32) into %stack.1, addrspace 5)
- ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec, implicit killed $vgpr14_vgpr15 :: (store (s32) into %stack.1 + 4, addrspace 5)
- ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit-def $vgpr10_vgpr11, implicit $vgpr10_vgpr11 :: (store (s32) into %stack.2, addrspace 5)
- ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec, implicit killed $vgpr10_vgpr11 :: (store (s32) into %stack.2 + 4, addrspace 5)
+ ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec, implicit-def $vgpr10_vgpr11, implicit $vgpr10_vgpr11 :: (store (s32) into %stack.1, addrspace 5)
+ ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec, implicit killed $vgpr10_vgpr11 :: (store (s32) into %stack.1 + 4, addrspace 5)
; GCN-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr16_sgpr17, 0, csr_amdgpu, implicit-def dead $vgpr0
- ; GCN-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec, implicit-def $vgpr14_vgpr15 :: (load (s32) from %stack.1, addrspace 5)
- ; GCN-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec, implicit-def $vgpr14_vgpr15 :: (load (s32) from %stack.1 + 4, addrspace 5)
+ ; GCN-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit-def $vgpr14_vgpr15 :: (load (s32) from %stack.2, addrspace 5)
+ ; GCN-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec, implicit-def $vgpr14_vgpr15 :: (load (s32) from %stack.2 + 4, addrspace 5)
; GCN-NEXT: renamable $vgpr0_vgpr1 = nofpexcept V_FMA_F64_e64 0, killed $vgpr45_vgpr46, 0, killed $vgpr41_vgpr42, 0, killed $vgpr60_vgpr61, 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: FLAT_STORE_DWORDX2 killed renamable $vgpr58_vgpr59, killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
- ; GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.2, addrspace 5)
- ; GCN-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.2 + 4, addrspace 5)
+ ; GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.1, addrspace 5)
+ ; GCN-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.1 + 4, addrspace 5)
; GCN-NEXT: FLAT_STORE_DWORDX2 killed renamable $vgpr0_vgpr1, killed renamable $vgpr56_vgpr57, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
diff --git a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
index 08db1e7fee259d6..9955aca981518df 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
@@ -10093,7 +10093,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: v_mov_b32_e32 v8, v6
; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[7:8], s[4:7], 0 addr64 offset:240
; GFX6-NEXT: s_addc_u32 s41, s41, 0
-; GFX6-NEXT: s_mov_b32 s2, 0x83800
+; GFX6-NEXT: s_mov_b32 s2, 0x83c00
; GFX6-NEXT: s_mov_b64 s[8:9], exec
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
@@ -10103,7 +10103,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[7:8], s[4:7], 0 addr64 offset:224
-; GFX6-NEXT: s_mov_b32 s2, 0x83400
+; GFX6-NEXT: s_mov_b32 s2, 0x83800
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -10112,7 +10112,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[7:8], s[4:7], 0 addr64 offset:208
-; GFX6-NEXT: s_mov_b32 s2, 0x83000
+; GFX6-NEXT: s_mov_b32 s2, 0x83400
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -10121,7 +10121,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[7:8], s[4:7], 0 addr64 offset:192
-; GFX6-NEXT: s_mov_b32 s2, 0x82c00
+; GFX6-NEXT: s_mov_b32 s2, 0x83000
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -10130,7 +10130,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[7:8], s[4:7], 0 addr64 offset:176
-; GFX6-NEXT: s_mov_b32 s2, 0x82800
+; GFX6-NEXT: s_mov_b32 s2, 0x82c00
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -10139,7 +10139,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[7:8], s[4:7], 0 addr64 offset:160
-; GFX6-NEXT: s_mov_b32 s2, 0x82400
+; GFX6-NEXT: s_mov_b32 s2, 0x82800
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -10148,7 +10148,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[7:8], s[4:7], 0 addr64 offset:144
-; GFX6-NEXT: s_mov_b32 s2, 0x82000
+; GFX6-NEXT: s_mov_b32 s2, 0x82400
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -10157,7 +10157,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[7:8], s[4:7], 0 addr64 offset:128
-; GFX6-NEXT: s_mov_b32 s2, 0x81c00
+; GFX6-NEXT: s_mov_b32 s2, 0x82000
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -10166,7 +10166,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[7:8], s[4:7], 0 addr64 offset:112
-; GFX6-NEXT: s_mov_b32 s2, 0x81800
+; GFX6-NEXT: s_mov_b32 s2, 0x81c00
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -10175,7 +10175,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[7:8], s[4:7], 0 addr64 offset:96
-; GFX6-NEXT: s_mov_b32 s2, 0x81400
+; GFX6-NEXT: s_mov_b32 s2, 0x81800
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -10184,7 +10184,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dwordx4 v[0:3], v[7:8], s[4:7], 0 addr64 offset:80
-; GFX6-NEXT: s_mov_b32 s2, 0x81000
+; GFX6-NEXT: s_mov_b32 s2, 0x81400
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -10218,7 +10218,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_mov_b64 exec, s[8:9]
; GFX6-NEXT: buffer_load_dwordx4 v[7:10], v[7:8], s[4:7], 0 addr64 offset:48
-; GFX6-NEXT: s_mov_b32 s2, 0x80c00
+; GFX6-NEXT: s_mov_b32 s2, 0x81000
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 13, v0
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 16, v4
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -10245,7 +10245,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: v_writelane_b32 v4, s9, 5
; GFX6-NEXT: v_writelane_b32 v4, s10, 6
; GFX6-NEXT: v_writelane_b32 v4, s11, 7
-; GFX6-NEXT: s_mov_b32 s12, 0x83c00
+; GFX6-NEXT: s_mov_b32 s12, 0x84000
; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], s12 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
@@ -10273,197 +10273,183 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: s_and_saveexec_b64 s[34:35], vcc
; GFX6-NEXT: s_cbranch_execz .LBB1_2
; GFX6-NEXT: ; %bb.1: ; %bb0
-; GFX6-NEXT: s_mov_b64 s[36:37], exec
+; GFX6-NEXT: s_mov_b64 s[0:1], exec
; GFX6-NEXT: s_mov_b64 exec, 0xff
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_writelane_b32 v4, s8, 0
-; GFX6-NEXT: v_writelane_b32 v4, s9, 1
-; GFX6-NEXT: v_writelane_b32 v4, s10, 2
-; GFX6-NEXT: v_writelane_b32 v4, s11, 3
-; GFX6-NEXT: v_writelane_b32 v4, s12, 4
-; GFX6-NEXT: v_writelane_b32 v4, s13, 5
-; GFX6-NEXT: v_writelane_b32 v4, s14, 6
-; GFX6-NEXT: v_writelane_b32 v4, s15, 7
-; GFX6-NEXT: s_mov_b32 s38, 0x84400
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], s38 ; 4-byte Folded Spill
+; GFX6-NEXT: v_writelane_b32 v0, s8, 0
+; GFX6-NEXT: v_writelane_b32 v0, s9, 1
+; GFX6-NEXT: v_writelane_b32 v0, s10, 2
+; GFX6-NEXT: v_writelane_b32 v0, s11, 3
+; GFX6-NEXT: v_writelane_b32 v0, s12, 4
+; GFX6-NEXT: v_writelane_b32 v0, s13, 5
+; GFX6-NEXT: v_writelane_b32 v0, s14, 6
+; GFX6-NEXT: v_writelane_b32 v0, s15, 7
+; GFX6-NEXT: s_mov_b32 s36, 0x80800
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s36 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: s_mov_b64 exec, s[36:37]
-; GFX6-NEXT: s_mov_b64 s[36:37], exec
+; GFX6-NEXT: s_mov_b64 exec, s[0:1]
+; GFX6-NEXT: s_mov_b64 s[0:1], exec
; GFX6-NEXT: s_mov_b64 exec, 0xff
-; GFX6-NEXT: s_mov_b32 s38, 0x83c00
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
+; GFX6-NEXT: s_mov_b32 s36, 0x84000
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], s38 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], s36 ; 4-byte Folded Reload
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: v_readlane_b32 s8, v4, 0
-; GFX6-NEXT: v_readlane_b32 s9, v4, 1
-; GFX6-NEXT: v_readlane_b32 s10, v4, 2
-; GFX6-NEXT: v_readlane_b32 s11, v4, 3
-; GFX6-NEXT: v_readlane_b32 s12, v4, 4
-; GFX6-NEXT: v_readlane_b32 s13, v4, 5
-; GFX6-NEXT: v_readlane_b32 s14, v4, 6
-; GFX6-NEXT: v_readlane_b32 s15, v4, 7
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
+; GFX6-NEXT: v_readlane_b32 s8, v0, 0
+; GFX6-NEXT: v_readlane_b32 s9, v0, 1
+; GFX6-NEXT: v_readlane_b32 s10, v0, 2
+; GFX6-NEXT: v_readlane_b32 s11, v0, 3
+; GFX6-NEXT: v_readlane_b32 s12, v0, 4
+; GFX6-NEXT: v_readlane_b32 s13, v0, 5
+; GFX6-NEXT: v_readlane_b32 s14, v0, 6
+; GFX6-NEXT: v_readlane_b32 s15, v0, 7
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: s_mov_b64 exec, s[36:37]
-; GFX6-NEXT: s_mov_b64 s[36:37], exec
+; GFX6-NEXT: s_mov_b64 exec, s[0:1]
+; GFX6-NEXT: s_mov_b64 s[0:1], exec
; GFX6-NEXT: s_mov_b64 exec, 0xff
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_writelane_b32 v4, s16, 0
-; GFX6-NEXT: v_writelane_b32 v4, s17, 1
-; GFX6-NEXT: v_writelane_b32 v4, s18, 2
-; GFX6-NEXT: v_writelane_b32 v4, s19, 3
-; GFX6-NEXT: v_writelane_b32 v4, s20, 4
-; GFX6-NEXT: v_writelane_b32 v4, s21, 5
-; GFX6-NEXT: v_writelane_b32 v4, s22, 6
-; GFX6-NEXT: v_writelane_b32 v4, s23, 7
-; GFX6-NEXT: s_mov_b32 s38, 0x84c00
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], s38 ; 4-byte Folded Spill
+; GFX6-NEXT: v_writelane_b32 v0, s16, 0
+; GFX6-NEXT: v_writelane_b32 v0, s17, 1
+; GFX6-NEXT: v_writelane_b32 v0, s18, 2
+; GFX6-NEXT: v_writelane_b32 v0, s19, 3
+; GFX6-NEXT: v_writelane_b32 v0, s20, 4
+; GFX6-NEXT: v_writelane_b32 v0, s21, 5
+; GFX6-NEXT: v_writelane_b32 v0, s22, 6
+; GFX6-NEXT: v_writelane_b32 v0, s23, 7
+; GFX6-NEXT: s_mov_b32 s36, 0x84800
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s36 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: s_mov_b64 exec, s[36:37]
-; GFX6-NEXT: s_mov_b64 s[36:37], exec
+; GFX6-NEXT: s_mov_b64 exec, s[0:1]
+; GFX6-NEXT: s_mov_b64 s[0:1], exec
; GFX6-NEXT: s_mov_b64 exec, 0xff
-; GFX6-NEXT: s_mov_b32 s38, 0x84400
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
+; GFX6-NEXT: s_mov_b32 s36, 0x80800
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], s38 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], s36 ; 4-byte Folded Reload
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: v_readlane_b32 s16, v4, 0
-; GFX6-NEXT: v_readlane_b32 s17, v4, 1
-; GFX6-NEXT: v_readlane_b32 s18, v4, 2
-; GFX6-NEXT: v_readlane_b32 s19, v4, 3
-; GFX6-NEXT: v_readlane_b32 s20, v4, 4
-; GFX6-NEXT: v_readlane_b32 s21, v4, 5
-; GFX6-NEXT: v_readlane_b32 s22, v4, 6
-; GFX6-NEXT: v_readlane_b32 s23, v4, 7
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
+; GFX6-NEXT: v_readlane_b32 s16, v0, 0
+; GFX6-NEXT: v_readlane_b32 s17, v0, 1
+; GFX6-NEXT: v_readlane_b32 s18, v0, 2
+; GFX6-NEXT: v_readlane_b32 s19, v0, 3
+; GFX6-NEXT: v_readlane_b32 s20, v0, 4
+; GFX6-NEXT: v_readlane_b32 s21, v0, 5
+; GFX6-NEXT: v_readlane_b32 s22, v0, 6
+; GFX6-NEXT: v_readlane_b32 s23, v0, 7
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: s_mov_b64 exec, s[36:37]
-; GFX6-NEXT: s_mov_b64 s[36:37], exec
+; GFX6-NEXT: s_mov_b64 exec, s[0:1]
+; GFX6-NEXT: s_mov_b64 s[0:1], exec
; GFX6-NEXT: s_mov_b64 exec, 0xff
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_writelane_b32 v4, s24, 0
-; GFX6-NEXT: v_writelane_b32 v4, s25, 1
-; GFX6-NEXT: v_writelane_b32 v4, s26, 2
-; GFX6-NEXT: v_writelane_b32 v4, s27, 3
-; GFX6-NEXT: v_writelane_b32 v4, s28, 4
-; GFX6-NEXT: v_writelane_b32 v4, s29, 5
-; GFX6-NEXT: v_writelane_b32 v4, s30, 6
-; GFX6-NEXT: v_writelane_b32 v4, s31, 7
-; GFX6-NEXT: s_mov_b32 s38, 0x85400
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], s38 ; 4-byte Folded Spill
+; GFX6-NEXT: v_writelane_b32 v0, s24, 0
+; GFX6-NEXT: v_writelane_b32 v0, s25, 1
+; GFX6-NEXT: v_writelane_b32 v0, s26, 2
+; GFX6-NEXT: v_writelane_b32 v0, s27, 3
+; GFX6-NEXT: v_writelane_b32 v0, s28, 4
+; GFX6-NEXT: v_writelane_b32 v0, s29, 5
+; GFX6-NEXT: v_writelane_b32 v0, s30, 6
+; GFX6-NEXT: v_writelane_b32 v0, s31, 7
+; GFX6-NEXT: s_mov_b32 s36, 0x85000
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s36 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: s_mov_b64 exec, s[36:37]
-; GFX6-NEXT: s_mov_b64 s[36:37], exec
+; GFX6-NEXT: s_mov_b64 exec, s[0:1]
+; GFX6-NEXT: s_mov_b64 s[0:1], exec
; GFX6-NEXT: s_mov_b64 exec, 0xff
-; GFX6-NEXT: s_mov_b32 s38, 0x84c00
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
+; GFX6-NEXT: s_mov_b32 s36, 0x84800
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], s38 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], s36 ; 4-byte Folded Reload
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: v_readlane_b32 s24, v4, 0
-; GFX6-NEXT: v_readlane_b32 s25, v4, 1
-; GFX6-NEXT: v_readlane_b32 s26, v4, 2
-; GFX6-NEXT: v_readlane_b32 s27, v4, 3
-; GFX6-NEXT: v_readlane_b32 s28, v4, 4
-; GFX6-NEXT: v_readlane_b32 s29, v4, 5
-; GFX6-NEXT: v_readlane_b32 s30, v4, 6
-; GFX6-NEXT: v_readlane_b32 s31, v4, 7
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
+; GFX6-NEXT: v_readlane_b32 s24, v0, 0
+; GFX6-NEXT: v_readlane_b32 s25, v0, 1
+; GFX6-NEXT: v_readlane_b32 s26, v0, 2
+; GFX6-NEXT: v_readlane_b32 s27, v0, 3
+; GFX6-NEXT: v_readlane_b32 s28, v0, 4
+; GFX6-NEXT: v_readlane_b32 s29, v0, 5
+; GFX6-NEXT: v_readlane_b32 s30, v0, 6
+; GFX6-NEXT: v_readlane_b32 s31, v0, 7
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: s_mov_b64 exec, s[36:37]
-; GFX6-NEXT: s_mov_b64 s[36:37], exec
-; GFX6-NEXT: s_mov_b64 exec, 15
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
-; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_writelane_b32 v4, s0, 0
-; GFX6-NEXT: v_writelane_b32 v4, s1, 1
-; GFX6-NEXT: v_writelane_b32 v4, s2, 2
-; GFX6-NEXT: v_writelane_b32 v4, s3, 3
-; GFX6-NEXT: s_mov_b32 s38, 0x85c00
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], s38 ; 4-byte Folded Spill
-; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
-; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: s_mov_b64 exec, s[36:37]
+; GFX6-NEXT: s_mov_b64 exec, s[0:1]
; GFX6-NEXT: s_mov_b64 s[0:1], exec
; GFX6-NEXT: s_mov_b64 exec, 15
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_writelane_b32 v4, s4, 0
-; GFX6-NEXT: v_writelane_b32 v4, s5, 1
-; GFX6-NEXT: v_writelane_b32 v4, s6, 2
-; GFX6-NEXT: v_writelane_b32 v4, s7, 3
-; GFX6-NEXT: s_mov_b32 s36, 0x86000
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], s36 ; 4-byte Folded Spill
+; GFX6-NEXT: v_writelane_b32 v0, s4, 0
+; GFX6-NEXT: v_writelane_b32 v0, s5, 1
+; GFX6-NEXT: v_writelane_b32 v0, s6, 2
+; GFX6-NEXT: v_writelane_b32 v0, s7, 3
+; GFX6-NEXT: s_mov_b32 s36, 0x85800
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s36 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_mov_b64 exec, s[0:1]
; GFX6-NEXT: s_mov_b64 s[0:1], exec
; GFX6-NEXT: s_mov_b64 exec, 3
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_writelane_b32 v4, s2, 0
-; GFX6-NEXT: v_writelane_b32 v4, s3, 1
-; GFX6-NEXT: s_mov_b32 s4, 0x86400
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], s4 ; 4-byte Folded Spill
+; GFX6-NEXT: v_writelane_b32 v0, s2, 0
+; GFX6-NEXT: v_writelane_b32 v0, s3, 1
+; GFX6-NEXT: s_mov_b32 s4, 0x85c00
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s4 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_mov_b64 exec, s[0:1]
; GFX6-NEXT: s_mov_b64 s[36:37], exec
; GFX6-NEXT: s_mov_b64 exec, 0xff
-; GFX6-NEXT: s_mov_b32 s38, 0x85400
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
+; GFX6-NEXT: s_mov_b32 s38, 0x85000
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], s38 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], s38 ; 4-byte Folded Reload
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: v_readlane_b32 s0, v4, 0
-; GFX6-NEXT: v_readlane_b32 s1, v4, 1
-; GFX6-NEXT: v_readlane_b32 s2, v4, 2
-; GFX6-NEXT: v_readlane_b32 s3, v4, 3
-; GFX6-NEXT: v_readlane_b32 s4, v4, 4
-; GFX6-NEXT: v_readlane_b32 s5, v4, 5
-; GFX6-NEXT: v_readlane_b32 s6, v4, 6
-; GFX6-NEXT: v_readlane_b32 s7, v4, 7
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
+; GFX6-NEXT: v_readlane_b32 s0, v0, 0
+; GFX6-NEXT: v_readlane_b32 s1, v0, 1
+; GFX6-NEXT: v_readlane_b32 s2, v0, 2
+; GFX6-NEXT: v_readlane_b32 s3, v0, 3
+; GFX6-NEXT: v_readlane_b32 s4, v0, 4
+; GFX6-NEXT: v_readlane_b32 s5, v0, 5
+; GFX6-NEXT: v_readlane_b32 s6, v0, 6
+; GFX6-NEXT: v_readlane_b32 s7, v0, 7
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_mov_b64 exec, s[36:37]
; GFX6-NEXT: s_mov_b64 s[44:45], exec
; GFX6-NEXT: s_mov_b64 exec, 15
-; GFX6-NEXT: v_mov_b32_e32 v7, 0x2180
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x2160
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v4, v7, s[40:43], 0 offen ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v0, v1, s[40:43], 0 offen ; 4-byte Folded Reload
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: v_readlane_b32 s36, v4, 0
-; GFX6-NEXT: v_readlane_b32 s37, v4, 1
-; GFX6-NEXT: v_readlane_b32 s38, v4, 2
-; GFX6-NEXT: v_readlane_b32 s39, v4, 3
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
+; GFX6-NEXT: v_readlane_b32 s36, v0, 0
+; GFX6-NEXT: v_readlane_b32 s37, v0, 1
+; GFX6-NEXT: v_readlane_b32 s38, v0, 2
+; GFX6-NEXT: v_readlane_b32 s39, v0, 3
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_mov_b64 exec, s[44:45]
; GFX6-NEXT: s_mov_b64 vcc, s[34:35]
; GFX6-NEXT: s_mov_b64 s[44:45], exec
; GFX6-NEXT: s_mov_b64 exec, 3
-; GFX6-NEXT: v_mov_b32_e32 v7, 0x2190
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x2170
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v4, v7, s[40:43], 0 offen ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v0, v1, s[40:43], 0 offen ; 4-byte Folded Reload
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: v_readlane_b32 s34, v4, 0
-; GFX6-NEXT: v_readlane_b32 s35, v4, 1
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
+; GFX6-NEXT: v_readlane_b32 s34, v0, 0
+; GFX6-NEXT: v_readlane_b32 s35, v0, 1
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_mov_b64 exec, s[44:45]
; GFX6-NEXT: ;;#ASMSTART
@@ -10472,44 +10458,31 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: s_mov_b64 s[34:35], vcc
; GFX6-NEXT: s_mov_b64 s[4:5], exec
; GFX6-NEXT: s_mov_b64 exec, 15
-; GFX6-NEXT: s_mov_b32 s6, 0x85c00
-; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
+; GFX6-NEXT: s_mov_b32 s6, 0x85e00
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], s6 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], s6 ; 4-byte Folded Reload
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: v_readlane_b32 s0, v4, 0
-; GFX6-NEXT: v_readlane_b32 s1, v4, 1
-; GFX6-NEXT: v_readlane_b32 s2, v4, 2
-; GFX6-NEXT: v_readlane_b32 s3, v4, 3
-; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
+; GFX6-NEXT: v_readlane_b32 s0, v0, 0
+; GFX6-NEXT: v_readlane_b32 s1, v0, 1
+; GFX6-NEXT: v_readlane_b32 s2, v0, 2
+; GFX6-NEXT: v_readlane_b32 s3, v0, 3
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_mov_b64 exec, s[4:5]
-; GFX6-NEXT: s_mov_b32 s2, 0x83c00
-; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s2 ; 4-byte Folded Spill
-; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dword v1, off, s[40:43], s2 offset:4 ; 4-byte Folded Spill
-; GFX6-NEXT: buffer_store_dword v2, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
-; GFX6-NEXT: buffer_store_dword v3, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
-; GFX6-NEXT: s_mov_b32 s2, 0x84400
-; GFX6-NEXT: buffer_store_dword v13, off, s[40:43], s2 ; 4-byte Folded Spill
-; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: buffer_store_dword v14, off, s[40:43], s2 offset:4 ; 4-byte Folded Spill
-; GFX6-NEXT: buffer_store_dword v15, off, s[40:43], s2 offset:8 ; 4-byte Folded Spill
-; GFX6-NEXT: buffer_store_dword v16, off, s[40:43], s2 offset:12 ; 4-byte Folded Spill
-; GFX6-NEXT: s_waitcnt expcnt(4)
; GFX6-NEXT: v_mov_b32_e32 v0, v17
; GFX6-NEXT: v_mov_b32_e32 v1, v18
; GFX6-NEXT: v_mov_b32_e32 v2, v19
; GFX6-NEXT: v_mov_b32_e32 v3, v20
-; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: ;;#ASMSTART
; GFX6-NEXT: ;;#ASMEND
+; GFX6-NEXT: s_mov_b32 s2, 0x84800
; GFX6-NEXT: v_mov_b32_e32 v20, v3
; GFX6-NEXT: buffer_load_dword v13, off, s[40:43], s2 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v14, off, s[40:43], s2 offset:4 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v15, off, s[40:43], s2 offset:8 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v16, off, s[40:43], s2 offset:12 ; 4-byte Folded Reload
-; GFX6-NEXT: s_mov_b32 s2, 0x83c00
+; GFX6-NEXT: s_mov_b32 s2, 0x84000
; GFX6-NEXT: v_mov_b32_e32 v19, v2
; GFX6-NEXT: v_mov_b32_e32 v18, v1
; GFX6-NEXT: v_mov_b32_e32 v17, v0
@@ -10545,14 +10518,14 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_mov_b64 exec, s[2:3]
-; GFX6-NEXT: s_mov_b32 s4, 0x83800
+; GFX6-NEXT: s_mov_b32 s4, 0x83c00
; GFX6-NEXT: v_lshl_b64 v[4:5], v[5:6], 8
; GFX6-NEXT: buffer_load_dword v6, off, s[40:43], s4 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s4 offset:4 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s4 offset:8 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s4 offset:12 ; 4-byte Folded Reload
; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
-; GFX6-NEXT: s_mov_b32 s4, 0x83400
+; GFX6-NEXT: s_mov_b32 s4, 0x83800
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[0:3], 0 addr64 offset:240
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10560,7 +10533,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s4 offset:4 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s4 offset:8 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s4 offset:12 ; 4-byte Folded Reload
-; GFX6-NEXT: s_mov_b32 s4, 0x83000
+; GFX6-NEXT: s_mov_b32 s4, 0x83400
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[0:3], 0 addr64 offset:224
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10568,7 +10541,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s4 offset:4 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s4 offset:8 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s4 offset:12 ; 4-byte Folded Reload
-; GFX6-NEXT: s_mov_b32 s4, 0x82c00
+; GFX6-NEXT: s_mov_b32 s4, 0x83000
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[0:3], 0 addr64 offset:208
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10576,7 +10549,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s4 offset:4 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s4 offset:8 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s4 offset:12 ; 4-byte Folded Reload
-; GFX6-NEXT: s_mov_b32 s4, 0x82800
+; GFX6-NEXT: s_mov_b32 s4, 0x82c00
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[0:3], 0 addr64 offset:192
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10584,7 +10557,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s4 offset:4 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s4 offset:8 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s4 offset:12 ; 4-byte Folded Reload
-; GFX6-NEXT: s_mov_b32 s4, 0x82400
+; GFX6-NEXT: s_mov_b32 s4, 0x82800
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[0:3], 0 addr64 offset:176
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10592,7 +10565,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s4 offset:4 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s4 offset:8 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s4 offset:12 ; 4-byte Folded Reload
-; GFX6-NEXT: s_mov_b32 s4, 0x82000
+; GFX6-NEXT: s_mov_b32 s4, 0x82400
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[0:3], 0 addr64 offset:160
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10600,7 +10573,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s4 offset:4 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s4 offset:8 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s4 offset:12 ; 4-byte Folded Reload
-; GFX6-NEXT: s_mov_b32 s4, 0x81c00
+; GFX6-NEXT: s_mov_b32 s4, 0x82000
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[0:3], 0 addr64 offset:144
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10608,7 +10581,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s4 offset:4 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s4 offset:8 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s4 offset:12 ; 4-byte Folded Reload
-; GFX6-NEXT: s_mov_b32 s4, 0x81800
+; GFX6-NEXT: s_mov_b32 s4, 0x81c00
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[0:3], 0 addr64 offset:128
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10616,7 +10589,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s4 offset:4 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s4 offset:8 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s4 offset:12 ; 4-byte Folded Reload
-; GFX6-NEXT: s_mov_b32 s4, 0x81400
+; GFX6-NEXT: s_mov_b32 s4, 0x81800
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[0:3], 0 addr64 offset:112
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10624,7 +10597,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s4 offset:4 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s4 offset:8 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s4 offset:12 ; 4-byte Folded Reload
-; GFX6-NEXT: s_mov_b32 s4, 0x81000
+; GFX6-NEXT: s_mov_b32 s4, 0x81400
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[0:3], 0 addr64 offset:96
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10632,7 +10605,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: buffer_load_dword v7, off, s[40:43], s4 offset:4 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v8, off, s[40:43], s4 offset:8 ; 4-byte Folded Reload
; GFX6-NEXT: buffer_load_dword v9, off, s[40:43], s4 offset:12 ; 4-byte Folded Reload
-; GFX6-NEXT: s_mov_b32 s4, 0x80c00
+; GFX6-NEXT: s_mov_b32 s4, 0x81000
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[0:3], 0 addr64 offset:80
; GFX6-NEXT: buffer_store_dwordx4 v[17:20], v[4:5], s[0:3], 0 addr64 offset:64
@@ -10664,19 +10637,19 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:240
; GFX9-FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20b0
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20c0
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 1
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[8:11], v0, s[38:39] offset:224
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:208
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20a0
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20b0
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[20:23], v0, s[38:39] offset:192
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:176
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2090
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20a0
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[16:19], v0, s[38:39] offset:160
@@ -10685,7 +10658,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:128
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20c0
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2090
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[1:4], v0, s[38:39] offset:112
@@ -10746,26 +10719,24 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX9-FLATSCR-NEXT: s_and_saveexec_b64 s[34:35], vcc
; GFX9-FLATSCR-NEXT: s_cbranch_execz .LBB1_2
; GFX9-FLATSCR-NEXT: ; %bb.1: ; %bb0
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, v16
; GFX9-FLATSCR-NEXT: ;;#ASMSTART
; GFX9-FLATSCR-NEXT: ; use s[0:7],s[8:15],s[16:23],s[24:31],s[40:43],s[38:39]
; GFX9-FLATSCR-NEXT: ;;#ASMEND
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20d0
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20e0
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[16:19], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20f0
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[20:23], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2100
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[8:11], s0 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_nop 0
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, v17
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, v18
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, v19
; GFX9-FLATSCR-NEXT: ;;#ASMSTART
; GFX9-FLATSCR-NEXT: ;;#ASMEND
-; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[8:11], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20f0
-; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[20:23], off, s0 ; 16-byte Folded Reload
+; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[8:11], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20e0
-; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[16:19], off, s0 ; 16-byte Folded Reload
+; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[20:23], off, s0 ; 16-byte Folded Reload
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v19, v3
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20d0
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v18, v2
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v17, v1
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, v0
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: ;;#ASMSTART
; GFX9-FLATSCR-NEXT: ;;#ASMEND
@@ -10781,18 +10752,18 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX9-FLATSCR-NEXT: ;;#ASMEND
; GFX9-FLATSCR-NEXT: .LBB1_2: ; %ret
; GFX9-FLATSCR-NEXT: s_or_b64 exec, exec, s[34:35]
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20b0
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20c0
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[12:15], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: v_lshlrev_b64 v[4:5], 8, v[5:6]
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, s37
; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v4, vcc, s36, v4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20a0
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20b0
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[4:5], v[12:15], off offset:240
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[4:5], v[8:11], off offset:224
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[6:9], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2090
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20a0
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[4:5], v[6:9], off offset:208
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[4:5], v[20:23], off offset:192
@@ -10802,7 +10773,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[4:5], v[20:23], off offset:176
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[4:5], v[16:19], off offset:160
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[16:19], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x20c0
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2090
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[6:9], off, s0 ; 16-byte Folded Reload
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2060
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[12:15], off, s0 ; 16-byte Folded Reload
@@ -10897,10 +10868,6 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX10-FLATSCR-NEXT: v_cmpx_eq_u32_e32 0, v0
; GFX10-FLATSCR-NEXT: s_cbranch_execz .LBB1_2
; GFX10-FLATSCR-NEXT: ; %bb.1: ; %bb0
-; GFX10-FLATSCR-NEXT: ;;#ASMSTART
-; GFX10-FLATSCR-NEXT: ; use s[0:7],s[8:15],s[16:23],s[24:31],s[40:43],s[34:35]
-; GFX10-FLATSCR-NEXT: ;;#ASMEND
-; GFX10-FLATSCR-NEXT: s_movk_i32 s0, 0x2010
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v88, v59
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v92, v63
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v87, v58
@@ -10910,7 +10877,6 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v90, v61
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v89, v60
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v60, v35
-; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[64:67], s0 ; 16-byte Folded Spill
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v68, v39
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v59, v34
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v58, v33
@@ -10959,6 +10925,9 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v55, v30
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v54, v29
; GFX10-FLATSCR-NEXT: ;;#ASMSTART
+; GFX10-FLATSCR-NEXT: ; use s[0:7],s[8:15],s[16:23],s[24:31],s[40:43],s[34:35]
+; GFX10-FLATSCR-NEXT: ;;#ASMEND
+; GFX10-FLATSCR-NEXT: ;;#ASMSTART
; GFX10-FLATSCR-NEXT: ;;#ASMEND
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v8, v33
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v28, v53
@@ -10990,6 +10959,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v35, v60
; GFX10-FLATSCR-NEXT: ;;#ASMSTART
; GFX10-FLATSCR-NEXT: ;;#ASMEND
+; GFX10-FLATSCR-NEXT: s_movk_i32 s0, 0x2010
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v36, v65
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v37, v66
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v38, v67
diff --git a/llvm/test/CodeGen/AMDGPU/swdev380865.ll b/llvm/test/CodeGen/AMDGPU/swdev380865.ll
index 7201ffaf561662a..70687e15947c1d5 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev380865.ll
+++ b/llvm/test/CodeGen/AMDGPU/swdev380865.ll
@@ -16,88 +16,63 @@ define amdgpu_kernel void @_Z6kernelILi4000ELi1EEvPd(ptr addrspace(1) %x.coerce)
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_mov_b64 s[0:1], 0
; CHECK-NEXT: s_load_dword s2, s[0:1], 0x0
-; CHECK-NEXT: ; implicit-def: $vgpr2 : SGPR spill to VGPR lane
+; CHECK-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x0
; CHECK-NEXT: ; kill: killed $sgpr0_sgpr1
-; CHECK-NEXT: s_mov_b32 s7, 0x401c0000
-; CHECK-NEXT: s_mov_b32 s5, 0x40280000
-; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: v_writelane_b32 v2, s2, 0
-; CHECK-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; CHECK-NEXT: s_mov_b32 s0, 0
+; CHECK-NEXT: ; implicit-def: $vgpr2 : SGPR spill to VGPR lane
; CHECK-NEXT: s_mov_b32 s1, 0x40140000
; CHECK-NEXT: s_mov_b32 s1, 0x40180000
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: v_writelane_b32 v2, s2, 0
; CHECK-NEXT: v_writelane_b32 v2, s0, 1
; CHECK-NEXT: v_writelane_b32 v2, s1, 2
-; CHECK-NEXT: s_mov_b32 s1, 0x40220000
+; CHECK-NEXT: s_mov_b32 s1, 0x40240000
; CHECK-NEXT: v_writelane_b32 v2, s0, 3
+; CHECK-NEXT: v_mov_b32_e32 v0, s6
; CHECK-NEXT: v_writelane_b32 v2, s1, 4
-; CHECK-NEXT: s_mov_b32 s1, 0x40240000
-; CHECK-NEXT: v_writelane_b32 v2, s0, 5
-; CHECK-NEXT: v_writelane_b32 v2, s1, 6
-; CHECK-NEXT: s_mov_b32 s1, 0x40260000
-; CHECK-NEXT: v_writelane_b32 v2, s0, 7
-; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: v_mov_b32_e32 v0, s2
-; CHECK-NEXT: v_writelane_b32 v2, s1, 8
-; CHECK-NEXT: v_mov_b32_e32 v1, s3
+; CHECK-NEXT: s_mov_b32 s3, 0x40260000
+; CHECK-NEXT: s_mov_b32 s5, 0x40280000
+; CHECK-NEXT: v_mov_b32_e32 v1, s7
; CHECK-NEXT: .LBB0_1: ; %for.cond4.preheader
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], 0
-; CHECK-NEXT: s_mov_b32 s2, 0
-; CHECK-NEXT: s_mov_b32 s3, 0x40140000
-; CHECK-NEXT: v_writelane_b32 v2, s6, 9
-; CHECK-NEXT: v_writelane_b32 v2, s7, 10
-; CHECK-NEXT: v_writelane_b32 v2, s0, 11
+; CHECK-NEXT: s_mov_b32 s6, 0
+; CHECK-NEXT: s_mov_b32 s7, 0x40140000
+; CHECK-NEXT: v_writelane_b32 v2, s0, 5
+; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]
; CHECK-NEXT: v_readlane_b32 s6, v2, 1
; CHECK-NEXT: v_readlane_b32 s7, v2, 2
-; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[2:3]
; CHECK-NEXT: s_mov_b32 s1, s7
-; CHECK-NEXT: s_mov_b32 s0, s2
-; CHECK-NEXT: v_writelane_b32 v2, s6, 1
-; CHECK-NEXT: v_writelane_b32 v2, s7, 2
-; CHECK-NEXT: v_readlane_b32 s6, v2, 9
-; CHECK-NEXT: v_readlane_b32 s7, v2, 10
-; CHECK-NEXT: s_mov_b32 s6, s2
+; CHECK-NEXT: s_mov_b32 s6, 0
+; CHECK-NEXT: s_mov_b32 s7, 0x40140000
+; CHECK-NEXT: s_mov_b32 s0, s6
+; CHECK-NEXT: v_readlane_b32 s6, v2, 6
; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[0:1]
-; CHECK-NEXT: v_readlane_b32 s0, v2, 3
-; CHECK-NEXT: v_readlane_b32 s1, v2, 4
-; CHECK-NEXT: s_mov_b32 s3, s1
; CHECK-NEXT: s_mov_b32 s0, 0
+; CHECK-NEXT: v_readlane_b32 s7, v2, 7
; CHECK-NEXT: s_mov_b32 s1, 0x40140000
-; CHECK-NEXT: s_mov_b32 s2, s0
-; CHECK-NEXT: s_mov_b32 s1, s3
+; CHECK-NEXT: s_mov_b32 s6, s0
; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]
-; CHECK-NEXT: v_writelane_b32 v2, s0, 3
-; CHECK-NEXT: v_writelane_b32 v2, s1, 4
-; CHECK-NEXT: v_readlane_b32 s0, v2, 5
-; CHECK-NEXT: v_readlane_b32 s1, v2, 6
-; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[2:3]
-; CHECK-NEXT: s_mov_b32 s3, s1
-; CHECK-NEXT: s_mov_b32 s0, 0
-; CHECK-NEXT: s_mov_b32 s1, 0x40140000
-; CHECK-NEXT: s_mov_b32 s2, s0
-; CHECK-NEXT: s_mov_b32 s1, s3
-; CHECK-NEXT: v_writelane_b32 v2, s0, 5
-; CHECK-NEXT: v_writelane_b32 v2, s1, 6
-; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[2:3]
-; CHECK-NEXT: v_readlane_b32 s0, v2, 7
-; CHECK-NEXT: v_readlane_b32 s1, v2, 8
-; CHECK-NEXT: s_mov_b32 s3, s1
-; CHECK-NEXT: s_mov_b32 s0, 0
-; CHECK-NEXT: s_mov_b32 s1, 0x40140000
-; CHECK-NEXT: s_mov_b32 s2, s0
-; CHECK-NEXT: s_mov_b32 s1, s3
-; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[2:3]
-; CHECK-NEXT: v_writelane_b32 v2, s0, 7
-; CHECK-NEXT: s_mov_b32 s4, s0
-; CHECK-NEXT: v_writelane_b32 v2, s1, 8
+; CHECK-NEXT: v_readlane_b32 s6, v2, 8
+; CHECK-NEXT: v_readlane_b32 s7, v2, 9
+; CHECK-NEXT: s_mov_b32 s6, s0
+; CHECK-NEXT: v_readlane_b32 s0, v2, 3
+; CHECK-NEXT: v_readlane_b32 s1, v2, 4
+; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]
+; CHECK-NEXT: s_mov_b32 s6, 0
+; CHECK-NEXT: s_mov_b32 s7, 0x40140000
+; CHECK-NEXT: s_mov_b32 s0, s6
+; CHECK-NEXT: s_mov_b32 s2, s6
+; CHECK-NEXT: s_mov_b32 s4, s6
+; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[0:1]
; CHECK-NEXT: v_readlane_b32 s0, v2, 0
-; CHECK-NEXT: v_readlane_b32 s2, v2, 11
+; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[2:3]
+; CHECK-NEXT: v_readlane_b32 s2, v2, 5
; CHECK-NEXT: s_add_i32 s2, s2, s0
-; CHECK-NEXT: v_writelane_b32 v2, s2, 11
-; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[4:5]
-; CHECK-NEXT: v_readlane_b32 s0, v2, 11
+; CHECK-NEXT: v_writelane_b32 v2, s2, 5
+; CHECK-NEXT: v_readlane_b32 s0, v2, 5
; CHECK-NEXT: s_cmpk_lt_i32 s0, 0xa00
+; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[4:5]
; CHECK-NEXT: s_cbranch_scc1 .LBB0_1
; CHECK-NEXT: ; %bb.2: ; %for.cond.cleanup.loopexit
; CHECK-NEXT: v_mov_b32_e32 v3, 0
diff --git a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
index 67f4dd72ea0b2db..d30fb39f874110c 100644
--- a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
+++ b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
@@ -153,8 +153,8 @@ body: |
%13 = S2_asl_r_p_acc %13, %47, %8.isub_lo
%51 = A2_tfrpi 0
- ; CHECK: $d2 = S2_extractup undef renamable $d0, 6, 25
- ; CHECK: $d0 = A2_tfrpi 2
+ ; CHECK: $d0 = S2_extractup undef renamable $d0, 6, 25
+ ; CHECK: $d1 = A2_tfrpi 2
; CHECK: $d13 = A2_tfrpi -1
; CHECK-NOT: undef $r4
diff --git a/llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll b/llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
index 45bb70ec44b737a..a0ac03e9e862f22 100644
--- a/llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
@@ -1024,10 +1024,8 @@ middle.block: ; preds = %vector.body
define void @DCT_mve7(ptr nocapture readonly %S, ptr nocapture readonly %pIn, ptr nocapture %pOut) {
; CHECK-LABEL: DCT_mve7:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: .pad #4
-; CHECK-NEXT: sub sp, #4
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r11, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #72
@@ -1074,7 +1072,6 @@ define void @DCT_mve7(ptr nocapture readonly %S, ptr nocapture readonly %pIn, pt
; CHECK-NEXT: vmov q4, q2
; CHECK-NEXT: vmov q5, q2
; CHECK-NEXT: vmov q3, q2
-; CHECK-NEXT: vmov q6, q2
; CHECK-NEXT: vmov q1, q2
; CHECK-NEXT: mov r12, r7
; CHECK-NEXT: vstrw.32 q2, [sp, #56] @ 16-byte Spill
@@ -1083,20 +1080,16 @@ define void @DCT_mve7(ptr nocapture readonly %S, ptr nocapture readonly %pIn, pt
; CHECK-NEXT: @ Parent Loop BB6_2 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
; CHECK-NEXT: vctp.32 r12
-; CHECK-NEXT: add.w r10, r3, r5
+; CHECK-NEXT: adds r6, r3, r5
; CHECK-NEXT: vpstt
; CHECK-NEXT: vldrwt.u32 q7, [r1], #16
; CHECK-NEXT: vldrwt.u32 q0, [r3], #16
-; CHECK-NEXT: add.w r11, r10, r5
+; CHECK-NEXT: add.w r11, r6, r5
; CHECK-NEXT: sub.w r12, r12, #4
; CHECK-NEXT: vpstt
; CHECK-NEXT: vfmat.f32 q5, q0, q7
-; CHECK-NEXT: vldrwt.u32 q0, [r10]
-; CHECK-NEXT: add.w r6, r11, r5
-; CHECK-NEXT: vpstt
-; CHECK-NEXT: vfmat.f32 q6, q0, q7
; CHECK-NEXT: vldrwt.u32 q0, [r11]
-; CHECK-NEXT: vstrw.32 q6, [sp, #40] @ 16-byte Spill
+; CHECK-NEXT: add.w r6, r11, r5
; CHECK-NEXT: vmov q6, q5
; CHECK-NEXT: vpst
; CHECK-NEXT: vfmat.f32 q1, q0, q7
@@ -1178,8 +1171,7 @@ define void @DCT_mve7(ptr nocapture readonly %S, ptr nocapture readonly %pIn, pt
; CHECK-NEXT: .LBB6_5: @ %for.cond.cleanup
; CHECK-NEXT: add sp, #72
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: add sp, #4
-; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r11, pc}
entry:
%NumInputs = getelementptr inbounds %struct.DCT_InstanceTypeDef, ptr %S, i32 0, i32 2
%i = load i32, ptr %NumInputs, align 4
@@ -1354,7 +1346,6 @@ define void @DCT_mve8(ptr nocapture readonly %S, ptr nocapture readonly %pIn, pt
; CHECK-NEXT: adds r1, r0, #1
; CHECK-NEXT: mov r3, r12
; CHECK-NEXT: vmov q5, q3
-; CHECK-NEXT: vmov q6, q3
; CHECK-NEXT: vmov q4, q3
; CHECK-NEXT: vmov q7, q3
; CHECK-NEXT: vmov q2, q3
@@ -1367,46 +1358,43 @@ define void @DCT_mve8(ptr nocapture readonly %S, ptr nocapture readonly %pIn, pt
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
; CHECK-NEXT: vctp.32 r10
; CHECK-NEXT: add.w r11, r3, r6
-; CHECK-NEXT: vpstt
-; CHECK-NEXT: vldrwt.u32 q0, [r9], #16
+; CHECK-NEXT: vpsttt
; CHECK-NEXT: vldrwt.u32 q1, [r3], #16
-; CHECK-NEXT: add.w r5, r11, r6
-; CHECK-NEXT: sub.w r10, r10, #4
-; CHECK-NEXT: vpstt
-; CHECK-NEXT: vfmat.f32 q6, q1, q0
+; CHECK-NEXT: vldrwt.u32 q0, [r9], #16
; CHECK-NEXT: vldrwt.u32 q1, [r11]
-; CHECK-NEXT: vstrw.32 q6, [sp, #40] @ 16-byte Spill
+; CHECK-NEXT: add.w r5, r11, r6
; CHECK-NEXT: vmov q6, q5
+; CHECK-NEXT: vmov q5, q3
; CHECK-NEXT: vpst
; CHECK-NEXT: vfmat.f32 q7, q1, q0
-; CHECK-NEXT: vmov q5, q3
; CHECK-NEXT: vmov q3, q4
; CHECK-NEXT: vmov q4, q2
; CHECK-NEXT: vpst
; CHECK-NEXT: vldrwt.u32 q1, [r5]
; CHECK-NEXT: vldrw.u32 q2, [sp, #56] @ 16-byte Reload
; CHECK-NEXT: adds r7, r5, r6
+; CHECK-NEXT: adds r5, r7, r6
+; CHECK-NEXT: sub.w r10, r10, #4
; CHECK-NEXT: vpstt
; CHECK-NEXT: vfmat.f32 q2, q1, q0
; CHECK-NEXT: vldrwt.u32 q1, [r7]
; CHECK-NEXT: vstrw.32 q2, [sp, #56] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [sp, #72] @ 16-byte Reload
-; CHECK-NEXT: adds r5, r7, r6
+; CHECK-NEXT: adds r7, r5, r6
; CHECK-NEXT: vpstt
; CHECK-NEXT: vfmat.f32 q2, q1, q0
; CHECK-NEXT: vldrwt.u32 q1, [r5]
-; CHECK-NEXT: adds r7, r5, r6
; CHECK-NEXT: vstrw.32 q2, [sp, #72] @ 16-byte Spill
; CHECK-NEXT: vmov q2, q4
-; CHECK-NEXT: vmov q4, q3
; CHECK-NEXT: vpstt
; CHECK-NEXT: vfmat.f32 q2, q1, q0
; CHECK-NEXT: vldrwt.u32 q1, [r7]
+; CHECK-NEXT: vmov q4, q3
; CHECK-NEXT: adds r5, r7, r6
-; CHECK-NEXT: vmov q3, q5
; CHECK-NEXT: vpstt
; CHECK-NEXT: vfmat.f32 q4, q1, q0
; CHECK-NEXT: vldrwt.u32 q1, [r5]
+; CHECK-NEXT: vmov q3, q5
; CHECK-NEXT: vmov q5, q6
; CHECK-NEXT: add r5, r6
; CHECK-NEXT: vpstt
diff --git a/llvm/test/CodeGen/Thumb2/mve-vst3.ll b/llvm/test/CodeGen/Thumb2/mve-vst3.ll
index d80dd5a673e20f2..d5f472be0432165 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vst3.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vst3.ll
@@ -1077,63 +1077,58 @@ define void @vst3_v16f32(ptr %src, ptr %dst) {
; CHECK-NEXT: vldrw.u32 q2, [r0, #64]
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #128]
-; CHECK-NEXT: vstrw.32 q3, [sp, #112] @ 16-byte Spill
+; CHECK-NEXT: vstrw.32 q3, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q3, [r0, #160]
-; CHECK-NEXT: vmov.f32 s24, s9
-; CHECK-NEXT: vldrw.u32 q5, [r0, #144]
-; CHECK-NEXT: vstrw.32 q3, [sp, #96] @ 16-byte Spill
-; CHECK-NEXT: vldrw.u32 q3, [r0, #96]
-; CHECK-NEXT: vmov.f32 s26, s6
; CHECK-NEXT: vldrw.u32 q7, [r0, #112]
+; CHECK-NEXT: vldrw.u32 q4, [r0, #48]
+; CHECK-NEXT: vstrw.32 q3, [sp, #112] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q3, [r0, #96]
+; CHECK-NEXT: vmov.f32 s25, s1
+; CHECK-NEXT: vldrw.u32 q5, [r0, #144]
; CHECK-NEXT: vstrw.32 q3, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q3, [r0, #80]
-; CHECK-NEXT: vmov.f32 s27, s10
-; CHECK-NEXT: vldrw.u32 q4, [r0, #48]
+; CHECK-NEXT: vmov.f32 s24, s9
; CHECK-NEXT: vstrw.32 q3, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
-; CHECK-NEXT: vmov.f32 s25, s1
+; CHECK-NEXT: vmov.f32 s26, s6
; CHECK-NEXT: vstrw.32 q3, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
-; CHECK-NEXT: vstrw.32 q6, [r1, #16]
-; CHECK-NEXT: vmov.f32 s24, s2
-; CHECK-NEXT: vstrw.32 q3, [sp, #80] @ 16-byte Spill
-; CHECK-NEXT: vmov.f32 s27, s3
+; CHECK-NEXT: vmov.f32 s27, s10
+; CHECK-NEXT: vstrw.32 q3, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s14, s0
-; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s12, s4
-; CHECK-NEXT: vmov.f32 s15, s5
+; CHECK-NEXT: vstrw.32 q6, [r1, #16]
; CHECK-NEXT: vmov.f32 s13, s8
+; CHECK-NEXT: vmov.f32 s15, s5
; CHECK-NEXT: vstrw.32 q3, [sp, #64] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q3, [sp, #80] @ 16-byte Reload
+; CHECK-NEXT: vmov.f32 s24, s2
+; CHECK-NEXT: vmov.f32 s27, s3
+; CHECK-NEXT: vmov.f32 s2, s12
+; CHECK-NEXT: vmov.f32 s0, s16
+; CHECK-NEXT: vmov.f32 s1, s28
+; CHECK-NEXT: vmov.f32 s3, s17
; CHECK-NEXT: vmov.f32 s25, s7
-; CHECK-NEXT: vmov.f32 s6, s0
-; CHECK-NEXT: vmov.f32 s13, s1
-; CHECK-NEXT: vmov.f32 s0, s2
-; CHECK-NEXT: vmov.f32 s4, s16
-; CHECK-NEXT: vmov.f32 s5, s28
-; CHECK-NEXT: vmov.f32 s7, s17
-; CHECK-NEXT: vmov.f32 s1, s19
-; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill
-; CHECK-NEXT: vmov.f32 s2, s31
; CHECK-NEXT: vldrw.u32 q1, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s26, s11
; CHECK-NEXT: vldrw.u32 q2, [sp, #16] @ 16-byte Reload
-; CHECK-NEXT: vstrw.32 q0, [sp, #112] @ 16-byte Spill
-; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload
+; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s15, s30
; CHECK-NEXT: vstrw.32 q6, [r1, #32]
; CHECK-NEXT: vmov.f32 s17, s1
-; CHECK-NEXT: vldrw.u32 q6, [sp, #80] @ 16-byte Reload
+; CHECK-NEXT: vldrw.u32 q6, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s30, s0
; CHECK-NEXT: vmov.f32 s0, s2
; CHECK-NEXT: vmov.f32 s1, s11
; CHECK-NEXT: vmov.f32 s2, s7
; CHECK-NEXT: vmov.f32 s14, s18
-; CHECK-NEXT: vstrw.32 q0, [sp, #96] @ 16-byte Spill
+; CHECK-NEXT: vstrw.32 q0, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s18, s10
; CHECK-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s28, s8
; CHECK-NEXT: vmov.f32 s31, s9
-; CHECK-NEXT: vldrw.u32 q2, [sp, #80] @ 16-byte Reload
+; CHECK-NEXT: vldrw.u32 q2, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s12, s29
; CHECK-NEXT: vmov.f32 s29, s4
; CHECK-NEXT: vstrw.32 q3, [r1, #160]
@@ -1148,14 +1143,14 @@ define void @vst3_v16f32(ptr %src, ptr %dst) {
; CHECK-NEXT: vmov.f32 s8, s1
; CHECK-NEXT: vmov.f32 s11, s2
; CHECK-NEXT: vmov.f32 s22, s3
-; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload
+; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s7, s9
; CHECK-NEXT: vstrw.32 q0, [r1, #128]
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s9, s21
; CHECK-NEXT: vstrw.32 q1, [r1, #48]
; CHECK-NEXT: vstrw.32 q0, [r1, #144]
-; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
+; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s21, s27
; CHECK-NEXT: vstrw.32 q2, [r1, #64]
; CHECK-NEXT: vstrw.32 q0, [r1, #176]
>From 5337990e01d2c2d836318816bbe7162009f66087 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Wed, 4 Oct 2023 08:25:12 +0300
Subject: [PATCH 3/3] Don't recurse through copies if using subranges
This has a worse result for the motivating example, so
I think something better is possible by inspecting the
individual ranges in a future patch.
---
llvm/lib/CodeGen/InlineSpiller.cpp | 18 +++--
.../identical-subrange-spill-infloop.ll | 16 -----
.../CodeGen/AMDGPU/spill-scavenge-offset.ll | 72 +++++++++++--------
llvm/test/CodeGen/AMDGPU/swdev380865.ll | 42 ++++++-----
.../vector-interleaved-store-i64-stride-4.ll | 2 -
5 files changed, 81 insertions(+), 69 deletions(-)
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index da80addcc31331c..3a4c9853caec1bd 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -550,16 +550,22 @@ void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
continue;
SlotIndex Idx = LIS.getInstructionIndex(MI);
+ bool SameVNI = LI->getVNInfoAt(Idx) == VNI;
+
// The main range value numbers will differ if multiple instructions are
// used to define its various subregisters. Check the subregister value
// numbers as a fallback.
- if (LI->getVNInfoAt(Idx) != VNI &&
- (!SLI.hasSubRanges() ||
- !allSubRangeValNoSame(*LI, SLI, MI, MRI, TRI, Idx)))
- continue;
+ if (!SameVNI) {
+ if (!SLI.hasSubRanges() ||
+ !allSubRangeValNoSame(*LI, SLI, MI, MRI, TRI, Idx))
+ continue;
+ }
- // Follow sibling copies down the dominator tree.
- if (Register DstReg = isCopyOfBundle(MI, Reg, TII)) {
+ // Follow sibling copies down the dominator tree. Don't do this if we're
+ // relying on identical subranges to avoid infinitely recursing.
+ // TODO: Handle subrange case.
+ Register DstReg;
+ if (SameVNI && (DstReg = isCopyOfBundle(MI, Reg, TII))) {
if (isSibling(DstReg)) {
LiveInterval &DstLI = LIS.getInterval(DstReg);
VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot());
diff --git a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
index 27fa6712f9eb429..e06bed1774cd056 100644
--- a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
+++ b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
@@ -117,22 +117,6 @@ define void @main(i1 %arg) #0 {
; CHECK-NEXT: s_cbranch_execz .LBB0_3
; CHECK-NEXT: ; %bb.1: ; %bb48
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: v_writelane_b32 v4, s36, 32
-; CHECK-NEXT: v_writelane_b32 v4, s37, 33
-; CHECK-NEXT: v_writelane_b32 v4, s38, 34
-; CHECK-NEXT: v_writelane_b32 v4, s39, 35
-; CHECK-NEXT: v_writelane_b32 v4, s40, 36
-; CHECK-NEXT: v_writelane_b32 v4, s41, 37
-; CHECK-NEXT: v_writelane_b32 v4, s42, 38
-; CHECK-NEXT: v_writelane_b32 v4, s43, 39
-; CHECK-NEXT: v_writelane_b32 v4, s44, 40
-; CHECK-NEXT: v_writelane_b32 v4, s45, 41
-; CHECK-NEXT: v_writelane_b32 v4, s46, 42
-; CHECK-NEXT: v_writelane_b32 v4, s47, 43
-; CHECK-NEXT: v_writelane_b32 v4, s48, 44
-; CHECK-NEXT: v_writelane_b32 v4, s49, 45
-; CHECK-NEXT: v_writelane_b32 v4, s50, 46
-; CHECK-NEXT: v_writelane_b32 v4, s51, 47
; CHECK-NEXT: v_readlane_b32 s36, v4, 0
; CHECK-NEXT: v_readlane_b32 s44, v4, 8
; CHECK-NEXT: v_readlane_b32 s45, v4, 9
diff --git a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
index 9955aca981518df..207b154d0c12aa8 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
@@ -10273,7 +10273,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: s_and_saveexec_b64 s[34:35], vcc
; GFX6-NEXT: s_cbranch_execz .LBB1_2
; GFX6-NEXT: ; %bb.1: ; %bb0
-; GFX6-NEXT: s_mov_b64 s[0:1], exec
+; GFX6-NEXT: s_mov_b64 s[36:37], exec
; GFX6-NEXT: s_mov_b64 exec, 0xff
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10285,18 +10285,18 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: v_writelane_b32 v0, s13, 5
; GFX6-NEXT: v_writelane_b32 v0, s14, 6
; GFX6-NEXT: v_writelane_b32 v0, s15, 7
-; GFX6-NEXT: s_mov_b32 s36, 0x80800
-; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s36 ; 4-byte Folded Spill
+; GFX6-NEXT: s_mov_b32 s38, 0x80800
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s38 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: s_mov_b64 exec, s[0:1]
-; GFX6-NEXT: s_mov_b64 s[0:1], exec
+; GFX6-NEXT: s_mov_b64 exec, s[36:37]
+; GFX6-NEXT: s_mov_b64 s[36:37], exec
; GFX6-NEXT: s_mov_b64 exec, 0xff
-; GFX6-NEXT: s_mov_b32 s36, 0x84000
+; GFX6-NEXT: s_mov_b32 s38, 0x84000
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], s36 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], s38 ; 4-byte Folded Reload
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_readlane_b32 s8, v0, 0
; GFX6-NEXT: v_readlane_b32 s9, v0, 1
@@ -10308,8 +10308,8 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: v_readlane_b32 s15, v0, 7
; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: s_mov_b64 exec, s[0:1]
-; GFX6-NEXT: s_mov_b64 s[0:1], exec
+; GFX6-NEXT: s_mov_b64 exec, s[36:37]
+; GFX6-NEXT: s_mov_b64 s[36:37], exec
; GFX6-NEXT: s_mov_b64 exec, 0xff
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10321,18 +10321,18 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: v_writelane_b32 v0, s21, 5
; GFX6-NEXT: v_writelane_b32 v0, s22, 6
; GFX6-NEXT: v_writelane_b32 v0, s23, 7
-; GFX6-NEXT: s_mov_b32 s36, 0x84800
-; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s36 ; 4-byte Folded Spill
+; GFX6-NEXT: s_mov_b32 s38, 0x84800
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s38 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: s_mov_b64 exec, s[0:1]
-; GFX6-NEXT: s_mov_b64 s[0:1], exec
+; GFX6-NEXT: s_mov_b64 exec, s[36:37]
+; GFX6-NEXT: s_mov_b64 s[36:37], exec
; GFX6-NEXT: s_mov_b64 exec, 0xff
-; GFX6-NEXT: s_mov_b32 s36, 0x80800
+; GFX6-NEXT: s_mov_b32 s38, 0x80800
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], s36 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], s38 ; 4-byte Folded Reload
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_readlane_b32 s16, v0, 0
; GFX6-NEXT: v_readlane_b32 s17, v0, 1
@@ -10344,8 +10344,8 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: v_readlane_b32 s23, v0, 7
; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: s_mov_b64 exec, s[0:1]
-; GFX6-NEXT: s_mov_b64 s[0:1], exec
+; GFX6-NEXT: s_mov_b64 exec, s[36:37]
+; GFX6-NEXT: s_mov_b64 s[36:37], exec
; GFX6-NEXT: s_mov_b64 exec, 0xff
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10357,18 +10357,18 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: v_writelane_b32 v0, s29, 5
; GFX6-NEXT: v_writelane_b32 v0, s30, 6
; GFX6-NEXT: v_writelane_b32 v0, s31, 7
-; GFX6-NEXT: s_mov_b32 s36, 0x85000
-; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s36 ; 4-byte Folded Spill
+; GFX6-NEXT: s_mov_b32 s38, 0x85000
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s38 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: s_mov_b64 exec, s[0:1]
-; GFX6-NEXT: s_mov_b64 s[0:1], exec
+; GFX6-NEXT: s_mov_b64 exec, s[36:37]
+; GFX6-NEXT: s_mov_b64 s[36:37], exec
; GFX6-NEXT: s_mov_b64 exec, 0xff
-; GFX6-NEXT: s_mov_b32 s36, 0x84800
+; GFX6-NEXT: s_mov_b32 s38, 0x84800
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], s36 ; 4-byte Folded Reload
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], s38 ; 4-byte Folded Reload
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_readlane_b32 s24, v0, 0
; GFX6-NEXT: v_readlane_b32 s25, v0, 1
@@ -10380,7 +10380,21 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: v_readlane_b32 s31, v0, 7
; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: s_mov_b64 exec, s[0:1]
+; GFX6-NEXT: s_mov_b64 exec, s[36:37]
+; GFX6-NEXT: s_mov_b64 s[36:37], exec
+; GFX6-NEXT: s_mov_b64 exec, 15
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_writelane_b32 v0, s0, 0
+; GFX6-NEXT: v_writelane_b32 v0, s1, 1
+; GFX6-NEXT: v_writelane_b32 v0, s2, 2
+; GFX6-NEXT: v_writelane_b32 v0, s3, 3
+; GFX6-NEXT: s_mov_b32 s38, 0x85800
+; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s38 ; 4-byte Folded Spill
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: s_mov_b64 exec, s[36:37]
; GFX6-NEXT: s_mov_b64 s[0:1], exec
; GFX6-NEXT: s_mov_b64 exec, 15
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
@@ -10389,7 +10403,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: v_writelane_b32 v0, s5, 1
; GFX6-NEXT: v_writelane_b32 v0, s6, 2
; GFX6-NEXT: v_writelane_b32 v0, s7, 3
-; GFX6-NEXT: s_mov_b32 s36, 0x85800
+; GFX6-NEXT: s_mov_b32 s36, 0x85c00
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s36 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
@@ -10401,7 +10415,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_writelane_b32 v0, s2, 0
; GFX6-NEXT: v_writelane_b32 v0, s3, 1
-; GFX6-NEXT: s_mov_b32 s4, 0x85c00
+; GFX6-NEXT: s_mov_b32 s4, 0x86000
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], s4 ; 4-byte Folded Spill
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], 0
@@ -10427,7 +10441,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: s_mov_b64 exec, s[36:37]
; GFX6-NEXT: s_mov_b64 s[44:45], exec
; GFX6-NEXT: s_mov_b64 exec, 15
-; GFX6-NEXT: v_mov_b32_e32 v1, 0x2160
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x2170
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dword v0, v1, s[40:43], 0 offen ; 4-byte Folded Reload
@@ -10442,7 +10456,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: s_mov_b64 vcc, s[34:35]
; GFX6-NEXT: s_mov_b64 s[44:45], exec
; GFX6-NEXT: s_mov_b64 exec, 3
-; GFX6-NEXT: v_mov_b32_e32 v1, 0x2170
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x2180
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dword v0, v1, s[40:43], 0 offen ; 4-byte Folded Reload
@@ -10458,7 +10472,7 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
; GFX6-NEXT: s_mov_b64 s[34:35], vcc
; GFX6-NEXT: s_mov_b64 s[4:5], exec
; GFX6-NEXT: s_mov_b64 exec, 15
-; GFX6-NEXT: s_mov_b32 s6, 0x85e00
+; GFX6-NEXT: s_mov_b32 s6, 0x85800
; GFX6-NEXT: buffer_store_dword v0, off, s[40:43], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: buffer_load_dword v0, off, s[40:43], s6 ; 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/AMDGPU/swdev380865.ll b/llvm/test/CodeGen/AMDGPU/swdev380865.ll
index 70687e15947c1d5..84b28f644139538 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev380865.ll
+++ b/llvm/test/CodeGen/AMDGPU/swdev380865.ll
@@ -26,45 +26,55 @@ define amdgpu_kernel void @_Z6kernelILi4000ELi1EEvPd(ptr addrspace(1) %x.coerce)
; CHECK-NEXT: v_writelane_b32 v2, s2, 0
; CHECK-NEXT: v_writelane_b32 v2, s0, 1
; CHECK-NEXT: v_writelane_b32 v2, s1, 2
-; CHECK-NEXT: s_mov_b32 s1, 0x40240000
+; CHECK-NEXT: s_mov_b32 s1, 0x40260000
; CHECK-NEXT: v_writelane_b32 v2, s0, 3
; CHECK-NEXT: v_mov_b32_e32 v0, s6
; CHECK-NEXT: v_writelane_b32 v2, s1, 4
-; CHECK-NEXT: s_mov_b32 s3, 0x40260000
; CHECK-NEXT: s_mov_b32 s5, 0x40280000
; CHECK-NEXT: v_mov_b32_e32 v1, s7
; CHECK-NEXT: .LBB0_1: ; %for.cond4.preheader
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], 0
-; CHECK-NEXT: s_mov_b32 s6, 0
-; CHECK-NEXT: s_mov_b32 s7, 0x40140000
; CHECK-NEXT: v_writelane_b32 v2, s0, 5
-; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]
+; CHECK-NEXT: s_mov_b32 s0, 0
+; CHECK-NEXT: s_mov_b32 s1, 0x40140000
; CHECK-NEXT: v_readlane_b32 s6, v2, 1
; CHECK-NEXT: v_readlane_b32 s7, v2, 2
+; CHECK-NEXT: s_mov_b32 s2, 0
+; CHECK-NEXT: s_mov_b32 s3, 0x40140000
+; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[0:1]
; CHECK-NEXT: s_mov_b32 s1, s7
; CHECK-NEXT: s_mov_b32 s6, 0
; CHECK-NEXT: s_mov_b32 s7, 0x40140000
; CHECK-NEXT: s_mov_b32 s0, s6
-; CHECK-NEXT: v_readlane_b32 s6, v2, 6
+; CHECK-NEXT: s_mov_b32 s7, s1
+; CHECK-NEXT: v_writelane_b32 v2, s6, 1
+; CHECK-NEXT: v_writelane_b32 v2, s7, 2
; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[0:1]
+; CHECK-NEXT: v_readlane_b32 s6, v2, 6
; CHECK-NEXT: s_mov_b32 s0, 0
; CHECK-NEXT: v_readlane_b32 s7, v2, 7
; CHECK-NEXT: s_mov_b32 s1, 0x40140000
; CHECK-NEXT: s_mov_b32 s6, s0
+; CHECK-NEXT: v_readlane_b32 s0, v2, 8
+; CHECK-NEXT: v_readlane_b32 s1, v2, 9
; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]
-; CHECK-NEXT: v_readlane_b32 s6, v2, 8
-; CHECK-NEXT: v_readlane_b32 s7, v2, 9
+; CHECK-NEXT: s_mov_b32 s7, s1
+; CHECK-NEXT: v_readlane_b32 s0, v2, 10
+; CHECK-NEXT: v_readlane_b32 s1, v2, 11
+; CHECK-NEXT: s_mov_b32 s0, s2
+; CHECK-NEXT: v_readlane_b32 s2, v2, 3
+; CHECK-NEXT: v_readlane_b32 s3, v2, 4
+; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[0:1]
+; CHECK-NEXT: s_mov_b32 s0, 0
+; CHECK-NEXT: s_mov_b32 s1, 0x40140000
; CHECK-NEXT: s_mov_b32 s6, s0
-; CHECK-NEXT: v_readlane_b32 s0, v2, 3
-; CHECK-NEXT: v_readlane_b32 s1, v2, 4
+; CHECK-NEXT: s_mov_b32 s2, s0
+; CHECK-NEXT: s_mov_b32 s1, s3
+; CHECK-NEXT: v_writelane_b32 v2, s0, 3
+; CHECK-NEXT: s_mov_b32 s4, s0
; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]
-; CHECK-NEXT: s_mov_b32 s6, 0
-; CHECK-NEXT: s_mov_b32 s7, 0x40140000
-; CHECK-NEXT: s_mov_b32 s0, s6
-; CHECK-NEXT: s_mov_b32 s2, s6
-; CHECK-NEXT: s_mov_b32 s4, s6
-; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[0:1]
+; CHECK-NEXT: v_writelane_b32 v2, s1, 4
; CHECK-NEXT: v_readlane_b32 s0, v2, 0
; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[2:3]
; CHECK-NEXT: v_readlane_b32 s2, v2, 5
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll
index c0200ee6f6ebcf5..80ae5f93ea66d8c 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll
@@ -4263,8 +4263,6 @@ define void @store_i64_stride4_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FAST: {{.*}}
; AVX2-FAST-PERLANE: {{.*}}
; AVX2-SLOW: {{.*}}
-; AVX512-FAST: {{.*}}
-; AVX512-SLOW: {{.*}}
; AVX512BW-FAST: {{.*}}
; AVX512BW-ONLY-FAST: {{.*}}
; AVX512BW-ONLY-SLOW: {{.*}}
More information about the llvm-commits
mailing list