[llvm] [AMDGPU] Add writelane and readlane pseudos for SGPR spilling (PR #69923)

[Christudasan Devadasan via llvm-commits]

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@@ -4301,7 +4311,9 @@ static bool shouldReadExec(const MachineInstr &MI) {
   if (SIInstrInfo::isVALU(MI)) {
     switch (MI.getOpcode()) {
     case AMDGPU::V_READLANE_B32:
+    case AMDGPU::SI_RELOAD_S32_FROM_VGPR:
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cdevadas wrote:

To avoid MIR verifier error. Even though readlane/writelane are VALU operations, we don't add implicit EXEC operand to them.

https://github.com/llvm/llvm-project/pull/69923