[llvm] [RISCV] Macro-fusion support for veyron-v1 CPU. (PR #70012)

[Craig Topper via llvm-commits]

================
@@ -27,29 +111,18 @@ static bool isLUIADDI(const MachineInstr *FirstMI,
   if (SecondMI.getOpcode() != RISCV::ADDI &&
       SecondMI.getOpcode() != RISCV::ADDIW)
     return false;
-
   // Assume the 1st instr to be a wildcard if it is unspecified.
   if (!FirstMI)
     return true;
 
   if (FirstMI->getOpcode() != RISCV::LUI)
     return false;
 
-  Register FirstDest = FirstMI->getOperand(0).getReg();
-
-  // Destination of LUI should be the ADDI(W) source register.
-  if (SecondMI.getOperand(1).getReg() != FirstDest)
+  // The first operand of ADDI might be a frame index.
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topperc wrote:

As was explained in #68701, if the ADDI operand isn't a register then there can be no data dependency between the LUI and the ADDi so it wouldn't be considered for macrofusion.

https://github.com/llvm/llvm-project/pull/70012