[llvm] [RISCV] Macro-fusion support for veyron-v1 CPU. (PR #70012)

[Mikhail Gudim via llvm-commits]

================
@@ -27,29 +111,18 @@ static bool isLUIADDI(const MachineInstr *FirstMI,
   if (SecondMI.getOpcode() != RISCV::ADDI &&
       SecondMI.getOpcode() != RISCV::ADDIW)
     return false;
-
   // Assume the 1st instr to be a wildcard if it is unspecified.
   if (!FirstMI)
     return true;
 
   if (FirstMI->getOpcode() != RISCV::LUI)
     return false;
 
-  Register FirstDest = FirstMI->getOperand(0).getReg();
-
-  // Destination of LUI should be the ADDI(W) source register.
-  if (SecondMI.getOperand(1).getReg() != FirstDest)
+  // The first operand of ADDI might be a frame index.
----------------
mgudim wrote:

In this code:

```
$rd0 =  lui $imm0
$rd1 = addi $rs0, $imm1
```

In order for fusion to happen it must be that `$rd0 == rd1` and `$rd0 == rs0`. Same for other fusions. Both checks are done in `checkRegisters` now. I think both checks were needed before two, according to this comment:

```
// Fuse LUI followed by ADDI or ADDIW.
// rd = imm[31:0] which decomposes to
// lui rd, imm[31:12]
// addi(w) rd, rd, imm[11:0]

```

https://github.com/llvm/llvm-project/pull/70012