[llvm] [RISCV] Add an experimental pseudoinstruction to represent a rematerializable constant materialization sequence. (PR #69983)

[Wang Pengcheng via llvm-commits]

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@@ -0,0 +1,156 @@
+//===-- RISCVPostRAExpandPseudoInsts.cpp - Expand pseudo instrs ----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains a pass that expands the pseudo instruction pseudolisimm32
+// into target instructions. This pass should be run during the post-regalloc
+// passes, before assembly emission. It is used when the TunePseudoLISimm32
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wangpc-pp wrote:

I don't see `TunePseudoLISimm32`.

https://github.com/llvm/llvm-project/pull/69983