[llvm] [RISCV] Apply `IsSignExtendingOpW = 1` on `fcvtmod.w.d` (PR #69633)

Min-Yih Hsu via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 19 14:55:39 PDT 2023


https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/69633


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