[llvm] [AArch64] Implement support to read/write FPMR (PR #69618)
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Thu Oct 19 11:04:55 PDT 2023
https://github.com/hassnaaHamdi updated https://github.com/llvm/llvm-project/pull/69618
>From 8ddd3dac6b7431d71c890859cbbbf29e864269d4 Mon Sep 17 00:00:00 2001
From: Caroline Concatto <caroline.concatto at arm.com>
Date: Wed, 25 Jan 2023 17:24:14 +0000
Subject: [PATCH] [AArch64] Implement support to read/write FPMR
Also add Read only registers:
ID_AA64FPFR0_EL1
ID_AA64ISAR3_EL1
This is based on this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09
Change-Id: If1d6071a2582ef8a1d4b54947981b2ef47e0a342
---
.../llvm/TargetParser/AArch64TargetParser.h | 4 ++-
llvm/lib/Target/AArch64/AArch64.td | 3 ++
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 2 ++
.../Target/AArch64/AArch64SystemOperands.td | 10 ++++++
.../AArch64/AsmParser/AArch64AsmParser.cpp | 1 +
llvm/test/MC/AArch64/FP8/system-regs.s | 32 +++++++++++++++++++
llvm/test/MC/AArch64/arm64-system-encoding.s | 2 ++
.../TargetParser/TargetParserTest.cpp | 4 ++-
8 files changed, 56 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/MC/AArch64/FP8/system-regs.s
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 616f2d79028615d..bf14473f133fab7 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -159,7 +159,8 @@ enum ArchExtKind : unsigned {
AEK_RASv2 = 55, // FEAT_RASv2
AEK_ITE = 56, // FEAT_ITE
AEK_GCS = 57, // FEAT_GCS
- AEK_NUM_EXTENSIONS = AEK_GCS + 1
+ AEK_FPMR = 58, // FEAT_FPMR
+ AEK_NUM_EXTENSIONS
};
using ExtensionBitset = Bitset<AEK_NUM_EXTENSIONS>;
// clang-format on
@@ -267,6 +268,7 @@ inline constexpr ExtensionInfo Extensions[] = {
{"tme", AArch64::AEK_TME, "+tme", "-tme", FEAT_INIT, "", 0},
{"wfxt", AArch64::AEK_NONE, {}, {}, FEAT_WFXT, "+wfxt", 550},
{"gcs", AArch64::AEK_GCS, "+gcs", "-gcs", FEAT_INIT, "", 0},
+ {"fpmr", AArch64::AEK_FPMR, "+fpmr", "-fpmr", FEAT_INIT, "", 0},
// Special cases
{"none", AArch64::AEK_NONE, {}, {}, FEAT_INIT, "", ExtensionInfo::MaxFMVPriority},
};
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 70973c92305aa62..ced1d4389203653 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -127,6 +127,9 @@ def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
"Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16]>;
+def FeatureFPMR : SubtargetFeature<"fpmr", "HasFPMR", "true",
+ "Enable FPMR Register (FEAT_FPMR)">;
+
// This flag is currently still labeled as Experimental, but when fully
// implemented this should tell the compiler to use the zeroing pseudos to
// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index df59dc4ad27fadb..382d3956f105f8c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -160,6 +160,8 @@ def HasSME2 : Predicate<"Subtarget->hasSME2()">,
AssemblerPredicateWithAll<(all_of FeatureSME2), "sme2">;
def HasSME2p1 : Predicate<"Subtarget->hasSME2p1()">,
AssemblerPredicateWithAll<(all_of FeatureSME2p1), "sme2p1">;
+def HasFPMR : Predicate<"Subtarget->hasFPMR()">,
+ AssemblerPredicateWithAll<(all_of FeatureFPMR), "fpmr">;
// A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
// they should be enabled if either has been specified.
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 3e7d4d81b242aa4..96afef6228b3350 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -743,6 +743,7 @@ def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>;
def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>;
def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>;
def : ROSysReg<"ID_AA64ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b010>;
+def : ROSysReg<"ID_AA64ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b011>;
def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>;
def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>;
def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010>;
@@ -1927,3 +1928,12 @@ def : RWSysReg<"PFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b101>;
// v9.4a Exception-based event profiling (FEAT_EBEP)
// Op0 Op1 CRn CRm Op2
def : RWSysReg<"PM", 0b11, 0b000, 0b0100, 0b0011, 0b001>;
+
+// 2023 ISA Extension
+// AArch64 Floating-point Mode Register controls behaviors of the FP8
+// instructions (FEAT_FPMR)
+let Requires = [{ {AArch64::FeatureFPMR} }] in {
+// Op0 Op1 CRn CRm Op2
+def : ROSysReg<"ID_AA64FPFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b111>;
+def : RWSysReg<"FPMR", 0b11, 0b011, 0b0100, 0b0100, 0b010>;
+}
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index cbcb49c3e2d74dc..6e70deec3f89092 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3638,6 +3638,7 @@ static const struct Extension {
{"sb", {AArch64::FeatureSB}},
{"ssbs", {AArch64::FeatureSSBS}},
{"tme", {AArch64::FeatureTME}},
+ {"fpmr", {AArch64::FeatureFPMR}},
};
static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
diff --git a/llvm/test/MC/AArch64/FP8/system-regs.s b/llvm/test/MC/AArch64/FP8/system-regs.s
new file mode 100644
index 000000000000000..4a396d4dff82bdd
--- /dev/null
+++ b/llvm/test/MC/AArch64/FP8/system-regs.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fpmr < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fpmr < %s \
+// RUN: | llvm-objdump -d --mattr=+fpmr - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fpmr < %s \
+// RUN: | llvm-objdump --mattr=-fpmr -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+// --------------------------------------------------------------------------//
+// read
+
+mrs x3, FPMR
+// CHECK-INST: mrs x3, FPMR
+// CHECK-ENCODING: [0x43,0x44,0x3b,0xd5]
+// CHECK-ERROR: expected readable system register
+// CHECK-UNKNOWN: d53b4443 mrs x3, S3_3_C4_C4_2
+
+mrs x3, ID_AA64FPFR0_EL1
+// CHECK-INST: mrs x3, ID_AA64FPFR0_EL1
+// CHECK-ENCODING: [0xe3,0x04,0x38,0xd5]
+// CHECK-ERROR: expected readable system register
+// CHECK-UNKNOWN: d53804e3 mrs x3, S3_0_C0_C4_7
+
+// --------------------------------------------------------------------------//
+// write
+
+msr FPMR, x3
+// CHECK-INST: msr FPMR, x3
+// CHECK-ENCODING: [0x43,0x44,0x1b,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: d51b4443 msr S3_3_C4_C4_2, x3
diff --git a/llvm/test/MC/AArch64/arm64-system-encoding.s b/llvm/test/MC/AArch64/arm64-system-encoding.s
index b30a0c4b0af8983..313ec9117746035 100644
--- a/llvm/test/MC/AArch64/arm64-system-encoding.s
+++ b/llvm/test/MC/AArch64/arm64-system-encoding.s
@@ -336,6 +336,7 @@ foo:
mrs x3, ID_AA64ISAR0_EL1
mrs x3, ID_AA64ISAR1_EL1
mrs x3, ID_AA64ISAR2_EL1
+ mrs x3, ID_AA64ISAR3_EL1
mrs x3, ID_AA64MMFR0_EL1
mrs x3, ID_AA64MMFR1_EL1
mrs x3, ID_AA64MMFR2_EL1
@@ -556,6 +557,7 @@ foo:
; CHECK: mrs x3, ID_AA64ISAR0_EL1 ; encoding: [0x03,0x06,0x38,0xd5]
; CHECK: mrs x3, ID_AA64ISAR1_EL1 ; encoding: [0x23,0x06,0x38,0xd5]
; CHECK: mrs x3, ID_AA64ISAR2_EL1 ; encoding: [0x43,0x06,0x38,0xd5]
+; CHECK: mrs x3, ID_AA64ISAR3_EL1 ; encoding: [0x63,0x06,0x38,0xd5]
; CHECK: mrs x3, ID_AA64MMFR0_EL1 ; encoding: [0x03,0x07,0x38,0xd5]
; CHECK: mrs x3, ID_AA64MMFR1_EL1 ; encoding: [0x23,0x07,0x38,0xd5]
; CHECK: mrs x3, ID_AA64MMFR2_EL1 ; encoding: [0x43,0x07,0x38,0xd5]
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index f8ef18efe5a086f..b432e7ac2d86871 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1731,7 +1731,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_B16B16, AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
AArch64::AEK_RCPC3, AArch64::AEK_THE, AArch64::AEK_D128,
AArch64::AEK_LSE128, AArch64::AEK_SPECRES2, AArch64::AEK_RASv2,
- AArch64::AEK_ITE, AArch64::AEK_GCS,
+ AArch64::AEK_ITE, AArch64::AEK_GCS, AArch64::AEK_FPMR,
};
std::vector<StringRef> Features;
@@ -1804,6 +1804,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+specres2"));
EXPECT_TRUE(llvm::is_contained(Features, "+ite"));
EXPECT_TRUE(llvm::is_contained(Features, "+gcs"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+fpmr"));
// Assuming we listed every extension above, this should produce the same
// result. (note that AEK_NONE doesn't have a name so it won't be in the
@@ -1927,6 +1928,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"predres2", "nopredres2", "+specres2", "-specres2"},
{"rasv2", "norasv2", "+rasv2", "-rasv2"},
{"gcs", "nogcs", "+gcs", "-gcs"},
+ {"fpmr", "nofpmr", "+fpmr", "-fpmr"},
};
for (unsigned i = 0; i < std::size(ArchExt); i++) {
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