[llvm] [AMDGPU] Constant fold FMAD_FTZ (PR #69443)
Pierre van Houtryve via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 18 23:43:21 PDT 2023
https://github.com/Pierre-vh updated https://github.com/llvm/llvm-project/pull/69443
>From 5ec3fc08aea321045233fe3f8944b2297a94a2a9 Mon Sep 17 00:00:00 2001
From: pvanhout <pierre.vanhoutryve at amd.com>
Date: Wed, 18 Oct 2023 12:21:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Constant fold FMAD_FTZ
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 13 +
.../AMDGPU/amdgpu-codegenprepare-idiv.ll | 1151 ++++++-----------
llvm/test/CodeGen/AMDGPU/udiv.ll | 116 +-
llvm/test/CodeGen/AMDGPU/udiv64.ll | 160 +--
llvm/test/CodeGen/AMDGPU/urem64.ll | 85 +-
5 files changed, 555 insertions(+), 970 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 607d59db7bcf709..10ac79d0fa0e1ba 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -5041,6 +5041,19 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
return performAssertSZExtCombine(N, DCI);
case ISD::INTRINSIC_WO_CHAIN:
return performIntrinsicWOChainCombine(N, DCI);
+ case AMDGPUISD::FMAD_FTZ: {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ EVT VT = N->getValueType(0);
+
+ // FMAD_FTZ is a FMAD, but flushing to zero is allowed (not required).
+ // if all operands are constant we can just constant-fold it like a FMAD.
+ if (isa<ConstantFPSDNode>(N0) && isa<ConstantFPSDNode>(N1) &&
+ isa<ConstantFPSDNode>(N2))
+ return DAG.getNode(ISD::FMAD, DL, VT, {N0, N1, N2});
+ break;
+ }
}
return SDValue();
}
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
index c793f9ee682f8c4..7eb1cb926c190de 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
@@ -7139,70 +7139,42 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
;
; GFX6-LABEL: udiv_i64_oddk_denom:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f176a73
-; GFX6-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GFX6-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
-; GFX6-NEXT: v_rcp_f32_e32 v0, v0
-; GFX6-NEXT: s_movk_i32 s4, 0xfee0
-; GFX6-NEXT: s_mov_b32 s5, 0x68958c89
+; GFX6-NEXT: s_add_u32 s4, 3, 0
+; GFX6-NEXT: v_mov_b32_e32 v0, 0xe3e0f6
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: s_addc_u32 s5, 0, 0
+; GFX6-NEXT: s_or_b32 s4, vcc_lo, vcc_hi
+; GFX6-NEXT: s_cmp_lg_u32 s4, 0
+; GFX6-NEXT: s_mov_b32 s4, 0x68958c89
+; GFX6-NEXT: s_movk_i32 s6, 0xfee0
+; GFX6-NEXT: v_mul_lo_u32 v1, v0, s6
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, s4
+; GFX6-NEXT: s_addc_u32 s5, s5, 0
+; GFX6-NEXT: s_mul_i32 s6, s5, 0x68958c89
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX6-NEXT: v_trunc_f32_e32 v1, v1
-; GFX6-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: s_movk_i32 s8, 0x11f
-; GFX6-NEXT: s_mov_b32 s9, 0x976a7377
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v0, s4
-; GFX6-NEXT: v_mul_hi_u32 v3, v0, s5
-; GFX6-NEXT: v_mul_lo_u32 v4, v1, s5
-; GFX6-NEXT: v_mul_lo_u32 v5, v0, s5
-; GFX6-NEXT: s_mov_b32 s7, 0xf000
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GFX6-NEXT: v_mul_lo_u32 v3, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v4, v0, v5
-; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; GFX6-NEXT: v_mul_lo_u32 v3, v0, v1
+; GFX6-NEXT: v_mul_hi_u32 v4, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v5, v0, v1
+; GFX6-NEXT: v_mul_hi_u32 v6, s5, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s5, v1
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
-; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5
-; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5
-; GFX6-NEXT: s_mov_b32 s6, -1
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX6-NEXT: v_mul_lo_u32 v2, v0, s4
-; GFX6-NEXT: v_mul_hi_u32 v3, v0, s5
-; GFX6-NEXT: v_mul_lo_u32 v4, v1, s5
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v5, s5, v2
+; GFX6-NEXT: v_mul_hi_u32 v2, s5, v2
+; GFX6-NEXT: s_movk_i32 s8, 0x11f
+; GFX6-NEXT: s_mov_b32 s9, 0x976a7377
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v6, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, s5
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s4, s0
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT: v_mul_lo_u32 v3, v0, s5
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2
-; GFX6-NEXT: v_mul_lo_u32 v4, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v5, v0, v3
-; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
-; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
-; GFX6-NEXT: s_mov_b32 s5, s1
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0
; GFX6-NEXT: v_mul_hi_u32 v4, s2, v1
@@ -7212,6 +7184,8 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
@@ -7221,6 +7195,7 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX6-NEXT: v_mul_hi_u32 v3, v0, s9
; GFX6-NEXT: v_mul_lo_u32 v4, v1, s9
; GFX6-NEXT: v_mov_b32_e32 v5, 0x11f
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_mul_lo_u32 v3, v0, s9
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2
@@ -7253,6 +7228,7 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s8, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
@@ -7260,44 +7236,14 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
;
; GFX9-LABEL: udiv_i64_oddk_denom:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f176a73
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GFX9-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
-; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX9-NEXT: v_trunc_f32_e32 v1, v1
-; GFX9-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: s_mul_i32 s1, s0, 0xfffffee0
-; GFX9-NEXT: s_mul_hi_u32 s2, s0, 0x68958c89
-; GFX9-NEXT: s_add_i32 s1, s2, s1
-; GFX9-NEXT: v_readfirstlane_b32 s2, v1
-; GFX9-NEXT: s_mul_i32 s3, s2, 0x68958c89
-; GFX9-NEXT: s_add_i32 s1, s1, s3
-; GFX9-NEXT: s_mul_i32 s9, s0, 0x68958c89
-; GFX9-NEXT: s_mul_hi_u32 s3, s0, s1
-; GFX9-NEXT: s_mul_i32 s8, s0, s1
-; GFX9-NEXT: s_mul_hi_u32 s0, s0, s9
-; GFX9-NEXT: s_add_u32 s0, s0, s8
-; GFX9-NEXT: s_addc_u32 s3, 0, s3
-; GFX9-NEXT: s_mul_hi_u32 s10, s2, s9
-; GFX9-NEXT: s_mul_i32 s9, s2, s9
-; GFX9-NEXT: s_add_u32 s0, s0, s9
-; GFX9-NEXT: s_mul_hi_u32 s8, s2, s1
-; GFX9-NEXT: s_addc_u32 s0, s3, s10
-; GFX9-NEXT: s_addc_u32 s3, s8, 0
-; GFX9-NEXT: s_mul_i32 s1, s2, s1
-; GFX9-NEXT: s_add_u32 s0, s0, s1
-; GFX9-NEXT: s_addc_u32 s1, 0, s3
+; GFX9-NEXT: s_add_u32 s0, 3, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, 0xe3e0f6
+; GFX9-NEXT: s_addc_u32 s1, 0, 0
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s0, s2, s1
; GFX9-NEXT: v_readfirstlane_b32 s2, v0
+; GFX9-NEXT: s_addc_u32 s0, s1, 0
; GFX9-NEXT: s_mul_i32 s3, s2, 0xfffffee0
; GFX9-NEXT: s_mul_hi_u32 s8, s2, 0x68958c89
; GFX9-NEXT: s_mul_i32 s1, s0, 0x68958c89
@@ -7385,6 +7331,7 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX9-NEXT: v_mov_b32_e32 v4, s2
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
@@ -7529,74 +7476,53 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(ptr addrspace(1) %out, <
;
; GFX6-LABEL: udiv_v2i64_mixed_pow2k_denom:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f800000
-; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000
-; GFX6-NEXT: v_rcp_f32_e32 v0, v0
-; GFX6-NEXT: s_movk_i32 s6, 0xf001
-; GFX6-NEXT: s_movk_i32 s8, 0xfff
-; GFX6-NEXT: s_mov_b32 s7, 0xf000
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX6-NEXT: v_trunc_f32_e32 v1, v1
-; GFX6-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
-; GFX6-NEXT: v_mul_hi_u32 v2, v0, s6
-; GFX6-NEXT: v_mul_lo_u32 v4, v1, s6
-; GFX6-NEXT: v_mul_lo_u32 v3, v0, s6
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s2, 0x2ff2fc01
+; GFX6-NEXT: v_bfrev_b32_e32 v0, 7
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], 12
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GFX6-NEXT: v_mul_hi_u32 v5, v0, v3
-; GFX6-NEXT: v_mul_lo_u32 v4, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
-; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX6-NEXT: v_mul_hi_u32 v2, v0, s6
-; GFX6-NEXT: v_mul_lo_u32 v3, v1, s6
-; GFX6-NEXT: v_mul_lo_u32 v4, v0, s6
-; GFX6-NEXT: s_mov_b32 s6, -1
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_mul_lo_u32 v3, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v5, v0, v4
-; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3
-; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
-; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1
-; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0
-; GFX6-NEXT: v_mul_hi_u32 v4, s2, v1
-; GFX6-NEXT: v_mul_hi_u32 v5, s3, v1
-; GFX6-NEXT: v_mul_lo_u32 v1, s3, v1
+; GFX6-NEXT: s_lshr_b64 s[4:5], s[4:5], 12
+; GFX6-NEXT: s_add_u32 s2, 0xe037f, s2
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, s2, v0
+; GFX6-NEXT: s_addc_u32 s3, 0, 0
+; GFX6-NEXT: s_or_b32 s2, vcc_lo, vcc_hi
+; GFX6-NEXT: s_cmp_lg_u32 s2, 0
+; GFX6-NEXT: s_movk_i32 s2, 0xf001
+; GFX6-NEXT: v_mul_hi_u32 v1, v0, s2
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2
+; GFX6-NEXT: s_addc_u32 s8, s3, 0x1000ff
+; GFX6-NEXT: s_mul_i32 s3, s8, 0xfffff001
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, s3, v1
+; GFX6-NEXT: v_mul_lo_u32 v3, v0, v1
+; GFX6-NEXT: v_mul_hi_u32 v4, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v5, v0, v1
+; GFX6-NEXT: v_mul_hi_u32 v6, s8, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s8, v1
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v5, s8, v2
+; GFX6-NEXT: v_mul_hi_u32 v2, s8, v2
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v6, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, s8
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, s6, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0
+; GFX6-NEXT: v_mul_hi_u32 v4, s6, v1
+; GFX6-NEXT: v_mul_hi_u32 v5, s7, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0
-; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0
+; GFX6-NEXT: s_movk_i32 s8, 0xfff
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
@@ -7610,73 +7536,46 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(ptr addrspace(1) %out, <
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 2, v0
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5
-; GFX6-NEXT: v_mov_b32_e32 v5, s3
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s2, v8
+; GFX6-NEXT: v_mov_b32_e32 v5, s7
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s6, v8
; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v5, v4, vcc
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s8, v8
; GFX6-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
-; GFX6-NEXT: s_movk_i32 s2, 0xffe
-; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s2, v5
+; GFX6-NEXT: s_movk_i32 s6, 0xffe
+; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s6, v5
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GFX6-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
-; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s2, v8
+; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s6, v8
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; GFX6-NEXT: v_cndmask_b32_e32 v4, -1, v5, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GFX6-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
-; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX9-LABEL: udiv_v2i64_mixed_pow2k_denom:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x457ff000
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GFX9-NEXT: v_mac_f32_e32 v0, 0, v1
-; GFX9-NEXT: v_rcp_f32_e32 v0, v0
-; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_mov_b32 s8, 0x2ff2fc01
+; GFX9-NEXT: v_bfrev_b32_e32 v0, 7
; GFX9-NEXT: v_mov_b32_e32 v4, 0
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX9-NEXT: v_trunc_f32_e32 v1, v1
-; GFX9-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshr_b64 s[0:1], s[4:5], 12
-; GFX9-NEXT: v_readfirstlane_b32 s4, v0
-; GFX9-NEXT: s_mul_hi_u32 s5, s4, 0xfffff001
-; GFX9-NEXT: v_readfirstlane_b32 s8, v1
-; GFX9-NEXT: s_sub_i32 s5, s5, s4
-; GFX9-NEXT: s_mul_i32 s9, s8, 0xfffff001
-; GFX9-NEXT: s_add_i32 s5, s5, s9
-; GFX9-NEXT: s_mul_i32 s11, s4, 0xfffff001
-; GFX9-NEXT: s_mul_hi_u32 s9, s4, s5
-; GFX9-NEXT: s_mul_i32 s10, s4, s5
-; GFX9-NEXT: s_mul_hi_u32 s4, s4, s11
-; GFX9-NEXT: s_add_u32 s4, s4, s10
-; GFX9-NEXT: s_addc_u32 s9, 0, s9
-; GFX9-NEXT: s_mul_hi_u32 s12, s8, s11
-; GFX9-NEXT: s_mul_i32 s11, s8, s11
-; GFX9-NEXT: s_add_u32 s4, s4, s11
-; GFX9-NEXT: s_mul_hi_u32 s10, s8, s5
-; GFX9-NEXT: s_addc_u32 s4, s9, s12
-; GFX9-NEXT: s_addc_u32 s9, s10, 0
-; GFX9-NEXT: s_mul_i32 s5, s8, s5
-; GFX9-NEXT: s_add_u32 s4, s4, s5
-; GFX9-NEXT: s_addc_u32 s5, 0, s9
+; GFX9-NEXT: s_add_u32 s4, 0xe037f, s8
+; GFX9-NEXT: s_addc_u32 s5, 0, 0
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s4, v0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s4, s8, s5
; GFX9-NEXT: v_readfirstlane_b32 s8, v0
+; GFX9-NEXT: s_addc_u32 s4, s5, 0x1000ff
; GFX9-NEXT: s_mul_hi_u32 s9, s8, 0xfffff001
; GFX9-NEXT: s_mul_i32 s5, s4, 0xfffff001
; GFX9-NEXT: s_sub_i32 s9, s9, s8
@@ -7824,165 +7723,110 @@ define amdgpu_kernel void @urem_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
;
; GFX6-LABEL: urem_i64_oddk_denom:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f1761f8
-; GFX6-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GFX6-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
-; GFX6-NEXT: v_rcp_f32_e32 v0, v0
+; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NEXT: s_add_u32 s0, 4, 0
+; GFX6-NEXT: v_mov_b32_e32 v0, 0xe3e0fc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: s_addc_u32 s1, 0, 0
+; GFX6-NEXT: s_or_b32 s0, vcc_lo, vcc_hi
+; GFX6-NEXT: s_cmp_lg_u32 s0, 0
+; GFX6-NEXT: s_mov_b32 s0, 0x689e0837
; GFX6-NEXT: s_movk_i32 s2, 0xfee0
-; GFX6-NEXT: s_mov_b32 s3, 0x689e0837
-; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX6-NEXT: v_trunc_f32_e32 v1, v1
-; GFX6-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, v0, s2
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, s0
+; GFX6-NEXT: s_addc_u32 s1, s1, 0
+; GFX6-NEXT: s_mul_i32 s2, s1, 0x689e0837
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_mov_b32 s8, s4
-; GFX6-NEXT: s_movk_i32 s4, 0x11f
-; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2
-; GFX6-NEXT: v_mul_hi_u32 v3, v0, s3
-; GFX6-NEXT: v_mul_lo_u32 v4, v1, s3
-; GFX6-NEXT: v_mul_lo_u32 v5, v0, s3
-; GFX6-NEXT: s_mov_b32 s12, 0x9761f7c9
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GFX6-NEXT: v_mul_lo_u32 v3, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v4, v0, v5
-; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT: s_mov_b32 s4, s8
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, s2, v1
+; GFX6-NEXT: v_mul_lo_u32 v3, v0, v1
+; GFX6-NEXT: v_mul_hi_u32 v4, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v5, v0, v1
+; GFX6-NEXT: v_mul_hi_u32 v6, s1, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
-; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5
-; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5
-; GFX6-NEXT: s_mov_b32 s9, s5
-; GFX6-NEXT: s_movk_i32 s5, 0x11e
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2
-; GFX6-NEXT: v_mul_hi_u32 v3, v0, s3
-; GFX6-NEXT: v_mul_lo_u32 v4, v1, s3
-; GFX6-NEXT: s_mov_b32 s11, 0xf000
-; GFX6-NEXT: s_mov_b32 s10, -1
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT: v_mul_lo_u32 v3, v0, s3
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2
-; GFX6-NEXT: v_mul_lo_u32 v4, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v5, v0, v3
-; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
-; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX6-NEXT: v_mul_lo_u32 v2, s6, v1
-; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0
-; GFX6-NEXT: v_mul_hi_u32 v4, s6, v1
-; GFX6-NEXT: v_mul_hi_u32 v5, s7, v1
-; GFX6-NEXT: v_mul_lo_u32 v1, s7, v1
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v5, s1, v2
+; GFX6-NEXT: v_mul_hi_u32 v2, s1, v2
+; GFX6-NEXT: s_movk_i32 s8, 0x11f
+; GFX6-NEXT: s_mov_b32 s12, 0x9761f7c9
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v6, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, s1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, s10, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s10, v0
+; GFX6-NEXT: v_mul_hi_u32 v4, s10, v1
+; GFX6-NEXT: v_mul_hi_u32 v5, s11, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s11, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0
-; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, s11, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0
+; GFX6-NEXT: s_mov_b32 s5, s9
+; GFX6-NEXT: s_movk_i32 s9, 0x11e
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
-; GFX6-NEXT: v_mul_lo_u32 v2, v0, s4
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s8
; GFX6-NEXT: v_mul_hi_u32 v3, v0, s12
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s12
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s12
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s7, v1
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s11, v1
; GFX6-NEXT: v_mov_b32_e32 v3, 0x11f
-; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s10, v0
; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
; GFX6-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0
; GFX6-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
-; GFX6-NEXT: v_cmp_lt_u32_e64 s[2:3], s5, v5
-; GFX6-NEXT: s_mov_b32 s6, 0x9761f7c8
+; GFX6-NEXT: v_cmp_lt_u32_e64 s[2:3], s9, v5
+; GFX6-NEXT: s_mov_b32 s10, 0x9761f7c8
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3]
-; GFX6-NEXT: v_cmp_lt_u32_e64 s[2:3], s6, v4
+; GFX6-NEXT: v_cmp_lt_u32_e64 s[2:3], s10, v4
; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
-; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s4, v5
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s8, v5
; GFX6-NEXT: v_subrev_i32_e64 v3, s[0:1], s12, v4
; GFX6-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3]
; GFX6-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
; GFX6-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[0:1]
-; GFX6-NEXT: v_mov_b32_e32 v4, s7
+; GFX6-NEXT: v_mov_b32_e32 v4, s11
; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc
-; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s5, v1
+; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s9, v1
; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
-; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
+; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s10, v0
; GFX6-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s4, v1
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s8, v1
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
; GFX9-LABEL: urem_i64_oddk_denom:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f1761f8
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GFX9-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
-; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NEXT: s_mov_b32 s12, 0x9761f7c8
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX9-NEXT: v_trunc_f32_e32 v1, v1
-; GFX9-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: s_mul_i32 s1, s0, 0xfffffee0
-; GFX9-NEXT: s_mul_hi_u32 s2, s0, 0x689e0837
-; GFX9-NEXT: s_add_i32 s1, s2, s1
-; GFX9-NEXT: v_readfirstlane_b32 s2, v1
-; GFX9-NEXT: s_mul_i32 s3, s2, 0x689e0837
-; GFX9-NEXT: s_add_i32 s1, s1, s3
-; GFX9-NEXT: s_mul_i32 s9, s0, 0x689e0837
-; GFX9-NEXT: s_mul_hi_u32 s3, s0, s1
-; GFX9-NEXT: s_mul_i32 s8, s0, s1
-; GFX9-NEXT: s_mul_hi_u32 s0, s0, s9
-; GFX9-NEXT: s_add_u32 s0, s0, s8
-; GFX9-NEXT: s_addc_u32 s3, 0, s3
-; GFX9-NEXT: s_mul_hi_u32 s10, s2, s9
-; GFX9-NEXT: s_mul_i32 s9, s2, s9
-; GFX9-NEXT: s_add_u32 s0, s0, s9
-; GFX9-NEXT: s_mul_hi_u32 s8, s2, s1
-; GFX9-NEXT: s_addc_u32 s0, s3, s10
-; GFX9-NEXT: s_addc_u32 s3, s8, 0
-; GFX9-NEXT: s_mul_i32 s1, s2, s1
-; GFX9-NEXT: s_add_u32 s0, s0, s1
-; GFX9-NEXT: s_addc_u32 s1, 0, s3
+; GFX9-NEXT: s_add_u32 s0, 4, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, 0xe3e0fc
+; GFX9-NEXT: s_addc_u32 s1, 0, 0
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s0, s2, s1
; GFX9-NEXT: v_readfirstlane_b32 s2, v0
+; GFX9-NEXT: s_addc_u32 s0, s1, 0
; GFX9-NEXT: s_mul_i32 s3, s2, 0xfffffee0
; GFX9-NEXT: s_mul_hi_u32 s8, s2, 0x689e0837
; GFX9-NEXT: s_mul_i32 s1, s0, 0x689e0837
@@ -8038,6 +7882,7 @@ define amdgpu_kernel void @urem_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: s_subb_u32 s10, s6, 0
; GFX9-NEXT: s_cmpk_gt_u32 s10, 0x11e
+; GFX9-NEXT: s_mov_b32 s12, 0x9761f7c8
; GFX9-NEXT: s_cselect_b32 s11, -1, 0
; GFX9-NEXT: v_cmp_lt_u32_e64 s[2:3], s12, v1
; GFX9-NEXT: s_cmpk_eq_i32 s10, 0x11f
@@ -8067,6 +7912,7 @@ define amdgpu_kernel void @urem_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX9-NEXT: v_mov_b32_e32 v5, s0
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
@@ -8274,69 +8120,44 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
;
; GFX6-LABEL: sdiv_i64_oddk_denom:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f800000
-; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8
-; GFX6-NEXT: v_rcp_f32_e32 v0, v0
-; GFX6-NEXT: s_mov_b32 s8, 0xffed2705
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT: s_mov_b32 s3, 0xf000
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX6-NEXT: v_trunc_f32_e32 v1, v1
-; GFX6-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: s_mov_b32 s0, 0x33fe64
+; GFX6-NEXT: s_add_u32 s1, 0x396, s0
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x28100000
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, s1, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s0, s4
-; GFX6-NEXT: s_mov_b32 s4, 0x12d8fb
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, s8
-; GFX6-NEXT: v_mul_hi_u32 v3, v0, s8
-; GFX6-NEXT: v_mul_lo_u32 v4, v0, s8
-; GFX6-NEXT: s_mov_b32 s2, -1
-; GFX6-NEXT: s_mov_b32 s1, s5
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; GFX6-NEXT: v_mul_hi_u32 v3, v0, v4
-; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX6-NEXT: s_addc_u32 s4, 0, 0
+; GFX6-NEXT: s_or_b32 s1, vcc_lo, vcc_hi
+; GFX6-NEXT: s_cmp_lg_u32 s1, 0
+; GFX6-NEXT: s_mov_b32 s1, 0xffed2705
+; GFX6-NEXT: v_mul_hi_u32 v1, v0, s1
+; GFX6-NEXT: s_addc_u32 s4, s4, 0xd95
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s1
+; GFX6-NEXT: s_mul_i32 s8, s4, 0xffed2705
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, s8, v1
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v0
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
-; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, s8
-; GFX6-NEXT: v_mul_hi_u32 v3, v0, s8
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT: v_mul_lo_u32 v3, v0, s8
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; GFX6-NEXT: v_mul_lo_u32 v6, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v7, v0, v3
-; GFX6-NEXT: v_mul_hi_u32 v8, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v5, v1, v3
-; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3
-; GFX6-NEXT: v_mul_hi_u32 v4, v1, v2
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6
-; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_mul_hi_u32 v7, v0, v1
+; GFX6-NEXT: v_mul_hi_u32 v4, s4, v2
+; GFX6-NEXT: v_mul_lo_u32 v2, s4, v2
+; GFX6-NEXT: v_mul_hi_u32 v3, s4, v1
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc
+; GFX6-NEXT: v_mul_lo_u32 v1, s4, v1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v6, v4, vcc
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: s_ashr_i32 s8, s7, 31
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
; GFX6-NEXT: s_add_u32 s6, s6, s8
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, s4
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: s_mov_b32 s9, s8
; GFX6-NEXT: s_addc_u32 s7, s7, s8
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc
; GFX6-NEXT: s_xor_b64 s[6:7], s[6:7], s[8:9]
; GFX6-NEXT: v_mul_lo_u32 v2, s6, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0
@@ -8347,6 +8168,8 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0
+; GFX6-NEXT: s_mov_b32 s4, 0x12d8fb
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
@@ -8377,55 +8200,28 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; GFX6-NEXT: v_cndmask_b32_e32 v4, -1, v5, vcc
-; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0
-; GFX6-NEXT: v_xor_b32_e32 v1, s8, v1
-; GFX6-NEXT: v_mov_b32_e32 v2, s8
-; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
-; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
-; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX6-NEXT: s_endpgm
-;
-; GFX9-LABEL: sdiv_i64_oddk_denom:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x4996c7d8
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GFX9-NEXT: v_mac_f32_e32 v0, 0, v1
-; GFX9-NEXT: v_rcp_f32_e32 v0, v0
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX9-NEXT: v_trunc_f32_e32 v1, v1
-; GFX9-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s4, v1
-; GFX9-NEXT: v_readfirstlane_b32 s5, v0
-; GFX9-NEXT: s_mul_hi_u32 s6, s5, 0xffed2705
-; GFX9-NEXT: s_mul_i32 s7, s4, 0xffed2705
-; GFX9-NEXT: s_add_i32 s6, s6, s7
-; GFX9-NEXT: s_sub_i32 s6, s6, s5
-; GFX9-NEXT: s_mul_i32 s9, s5, 0xffed2705
-; GFX9-NEXT: s_mul_hi_u32 s7, s5, s6
-; GFX9-NEXT: s_mul_i32 s8, s5, s6
-; GFX9-NEXT: s_mul_hi_u32 s5, s5, s9
-; GFX9-NEXT: s_add_u32 s5, s5, s8
-; GFX9-NEXT: s_addc_u32 s7, 0, s7
-; GFX9-NEXT: s_mul_hi_u32 s10, s4, s9
-; GFX9-NEXT: s_mul_i32 s9, s4, s9
-; GFX9-NEXT: s_add_u32 s5, s5, s9
-; GFX9-NEXT: s_mul_hi_u32 s8, s4, s6
-; GFX9-NEXT: s_addc_u32 s5, s7, s10
-; GFX9-NEXT: s_addc_u32 s7, s8, 0
-; GFX9-NEXT: s_mul_i32 s6, s4, s6
-; GFX9-NEXT: s_add_u32 s5, s5, s6
-; GFX9-NEXT: s_addc_u32 s6, 0, s7
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s5, v0
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0
+; GFX6-NEXT: v_xor_b32_e32 v1, s8, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, s8
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_i64_oddk_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_mov_b32 s4, 0x33fe64
+; GFX9-NEXT: s_add_u32 s4, 0x396, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x28100000
+; GFX9-NEXT: s_addc_u32 s5, 0, 0
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s4, v0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s4, s4, s6
+; GFX9-NEXT: s_addc_u32 s4, s5, 0xd95
; GFX9-NEXT: v_readfirstlane_b32 s6, v0
; GFX9-NEXT: s_mul_i32 s5, s4, 0xffed2705
; GFX9-NEXT: s_mul_hi_u32 s7, s6, 0xffed2705
@@ -8440,6 +8236,7 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX9-NEXT: s_mul_i32 s10, s4, s8
; GFX9-NEXT: s_addc_u32 s8, 0, s11
; GFX9-NEXT: s_add_u32 s6, s6, s10
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_mul_hi_u32 s7, s4, s5
; GFX9-NEXT: s_addc_u32 s6, s8, s9
; GFX9-NEXT: s_addc_u32 s7, s7, 0
@@ -8455,65 +8252,59 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX9-NEXT: s_mov_b32 s5, s4
; GFX9-NEXT: s_addc_u32 s3, s3, s4
; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
-; GFX9-NEXT: v_readfirstlane_b32 s8, v0
-; GFX9-NEXT: s_mul_i32 s7, s2, s6
-; GFX9-NEXT: s_mul_hi_u32 s9, s2, s8
-; GFX9-NEXT: s_mul_hi_u32 s5, s2, s6
-; GFX9-NEXT: s_add_u32 s7, s9, s7
-; GFX9-NEXT: s_addc_u32 s5, 0, s5
-; GFX9-NEXT: s_mul_hi_u32 s10, s3, s8
-; GFX9-NEXT: s_mul_i32 s8, s3, s8
-; GFX9-NEXT: s_add_u32 s7, s7, s8
-; GFX9-NEXT: s_mul_hi_u32 s9, s3, s6
-; GFX9-NEXT: s_addc_u32 s5, s5, s10
-; GFX9-NEXT: s_addc_u32 s7, s9, 0
+; GFX9-NEXT: v_readfirstlane_b32 s9, v0
+; GFX9-NEXT: s_mul_i32 s8, s2, s6
+; GFX9-NEXT: s_mul_hi_u32 s10, s2, s9
+; GFX9-NEXT: s_mul_hi_u32 s7, s2, s6
+; GFX9-NEXT: s_add_u32 s8, s10, s8
+; GFX9-NEXT: s_addc_u32 s7, 0, s7
+; GFX9-NEXT: s_mul_hi_u32 s11, s3, s9
+; GFX9-NEXT: s_mul_i32 s9, s3, s9
+; GFX9-NEXT: s_add_u32 s8, s8, s9
+; GFX9-NEXT: s_mul_hi_u32 s10, s3, s6
+; GFX9-NEXT: s_addc_u32 s7, s7, s11
+; GFX9-NEXT: s_addc_u32 s8, s10, 0
; GFX9-NEXT: s_mul_i32 s6, s3, s6
-; GFX9-NEXT: s_add_u32 s5, s5, s6
-; GFX9-NEXT: s_addc_u32 s6, 0, s7
-; GFX9-NEXT: s_add_u32 s7, s5, 1
-; GFX9-NEXT: s_addc_u32 s8, s6, 0
-; GFX9-NEXT: s_add_u32 s9, s5, 2
-; GFX9-NEXT: s_mul_i32 s12, s6, 0x12d8fb
-; GFX9-NEXT: s_mul_hi_u32 s13, s5, 0x12d8fb
-; GFX9-NEXT: s_addc_u32 s10, s6, 0
-; GFX9-NEXT: s_add_i32 s13, s13, s12
-; GFX9-NEXT: s_mul_i32 s12, s5, 0x12d8fb
-; GFX9-NEXT: v_mov_b32_e32 v0, s12
+; GFX9-NEXT: s_add_u32 s6, s7, s6
+; GFX9-NEXT: s_addc_u32 s7, 0, s8
+; GFX9-NEXT: s_add_u32 s8, s6, 1
+; GFX9-NEXT: s_addc_u32 s9, s7, 0
+; GFX9-NEXT: s_add_u32 s10, s6, 2
+; GFX9-NEXT: s_mul_i32 s13, s7, 0x12d8fb
+; GFX9-NEXT: s_mul_hi_u32 s14, s6, 0x12d8fb
+; GFX9-NEXT: s_addc_u32 s11, s7, 0
+; GFX9-NEXT: s_add_i32 s14, s14, s13
+; GFX9-NEXT: s_mul_i32 s13, s6, 0x12d8fb
+; GFX9-NEXT: v_mov_b32_e32 v0, s13
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s2, v0
-; GFX9-NEXT: s_mov_b32 s11, 0x12d8fb
+; GFX9-NEXT: s_mov_b32 s12, 0x12d8fb
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_subb_u32 s2, s3, s13
-; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s11, v0
+; GFX9-NEXT: s_subb_u32 s2, s3, s14
+; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s12, v0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_subb_u32 s3, s2, 0
-; GFX9-NEXT: s_mov_b32 s11, 0x12d8fa
-; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s11, v1
+; GFX9-NEXT: v_readfirstlane_b32 s12, v1
+; GFX9-NEXT: s_cmp_gt_u32 s12, 0x12d8fa
+; GFX9-NEXT: s_cselect_b32 s12, -1, 0
; GFX9-NEXT: s_cmp_eq_u32 s3, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
-; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v1, -1, v1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v3, s7
-; GFX9-NEXT: v_mov_b32_e32 v4, s9
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX9-NEXT: v_mov_b32_e32 v3, s8
-; GFX9-NEXT: v_mov_b32_e32 v4, s10
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s11, v0
+; GFX9-NEXT: s_cselect_b32 s3, s12, -1
+; GFX9-NEXT: s_cmp_lg_u32 s3, 0
+; GFX9-NEXT: s_cselect_b32 s3, s11, s9
+; GFX9-NEXT: v_readfirstlane_b32 s9, v0
+; GFX9-NEXT: s_cselect_b32 s8, s10, s8
+; GFX9-NEXT: s_cmp_gt_u32 s9, 0x12d8fa
+; GFX9-NEXT: s_cselect_b32 s9, -1, 0
; GFX9-NEXT: s_cmp_eq_u32 s2, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
-; GFX9-NEXT: v_mov_b32_e32 v4, s6
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc
-; GFX9-NEXT: v_mov_b32_e32 v3, s5
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1
-; GFX9-NEXT: v_xor_b32_e32 v3, s4, v0
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
-; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s4, v1
-; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v3, v4, vcc
+; GFX9-NEXT: s_cselect_b32 s2, s9, -1
+; GFX9-NEXT: s_cmp_lg_u32 s2, 0
+; GFX9-NEXT: s_cselect_b32 s3, s3, s7
+; GFX9-NEXT: s_cselect_b32 s2, s8, s6
+; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
+; GFX9-NEXT: s_sub_u32 s2, s2, s4
+; GFX9-NEXT: s_subb_u32 s3, s3, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9-NEXT: s_endpgm
%r = sdiv i64 %x, 1235195
@@ -8940,84 +8731,62 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(ptr addrspace(1) %out,
;
; GFX6-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v0, 0x457ff000
-; GFX6-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GFX6-NEXT: v_mac_f32_e32 v0, 0, v1
-; GFX6-NEXT: v_rcp_f32_e32 v0, v0
-; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
-; GFX6-NEXT: s_movk_i32 s6, 0xf001
-; GFX6-NEXT: s_mov_b32 s7, 0xf000
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX6-NEXT: v_trunc_f32_e32 v1, v1
-; GFX6-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s2, 0x2ff2fc01
+; GFX6-NEXT: v_bfrev_b32_e32 v0, 7
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_ashr_i32 s8, s1, 31
+; GFX6-NEXT: s_ashr_i32 s8, s5, 31
; GFX6-NEXT: s_lshr_b32 s8, s8, 20
-; GFX6-NEXT: v_mul_hi_u32 v2, v0, s6
-; GFX6-NEXT: v_mul_lo_u32 v3, v1, s6
-; GFX6-NEXT: s_add_u32 s0, s0, s8
-; GFX6-NEXT: s_addc_u32 s1, s1, 0
-; GFX6-NEXT: s_ashr_i64 s[0:1], s[0:1], 12
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_mul_lo_u32 v3, v0, s6
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; GFX6-NEXT: v_mul_lo_u32 v4, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v5, v0, v3
+; GFX6-NEXT: s_add_u32 s4, s4, s8
+; GFX6-NEXT: s_addc_u32 s5, s5, 0
+; GFX6-NEXT: s_ashr_i64 s[4:5], s[4:5], 12
+; GFX6-NEXT: s_add_u32 s2, 0xe037f, s2
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, s2, v0
+; GFX6-NEXT: s_addc_u32 s8, 0, 0
+; GFX6-NEXT: s_or_b32 s2, vcc_lo, vcc_hi
+; GFX6-NEXT: s_cmp_lg_u32 s2, 0
+; GFX6-NEXT: s_movk_i32 s2, 0xf001
+; GFX6-NEXT: v_mul_hi_u32 v1, v0, s2
+; GFX6-NEXT: s_addc_u32 s8, s8, 0x1000ff
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2
+; GFX6-NEXT: s_mul_i32 s9, s8, 0xfffff001
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, s9, v1
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v0
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
-; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
-; GFX6-NEXT: s_ashr_i32 s8, s3, 31
-; GFX6-NEXT: s_add_u32 s2, s2, s8
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, s6
-; GFX6-NEXT: v_mul_hi_u32 v3, v0, s6
+; GFX6-NEXT: v_mul_hi_u32 v7, v0, v1
+; GFX6-NEXT: v_mul_hi_u32 v4, s8, v2
+; GFX6-NEXT: v_mul_lo_u32 v2, s8, v2
+; GFX6-NEXT: v_mul_hi_u32 v3, s8, v1
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc
+; GFX6-NEXT: v_mul_lo_u32 v1, s8, v1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v6, v4, vcc
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v3, s8
+; GFX6-NEXT: s_ashr_i32 s8, s7, 31
+; GFX6-NEXT: s_add_u32 s6, s6, s8
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: s_mov_b32 s9, s8
-; GFX6-NEXT: s_addc_u32 s3, s3, s8
-; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9]
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT: v_mul_lo_u32 v3, v0, s6
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; GFX6-NEXT: v_mul_lo_u32 v6, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v7, v0, v3
-; GFX6-NEXT: v_mul_hi_u32 v8, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v5, v1, v3
-; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3
-; GFX6-NEXT: v_mul_hi_u32 v4, v1, v2
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6
-; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1
-; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0
-; GFX6-NEXT: v_mul_hi_u32 v4, s2, v1
-; GFX6-NEXT: v_mul_hi_u32 v5, s3, v1
-; GFX6-NEXT: v_mul_lo_u32 v1, s3, v1
+; GFX6-NEXT: s_addc_u32 s7, s7, s8
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc
+; GFX6-NEXT: s_xor_b64 s[6:7], s[6:7], s[8:9]
+; GFX6-NEXT: v_mul_lo_u32 v2, s6, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0
+; GFX6-NEXT: v_mul_hi_u32 v4, s6, v1
+; GFX6-NEXT: v_mul_hi_u32 v5, s7, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0
-; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX6-NEXT: s_movk_i32 s9, 0xfff
-; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
@@ -9031,20 +8800,20 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(ptr addrspace(1) %out,
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 2, v0
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5
-; GFX6-NEXT: v_mov_b32_e32 v5, s3
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s2, v8
+; GFX6-NEXT: v_mov_b32_e32 v5, s7
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s6, v8
; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v5, v4, vcc
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s9, v8
; GFX6-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
-; GFX6-NEXT: s_movk_i32 s2, 0xffe
-; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s2, v5
+; GFX6-NEXT: s_movk_i32 s6, 0xffe
+; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s6, v5
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GFX6-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
-; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s2, v8
+; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s6, v8
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; GFX6-NEXT: v_cndmask_b32_e32 v4, -1, v5, vcc
@@ -9056,57 +8825,30 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(ptr addrspace(1) %out,
; GFX6-NEXT: v_mov_b32_e32 v3, s8
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s8, v0
; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
-; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX9-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x457ff000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x4f800000
-; GFX9-NEXT: v_mac_f32_e32 v1, 0, v2
-; GFX9-NEXT: v_rcp_f32_e32 v1, v1
-; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
-; GFX9-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
-; GFX9-NEXT: v_trunc_f32_e32 v2, v2
-; GFX9-NEXT: v_madmk_f32 v1, v2, 0xcf800000, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_mov_b32 s8, 0x2ff2fc01
+; GFX9-NEXT: v_bfrev_b32_e32 v0, 7
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s0, s5, 31
; GFX9-NEXT: s_lshr_b32 s0, s0, 20
; GFX9-NEXT: s_add_u32 s0, s4, s0
-; GFX9-NEXT: v_readfirstlane_b32 s4, v1
-; GFX9-NEXT: v_readfirstlane_b32 s8, v2
; GFX9-NEXT: s_addc_u32 s1, s5, 0
-; GFX9-NEXT: s_mul_hi_u32 s5, s4, 0xfffff001
-; GFX9-NEXT: s_mul_i32 s9, s8, 0xfffff001
-; GFX9-NEXT: s_add_i32 s5, s5, s9
-; GFX9-NEXT: s_sub_i32 s5, s5, s4
-; GFX9-NEXT: s_mul_i32 s11, s4, 0xfffff001
; GFX9-NEXT: s_ashr_i64 s[0:1], s[0:1], 12
-; GFX9-NEXT: s_mul_hi_u32 s9, s4, s5
-; GFX9-NEXT: s_mul_i32 s10, s4, s5
-; GFX9-NEXT: s_mul_hi_u32 s4, s4, s11
-; GFX9-NEXT: s_add_u32 s4, s4, s10
-; GFX9-NEXT: s_addc_u32 s9, 0, s9
-; GFX9-NEXT: s_mul_hi_u32 s12, s8, s11
-; GFX9-NEXT: s_mul_i32 s11, s8, s11
-; GFX9-NEXT: s_add_u32 s4, s4, s11
-; GFX9-NEXT: s_mul_hi_u32 s10, s8, s5
-; GFX9-NEXT: s_addc_u32 s4, s9, s12
-; GFX9-NEXT: s_addc_u32 s9, s10, 0
-; GFX9-NEXT: s_mul_i32 s5, s8, s5
-; GFX9-NEXT: s_add_u32 s4, s4, s5
-; GFX9-NEXT: s_addc_u32 s5, 0, s9
-; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s4, v1
+; GFX9-NEXT: s_add_u32 s4, 0xe037f, s8
+; GFX9-NEXT: s_addc_u32 s5, 0, 0
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s4, v0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s4, s8, s5
-; GFX9-NEXT: v_readfirstlane_b32 s8, v1
+; GFX9-NEXT: s_addc_u32 s4, s5, 0x1000ff
+; GFX9-NEXT: v_readfirstlane_b32 s8, v0
; GFX9-NEXT: s_mul_i32 s5, s4, 0xfffff001
; GFX9-NEXT: s_mul_hi_u32 s9, s8, 0xfffff001
; GFX9-NEXT: s_add_i32 s9, s9, s5
@@ -9126,7 +8868,7 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(ptr addrspace(1) %out,
; GFX9-NEXT: s_mul_i32 s5, s4, s5
; GFX9-NEXT: s_add_u32 s5, s8, s5
; GFX9-NEXT: s_addc_u32 s8, 0, s9
-; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s5, v1
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s5, v0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_addc_u32 s8, s4, s8
; GFX9-NEXT: s_ashr_i32 s4, s7, 31
@@ -9134,68 +8876,61 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(ptr addrspace(1) %out,
; GFX9-NEXT: s_mov_b32 s5, s4
; GFX9-NEXT: s_addc_u32 s7, s7, s4
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
-; GFX9-NEXT: v_readfirstlane_b32 s10, v1
-; GFX9-NEXT: s_mul_i32 s9, s6, s8
-; GFX9-NEXT: s_mul_hi_u32 s11, s6, s10
-; GFX9-NEXT: s_mul_hi_u32 s5, s6, s8
-; GFX9-NEXT: s_add_u32 s9, s11, s9
-; GFX9-NEXT: s_addc_u32 s5, 0, s5
-; GFX9-NEXT: s_mul_hi_u32 s12, s7, s10
-; GFX9-NEXT: s_mul_i32 s10, s7, s10
-; GFX9-NEXT: s_add_u32 s9, s9, s10
-; GFX9-NEXT: s_mul_hi_u32 s11, s7, s8
-; GFX9-NEXT: s_addc_u32 s5, s5, s12
-; GFX9-NEXT: s_addc_u32 s9, s11, 0
+; GFX9-NEXT: v_readfirstlane_b32 s11, v0
+; GFX9-NEXT: s_mul_i32 s10, s6, s8
+; GFX9-NEXT: s_mul_hi_u32 s12, s6, s11
+; GFX9-NEXT: s_mul_hi_u32 s9, s6, s8
+; GFX9-NEXT: s_add_u32 s10, s12, s10
+; GFX9-NEXT: s_addc_u32 s9, 0, s9
+; GFX9-NEXT: s_mul_hi_u32 s13, s7, s11
+; GFX9-NEXT: s_mul_i32 s11, s7, s11
+; GFX9-NEXT: s_add_u32 s10, s10, s11
+; GFX9-NEXT: s_mul_hi_u32 s12, s7, s8
+; GFX9-NEXT: s_addc_u32 s9, s9, s13
+; GFX9-NEXT: s_addc_u32 s10, s12, 0
; GFX9-NEXT: s_mul_i32 s8, s7, s8
-; GFX9-NEXT: s_add_u32 s5, s5, s8
-; GFX9-NEXT: s_addc_u32 s8, 0, s9
-; GFX9-NEXT: s_add_u32 s9, s5, 1
-; GFX9-NEXT: s_addc_u32 s10, s8, 0
-; GFX9-NEXT: s_add_u32 s11, s5, 2
-; GFX9-NEXT: s_mul_i32 s14, s8, 0xfff
-; GFX9-NEXT: s_mul_hi_u32 s15, s5, 0xfff
-; GFX9-NEXT: s_addc_u32 s12, s8, 0
-; GFX9-NEXT: s_add_i32 s15, s15, s14
-; GFX9-NEXT: s_mul_i32 s14, s5, 0xfff
-; GFX9-NEXT: v_mov_b32_e32 v1, s14
-; GFX9-NEXT: v_sub_co_u32_e32 v1, vcc, s6, v1
-; GFX9-NEXT: s_movk_i32 s13, 0xfff
+; GFX9-NEXT: s_add_u32 s8, s9, s8
+; GFX9-NEXT: s_addc_u32 s9, 0, s10
+; GFX9-NEXT: s_add_u32 s10, s8, 1
+; GFX9-NEXT: s_addc_u32 s11, s9, 0
+; GFX9-NEXT: s_add_u32 s12, s8, 2
+; GFX9-NEXT: s_mul_i32 s15, s9, 0xfff
+; GFX9-NEXT: s_mul_hi_u32 s16, s8, 0xfff
+; GFX9-NEXT: s_addc_u32 s13, s9, 0
+; GFX9-NEXT: s_add_i32 s16, s16, s15
+; GFX9-NEXT: s_mul_i32 s15, s8, 0xfff
+; GFX9-NEXT: v_mov_b32_e32 v0, s15
+; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s6, v0
+; GFX9-NEXT: s_movk_i32 s14, 0xfff
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_subb_u32 s6, s7, s15
-; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s13, v1
+; GFX9-NEXT: s_subb_u32 s6, s7, s16
+; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s14, v0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_subb_u32 s7, s6, 0
-; GFX9-NEXT: s_movk_i32 s13, 0xffe
-; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s13, v2
+; GFX9-NEXT: v_readfirstlane_b32 s14, v1
+; GFX9-NEXT: s_cmpk_gt_u32 s14, 0xffe
+; GFX9-NEXT: s_cselect_b32 s14, -1, 0
; GFX9-NEXT: s_cmp_eq_u32 s7, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
-; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc
-; GFX9-NEXT: v_mov_b32_e32 v3, s9
-; GFX9-NEXT: v_mov_b32_e32 v4, s11
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
-; GFX9-NEXT: v_mov_b32_e32 v4, s12
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s13, v1
+; GFX9-NEXT: s_cselect_b32 s7, s14, -1
+; GFX9-NEXT: s_cmp_lg_u32 s7, 0
+; GFX9-NEXT: s_cselect_b32 s7, s13, s11
+; GFX9-NEXT: v_readfirstlane_b32 s11, v0
+; GFX9-NEXT: s_cselect_b32 s10, s12, s10
+; GFX9-NEXT: s_cmpk_gt_u32 s11, 0xffe
+; GFX9-NEXT: s_cselect_b32 s11, -1, 0
; GFX9-NEXT: s_cmp_eq_u32 s6, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
-; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v1, -1, v1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v4, s8
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
-; GFX9-NEXT: v_mov_b32_e32 v3, s5
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX9-NEXT: v_xor_b32_e32 v2, s4, v2
-; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1
-; GFX9-NEXT: v_mov_b32_e32 v4, s4
-; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s4, v2
-; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v1, v4, vcc
-; GFX9-NEXT: v_mov_b32_e32 v1, s0
-; GFX9-NEXT: v_mov_b32_e32 v2, s1
-; GFX9-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3]
+; GFX9-NEXT: s_cselect_b32 s6, s11, -1
+; GFX9-NEXT: s_cmp_lg_u32 s6, 0
+; GFX9-NEXT: s_cselect_b32 s7, s7, s9
+; GFX9-NEXT: s_cselect_b32 s6, s10, s8
+; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
+; GFX9-NEXT: s_sub_u32 s5, s6, s4
+; GFX9-NEXT: s_subb_u32 s4, s7, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-NEXT: v_mov_b32_e32 v3, s4
+; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
; GFX9-NEXT: s_endpgm
%r = sdiv <2 x i64> %x, <i64 4096, i64 4095>
store <2 x i64> %r, ptr addrspace(1) %out
@@ -9780,66 +9515,43 @@ define amdgpu_kernel void @srem_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
;
; GFX6-LABEL: srem_i64_oddk_denom:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f800000
-; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8
-; GFX6-NEXT: v_rcp_f32_e32 v0, v0
-; GFX6-NEXT: s_mov_b32 s8, 0xffed2705
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT: s_mov_b32 s3, 0xf000
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX6-NEXT: v_trunc_f32_e32 v1, v1
-; GFX6-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: s_mov_b32 s2, -1
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, s8
-; GFX6-NEXT: v_mul_hi_u32 v3, v0, s8
-; GFX6-NEXT: v_mul_lo_u32 v4, v0, s8
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; GFX6-NEXT: v_mul_hi_u32 v3, v0, v4
-; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX6-NEXT: s_mov_b32 s0, 0x33fe64
+; GFX6-NEXT: s_add_u32 s0, 0x396, s0
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x28100000
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: s_addc_u32 s1, 0, 0
+; GFX6-NEXT: s_or_b32 s0, vcc_lo, vcc_hi
+; GFX6-NEXT: s_cmp_lg_u32 s0, 0
+; GFX6-NEXT: s_mov_b32 s0, 0xffed2705
+; GFX6-NEXT: v_mul_hi_u32 v1, v0, s0
+; GFX6-NEXT: s_addc_u32 s1, s1, 0xd95
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s0
+; GFX6-NEXT: s_mul_i32 s8, s1, 0xffed2705
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, s8, v1
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v0
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
-; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, s8
-; GFX6-NEXT: v_mul_hi_u32 v3, v0, s8
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT: v_mul_lo_u32 v3, v0, s8
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; GFX6-NEXT: v_mul_lo_u32 v6, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v7, v0, v3
-; GFX6-NEXT: v_mul_hi_u32 v8, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v5, v1, v3
-; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3
-; GFX6-NEXT: v_mul_hi_u32 v4, v1, v2
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6
-; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
-; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc
-; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_mul_hi_u32 v7, v0, v1
+; GFX6-NEXT: v_mul_hi_u32 v4, s1, v2
+; GFX6-NEXT: v_mul_lo_u32 v2, s1, v2
+; GFX6-NEXT: v_mul_hi_u32 v3, s1, v1
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc
+; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v6, v4, vcc
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_ashr_i32 s8, s7, 31
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
; GFX6-NEXT: s_add_u32 s0, s6, s8
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, s1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: s_mov_b32 s9, s8
; GFX6-NEXT: s_addc_u32 s1, s7, s8
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc
; GFX6-NEXT: s_xor_b64 s[6:7], s[0:1], s[8:9]
; GFX6-NEXT: v_mul_lo_u32 v2, s6, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0
@@ -9860,7 +9572,8 @@ define amdgpu_kernel void @srem_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s4
; GFX6-NEXT: v_mul_hi_u32 v2, v0, s4
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s4
-; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_mov_b32_e32 v2, s7
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
@@ -9888,48 +9601,20 @@ define amdgpu_kernel void @srem_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX6-NEXT: v_xor_b32_e32 v1, s8, v1
; GFX6-NEXT: v_mov_b32_e32 v2, s8
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
+; GFX6-NEXT: s_mov_b32 s1, s5
; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX9-LABEL: srem_i64_oddk_denom:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x4996c7d8
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GFX9-NEXT: v_mac_f32_e32 v0, 0, v1
-; GFX9-NEXT: v_rcp_f32_e32 v0, v0
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX9-NEXT: v_trunc_f32_e32 v1, v1
-; GFX9-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s4, v1
-; GFX9-NEXT: v_readfirstlane_b32 s5, v0
-; GFX9-NEXT: s_mul_hi_u32 s6, s5, 0xffed2705
-; GFX9-NEXT: s_mul_i32 s7, s4, 0xffed2705
-; GFX9-NEXT: s_add_i32 s6, s6, s7
-; GFX9-NEXT: s_sub_i32 s6, s6, s5
-; GFX9-NEXT: s_mul_i32 s9, s5, 0xffed2705
-; GFX9-NEXT: s_mul_hi_u32 s7, s5, s6
-; GFX9-NEXT: s_mul_i32 s8, s5, s6
-; GFX9-NEXT: s_mul_hi_u32 s5, s5, s9
-; GFX9-NEXT: s_add_u32 s5, s5, s8
-; GFX9-NEXT: s_addc_u32 s7, 0, s7
-; GFX9-NEXT: s_mul_hi_u32 s10, s4, s9
-; GFX9-NEXT: s_mul_i32 s9, s4, s9
-; GFX9-NEXT: s_add_u32 s5, s5, s9
-; GFX9-NEXT: s_mul_hi_u32 s8, s4, s6
-; GFX9-NEXT: s_addc_u32 s5, s7, s10
-; GFX9-NEXT: s_addc_u32 s7, s8, 0
-; GFX9-NEXT: s_mul_i32 s6, s4, s6
-; GFX9-NEXT: s_add_u32 s5, s5, s6
-; GFX9-NEXT: s_addc_u32 s6, 0, s7
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s5, v0
+; GFX9-NEXT: s_mov_b32 s4, 0x33fe64
+; GFX9-NEXT: s_add_u32 s4, 0x396, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x28100000
+; GFX9-NEXT: s_addc_u32 s5, 0, 0
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s4, v0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s4, s4, s6
+; GFX9-NEXT: s_addc_u32 s4, s5, 0xd95
; GFX9-NEXT: v_readfirstlane_b32 s6, v0
; GFX9-NEXT: s_mul_i32 s5, s4, 0xffed2705
; GFX9-NEXT: s_mul_hi_u32 s7, s6, 0xffed2705
@@ -9944,6 +9629,7 @@ define amdgpu_kernel void @srem_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX9-NEXT: s_mul_i32 s10, s4, s8
; GFX9-NEXT: s_addc_u32 s8, 0, s11
; GFX9-NEXT: s_add_u32 s6, s6, s10
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: s_mul_hi_u32 s7, s4, s5
; GFX9-NEXT: s_addc_u32 s6, s8, s9
; GFX9-NEXT: s_addc_u32 s7, s7, 0
@@ -10013,6 +9699,7 @@ define amdgpu_kernel void @srem_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX9-NEXT: v_xor_b32_e32 v1, s4, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s4, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll
index e554f912ff64886..5d1db03a1a35bbd 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv.ll
@@ -2520,59 +2520,38 @@ define i64 @v_test_udiv64_mulhi_fold(i64 %arg) {
; SI-LABEL: v_test_udiv64_mulhi_fold:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v2, 0x4f800000
-; SI-NEXT: v_madak_f32 v2, 0, v2, 0x47c35000
-; SI-NEXT: v_rcp_f32_e32 v2, v2
+; SI-NEXT: s_mov_b32 s4, 0x346d900
+; SI-NEXT: s_add_u32 s4, 0x4237, s4
+; SI-NEXT: v_mov_b32_e32 v2, 0xa9000000
+; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v2
+; SI-NEXT: s_addc_u32 s5, 0, 0
+; SI-NEXT: s_or_b32 s4, vcc_lo, vcc_hi
+; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: s_mov_b32 s4, 0xfffe7960
-; SI-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; SI-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
-; SI-NEXT: v_trunc_f32_e32 v3, v3
-; SI-NEXT: v_madmk_f32 v2, v3, 0xcf800000, v2
-; SI-NEXT: v_cvt_u32_f32_e32 v2, v2
-; SI-NEXT: v_cvt_u32_f32_e32 v3, v3
-; SI-NEXT: v_mul_hi_u32 v4, v2, s4
-; SI-NEXT: v_mul_lo_u32 v6, v3, s4
-; SI-NEXT: v_mul_lo_u32 v5, v2, s4
-; SI-NEXT: v_sub_i32_e32 v4, vcc, v4, v2
-; SI-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; SI-NEXT: v_mul_hi_u32 v7, v2, v5
-; SI-NEXT: v_mul_lo_u32 v6, v2, v4
-; SI-NEXT: v_mul_hi_u32 v8, v2, v4
-; SI-NEXT: v_mul_hi_u32 v9, v3, v4
-; SI-NEXT: v_mul_lo_u32 v4, v3, v4
-; SI-NEXT: v_add_i32_e32 v6, vcc, v7, v6
-; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
-; SI-NEXT: v_mul_lo_u32 v8, v3, v5
-; SI-NEXT: v_mul_hi_u32 v5, v3, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, v6, v8
-; SI-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc
-; SI-NEXT: v_addc_u32_e32 v6, vcc, 0, v9, vcc
-; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
-; SI-NEXT: v_mul_hi_u32 v4, v2, s4
-; SI-NEXT: v_mul_lo_u32 v5, v3, s4
-; SI-NEXT: v_mul_lo_u32 v6, v2, s4
+; SI-NEXT: v_mul_hi_u32 v3, v2, s4
+; SI-NEXT: v_mul_lo_u32 v4, v2, s4
+; SI-NEXT: s_addc_u32 s5, s5, 0xa7c5
+; SI-NEXT: s_mul_i32 s6, s5, 0xfffe7960
+; SI-NEXT: v_sub_i32_e32 v3, vcc, v3, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_mul_lo_u32 v5, v2, v3
+; SI-NEXT: v_mul_hi_u32 v6, v2, v4
+; SI-NEXT: v_mul_hi_u32 v7, v2, v3
+; SI-NEXT: v_mul_hi_u32 v8, s5, v3
+; SI-NEXT: v_mul_lo_u32 v3, s5, v3
+; SI-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; SI-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc
+; SI-NEXT: v_mul_lo_u32 v7, s5, v4
+; SI-NEXT: v_mul_hi_u32 v4, s5, v4
; SI-NEXT: s_mov_b32 s4, 0x186a0
-; SI-NEXT: v_sub_i32_e32 v4, vcc, v4, v2
-; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; SI-NEXT: v_mul_lo_u32 v5, v2, v4
-; SI-NEXT: v_mul_hi_u32 v7, v2, v6
-; SI-NEXT: v_mul_hi_u32 v8, v2, v4
-; SI-NEXT: v_mul_hi_u32 v9, v3, v4
-; SI-NEXT: v_mul_lo_u32 v4, v3, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, v7, v5
-; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
-; SI-NEXT: v_mul_lo_u32 v8, v3, v6
-; SI-NEXT: v_mul_hi_u32 v6, v3, v6
-; SI-NEXT: v_add_i32_e32 v5, vcc, v5, v8
-; SI-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; SI-NEXT: v_addc_u32_e32 v6, vcc, 0, v9, vcc
-; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
+; SI-NEXT: v_add_i32_e32 v5, vcc, v5, v7
+; SI-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc
+; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v8, vcc
+; SI-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; SI-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s5
+; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; SI-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
; SI-NEXT: v_mul_lo_u32 v4, v0, v3
; SI-NEXT: v_mul_hi_u32 v5, v0, v2
; SI-NEXT: v_mul_hi_u32 v6, v0, v3
@@ -2687,39 +2666,20 @@ define i64 @v_test_udiv64_mulhi_fold(i64 %arg) {
; GCN-LABEL: v_test_udiv64_mulhi_fold:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000
-; GCN-NEXT: v_madak_f32 v2, 0, v2, 0x47c35000
-; GCN-NEXT: v_rcp_f32_e32 v2, v2
+; GCN-NEXT: v_mov_b32_e32 v4, 0xa7c5
+; GCN-NEXT: v_mul_u32_u24_e32 v3, 0x500, v4
+; GCN-NEXT: v_mul_hi_u32_u24_e32 v2, 0x500, v4
+; GCN-NEXT: v_add_u32_e32 v3, vcc, 0x4237, v3
+; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc
+; GCN-NEXT: v_add_u32_e32 v6, vcc, 0xa9000000, v3
; GCN-NEXT: s_mov_b32 s6, 0xfffe7960
-; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
-; GCN-NEXT: v_trunc_f32_e32 v3, v3
-; GCN-NEXT: v_madmk_f32 v2, v3, 0xcf800000, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v6, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v7, v3
-; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, s6, 0
-; GCN-NEXT: v_mul_lo_u32 v4, v7, s6
-; GCN-NEXT: v_sub_u32_e32 v3, vcc, v3, v6
-; GCN-NEXT: v_add_u32_e32 v8, vcc, v3, v4
-; GCN-NEXT: v_mul_hi_u32 v5, v6, v2
-; GCN-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v8, 0
-; GCN-NEXT: v_add_u32_e32 v9, vcc, v5, v3
-; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v2, 0
-; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc
-; GCN-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v8, 0
-; GCN-NEXT: v_add_u32_e32 v2, vcc, v9, v2
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, v10, v3, vcc
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GCN-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GCN-NEXT: v_add_u32_e32 v6, vcc, v6, v2
-; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v3, vcc
; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, s6, 0
+; GCN-NEXT: v_addc_u32_e32 v7, vcc, v5, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v7, s6
; GCN-NEXT: v_sub_u32_e32 v3, vcc, v3, v6
+; GCN-NEXT: v_mul_hi_u32 v8, v6, v2
; GCN-NEXT: v_add_u32_e32 v5, vcc, v4, v3
; GCN-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v5, 0
-; GCN-NEXT: v_mul_hi_u32 v8, v6, v2
; GCN-NEXT: v_add_u32_e32 v8, vcc, v8, v3
; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v2, 0
; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v4, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll
index e23f3cfad89bc88..7aa36a8b377bff5 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll
@@ -1326,64 +1326,37 @@ define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) {
define amdgpu_kernel void @s_test_udiv_k_den_i64(ptr addrspace(1) %out, i64 %x) {
; GCN-LABEL: s_test_udiv_k_den_i64:
; GCN: ; %bb.0:
-; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000
-; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x41c00000
-; GCN-NEXT: v_rcp_f32_e32 v0, v0
-; GCN-NEXT: s_movk_i32 s8, 0xffe8
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: s_mov_b32 s2, -1
+; GCN-NEXT: s_add_u32 s1, 0, 0xaaaa0000
+; GCN-NEXT: v_mov_b32_e32 v0, 0xffffffe8
+; GCN-NEXT: v_mul_hi_u32 v0, s1, v0
+; GCN-NEXT: s_addc_u32 s8, 0, 42
+; GCN-NEXT: s_add_i32 s8, s8, 0xaaaaa80
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s0, s4
-; GCN-NEXT: v_mul_hi_u32 v2, v0, s8
-; GCN-NEXT: v_mul_lo_u32 v4, v1, s8
-; GCN-NEXT: v_mul_lo_u32 v3, v0, s8
-; GCN-NEXT: s_mov_b32 s1, s5
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT: v_mul_hi_u32 v5, v0, v3
-; GCN-NEXT: v_mul_lo_u32 v4, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v7, v1, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GCN-NEXT: v_mul_lo_u32 v6, v1, v3
-; GCN-NEXT: v_mul_hi_u32 v3, v1, v3
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GCN-NEXT: v_mul_hi_u32 v2, v0, s8
-; GCN-NEXT: v_mul_lo_u32 v3, v1, s8
-; GCN-NEXT: v_mul_lo_u32 v4, v0, s8
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_mul_lo_u32 v3, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v5, v0, v4
-; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v7, v1, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
-; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT: s_mul_i32 s4, s1, 0xffffffe8
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s1, v0
+; GCN-NEXT: s_mul_i32 s9, s8, 0xffffffe8
+; GCN-NEXT: v_mov_b32_e32 v1, s4
+; GCN-NEXT: v_add_i32_e32 v0, vcc, s9, v0
+; GCN-NEXT: v_mul_hi_u32 v2, s8, v1
+; GCN-NEXT: v_mul_lo_u32 v3, s1, v0
+; GCN-NEXT: v_mul_hi_u32 v1, s1, v1
+; GCN-NEXT: v_mul_hi_u32 v4, s1, v0
+; GCN-NEXT: s_mul_i32 s4, s8, s4
+; GCN-NEXT: s_mov_b32 s3, 0xf000
+; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v4, s8, v0
+; GCN-NEXT: v_mul_lo_u32 v0, s8, v0
+; GCN-NEXT: v_add_i32_e32 v1, vcc, s4, v1
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
+; GCN-NEXT: v_mov_b32_e32 v2, s8
+; GCN-NEXT: v_add_i32_e32 v0, vcc, s1, v0
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v2, s6, v1
; GCN-NEXT: v_mul_hi_u32 v3, s6, v0
; GCN-NEXT: v_mul_hi_u32 v4, s6, v1
@@ -1393,6 +1366,8 @@ define amdgpu_kernel void @s_test_udiv_k_den_i64(ptr addrspace(1) %out, i64 %x)
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v4, s7, v0
; GCN-NEXT: v_mul_hi_u32 v0, s7, v0
+; GCN-NEXT: s_mov_b32 s2, -1
+; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
@@ -1502,58 +1477,33 @@ define i64 @v_test_udiv_k_den_i64(i64 %x) {
; GCN-LABEL: v_test_udiv_k_den_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000
-; GCN-NEXT: v_madak_f32 v2, 0, v2, 0x41c00000
-; GCN-NEXT: v_rcp_f32_e32 v2, v2
-; GCN-NEXT: s_movk_i32 s4, 0xffe8
-; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
-; GCN-NEXT: v_trunc_f32_e32 v3, v3
-; GCN-NEXT: v_madmk_f32 v2, v3, 0xcf800000, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT: v_mul_hi_u32 v4, v2, s4
-; GCN-NEXT: v_mul_lo_u32 v6, v3, s4
-; GCN-NEXT: v_mul_lo_u32 v5, v2, s4
-; GCN-NEXT: v_sub_i32_e32 v4, vcc, v4, v2
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT: v_mul_hi_u32 v7, v2, v5
-; GCN-NEXT: v_mul_lo_u32 v6, v2, v4
-; GCN-NEXT: v_mul_hi_u32 v8, v2, v4
-; GCN-NEXT: v_mul_hi_u32 v9, v3, v4
-; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
-; GCN-NEXT: v_mul_lo_u32 v8, v3, v5
-; GCN-NEXT: v_mul_hi_u32 v5, v3, v5
-; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc
-; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v9, vcc
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
-; GCN-NEXT: v_mul_hi_u32 v4, v2, s4
-; GCN-NEXT: v_mul_lo_u32 v5, v3, s4
-; GCN-NEXT: v_mul_lo_u32 v6, v2, s4
-; GCN-NEXT: v_sub_i32_e32 v4, vcc, v4, v2
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT: v_mul_lo_u32 v5, v2, v4
-; GCN-NEXT: v_mul_hi_u32 v7, v2, v6
-; GCN-NEXT: v_mul_hi_u32 v8, v2, v4
-; GCN-NEXT: v_mul_hi_u32 v9, v3, v4
-; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
-; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
-; GCN-NEXT: v_mul_lo_u32 v8, v3, v6
-; GCN-NEXT: v_mul_hi_u32 v6, v3, v6
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v9, vcc
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT: s_add_u32 s4, 0, 0xaaaa0000
+; GCN-NEXT: v_mov_b32_e32 v2, 0xffffffe8
+; GCN-NEXT: v_mul_hi_u32 v2, s4, v2
+; GCN-NEXT: s_addc_u32 s5, 0, 42
+; GCN-NEXT: s_add_i32 s5, s5, 0xaaaaa80
+; GCN-NEXT: s_mul_i32 s6, s4, 0xffffffe8
+; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s4, v2
+; GCN-NEXT: s_mul_i32 s7, s5, 0xffffffe8
+; GCN-NEXT: v_mov_b32_e32 v3, s6
+; GCN-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; GCN-NEXT: v_mul_hi_u32 v4, s5, v3
+; GCN-NEXT: v_mul_lo_u32 v5, s4, v2
+; GCN-NEXT: v_mul_hi_u32 v3, s4, v3
+; GCN-NEXT: v_mul_hi_u32 v6, s4, v2
+; GCN-NEXT: s_mul_i32 s6, s5, s6
+; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
+; GCN-NEXT: v_mul_hi_u32 v6, s5, v2
+; GCN-NEXT: v_mul_lo_u32 v2, s5, v2
+; GCN-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
+; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT: v_mov_b32_e32 v4, s5
+; GCN-NEXT: v_add_i32_e32 v2, vcc, s4, v2
+; GCN-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v0, v3
; GCN-NEXT: v_mul_hi_u32 v5, v0, v2
; GCN-NEXT: v_mul_hi_u32 v6, v0, v3
diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll
index f68d14a32b929a5..91d09c01639ffcb 100644
--- a/llvm/test/CodeGen/AMDGPU/urem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/urem64.ll
@@ -894,64 +894,36 @@ define amdgpu_kernel void @s_test_urem_k_num_i64(ptr addrspace(1) %out, i64 %x)
define amdgpu_kernel void @s_test_urem_k_den_i64(ptr addrspace(1) %out, i64 %x) {
; GCN-LABEL: s_test_urem_k_den_i64:
; GCN: ; %bb.0:
-; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000
-; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x41c00000
-; GCN-NEXT: v_rcp_f32_e32 v0, v0
-; GCN-NEXT: s_movk_i32 s2, 0xffe8
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT: s_add_u32 s0, 0, 0xaaaa0000
+; GCN-NEXT: v_mov_b32_e32 v0, 0xffffffe8
+; GCN-NEXT: v_mul_hi_u32 v0, s0, v0
+; GCN-NEXT: s_addc_u32 s1, 0, 42
+; GCN-NEXT: s_add_i32 s1, s1, 0xaaaaa80
+; GCN-NEXT: s_mul_i32 s8, s0, 0xffffffe8
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
+; GCN-NEXT: s_mul_i32 s9, s1, 0xffffffe8
+; GCN-NEXT: v_mov_b32_e32 v1, s8
+; GCN-NEXT: v_add_i32_e32 v0, vcc, s9, v0
+; GCN-NEXT: v_mul_hi_u32 v2, s1, v1
+; GCN-NEXT: v_mul_lo_u32 v3, s0, v0
+; GCN-NEXT: v_mul_hi_u32 v1, s0, v1
+; GCN-NEXT: v_mul_hi_u32 v4, s0, v0
+; GCN-NEXT: s_mul_i32 s8, s1, s8
; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s0, s4
-; GCN-NEXT: s_mov_b32 s1, s5
-; GCN-NEXT: v_mul_hi_u32 v2, v0, s2
-; GCN-NEXT: v_mul_lo_u32 v4, v1, s2
-; GCN-NEXT: v_mul_lo_u32 v3, v0, s2
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT: v_mul_hi_u32 v5, v0, v3
-; GCN-NEXT: v_mul_lo_u32 v4, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v7, v1, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GCN-NEXT: v_mul_lo_u32 v6, v1, v3
-; GCN-NEXT: v_mul_hi_u32 v3, v1, v3
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; GCN-NEXT: v_mul_hi_u32 v2, v0, s2
-; GCN-NEXT: v_mul_lo_u32 v3, v1, s2
-; GCN-NEXT: v_mul_lo_u32 v4, v0, s2
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, v2, v0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_mul_lo_u32 v3, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v5, v0, v4
-; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v7, v1, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
-; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GCN-NEXT: v_mul_hi_u32 v4, s1, v0
+; GCN-NEXT: v_mul_lo_u32 v0, s1, v0
+; GCN-NEXT: v_add_i32_e32 v1, vcc, s8, v1
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
+; GCN-NEXT: v_mov_b32_e32 v2, s1
+; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v0
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mul_lo_u32 v2, s6, v1
; GCN-NEXT: v_mul_hi_u32 v3, s6, v0
; GCN-NEXT: v_mul_hi_u32 v4, s6, v1
@@ -961,6 +933,8 @@ define amdgpu_kernel void @s_test_urem_k_den_i64(ptr addrspace(1) %out, i64 %x)
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v4, s7, v0
; GCN-NEXT: v_mul_hi_u32 v0, s7, v0
+; GCN-NEXT: s_mov_b32 s2, -1
+; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
@@ -969,6 +943,7 @@ define amdgpu_kernel void @s_test_urem_k_den_i64(ptr addrspace(1) %out, i64 %x)
; GCN-NEXT: v_mul_lo_u32 v1, v1, 24
; GCN-NEXT: v_mul_hi_u32 v2, v0, 24
; GCN-NEXT: v_mul_lo_u32 v0, v0, 24
+; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; GCN-NEXT: v_mov_b32_e32 v2, s7
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
>From 85e7e5b1f2fed8773cf44d905bf9d5f181829ee7 Mon Sep 17 00:00:00 2001
From: pvanhout <pierre.vanhoutryve at amd.com>
Date: Thu, 19 Oct 2023 08:43:09 +0200
Subject: [PATCH 2/2] Add FTZ
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 23 +++++++++++++++----
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 10ac79d0fa0e1ba..69bf7d3d7d8c3a9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -5047,11 +5047,24 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
SDValue N2 = N->getOperand(2);
EVT VT = N->getValueType(0);
- // FMAD_FTZ is a FMAD, but flushing to zero is allowed (not required).
- // if all operands are constant we can just constant-fold it like a FMAD.
- if (isa<ConstantFPSDNode>(N0) && isa<ConstantFPSDNode>(N1) &&
- isa<ConstantFPSDNode>(N2))
- return DAG.getNode(ISD::FMAD, DL, VT, {N0, N1, N2});
+ // FMAD_FTZ is a FMAD + flush denormals to zero.
+ // We flush the inputs, the intermediate step, and the output.
+ ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
+ ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
+ ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2);
+ if (N0CFP && N1CFP && N2CFP) {
+ const auto FTZ = [](const APFloat &V) {
+ return V.isDenormal() ? APFloat(V.getSemantics(), 0) : V;
+ };
+
+ APFloat V0 = FTZ(N0CFP->getValueAPF());
+ APFloat V1 = FTZ(N1CFP->getValueAPF());
+ APFloat V2 = FTZ(N2CFP->getValueAPF());
+ V0.multiply(V1, APFloat::rmNearestTiesToEven);
+ V0 = FTZ(V0);
+ V0.add(V2, APFloat::rmNearestTiesToEven);
+ return DAG.getConstantFP(FTZ(V0), DL, VT);
+ }
break;
}
}
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