[llvm] [RISCV][GlobalISel] Create generic instructions to handle legalization and selection of G_GLOBAL_VALUE for medlow code model (PR #69562)

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``````````bash
git-clang-format --diff f4231bf446ed8663886a86eb5b8b2db57baff854 6144541a6d3c515cc3d2b6cab7090a5e3b145708 -- llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 757298f76fbe..eb2a445b7e05 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -164,7 +164,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
   preISelLower(MI, MIB, MRI);
   const unsigned Opc = MI.getOpcode();
 
-  switch(Opc) {
+  switch (Opc) {
   case RISCV::G_RISCV_ADD_LO: {
     Register DstReg = MI.getOperand(0).getReg();
     const LLT XLenLLT = LLT::scalar(STI.getXLen());
@@ -243,7 +243,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
     if (Subtarget->is64Bit() && Ty.isScalar() && Ty.getSizeInBits() == 32) {
       std::optional<int64_t> CstVal =
           getIConstantVRegSExtVal(MI.getOperand(2).getReg(), MRI);
-      if (CstVal && ((isInt<12>(*CstVal) && *CstVal != -2048) || *CstVal == 2048)) {
+      if (CstVal &&
+          ((isInt<12>(*CstVal) && *CstVal != -2048) || *CstVal == 2048)) {
         auto NewI = MIB.buildInstr(RISCV::ADDIW, {MI.getOperand(0).getReg()},
                                    {MI.getOperand(1).getReg()})
                         .addImm(-*CstVal);
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 69ae0266cdc1..af2c292fd383 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -205,7 +205,7 @@ bool RISCVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
                         .addGlobalAddress(GV, Offset, RISCVII::MO_HI);
 
       MIB.buildInstr(RISCV::G_RISCV_ADD_LO, {DstReg}, {AddrHi})
-                      .addGlobalAddress(GV, Offset, RISCVII::MO_LO);
+          .addGlobalAddress(GV, Offset, RISCVII::MO_LO);
 
       MI.eraseFromParent();
       return true;

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https://github.com/llvm/llvm-project/pull/69562