[llvm] [RISCV] Relax some Zvbb patterns and lowerings to Zvkb (PR #68115)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 3 08:02:28 PDT 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
<details>
<summary>Changes</summary>
vandn, vrev8 and vro{l,r} are now part of Zvkb, which Zvbb now implies. This
patch updates the predicates to check for Zvkb instead of Zvbb in the tablegen
patterns for the SD and VL nodes, as well as some of the lowering logic in
RISCVISelLowering.
---
Patch is 439.41 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/68115.diff
12 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+21-15)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td (+12-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll (+77-77)
- (modified) llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll (+209-209)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll (+44-44)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll (+368-368)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll (+230-233)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll (+454-454)
- (modified) llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll (+562-562)
- (modified) llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll (+396-396)
- (modified) llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll (+222-222)
- (modified) llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll (+442-442)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e47168e10d8dc13..b07e93fc65f5456 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -779,15 +779,22 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
// Splice
setOperationAction(ISD::VECTOR_SPLICE, VT, Custom);
+ if (Subtarget.hasStdExtZvkb()) {
+ setOperationAction(ISD::BSWAP, VT, Legal);
+ setOperationAction(ISD::VP_BSWAP, VT, Custom);
+ } else {
+ setOperationAction({ISD::BSWAP, ISD::VP_BSWAP}, VT, Expand);
+ setOperationAction({ISD::ROTL, ISD::ROTR}, VT, Expand);
+ }
+
if (Subtarget.hasStdExtZvbb()) {
- setOperationAction({ISD::BITREVERSE, ISD::BSWAP}, VT, Legal);
- setOperationAction({ISD::VP_BITREVERSE, ISD::VP_BSWAP}, VT, Custom);
+ setOperationAction(ISD::BITREVERSE, VT, Legal);
+ setOperationAction(ISD::VP_BITREVERSE, VT, Custom);
setOperationAction({ISD::VP_CTLZ, ISD::VP_CTLZ_ZERO_UNDEF, ISD::VP_CTTZ,
ISD::VP_CTTZ_ZERO_UNDEF, ISD::VP_CTPOP},
VT, Custom);
} else {
- setOperationAction({ISD::BITREVERSE, ISD::BSWAP}, VT, Expand);
- setOperationAction({ISD::VP_BITREVERSE, ISD::VP_BSWAP}, VT, Expand);
+ setOperationAction({ISD::BITREVERSE, ISD::VP_BITREVERSE}, VT, Expand);
setOperationAction({ISD::CTLZ, ISD::CTTZ, ISD::CTPOP}, VT, Expand);
setOperationAction({ISD::VP_CTLZ, ISD::VP_CTLZ_ZERO_UNDEF, ISD::VP_CTTZ,
ISD::VP_CTTZ_ZERO_UNDEF, ISD::VP_CTPOP},
@@ -802,8 +809,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_CTLZ_ZERO_UNDEF, ISD::VP_CTTZ_ZERO_UNDEF},
VT, Custom);
}
-
- setOperationAction({ISD::ROTL, ISD::ROTR}, VT, Expand);
}
}
@@ -1109,11 +1114,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(IntegerVPOps, VT, Custom);
+ if (Subtarget.hasStdExtZvkb())
+ setOperationAction({ISD::BSWAP, ISD::ROTL, ISD::ROTR}, VT, Custom);
+
if (Subtarget.hasStdExtZvbb()) {
- setOperationAction({ISD::BITREVERSE, ISD::BSWAP, ISD::CTLZ,
- ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ,
- ISD::CTTZ_ZERO_UNDEF, ISD::CTPOP, ISD::ROTL,
- ISD::ROTR},
+ setOperationAction({ISD::BITREVERSE, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF,
+ ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTPOP},
VT, Custom);
} else {
// Lower CTLZ_ZERO_UNDEF and CTTZ_ZERO_UNDEF if element of VT in the
@@ -4376,7 +4382,7 @@ static SDValue lowerBitreverseShuffle(ShuffleVectorSDNode *SVN,
// Given a shuffle mask like <3, 0, 1, 2, 7, 4, 5, 6> for v8i8, we can
// reinterpret it as a v2i32 and rotate it right by 8 instead. We can lower this
-// as a vror.vi if we have zvbb, or otherwise as a vsll, vsrl and vor.
+// as a vror.vi if we have zvkb, or otherwise as a vsll, vsrl and vor.
static SDValue lowerVECTOR_SHUFFLEAsRotate(ShuffleVectorSDNode *SVN,
SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
@@ -4527,9 +4533,9 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
lowerVECTOR_SHUFFLEAsVSlidedown(DL, VT, V1, V2, Mask, Subtarget, DAG))
return V;
- // A bitrotate will be one instruction on zvbb, so try to lower to it first if
+ // A bitrotate will be one instruction on zvkb, so try to lower to it first if
// available.
- if (Subtarget.hasStdExtZvbb())
+ if (Subtarget.hasStdExtZvkb())
if (SDValue V = lowerVECTOR_SHUFFLEAsRotate(SVN, DAG, Subtarget))
return V;
@@ -4660,7 +4666,7 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
return DAG.getNode(ISD::VSELECT, DL, VT, SelectMask, V1, V2);
// We might be able to express the shuffle as a bitrotate. But even if we
- // don't have zvbb and have to expand, the expanded sequence of approx. 2
+ // don't have zvkb and have to expand, the expanded sequence of approx. 2
// shifts and a vor will have a higher throughput than a vrgather.
if (SDValue V = lowerVECTOR_SHUFFLEAsRotate(SVN, DAG, Subtarget))
return V;
@@ -5482,7 +5488,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::ROTL:
case ISD::ROTR:
if (Op.getValueType().isFixedLengthVector()) {
- assert(Subtarget.hasStdExtZvbb());
+ assert(Subtarget.hasStdExtZvkb());
return lowerToScalableOp(Op, DAG);
}
assert(Subtarget.hasVendorXTHeadBb() &&
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index b904323a3bfb583..272d7f64b4d995e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -410,9 +410,10 @@ let Predicates = [HasStdExtZvksh] in {
// SDNode patterns
//===----------------------------------------------------------------------===//
-multiclass VPatUnarySDNode_V<SDPatternOperator op, string instruction_name> {
+multiclass VPatUnarySDNode_V<SDPatternOperator op, string instruction_name,
+ Predicate predicate = HasStdExtZvbb> {
foreach vti = AllIntegerVectors in {
- let Predicates = !listconcat([HasStdExtZvbb],
+ let Predicates = !listconcat([predicate],
GetVTypePredicates<vti>.Predicates) in {
def : Pat<(vti.Vector (op (vti.Vector vti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_V_"#vti.LMul.MX)
@@ -431,7 +432,7 @@ def riscv_vnot : PatFrag<(ops node:$rs1), (xor node:$rs1,
(riscv_splat_vector -1))>;
foreach vti = AllIntegerVectors in {
- let Predicates = !listconcat([HasStdExtZvbb],
+ let Predicates = !listconcat([HasStdExtZvkb],
GetVTypePredicates<vti>.Predicates) in {
def : Pat<(vti.Vector (and (riscv_vnot vti.RegClass:$rs1),
vti.RegClass:$rs2)),
@@ -452,7 +453,7 @@ foreach vti = AllIntegerVectors in {
}
defm : VPatUnarySDNode_V<bitreverse, "PseudoVBREV">;
-defm : VPatUnarySDNode_V<bswap, "PseudoVREV8">;
+defm : VPatUnarySDNode_V<bswap, "PseudoVREV8", HasStdExtZvkb>;
defm : VPatUnarySDNode_V<ctlz, "PseudoVCLZ">;
defm : VPatUnarySDNode_V<cttz, "PseudoVCTZ">;
defm : VPatUnarySDNode_V<ctpop, "PseudoVCPOP">;
@@ -480,7 +481,7 @@ def InvRot64Imm : SDNodeXForm<imm, [{
// Although there is no vrol.vi, an immediate rotate left can be achieved by
// negating the immediate in vror.vi
foreach vti = AllIntegerVectors in {
- let Predicates = !listconcat([HasStdExtZvbb],
+ let Predicates = !listconcat([HasStdExtZvkb],
GetVTypePredicates<vti>.Predicates) in {
def : Pat<(vti.Vector (rotl vti.RegClass:$rs2,
(vti.Vector (SplatPat_uimm6 uimm6:$rs1)))),
@@ -526,9 +527,10 @@ foreach vtiToWti = AllWidenableIntVectors in {
// VL patterns
//===----------------------------------------------------------------------===//
-multiclass VPatUnaryVL_V<SDPatternOperator op, string instruction_name> {
+multiclass VPatUnaryVL_V<SDPatternOperator op, string instruction_name,
+ Predicate predicate = HasStdExtZvbb> {
foreach vti = AllIntegerVectors in {
- let Predicates = !listconcat([HasStdExtZvbb],
+ let Predicates = !listconcat([predicate],
GetVTypePredicates<vti>.Predicates) in {
def : Pat<(vti.Vector (op (vti.Vector vti.RegClass:$rs1),
(vti.Vector vti.RegClass:$merge),
@@ -546,7 +548,7 @@ multiclass VPatUnaryVL_V<SDPatternOperator op, string instruction_name> {
}
foreach vti = AllIntegerVectors in {
- let Predicates = !listconcat([HasStdExtZvbb],
+ let Predicates = !listconcat([HasStdExtZvkb],
GetVTypePredicates<vti>.Predicates) in {
def : Pat<(vti.Vector (riscv_and_vl (riscv_xor_vl
(vti.Vector vti.RegClass:$rs1),
@@ -585,7 +587,7 @@ foreach vti = AllIntegerVectors in {
}
defm : VPatUnaryVL_V<riscv_bitreverse_vl, "PseudoVBREV">;
-defm : VPatUnaryVL_V<riscv_bswap_vl, "PseudoVREV8">;
+defm : VPatUnaryVL_V<riscv_bswap_vl, "PseudoVREV8", HasStdExtZvkb>;
defm : VPatUnaryVL_V<riscv_ctlz_vl, "PseudoVCLZ">;
defm : VPatUnaryVL_V<riscv_cttz_vl, "PseudoVCTZ">;
defm : VPatUnaryVL_V<riscv_ctpop_vl, "PseudoVCPOP">;
@@ -594,7 +596,7 @@ defm : VPatBinaryVL_VV_VX<riscv_rotl_vl, "PseudoVROL">;
// Although there is no vrol.vi, an immediate rotate left can be achieved by
// negating the immediate in vror.vi
foreach vti = AllIntegerVectors in {
- let Predicates = !listconcat([HasStdExtZvbb],
+ let Predicates = !listconcat([HasStdExtZvkb],
GetVTypePredicates<vti>.Predicates) in {
def : Pat<(riscv_rotl_vl vti.RegClass:$rs2,
(vti.Vector (SplatPat_uimm6 uimm6:$rs1)),
diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
index 690ecc6eab33b35..884bb206a31ebe2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
+; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
define <vscale x 1 x i16> @bswap_nxv1i16(<vscale x 1 x i16> %va) {
; CHECK-LABEL: bswap_nxv1i16:
@@ -13,11 +13,11 @@ define <vscale x 1 x i16> @bswap_nxv1i16(<vscale x 1 x i16> %va) {
; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: bswap_nxv1i16:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-ZVBB-NEXT: vrev8.v v8, v8
-; CHECK-ZVBB-NEXT: ret
+; CHECK-ZVKB-LABEL: bswap_nxv1i16:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 1 x i16> @llvm.bswap.nxv1i16(<vscale x 1 x i16> %va)
ret <vscale x 1 x i16> %a
}
@@ -32,11 +32,11 @@ define <vscale x 2 x i16> @bswap_nxv2i16(<vscale x 2 x i16> %va) {
; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: bswap_nxv2i16:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-ZVBB-NEXT: vrev8.v v8, v8
-; CHECK-ZVBB-NEXT: ret
+; CHECK-ZVKB-LABEL: bswap_nxv2i16:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 2 x i16> @llvm.bswap.nxv2i16(<vscale x 2 x i16> %va)
ret <vscale x 2 x i16> %a
}
@@ -51,11 +51,11 @@ define <vscale x 4 x i16> @bswap_nxv4i16(<vscale x 4 x i16> %va) {
; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: bswap_nxv4i16:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-ZVBB-NEXT: vrev8.v v8, v8
-; CHECK-ZVBB-NEXT: ret
+; CHECK-ZVKB-LABEL: bswap_nxv4i16:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 4 x i16> @llvm.bswap.nxv4i16(<vscale x 4 x i16> %va)
ret <vscale x 4 x i16> %a
}
@@ -70,11 +70,11 @@ define <vscale x 8 x i16> @bswap_nxv8i16(<vscale x 8 x i16> %va) {
; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: bswap_nxv8i16:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-ZVBB-NEXT: vrev8.v v8, v8
-; CHECK-ZVBB-NEXT: ret
+; CHECK-ZVKB-LABEL: bswap_nxv8i16:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 8 x i16> @llvm.bswap.nxv8i16(<vscale x 8 x i16> %va)
ret <vscale x 8 x i16> %a
}
@@ -89,11 +89,11 @@ define <vscale x 16 x i16> @bswap_nxv16i16(<vscale x 16 x i16> %va) {
; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: bswap_nxv16i16:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-ZVBB-NEXT: vrev8.v v8, v8
-; CHECK-ZVBB-NEXT: ret
+; CHECK-ZVKB-LABEL: bswap_nxv16i16:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 16 x i16> @llvm.bswap.nxv16i16(<vscale x 16 x i16> %va)
ret <vscale x 16 x i16> %a
}
@@ -108,11 +108,11 @@ define <vscale x 32 x i16> @bswap_nxv32i16(<vscale x 32 x i16> %va) {
; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-LABEL: bswap_nxv32i16:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; CHECK-ZVBB-NEXT: vrev8.v v8, v8
-; CHECK-ZVBB-NEXT: ret
+; CHECK-ZVKB-LABEL: bswap_nxv32i16:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 32 x i16> @llvm.bswap.nxv32i16(<vscale x 32 x i16> %va)
ret <vscale x 32 x i16> %a
}
@@ -151,11 +151,11 @@ define <vscale x 1 x i32> @bswap_nxv1i32(<vscale x 1 x i32> %va) {
; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: ret
;
-; CHECK-ZVBB-LABEL: bswap_nxv1i32:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-ZVBB-NEXT: vrev8.v v8, v8
-; CHECK-ZVBB-NEXT: ret
+; CHECK-ZVKB-LABEL: bswap_nxv1i32:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 1 x i32> @llvm.bswap.nxv1i32(<vscale x 1 x i32> %va)
ret <vscale x 1 x i32> %a
}
@@ -194,11 +194,11 @@ define <vscale x 2 x i32> @bswap_nxv2i32(<vscale x 2 x i32> %va) {
; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: ret
;
-; CHECK-ZVBB-LABEL: bswap_nxv2i32:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-ZVBB-NEXT: vrev8.v v8, v8
-; CHECK-ZVBB-NEXT: ret
+; CHECK-ZVKB-LABEL: bswap_nxv2i32:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.bswap.nxv2i32(<vscale x 2 x i32> %va)
ret <vscale x 2 x i32> %a
}
@@ -237,11 +237,11 @@ define <vscale x 4 x i32> @bswap_nxv4i32(<vscale x 4 x i32> %va) {
; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: ret
;
-; CHECK-ZVBB-LABEL: bswap_nxv4i32:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-ZVBB-NEXT: vrev8.v v8, v8
-; CHECK-ZVBB-NEXT: ret
+; CHECK-ZVKB-LABEL: bswap_nxv4i32:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32> %va)
ret <vscale x 4 x i32> %a
}
@@ -280,11 +280,11 @@ define <vscale x 8 x i32> @bswap_nxv8i32(<vscale x 8 x i32> %va) {
; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: ret
;
-; CHECK-ZVBB-LABEL: bswap_nxv8i32:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-ZVBB-NEXT: vrev8.v v8, v8
-; CHECK-ZVBB-NEXT: ret
+; CHECK-ZVKB-LABEL: bswap_nxv8i32:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 8 x i32> @llvm.bswap.nxv8i32(<vscale x 8 x i32> %va)
ret <vscale x 8 x i32> %a
}
@@ -323,11 +323,11 @@ define <vscale x 16 x i32> @bswap_nxv16i32(<vscale x 16 x i32> %va) {
; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: ret
;
-; CHECK-ZVBB-LABEL: bswap_nxv16i32:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-ZVBB-NEXT: vrev8.v v8, v8
-; CHECK-ZVBB-NEXT: ret
+; CHECK-ZVKB-LABEL: bswap_nxv16i32:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 16 x i32> @llvm.bswap.nxv16i32(<vscale x 16 x i32> %va)
ret <vscale x 16 x i32> %a
}
@@ -406,11 +406,11 @@ define <vscale x 1 x i64> @bswap_nxv1i64(<vscale x 1 x i64> %va) {
; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: ret
;
-; CHECK-ZVBB-LABEL: bswap_nxv1i64:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; CHECK-ZVBB-NEXT: vrev8.v v8, v8
-; CHECK-ZVBB-NEXT: ret
+; CHECK-ZVKB-LABEL: bswap_nxv1i64:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.bswap.nxv1i64(<vscale x 1 x i64> %va)
ret <vscale x 1 x i64> %a
}
@@ -489,11 +489,11 @@ define <vscale x 2 x i64> @bswap_nxv2i64(<vscale x 2 x i64> %va) {
; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: ret
;
-; CHECK-ZVBB-LABEL: bswap_nxv2i64:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-ZVBB-NEXT: vrev8.v v8, v8
-; CHECK-ZVBB-NEXT: ret
+; CHECK-ZVKB-LABEL: bswap_nxv2i64:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64> %va)
ret <vscale x 2 x i64> %a
}
@@ -572,11 +572,11 @@ define <vscale x 4 x i64> @bswap_nxv4i64(<vscale x 4 x i64> %va) {
; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: ret
;
-; CHECK-ZVBB-LABEL: bswap_nxv4i64:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-ZVBB-NEXT: vrev8.v v8, v8
-; CHECK-ZVBB-NEXT: ret
+; CHECK-ZVKB-LABEL: bswap_nxv4i64:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.bswap.nxv4i64(<vscale x 4 x i64> %va)
ret <vscale x 4 x i64> %a
}
@@ -669,11 +669,11 @@ define <vscale x 8 x i64> @bswap_nxv8i64(<vscale x 8 x i64> %va) {
; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: ret
;
-; CHECK-ZVBB-LABEL: bswap_nxv8i64:
-; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-ZVBB-NEXT: vrev8.v v8, v8
-; CHECK-ZVBB-NEXT: ret
+; CHECK-ZVKB-LABEL: bswap_nxv8i64:
+; CHECK-ZVKB: # %bb.0:
+; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-ZVKB-NEXT: vrev8.v v8, v8
+; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.bswap.nxv8i64(<vscale x 8 x i64> %va)
ret <vscale x 8 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
index be79222b5c5a7fa..3c4ff5e7d1cefc3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
@@ -3,10 +3,10 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCh...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/68115
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