[llvm] [AMDGPU] Add another SIFoldOperands instance after shrink (PR #67878)
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 3 02:14:43 PDT 2023
https://github.com/rampitec updated https://github.com/llvm/llvm-project/pull/67878
>From fa8ef5779a36039c345063b58c302f8b3951ee65 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: Sat, 30 Sep 2023 01:31:11 -0700
Subject: [PATCH 1/2] [AMDGPU] Add another SIFoldOperands instance after shrink
There is no fold operands pass past the shrink and at the same
time there are limited attempts to do shrinking right inside
folding. We seem to need to run shrinking before folding, hence
this patch. I can see some clear benefits in the tests we have.
I also need this for a future patch. We could extend our efforts
to do shrinkig inside folding, but at the end it will just result
in the recreation of the the shrinking pass there.
As an alternative I have tried to move previous instance of the
folding past the shrink, but the result is not as good as here and
there were few regressions. We may have some light compile time
regressions, hence it is disabled at -O1.
---
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 +
.../CodeGen/AMDGPU/GlobalISel/add.v2i16.ll | 5 +-
.../test/CodeGen/AMDGPU/GlobalISel/saddsat.ll | 161 +-
.../CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll | 8 +-
.../CodeGen/AMDGPU/GlobalISel/srem.i32.ll | 16 +-
.../CodeGen/AMDGPU/GlobalISel/srem.i64.ll | 4 +-
.../test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll | 161 +-
.../CodeGen/AMDGPU/GlobalISel/urem.i32.ll | 14 +-
.../CodeGen/AMDGPU/GlobalISel/urem.i64.ll | 6 +-
.../CodeGen/AMDGPU/ds-combine-large-stride.ll | 46 +-
.../CodeGen/AMDGPU/integer-mad-patterns.ll | 3 +-
llvm/test/CodeGen/AMDGPU/llc-pipeline.ll | 2 +
.../AMDGPU/promote-constOffset-to-imm.ll | 106 +-
llvm/test/CodeGen/AMDGPU/sdiv64.ll | 9 +-
.../CodeGen/AMDGPU/spill-scavenge-offset.ll | 1298 ++++++++---------
llvm/test/CodeGen/AMDGPU/srem64.ll | 9 +-
llvm/test/CodeGen/AMDGPU/udiv64.ll | 3 +-
llvm/test/CodeGen/AMDGPU/urem64.ll | 3 +-
18 files changed, 885 insertions(+), 971 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index bcbc03eb2559c4f..a674c52667c684b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1199,6 +1199,8 @@ void GCNPassConfig::addMachineSSAOptimization() {
}
addPass(&DeadMachineInstructionElimID);
addPass(createSIShrinkInstructionsPass());
+ if (TM->getOptLevel() > CodeGenOptLevel::Less)
+ addPass(&SIFoldOperandsID);
}
bool GCNPassConfig::addILPOpts() {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
index 26d1fbb09210c64..e9f30e8503b310e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
@@ -165,9 +165,8 @@ define <2 x i16> @v_add_v2i16_neg_inline_imm_splat(<2 x i16> %a) {
; GFX7-LABEL: v_add_v2i16_neg_inline_imm_splat:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_movk_i32 s4, 0xffc0
-; GFX7-NEXT: v_add_i32_e32 v0, vcc, s4, v0
-; GFX7-NEXT: v_add_i32_e32 v1, vcc, s4, v1
+; GFX7-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc0, v0
+; GFX7-NEXT: v_add_i32_e32 v1, vcc, 0xffffffc0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_add_v2i16_neg_inline_imm_splat:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
index cded5c94edf8cc3..c78d4533f4ddd3f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -231,14 +231,12 @@ define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v5, 0, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s5, v5
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x80000000, v5
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v1, v5, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v4
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
@@ -246,8 +244,8 @@ define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX6-NEXT: v_min_i32_e32 v4, 0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX6-NEXT: v_max_i32_e32 v3, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s5, v4
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x80000000, v4
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x7fffffff, v3
; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
@@ -512,15 +510,15 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, 0, v0
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, s5, v10
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s4, v8
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_max_i32_e32 v1, v10, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v8
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2
; GFX6-NEXT: v_min_i32_e32 v8, 0, v1
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v1
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s5, v8
@@ -1265,19 +1263,17 @@ define <2 x i32> @v_saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX6-LABEL: v_saddsat_v2i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v5, 0, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s5, v5
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x80000000, v5
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v2, v5, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_min_i32_e32 v4, 0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_max_i32_e32 v2, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s5, v4
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s4, v2
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x80000000, v4
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_max_i32_e32 v3, v4, v3
; GFX6-NEXT: v_min_i32_e32 v2, v3, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
@@ -1286,19 +1282,17 @@ define <2 x i32> @v_saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX8-LABEL: v_saddsat_v2i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s5, 1
; GFX8-NEXT: v_min_i32_e32 v5, 0, v0
-; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v4, 0, v0
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, s5, v5
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x80000000, v5
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_max_i32_e32 v2, v5, v2
; GFX8-NEXT: v_min_i32_e32 v2, v2, v4
; GFX8-NEXT: v_min_i32_e32 v4, 0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_max_i32_e32 v2, 0, v1
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, s5, v4
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s4, v2
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0x80000000, v4
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 0x7fffffff, v2
; GFX8-NEXT: v_max_i32_e32 v3, v4, v3
; GFX8-NEXT: v_min_i32_e32 v2, v3, v2
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v2
@@ -1383,26 +1377,25 @@ define <3 x i32> @v_saddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX6-LABEL: v_saddsat_v3i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v7, 0, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v6, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v7, vcc, s5, v7
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s4, v6
+; GFX6-NEXT: v_sub_i32_e32 v7, vcc, 0x80000000, v7
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x7fffffff, v6
; GFX6-NEXT: v_max_i32_e32 v3, v7, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v6
; GFX6-NEXT: v_min_i32_e32 v6, 0, v1
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GFX6-NEXT: v_max_i32_e32 v3, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s5, v6
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3
; GFX6-NEXT: v_max_i32_e32 v4, v6, v4
; GFX6-NEXT: v_min_i32_e32 v3, v4, v3
; GFX6-NEXT: v_min_i32_e32 v4, 0, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_max_i32_e32 v3, 0, v2
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s5, v4
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x80000000, v4
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x7fffffff, v3
; GFX6-NEXT: v_max_i32_e32 v4, v4, v5
; GFX6-NEXT: v_min_i32_e32 v3, v4, v3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
@@ -1411,26 +1404,25 @@ define <3 x i32> @v_saddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX8-LABEL: v_saddsat_v3i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s5, 1
; GFX8-NEXT: v_min_i32_e32 v7, 0, v0
-; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v6, 0, v0
-; GFX8-NEXT: v_sub_u32_e32 v7, vcc, s5, v7
-; GFX8-NEXT: v_sub_u32_e32 v6, vcc, s4, v6
+; GFX8-NEXT: v_sub_u32_e32 v7, vcc, 0x80000000, v7
+; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x7fffffff, v6
; GFX8-NEXT: v_max_i32_e32 v3, v7, v3
; GFX8-NEXT: v_min_i32_e32 v3, v3, v6
; GFX8-NEXT: v_min_i32_e32 v6, 0, v1
+; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_max_i32_e32 v3, 0, v1
-; GFX8-NEXT: v_sub_u32_e32 v6, vcc, s5, v6
+; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x80000000, v6
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s4, v3
; GFX8-NEXT: v_max_i32_e32 v4, v6, v4
; GFX8-NEXT: v_min_i32_e32 v3, v4, v3
; GFX8-NEXT: v_min_i32_e32 v4, 0, v2
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_max_i32_e32 v3, 0, v2
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, s5, v4
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s4, v3
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0x80000000, v4
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 0x7fffffff, v3
; GFX8-NEXT: v_max_i32_e32 v4, v4, v5
; GFX8-NEXT: v_min_i32_e32 v3, v4, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
@@ -1536,26 +1528,24 @@ define <4 x i32> @v_saddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX6-LABEL: v_saddsat_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v9, 0, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v9, vcc, s5, v9
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s4, v8
+; GFX6-NEXT: v_sub_i32_e32 v9, vcc, 0x80000000, v9
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_max_i32_e32 v4, v9, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v8
; GFX6-NEXT: v_min_i32_e32 v8, 0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_max_i32_e32 v4, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s5, v8
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x80000000, v8
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v5, v8, v5
; GFX6-NEXT: v_min_i32_e32 v4, v5, v4
; GFX6-NEXT: v_min_i32_e32 v5, 0, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_max_i32_e32 v4, 0, v2
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s5, v5
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x80000000, v5
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v5, v5, v6
; GFX6-NEXT: v_min_i32_e32 v4, v5, v4
; GFX6-NEXT: v_min_i32_e32 v5, 0, v3
@@ -1571,26 +1561,24 @@ define <4 x i32> @v_saddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX8-LABEL: v_saddsat_v4i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s5, 1
; GFX8-NEXT: v_min_i32_e32 v9, 0, v0
-; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v8, 0, v0
-; GFX8-NEXT: v_sub_u32_e32 v9, vcc, s5, v9
-; GFX8-NEXT: v_sub_u32_e32 v8, vcc, s4, v8
+; GFX8-NEXT: v_sub_u32_e32 v9, vcc, 0x80000000, v9
+; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 0x7fffffff, v8
; GFX8-NEXT: v_max_i32_e32 v4, v9, v4
; GFX8-NEXT: v_min_i32_e32 v4, v4, v8
; GFX8-NEXT: v_min_i32_e32 v8, 0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v4
; GFX8-NEXT: v_max_i32_e32 v4, 0, v1
-; GFX8-NEXT: v_sub_u32_e32 v8, vcc, s5, v8
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 0x80000000, v8
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_max_i32_e32 v5, v8, v5
; GFX8-NEXT: v_min_i32_e32 v4, v5, v4
; GFX8-NEXT: v_min_i32_e32 v5, 0, v2
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v4
; GFX8-NEXT: v_max_i32_e32 v4, 0, v2
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, s5, v5
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x80000000, v5
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_max_i32_e32 v5, v5, v6
; GFX8-NEXT: v_min_i32_e32 v4, v5, v4
; GFX8-NEXT: v_min_i32_e32 v5, 0, v3
@@ -1724,34 +1712,32 @@ define <5 x i32> @v_saddsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX6-LABEL: v_saddsat_v5i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_min_i32_e32 v12, 0, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
+; GFX6-NEXT: v_min_i32_e32 v11, 0, v0
; GFX6-NEXT: v_max_i32_e32 v10, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v12, vcc, s5, v12
-; GFX6-NEXT: v_sub_i32_e32 v10, vcc, s4, v10
-; GFX6-NEXT: v_max_i32_e32 v5, v12, v5
+; GFX6-NEXT: v_sub_i32_e32 v11, vcc, 0x80000000, v11
+; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 0x7fffffff, v10
+; GFX6-NEXT: v_max_i32_e32 v5, v11, v5
; GFX6-NEXT: v_min_i32_e32 v5, v5, v10
; GFX6-NEXT: v_min_i32_e32 v10, 0, v1
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v10, vcc, s5, v10
+; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 0x80000000, v10
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s4, v5
; GFX6-NEXT: v_max_i32_e32 v6, v10, v6
; GFX6-NEXT: v_min_i32_e32 v5, v6, v5
; GFX6-NEXT: v_min_i32_e32 v6, 0, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v2
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s5, v6
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s4, v5
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x7fffffff, v5
; GFX6-NEXT: v_max_i32_e32 v6, v6, v7
; GFX6-NEXT: v_min_i32_e32 v5, v6, v5
; GFX6-NEXT: v_min_i32_e32 v6, 0, v3
-; GFX6-NEXT: v_bfrev_b32_e32 v11, -2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v3
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v11, v5
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x7fffffff, v5
; GFX6-NEXT: v_max_i32_e32 v6, v6, v8
; GFX6-NEXT: v_min_i32_e32 v5, v6, v5
; GFX6-NEXT: v_min_i32_e32 v6, 0, v4
@@ -1767,34 +1753,32 @@ define <5 x i32> @v_saddsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX8-LABEL: v_saddsat_v5i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s5, 1
-; GFX8-NEXT: v_min_i32_e32 v12, 0, v0
-; GFX8-NEXT: s_brev_b32 s4, -2
+; GFX8-NEXT: v_min_i32_e32 v11, 0, v0
; GFX8-NEXT: v_max_i32_e32 v10, 0, v0
-; GFX8-NEXT: v_sub_u32_e32 v12, vcc, s5, v12
-; GFX8-NEXT: v_sub_u32_e32 v10, vcc, s4, v10
-; GFX8-NEXT: v_max_i32_e32 v5, v12, v5
+; GFX8-NEXT: v_sub_u32_e32 v11, vcc, 0x80000000, v11
+; GFX8-NEXT: v_sub_u32_e32 v10, vcc, 0x7fffffff, v10
+; GFX8-NEXT: v_max_i32_e32 v5, v11, v5
; GFX8-NEXT: v_min_i32_e32 v5, v5, v10
; GFX8-NEXT: v_min_i32_e32 v10, 0, v1
+; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v5
; GFX8-NEXT: v_max_i32_e32 v5, 0, v1
-; GFX8-NEXT: v_sub_u32_e32 v10, vcc, s5, v10
+; GFX8-NEXT: v_sub_u32_e32 v10, vcc, 0x80000000, v10
; GFX8-NEXT: v_sub_u32_e32 v5, vcc, s4, v5
; GFX8-NEXT: v_max_i32_e32 v6, v10, v6
; GFX8-NEXT: v_min_i32_e32 v5, v6, v5
; GFX8-NEXT: v_min_i32_e32 v6, 0, v2
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v5
; GFX8-NEXT: v_max_i32_e32 v5, 0, v2
-; GFX8-NEXT: v_sub_u32_e32 v6, vcc, s5, v6
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x80000000, v6
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x7fffffff, v5
; GFX8-NEXT: v_max_i32_e32 v6, v6, v7
; GFX8-NEXT: v_min_i32_e32 v5, v6, v5
; GFX8-NEXT: v_min_i32_e32 v6, 0, v3
-; GFX8-NEXT: v_bfrev_b32_e32 v11, -2
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_max_i32_e32 v5, 0, v3
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x80000000, v6
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v11, v5
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x7fffffff, v5
; GFX8-NEXT: v_max_i32_e32 v6, v6, v8
; GFX8-NEXT: v_min_i32_e32 v5, v6, v5
; GFX8-NEXT: v_min_i32_e32 v6, 0, v4
@@ -2766,13 +2750,11 @@ define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v5, 0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s5, v5
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x80000000, v5
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v2, v5, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
@@ -2780,8 +2762,8 @@ define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX6-NEXT: v_max_i32_e32 v3, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s5, v4
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x80000000, v4
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x7fffffff, v3
; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
@@ -2978,13 +2960,11 @@ define amdgpu_ps float @saddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: saddsat_v2i16_vs:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: s_brev_b32 s3, 1
; GFX6-NEXT: v_min_i32_e32 v3, 0, v0
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
-; GFX6-NEXT: s_brev_b32 s2, -2
; GFX6-NEXT: v_max_i32_e32 v2, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s3, v3
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x80000000, v3
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_max_i32_e32 v3, s0, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_min_i32_e32 v2, v3, v2
@@ -2992,8 +2972,8 @@ define amdgpu_ps float @saddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: s_lshl_b32 s0, s1, 16
; GFX6-NEXT: v_max_i32_e32 v2, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s3, v3
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x80000000, v3
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_max_i32_e32 v3, s0, v3
; GFX6-NEXT: v_min_i32_e32 v2, v3, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
@@ -3059,14 +3039,14 @@ define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v10, 0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, 0, v0
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, s5, v10
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s4, v8
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_max_i32_e32 v4, v10, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_min_i32_e32 v4, v4, v8
; GFX6-NEXT: v_min_i32_e32 v8, 0, v1
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v1
@@ -4847,8 +4827,7 @@ define <2 x i64> @v_saddsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[6:7], 0, v[4:5]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v9
-; GFX6-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, v0, v1
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0x80000000, v0
; GFX6-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
@@ -4871,8 +4850,7 @@ define <2 x i64> @v_saddsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[6:7], 0, v[4:5]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v9
-; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v0, v1
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0x80000000, v0
; GFX8-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
@@ -4895,8 +4873,7 @@ define <2 x i64> @v_saddsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[6:7], 0, v[4:5]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v9
-; GFX9-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v0, v1
+; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, 0x80000000, v0
; GFX9-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
index ab000d91a3ef23d..7f7788de6a7e1fe 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
@@ -295,7 +295,7 @@ define i32 @v_sdiv_i32_pow2k_denom(i32 %num) {
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0
; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[4:5]
-; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, s6, v0
+; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, 0x1000, v0
; CHECK-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[4:5]
; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v2
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
@@ -345,7 +345,7 @@ define <2 x i32> @v_sdiv_v2i32_pow2k_denom(<2 x i32> %num) {
; GISEL-NEXT: v_subrev_i32_e32 v7, vcc, s8, v0
; GISEL-NEXT: v_cmp_le_u32_e64 s[6:7], s8, v1
; GISEL-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[6:7]
-; GISEL-NEXT: v_subrev_i32_e32 v8, vcc, s8, v1
+; GISEL-NEXT: v_subrev_i32_e32 v8, vcc, 0x1000, v1
; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v7, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v5
; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[6:7]
@@ -437,7 +437,7 @@ define i32 @v_sdiv_i32_oddk_denom(i32 %num) {
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0
; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[4:5]
-; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, s6, v0
+; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, 0x12d8fb, v0
; CHECK-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[4:5]
; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v2
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
@@ -486,7 +486,7 @@ define <2 x i32> @v_sdiv_v2i32_oddk_denom(<2 x i32> %num) {
; GISEL-NEXT: v_subrev_i32_e32 v6, vcc, s8, v0
; GISEL-NEXT: v_cmp_le_u32_e64 s[6:7], s8, v1
; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, v9, s[6:7]
-; GISEL-NEXT: v_subrev_i32_e32 v7, vcc, s8, v1
+; GISEL-NEXT: v_subrev_i32_e32 v7, vcc, 0x12d8fb, v1
; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v4
; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[6:7]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
index 88ace1c51f5b023..6aff6200acff9f8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
@@ -268,10 +268,10 @@ define i32 @v_srem_i32_pow2k_denom(i32 %num) {
; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2
; CHECK-NEXT: v_lshlrev_b32_e32 v2, 12, v2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
-; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
+; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, 0x1000, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
+; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, 0x1000, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1
@@ -312,13 +312,13 @@ define <2 x i32> @v_srem_v2i32_pow2k_denom(<2 x i32> %num) {
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
-; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, s4, v1
+; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, 0x1000, v1
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
-; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, s4, v1
+; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, 0x1000, v1
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
@@ -399,10 +399,10 @@ define i32 @v_srem_i32_oddk_denom(i32 %num) {
; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2
; CHECK-NEXT: v_mul_lo_u32 v2, v2, s4
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
-; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
+; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, 0x12d8fb, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
+; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, 0x12d8fb, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1
@@ -443,13 +443,13 @@ define <2 x i32> @v_srem_v2i32_oddk_denom(<2 x i32> %num) {
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
-; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, s4, v1
+; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, 0x12d8fb, v1
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
-; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, s4, v1
+; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, 0x12d8fb, v1
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
index d0c55c69f508775..a89f01d62afa71f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
@@ -1078,7 +1078,7 @@ define i64 @v_srem_i64_pow2k_denom(i64 %num) {
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
-; CHECK-NEXT: v_sub_i32_e32 v4, vcc, v0, v6
+; CHECK-NEXT: v_subrev_i32_e32 v4, vcc, 0x1000, v0
; CHECK-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v4, v6
@@ -1699,7 +1699,7 @@ define i64 @v_srem_i64_oddk_denom(i64 %num) {
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
-; CHECK-NEXT: v_sub_i32_e32 v4, vcc, v0, v6
+; CHECK-NEXT: v_subrev_i32_e32 v4, vcc, 0x12d8fb, v0
; CHECK-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v4, v6
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index 65455d754be4f53..345982c1c693317 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -231,23 +231,21 @@ define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, -1, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_min_i32_e32 v5, -1, v0
-; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, 0x80000000, v5
; GFX6-NEXT: v_max_i32_e32 v1, v4, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v5
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX6-NEXT: v_max_i32_e32 v3, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x7fffffff, v3
; GFX6-NEXT: v_min_i32_e32 v4, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x80000000, v4
; GFX6-NEXT: v_max_i32_e32 v2, v3, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
@@ -506,20 +504,20 @@ define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, -1, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s4, v8
+; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_min_i32_e32 v10, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s5, v10
; GFX6-NEXT: v_max_i32_e32 v1, v8, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v10
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s4, v5
@@ -1265,19 +1263,17 @@ define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX6-LABEL: v_ssubsat_v2i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, -1, v0
-; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_min_i32_e32 v5, -1, v0
-; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, 0x80000000, v5
; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v5
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_max_i32_e32 v2, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s4, v2
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_min_i32_e32 v4, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x80000000, v4
; GFX6-NEXT: v_max_i32_e32 v2, v2, v3
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
@@ -1286,19 +1282,17 @@ define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX8-LABEL: v_ssubsat_v2i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v4, -1, v0
-; GFX8-NEXT: s_brev_b32 s5, 1
-; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_min_i32_e32 v5, -1, v0
-; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s5, v5
+; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, 0x80000000, v5
; GFX8-NEXT: v_max_i32_e32 v2, v4, v2
; GFX8-NEXT: v_min_i32_e32 v2, v2, v5
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_max_i32_e32 v2, -1, v1
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s4, v2
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 0x7fffffff, v2
; GFX8-NEXT: v_min_i32_e32 v4, -1, v1
-; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s5, v4
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 0x80000000, v4
; GFX8-NEXT: v_max_i32_e32 v2, v2, v3
; GFX8-NEXT: v_min_i32_e32 v2, v2, v4
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v2
@@ -1383,26 +1377,25 @@ define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX6-LABEL: v_ssubsat_v3i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v6, -1, v0
-; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s4, v6
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 0x7fffffff, v6
; GFX6-NEXT: v_min_i32_e32 v7, -1, v0
-; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, s5, v7
+; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 0x80000000, v7
; GFX6-NEXT: v_max_i32_e32 v3, v6, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v7
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; GFX6-NEXT: v_max_i32_e32 v3, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
; GFX6-NEXT: v_min_i32_e32 v6, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s5, v6
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v3, v3, v4
; GFX6-NEXT: v_min_i32_e32 v3, v3, v6
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_max_i32_e32 v3, -1, v2
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x7fffffff, v3
; GFX6-NEXT: v_min_i32_e32 v4, -1, v2
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x80000000, v4
; GFX6-NEXT: v_max_i32_e32 v3, v3, v5
; GFX6-NEXT: v_min_i32_e32 v3, v3, v4
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
@@ -1411,26 +1404,25 @@ define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX8-LABEL: v_ssubsat_v3i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v6, -1, v0
-; GFX8-NEXT: s_brev_b32 s5, 1
-; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s4, v6
+; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 0x7fffffff, v6
; GFX8-NEXT: v_min_i32_e32 v7, -1, v0
-; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, s5, v7
+; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 0x80000000, v7
; GFX8-NEXT: v_max_i32_e32 v3, v6, v3
; GFX8-NEXT: v_min_i32_e32 v3, v3, v7
+; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_max_i32_e32 v3, -1, v1
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s4, v3
; GFX8-NEXT: v_min_i32_e32 v6, -1, v1
-; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s5, v6
+; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 0x80000000, v6
; GFX8-NEXT: v_max_i32_e32 v3, v3, v4
; GFX8-NEXT: v_min_i32_e32 v3, v3, v6
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_max_i32_e32 v3, -1, v2
-; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s4, v3
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 0x7fffffff, v3
; GFX8-NEXT: v_min_i32_e32 v4, -1, v2
-; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s5, v4
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 0x80000000, v4
; GFX8-NEXT: v_max_i32_e32 v3, v3, v5
; GFX8-NEXT: v_min_i32_e32 v3, v3, v4
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v3
@@ -1536,26 +1528,24 @@ define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX6-LABEL: v_ssubsat_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, -1, v0
-; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s4, v8
+; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_min_i32_e32 v9, -1, v0
-; GFX6-NEXT: v_subrev_i32_e32 v9, vcc, s5, v9
+; GFX6-NEXT: v_subrev_i32_e32 v9, vcc, 0x80000000, v9
; GFX6-NEXT: v_max_i32_e32 v4, v8, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v9
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_max_i32_e32 v4, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_min_i32_e32 v8, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s5, v8
+; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, 0x80000000, v8
; GFX6-NEXT: v_max_i32_e32 v4, v4, v5
; GFX6-NEXT: v_min_i32_e32 v4, v4, v8
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_max_i32_e32 v4, -1, v2
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_min_i32_e32 v5, -1, v2
-; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, 0x80000000, v5
; GFX6-NEXT: v_max_i32_e32 v4, v4, v6
; GFX6-NEXT: v_min_i32_e32 v4, v4, v5
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v4
@@ -1571,26 +1561,24 @@ define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX8-LABEL: v_ssubsat_v4i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v8, -1, v0
-; GFX8-NEXT: s_brev_b32 s5, 1
-; GFX8-NEXT: v_subrev_u32_e32 v8, vcc, s4, v8
+; GFX8-NEXT: v_subrev_u32_e32 v8, vcc, 0x7fffffff, v8
; GFX8-NEXT: v_min_i32_e32 v9, -1, v0
-; GFX8-NEXT: v_subrev_u32_e32 v9, vcc, s5, v9
+; GFX8-NEXT: v_subrev_u32_e32 v9, vcc, 0x80000000, v9
; GFX8-NEXT: v_max_i32_e32 v4, v8, v4
; GFX8-NEXT: v_min_i32_e32 v4, v4, v9
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v4
; GFX8-NEXT: v_max_i32_e32 v4, -1, v1
-; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_min_i32_e32 v8, -1, v1
-; GFX8-NEXT: v_subrev_u32_e32 v8, vcc, s5, v8
+; GFX8-NEXT: v_subrev_u32_e32 v8, vcc, 0x80000000, v8
; GFX8-NEXT: v_max_i32_e32 v4, v4, v5
; GFX8-NEXT: v_min_i32_e32 v4, v4, v8
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v4
; GFX8-NEXT: v_max_i32_e32 v4, -1, v2
-; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_min_i32_e32 v5, -1, v2
-; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s5, v5
+; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, 0x80000000, v5
; GFX8-NEXT: v_max_i32_e32 v4, v4, v6
; GFX8-NEXT: v_min_i32_e32 v4, v4, v5
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v4
@@ -1724,32 +1712,30 @@ define <5 x i32> @v_ssubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX6-LABEL: v_ssubsat_v5i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v10, -1, v0
-; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s4, v10
-; GFX6-NEXT: v_min_i32_e32 v12, -1, v0
-; GFX6-NEXT: v_subrev_i32_e32 v12, vcc, s5, v12
+; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, 0x7fffffff, v10
+; GFX6-NEXT: v_min_i32_e32 v11, -1, v0
+; GFX6-NEXT: v_subrev_i32_e32 v11, vcc, 0x80000000, v11
; GFX6-NEXT: v_max_i32_e32 v5, v10, v5
-; GFX6-NEXT: v_min_i32_e32 v5, v5, v12
+; GFX6-NEXT: v_min_i32_e32 v5, v5, v11
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s4, v5
; GFX6-NEXT: v_min_i32_e32 v10, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s5, v10
+; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, 0x80000000, v10
; GFX6-NEXT: v_max_i32_e32 v5, v5, v6
; GFX6-NEXT: v_min_i32_e32 v5, v5, v10
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v2
-; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s4, v5
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, 0x7fffffff, v5
; GFX6-NEXT: v_min_i32_e32 v6, -1, v2
-; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s5, v6
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v5, v5, v7
; GFX6-NEXT: v_min_i32_e32 v5, v5, v6
-; GFX6-NEXT: v_bfrev_b32_e32 v11, -2
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v3
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v11
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, 0x7fffffff, v5
; GFX6-NEXT: v_min_i32_e32 v6, -1, v3
; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v5, v5, v8
@@ -1767,32 +1753,30 @@ define <5 x i32> @v_ssubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX8-LABEL: v_ssubsat_v5i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v10, -1, v0
-; GFX8-NEXT: s_brev_b32 s5, 1
-; GFX8-NEXT: v_subrev_u32_e32 v10, vcc, s4, v10
-; GFX8-NEXT: v_min_i32_e32 v12, -1, v0
-; GFX8-NEXT: v_subrev_u32_e32 v12, vcc, s5, v12
+; GFX8-NEXT: v_subrev_u32_e32 v10, vcc, 0x7fffffff, v10
+; GFX8-NEXT: v_min_i32_e32 v11, -1, v0
+; GFX8-NEXT: v_subrev_u32_e32 v11, vcc, 0x80000000, v11
; GFX8-NEXT: v_max_i32_e32 v5, v10, v5
-; GFX8-NEXT: v_min_i32_e32 v5, v5, v12
+; GFX8-NEXT: v_min_i32_e32 v5, v5, v11
+; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v5
; GFX8-NEXT: v_max_i32_e32 v5, -1, v1
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s4, v5
; GFX8-NEXT: v_min_i32_e32 v10, -1, v1
-; GFX8-NEXT: v_subrev_u32_e32 v10, vcc, s5, v10
+; GFX8-NEXT: v_subrev_u32_e32 v10, vcc, 0x80000000, v10
; GFX8-NEXT: v_max_i32_e32 v5, v5, v6
; GFX8-NEXT: v_min_i32_e32 v5, v5, v10
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v5
; GFX8-NEXT: v_max_i32_e32 v5, -1, v2
-; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, 0x7fffffff, v5
; GFX8-NEXT: v_min_i32_e32 v6, -1, v2
-; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s5, v6
+; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 0x80000000, v6
; GFX8-NEXT: v_max_i32_e32 v5, v5, v7
; GFX8-NEXT: v_min_i32_e32 v5, v5, v6
-; GFX8-NEXT: v_bfrev_b32_e32 v11, -2
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_max_i32_e32 v5, -1, v3
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v5, v11
+; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, 0x7fffffff, v5
; GFX8-NEXT: v_min_i32_e32 v6, -1, v3
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 0x80000000, v6
; GFX8-NEXT: v_max_i32_e32 v5, v5, v8
@@ -2766,22 +2750,20 @@ define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_min_i32_e32 v5, -1, v0
-; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, 0x80000000, v5
; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX6-NEXT: v_max_i32_e32 v3, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x7fffffff, v3
; GFX6-NEXT: v_min_i32_e32 v4, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x80000000, v4
; GFX6-NEXT: v_max_i32_e32 v2, v3, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
@@ -2978,22 +2960,20 @@ define amdgpu_ps float @ssubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: ssubsat_v2i16_vs:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: s_brev_b32 s2, -2
; GFX6-NEXT: v_max_i32_e32 v2, -1, v0
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
-; GFX6-NEXT: s_brev_b32 s3, 1
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_min_i32_e32 v3, -1, v0
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s3, v3
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_max_i32_e32 v2, s0, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_max_i32_e32 v2, -1, v1
; GFX6-NEXT: s_lshl_b32 s0, s1, 16
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_min_i32_e32 v3, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s3, v3
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_max_i32_e32 v2, s0, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
@@ -3056,16 +3036,16 @@ define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s4, v8
+; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_min_i32_e32 v10, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s5, v10
; GFX6-NEXT: v_max_i32_e32 v4, v8, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v10
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v1
@@ -4847,8 +4827,7 @@ define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]
; GFX6-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[4:5]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v9
-; GFX6-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, v0, v1
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0x80000000, v0
; GFX6-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
@@ -4871,8 +4850,7 @@ define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]
; GFX8-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[4:5]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v9
-; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v0, v1
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0x80000000, v0
; GFX8-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
@@ -4895,8 +4873,7 @@ define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[4:5]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v9
-; GFX9-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v0, v1
+; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, 0x80000000, v0
; GFX9-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
index 48f05a33f03649c..3af5ac98658ddac 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
@@ -222,10 +222,10 @@ define i32 @v_urem_i32_oddk_denom(i32 %num) {
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_mul_lo_u32 v1, v1, s4
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
-; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
+; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, 0x12d8fb, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
+; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, 0x12d8fb, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31]
@@ -253,13 +253,13 @@ define <2 x i32> @v_urem_v2i32_oddk_denom(<2 x i32> %num) {
; GISEL-NEXT: v_mul_lo_u32 v3, v3, v2
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
-; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
+; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, 0x12d8fb, v0
; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, 0x12d8fb, v1
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
+; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, 0x12d8fb, v0
; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, 0x12d8fb, v1
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
@@ -284,13 +284,13 @@ define <2 x i32> @v_urem_v2i32_oddk_denom(<2 x i32> %num) {
; CGP-NEXT: v_mul_lo_u32 v2, v2, s4
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
-; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
-; CGP-NEXT: v_subrev_i32_e32 v3, vcc, s4, v1
+; CGP-NEXT: v_subrev_i32_e32 v2, vcc, 0x12d8fb, v0
+; CGP-NEXT: v_subrev_i32_e32 v3, vcc, 0x12d8fb, v1
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
+; CGP-NEXT: v_subrev_i32_e32 v2, vcc, 0x12d8fb, v0
; CGP-NEXT: v_subrev_i32_e32 v3, vcc, 0x12d8fb, v1
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
index 097f6642cbc669b..f5b27906ed67ed8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
@@ -1068,7 +1068,7 @@ define i64 @v_urem_i64_oddk_denom(i64 %num) {
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
-; CHECK-NEXT: v_sub_i32_e32 v5, vcc, v0, v2
+; CHECK-NEXT: v_subrev_i32_e32 v5, vcc, 0x12d8fb, v0
; CHECK-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v4
; CHECK-NEXT: v_cndmask_b32_e64 v3, -1, v3, s[6:7]
; CHECK-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
@@ -1295,7 +1295,7 @@ define <2 x i64> @v_urem_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v3, v5
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4
; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
-; GISEL-NEXT: v_sub_i32_e32 v9, vcc, v2, v4
+; GISEL-NEXT: v_subrev_i32_e32 v9, vcc, 0x12d8fb, v2
; GISEL-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v7
; GISEL-NEXT: v_cndmask_b32_e64 v6, -1, v6, s[8:9]
; GISEL-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
@@ -1530,7 +1530,7 @@ define <2 x i64> @v_urem_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v3, v6
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4
; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
-; CGP-NEXT: v_sub_i32_e32 v9, vcc, v2, v4
+; CGP-NEXT: v_subrev_i32_e32 v9, vcc, 0x12d8fb, v2
; CGP-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v7
; CGP-NEXT: v_cndmask_b32_e64 v5, -1, v5, s[8:9]
; CGP-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll b/llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
index aa1d44c31606b8f..726203c4156708b 100644
--- a/llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
@@ -5,9 +5,9 @@
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x200, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x400, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x800, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x200, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]
@@ -50,8 +50,8 @@ bb:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x400, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x800, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x400, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x800, [[BASE]]
@@ -94,9 +94,9 @@ bb:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x800, [[BASE]]
; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x200, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]
@@ -173,9 +173,9 @@ bb:
; GCN-LABEL: ds_read32_combine_stride_8192_shifted:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
-; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
+; GFX9: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
+; VI-DAG: v_add_u32_e64 [[B1:v[0-9]+]], vcc, [[ARG]], 8
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 8, [[BASE]]
; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:32
@@ -209,7 +209,7 @@ bb:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x800, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]
; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:50
@@ -247,9 +247,9 @@ bb:
; GCN-LABEL: ds_read64_combine_stride_8192_shifted:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
-; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
+; GFX9: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
+; VI-DAG: v_add_u32_e64 [[B1:v[0-9]+]], vcc, [[ARG]], 8
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 8, [[BASE]]
; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:16
@@ -283,9 +283,9 @@ bb:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x200, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x400, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x800, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x200, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]
@@ -319,9 +319,9 @@ bb:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x800, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x400, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x200, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]
@@ -380,9 +380,9 @@ bb:
; GCN-LABEL: ds_write32_combine_stride_8192_shifted:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
-; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
+; GFX9: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[BASE:v[0-9]+]], vcc, 4, [[BASE]]
+; VI-DAG: v_add_u32_e64 [[BASE:v[0-9]+]], vcc, [[ARG]], 4
; GFX9-DAG: v_add_u32_e32 [[BASE:v[0-9]+]], 4, [[BASE]]
; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
@@ -409,7 +409,7 @@ bb:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x800, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]
; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:50
@@ -438,9 +438,9 @@ bb:
; GCN-LABEL: ds_write64_combine_stride_8192_shifted:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
-; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
+; GFX9: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[BASE]], vcc, 8, [[BASE]]
+; VI-DAG: v_add_u32_e64 [[BASE:v[0-9]+]], vcc, [[ARG]], 8
; GFX9-DAG: v_add_u32_e32 [[BASE]], 8, [[BASE]]
; GCN-DAG: ds_write2st64_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16
diff --git a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
index 61017e809c86365..70a7f67f5b8d0d6 100644
--- a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+++ b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
@@ -3273,9 +3273,8 @@ define <2 x i8> @clpeak_imad_pat_v2i8(<2 x i8> %x, <2 x i8> %y) {
; GFX67-SDAG-NEXT: v_lshlrev_b32_e32 v4, 8, v6
; GFX67-SDAG-NEXT: v_mul_u32_u24_e32 v5, v0, v2
; GFX67-SDAG-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX67-SDAG-NEXT: s_movk_i32 s4, 0x100
; GFX67-SDAG-NEXT: v_mad_u32_u24 v0, v0, v2, 1
-; GFX67-SDAG-NEXT: v_add_i32_e32 v3, vcc, s4, v3
+; GFX67-SDAG-NEXT: v_add_i32_e32 v3, vcc, 0x100, v3
; GFX67-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX67-SDAG-NEXT: v_lshlrev_b32_e32 v2, 8, v1
; GFX67-SDAG-NEXT: v_or_b32_e32 v0, v2, v0
diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
index b939c8d2e339de4..25047121f31ff61 100644
--- a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
@@ -920,6 +920,7 @@
; GCN-O2-NEXT: SI Fold Operands
; GCN-O2-NEXT: Remove dead machine instructions
; GCN-O2-NEXT: SI Shrink Instructions
+; GCN-O2-NEXT: SI Fold Operands
; GCN-O2-NEXT: Register Usage Information Propagation
; GCN-O2-NEXT: Detect Dead Lanes
; GCN-O2-NEXT: Remove dead machine instructions
@@ -1238,6 +1239,7 @@
; GCN-O3-NEXT: SI Fold Operands
; GCN-O3-NEXT: Remove dead machine instructions
; GCN-O3-NEXT: SI Shrink Instructions
+; GCN-O3-NEXT: SI Fold Operands
; GCN-O3-NEXT: Register Usage Information Propagation
; GCN-O3-NEXT: Detect Dead Lanes
; GCN-O3-NEXT: Remove dead machine instructions
diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
index a462c19ce645d4a..c2b10c160bf586a 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
@@ -54,13 +54,11 @@ define amdgpu_kernel void @clmem_read_simplified(ptr addrspace(1) %buffer) {
; GFX8-NEXT: s_movk_i32 s0, 0x2000
; GFX8-NEXT: v_add_u32_e32 v13, vcc, s0, v0
; GFX8-NEXT: v_addc_u32_e32 v14, vcc, 0, v1, vcc
-; GFX8-NEXT: s_movk_i32 s0, 0x2800
-; GFX8-NEXT: v_add_u32_e32 v15, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v15, vcc, 0x2800, v0
; GFX8-NEXT: v_addc_u32_e32 v16, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx2 v[13:14], v[13:14]
; GFX8-NEXT: flat_load_dwordx2 v[15:16], v[15:16]
-; GFX8-NEXT: s_movk_i32 s0, 0x3000
-; GFX8-NEXT: v_add_u32_e32 v17, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v17, vcc, 0x3000, v0
; GFX8-NEXT: v_addc_u32_e32 v18, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx2 v[17:18], v[17:18]
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x3800, v0
@@ -132,8 +130,7 @@ define amdgpu_kernel void @clmem_read_simplified(ptr addrspace(1) %buffer) {
; GFX900-NEXT: global_load_dwordx2 v[12:13], v[10:11], off offset:2048
; GFX900-NEXT: global_load_dwordx2 v[14:15], v[6:7], off
; GFX900-NEXT: global_load_dwordx2 v[16:17], v[6:7], off offset:2048
-; GFX900-NEXT: s_movk_i32 s0, 0x3000
-; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
+; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, 0x3000, v0
; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX900-NEXT: global_load_dwordx2 v[6:7], v[0:1], off
; GFX900-NEXT: global_load_dwordx2 v[10:11], v[0:1], off offset:2048
@@ -276,8 +273,7 @@ define amdgpu_kernel void @clmem_read_simplified(ptr addrspace(1) %buffer) {
; GFX90A-NEXT: global_load_dwordx2 v[12:13], v[10:11], off offset:2048
; GFX90A-NEXT: global_load_dwordx2 v[14:15], v[6:7], off
; GFX90A-NEXT: global_load_dwordx2 v[16:17], v[6:7], off offset:2048
-; GFX90A-NEXT: s_movk_i32 s0, 0x3000
-; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, 0x3000, v0
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX90A-NEXT: global_load_dwordx2 v[6:7], v[0:1], off
; GFX90A-NEXT: global_load_dwordx2 v[10:11], v[0:1], off offset:2048
@@ -573,21 +569,17 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX900-NEXT: v_mov_b32_e32 v3, s35
; GFX900-NEXT: v_add_co_u32_e32 v1, vcc, s34, v1
; GFX900-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v3, vcc
-; GFX900-NEXT: s_movk_i32 s0, 0x5000
-; GFX900-NEXT: v_add_co_u32_e32 v1, vcc, s0, v1
+; GFX900-NEXT: v_add_co_u32_e32 v1, vcc, 0x5000, v1
; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
-; GFX900-NEXT: s_movk_i32 s2, 0x7f
; GFX900-NEXT: v_mov_b32_e32 v4, 0
-; GFX900-NEXT: s_movk_i32 s0, 0xd000
-; GFX900-NEXT: s_movk_i32 s1, 0xe000
-; GFX900-NEXT: s_movk_i32 s3, 0xf000
+; GFX900-NEXT: s_movk_i32 s0, 0x7f
; GFX900-NEXT: .LBB1_1: ; %for.cond.preheader
; GFX900-NEXT: ; =>This Loop Header: Depth=1
; GFX900-NEXT: ; Child Loop BB1_2 Depth 2
; GFX900-NEXT: v_mov_b32_e32 v6, v2
; GFX900-NEXT: v_mov_b32_e32 v5, v1
-; GFX900-NEXT: s_mov_b32 s4, 0
+; GFX900-NEXT: s_mov_b32 s1, 0
; GFX900-NEXT: .LBB1_2: ; %for.body
; GFX900-NEXT: ; Parent Loop BB1_1 Depth=1
; GFX900-NEXT: ; => This Inner Loop Header: Depth=2
@@ -599,23 +591,23 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX900-NEXT: global_load_dwordx2 v[7:8], v[7:8], off
; GFX900-NEXT: v_addc_co_u32_e32 v14, vcc, -1, v6, vcc
; GFX900-NEXT: global_load_dwordx2 v[17:18], v[13:14], off offset:-2048
-; GFX900-NEXT: v_add_co_u32_e32 v15, vcc, s0, v5
+; GFX900-NEXT: v_add_co_u32_e32 v15, vcc, 0xffffd000, v5
; GFX900-NEXT: v_addc_co_u32_e32 v16, vcc, -1, v6, vcc
; GFX900-NEXT: global_load_dwordx2 v[15:16], v[15:16], off offset:-2048
-; GFX900-NEXT: v_add_co_u32_e32 v19, vcc, s1, v5
+; GFX900-NEXT: v_add_co_u32_e32 v19, vcc, 0xffffe000, v5
; GFX900-NEXT: global_load_dwordx2 v[13:14], v[13:14], off
; GFX900-NEXT: v_addc_co_u32_e32 v20, vcc, -1, v6, vcc
; GFX900-NEXT: global_load_dwordx2 v[23:24], v[19:20], off offset:-4096
; GFX900-NEXT: global_load_dwordx2 v[25:26], v[19:20], off offset:-2048
; GFX900-NEXT: global_load_dwordx2 v[27:28], v[19:20], off
-; GFX900-NEXT: v_add_co_u32_e32 v21, vcc, s3, v5
+; GFX900-NEXT: v_add_co_u32_e32 v21, vcc, 0xfffff000, v5
; GFX900-NEXT: v_addc_co_u32_e32 v22, vcc, -1, v6, vcc
; GFX900-NEXT: global_load_dwordx2 v[19:20], v[21:22], off offset:-2048
; GFX900-NEXT: global_load_dwordx2 v[29:30], v[5:6], off
; GFX900-NEXT: v_add_co_u32_e32 v5, vcc, 0x10000, v5
; GFX900-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
-; GFX900-NEXT: s_addk_i32 s4, 0x2000
-; GFX900-NEXT: s_cmp_gt_u32 s4, 0x3fffff
+; GFX900-NEXT: s_addk_i32 s1, 0x2000
+; GFX900-NEXT: s_cmp_gt_u32 s1, 0x3fffff
; GFX900-NEXT: s_waitcnt vmcnt(8)
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, v7, v3
; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
@@ -649,11 +641,11 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX900-NEXT: s_cbranch_scc0 .LBB1_2
; GFX900-NEXT: ; %bb.3: ; %while.cond.loopexit
; GFX900-NEXT: ; in Loop: Header=BB1_1 Depth=1
-; GFX900-NEXT: s_add_i32 s4, s2, -1
-; GFX900-NEXT: s_cmp_eq_u32 s2, 0
+; GFX900-NEXT: s_add_i32 s1, s0, -1
+; GFX900-NEXT: s_cmp_eq_u32 s0, 0
; GFX900-NEXT: s_cbranch_scc1 .LBB1_5
; GFX900-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1
-; GFX900-NEXT: s_mov_b32 s2, s4
+; GFX900-NEXT: s_mov_b32 s0, s1
; GFX900-NEXT: s_branch .LBB1_1
; GFX900-NEXT: .LBB1_5: ; %while.end
; GFX900-NEXT: v_mov_b32_e32 v1, s35
@@ -805,19 +797,15 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX90A-NEXT: v_mov_b32_e32 v2, s35
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, s34, v1
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v2, vcc
-; GFX90A-NEXT: s_movk_i32 s0, 0x5000
-; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, s0, v1
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x5000, v1
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
-; GFX90A-NEXT: s_movk_i32 s2, 0x7f
+; GFX90A-NEXT: s_movk_i32 s0, 0x7f
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], 0, 0
-; GFX90A-NEXT: s_movk_i32 s0, 0xd000
-; GFX90A-NEXT: s_movk_i32 s1, 0xe000
-; GFX90A-NEXT: s_movk_i32 s3, 0xf000
; GFX90A-NEXT: .LBB1_1: ; %for.cond.preheader
; GFX90A-NEXT: ; =>This Loop Header: Depth=1
; GFX90A-NEXT: ; Child Loop BB1_2 Depth 2
; GFX90A-NEXT: v_pk_mov_b32 v[6:7], v[2:3], v[2:3] op_sel:[0,1]
-; GFX90A-NEXT: s_mov_b32 s4, 0
+; GFX90A-NEXT: s_mov_b32 s1, 0
; GFX90A-NEXT: .LBB1_2: ; %for.body
; GFX90A-NEXT: ; Parent Loop BB1_1 Depth=1
; GFX90A-NEXT: ; => This Inner Loop Header: Depth=2
@@ -829,23 +817,23 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX90A-NEXT: global_load_dwordx2 v[12:13], v[12:13], off
; GFX90A-NEXT: v_addc_co_u32_e32 v15, vcc, -1, v7, vcc
; GFX90A-NEXT: global_load_dwordx2 v[18:19], v[14:15], off offset:-2048
-; GFX90A-NEXT: v_add_co_u32_e32 v16, vcc, s0, v6
+; GFX90A-NEXT: v_add_co_u32_e32 v16, vcc, 0xffffd000, v6
; GFX90A-NEXT: v_addc_co_u32_e32 v17, vcc, -1, v7, vcc
; GFX90A-NEXT: global_load_dwordx2 v[16:17], v[16:17], off offset:-2048
-; GFX90A-NEXT: v_add_co_u32_e32 v20, vcc, s1, v6
+; GFX90A-NEXT: v_add_co_u32_e32 v20, vcc, 0xffffe000, v6
; GFX90A-NEXT: global_load_dwordx2 v[14:15], v[14:15], off
; GFX90A-NEXT: v_addc_co_u32_e32 v21, vcc, -1, v7, vcc
; GFX90A-NEXT: global_load_dwordx2 v[24:25], v[20:21], off offset:-4096
; GFX90A-NEXT: global_load_dwordx2 v[26:27], v[20:21], off offset:-2048
; GFX90A-NEXT: global_load_dwordx2 v[28:29], v[20:21], off
-; GFX90A-NEXT: v_add_co_u32_e32 v22, vcc, s3, v6
+; GFX90A-NEXT: v_add_co_u32_e32 v22, vcc, 0xfffff000, v6
; GFX90A-NEXT: v_addc_co_u32_e32 v23, vcc, -1, v7, vcc
; GFX90A-NEXT: global_load_dwordx2 v[20:21], v[22:23], off offset:-2048
; GFX90A-NEXT: global_load_dwordx2 v[30:31], v[6:7], off
; GFX90A-NEXT: v_add_co_u32_e32 v6, vcc, 0x10000, v6
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
-; GFX90A-NEXT: s_addk_i32 s4, 0x2000
-; GFX90A-NEXT: s_cmp_gt_u32 s4, 0x3fffff
+; GFX90A-NEXT: s_addk_i32 s1, 0x2000
+; GFX90A-NEXT: s_cmp_gt_u32 s1, 0x3fffff
; GFX90A-NEXT: s_waitcnt vmcnt(8)
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, v12, v4
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v13, v5, vcc
@@ -879,11 +867,11 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX90A-NEXT: s_cbranch_scc0 .LBB1_2
; GFX90A-NEXT: ; %bb.3: ; %while.cond.loopexit
; GFX90A-NEXT: ; in Loop: Header=BB1_1 Depth=1
-; GFX90A-NEXT: s_add_i32 s4, s2, -1
-; GFX90A-NEXT: s_cmp_eq_u32 s2, 0
+; GFX90A-NEXT: s_add_i32 s1, s0, -1
+; GFX90A-NEXT: s_cmp_eq_u32 s0, 0
; GFX90A-NEXT: s_cbranch_scc1 .LBB1_5
; GFX90A-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1
-; GFX90A-NEXT: s_mov_b32 s2, s4
+; GFX90A-NEXT: s_mov_b32 s0, s1
; GFX90A-NEXT: s_branch .LBB1_1
; GFX90A-NEXT: .LBB1_5: ; %while.end
; GFX90A-NEXT: v_mov_b32_e32 v1, s35
@@ -1163,10 +1151,8 @@ define amdgpu_kernel void @Address32(ptr addrspace(1) %buffer) {
; GFX8-NEXT: s_movk_i32 s0, 0x1800
; GFX8-NEXT: v_add_u32_e32 v15, vcc, s0, v0
; GFX8-NEXT: v_addc_u32_e32 v16, vcc, 0, v1, vcc
-; GFX8-NEXT: s_movk_i32 s0, 0x1c00
-; GFX8-NEXT: v_add_u32_e32 v17, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v17, vcc, 0x1c00, v0
; GFX8-NEXT: v_addc_u32_e32 v18, vcc, 0, v1, vcc
-; GFX8-NEXT: s_movk_i32 s0, 0x2000
; GFX8-NEXT: flat_load_dword v2, v[0:1]
; GFX8-NEXT: flat_load_dword v19, v[5:6]
; GFX8-NEXT: flat_load_dword v7, v[7:8]
@@ -1175,7 +1161,7 @@ define amdgpu_kernel void @Address32(ptr addrspace(1) %buffer) {
; GFX8-NEXT: flat_load_dword v10, v[13:14]
; GFX8-NEXT: flat_load_dword v11, v[15:16]
; GFX8-NEXT: flat_load_dword v12, v[17:18]
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x2000, v0
; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x2400, v0
; GFX8-NEXT: flat_load_dword v5, v[5:6]
@@ -1230,10 +1216,9 @@ define amdgpu_kernel void @Address32(ptr addrspace(1) %buffer) {
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v4
; GFX900-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v0, vcc
; GFX900-NEXT: v_lshlrev_b64 v[0:1], 2, v[1:2]
-; GFX900-NEXT: s_movk_i32 s0, 0x1000
; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0
; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v1, vcc
-; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, s0, v0
+; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, 0x1000, v0
; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX900-NEXT: global_load_dword v5, v[0:1], off
; GFX900-NEXT: global_load_dword v6, v[0:1], off offset:1024
@@ -1357,8 +1342,7 @@ define amdgpu_kernel void @Address32(ptr addrspace(1) %buffer) {
; GFX90A-NEXT: v_lshlrev_b64 v[0:1], 2, v[2:3]
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v5, v0
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v1, vcc
-; GFX90A-NEXT: s_movk_i32 s0, 0x1000
-; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, s0, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x1000, v0
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX90A-NEXT: global_load_dword v5, v[0:1], off
; GFX90A-NEXT: global_load_dword v6, v[0:1], off offset:1024
@@ -1526,10 +1510,9 @@ define amdgpu_kernel void @Offset64(ptr addrspace(1) %buffer) {
; GFX8-NEXT: s_movk_i32 s0, 0xf000
; GFX8-NEXT: v_add_u32_e32 v5, vcc, s0, v0
; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc
-; GFX8-NEXT: s_movk_i32 s0, 0xf800
; GFX8-NEXT: flat_load_dwordx2 v[7:8], v[0:1]
; GFX8-NEXT: flat_load_dwordx2 v[5:6], v[5:6]
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0xfffff800, v0
; GFX8-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx2 v[9:10], v[9:10]
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0
@@ -1804,11 +1787,9 @@ define amdgpu_kernel void @p32Offset64(ptr addrspace(1) %buffer) {
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v3, v0
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
-; GFX8-NEXT: s_mov_b32 s0, 0x7ffff800
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7ffff800, v0
; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc
-; GFX8-NEXT: s_mov_b32 s0, 0x7ffffc00
-; GFX8-NEXT: v_add_u32_e32 v7, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, 0x7ffffc00, v0
; GFX8-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v2, v[0:1]
; GFX8-NEXT: flat_load_dword v5, v[5:6]
@@ -2348,13 +2329,11 @@ define amdgpu_kernel void @ReverseOrder(ptr addrspace(1) %buffer) {
; GFX8-NEXT: s_movk_i32 s0, 0x2000
; GFX8-NEXT: v_add_u32_e32 v13, vcc, s0, v0
; GFX8-NEXT: v_addc_u32_e32 v14, vcc, 0, v1, vcc
-; GFX8-NEXT: s_movk_i32 s0, 0x1800
-; GFX8-NEXT: v_add_u32_e32 v15, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v15, vcc, 0x1800, v0
; GFX8-NEXT: v_addc_u32_e32 v16, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx2 v[13:14], v[13:14]
; GFX8-NEXT: flat_load_dwordx2 v[15:16], v[15:16]
-; GFX8-NEXT: s_movk_i32 s0, 0x1000
-; GFX8-NEXT: v_add_u32_e32 v17, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v17, vcc, 0x1000, v0
; GFX8-NEXT: v_addc_u32_e32 v18, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx2 v[17:18], v[17:18]
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x800, v0
@@ -2424,8 +2403,7 @@ define amdgpu_kernel void @ReverseOrder(ptr addrspace(1) %buffer) {
; GFX900-NEXT: v_add_co_u32_e32 v4, vcc, s0, v0
; GFX900-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
; GFX900-NEXT: global_load_dwordx2 v[10:11], v[4:5], off offset:2048
-; GFX900-NEXT: s_movk_i32 s0, 0x1000
-; GFX900-NEXT: v_add_co_u32_e32 v12, vcc, s0, v0
+; GFX900-NEXT: v_add_co_u32_e32 v12, vcc, 0x1000, v0
; GFX900-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v1, vcc
; GFX900-NEXT: global_load_dwordx2 v[14:15], v[12:13], off
; GFX900-NEXT: global_load_dwordx2 v[16:17], v[4:5], off
@@ -2571,8 +2549,7 @@ define amdgpu_kernel void @ReverseOrder(ptr addrspace(1) %buffer) {
; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, s0, v0
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
; GFX90A-NEXT: global_load_dwordx2 v[10:11], v[4:5], off offset:2048
-; GFX90A-NEXT: s_movk_i32 s0, 0x1000
-; GFX90A-NEXT: v_add_co_u32_e32 v12, vcc, s0, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v12, vcc, 0x1000, v0
; GFX90A-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v1, vcc
; GFX90A-NEXT: global_load_dwordx2 v[14:15], v[12:13], off
; GFX90A-NEXT: global_load_dwordx2 v[16:17], v[4:5], off
@@ -2743,8 +2720,7 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v0
; GFX8-NEXT: v_addc_u32_e32 v6, vcc, v4, v1, vcc
-; GFX8-NEXT: s_movk_i32 s0, 0x800
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x800, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, -1, v6, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0, v2
; GFX8-NEXT: v_addc_u32_e32 v6, vcc, -1, v6, vcc
@@ -2784,10 +2760,9 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v8
; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v0, vcc
; GFX900-NEXT: v_lshlrev_b64 v[0:1], 3, v[1:2]
-; GFX900-NEXT: s_movk_i32 s0, 0x1000
; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, v3, v0
; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v1, vcc
-; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2
+; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v2
; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v3, vcc
; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, 0, v2
; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc
@@ -2871,8 +2846,7 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf
; GFX90A-NEXT: v_lshlrev_b64 v[0:1], 3, v[2:3]
; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v4, v0
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v1, vcc
-; GFX90A-NEXT: s_movk_i32 s0, 0x1000
-; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2
+; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v3, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
index 705a2af73959065..7361d9d9f795e39 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
@@ -1394,8 +1394,7 @@ define i64 @v_test_sdiv_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4
; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1
; GCN-IR-NEXT: v_min_u32_e32 v8, v4, v5
-; GCN-IR-NEXT: s_movk_i32 s6, 0xffc5
-; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, s6, v8
+; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, 0xffffffc5, v8
; GCN-IR-NEXT: v_addc_u32_e64 v6, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[5:6]
@@ -1587,8 +1586,7 @@ define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4
; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1
; GCN-IR-NEXT: v_min_u32_e32 v8, v4, v5
-; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0
-; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, s6, v8
+; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, 0xffffffd0, v8
; GCN-IR-NEXT: v_addc_u32_e64 v6, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[5:6]
@@ -1722,13 +1720,12 @@ define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
-; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: .LBB13_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[9:10], v[9:10], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v4
; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
-; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, s12, v0
+; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, 0x7fff, v0
; GCN-IR-NEXT: v_subb_u32_e32 v5, vcc, 0, v10, vcc
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v7
; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1
diff --git a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
index 08db1e7fee259d6..dd4eb0ae2a09ed6 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
@@ -5000,22 +5000,14 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
; GFX9-FLATSCR-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
; GFX9-FLATSCR-NEXT: v_lshlrev_b32_e32 v5, 13, v0
-; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x80
+; GFX9-FLATSCR-NEXT: s_mov_b32 s4, 4
; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v2, vcc, s2, v5
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, s3
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v0, vcc
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s4, v2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x80, v2
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
-; GFX9-FLATSCR-NEXT: s_mov_b32 s4, 4
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0x84
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x104
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x184
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x204
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x284
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x304
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x384
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
@@ -5043,1268 +5035,1268 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4080
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x100, v2
; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x74
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x100
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s4, v2
-; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x84
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0x94
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x94
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0xa4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0xb4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0xc4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0xd4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0xe4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0xf4
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0x180
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s5, v2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x180, v2
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x104
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x114
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x114
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x124
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x124
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x134
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x134
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x144
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x144
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x154
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x154
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x164
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x164
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x174
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x200
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s6, v2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x200, v2
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x174
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x184
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x194
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x194
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x1a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x1b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x1c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x1d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x1e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x1f4
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x280
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s7, v2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x280, v2
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1f4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x204
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x214
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x214
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x224
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x224
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x234
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x234
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x244
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x244
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x254
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x254
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x264
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x264
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x274
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x300
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s8, v2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x300, v2
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x274
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x284
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x294
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x294
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x2a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x2a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x2b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x2b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x2c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x2c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x2d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x2d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x2e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x2e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x2f4
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x380
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s9, v2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x380, v2
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x2f4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x304
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x314
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x314
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x324
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x324
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x334
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x334
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x344
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x344
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x354
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x354
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x364
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x364
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x374
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x400
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s10, v2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x400, v2
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x374
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x384
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x394
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x394
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x3a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x3a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x3b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x3b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x3c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x3c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x3d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x3d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4064
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x3e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x3e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(1)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s11 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x3f4
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x3f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(1)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3]
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x404
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x404
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, s1
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:16
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x414
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x414
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:32
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x424
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x424
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:48
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x434
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x434
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:64
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x444
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x444
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:80
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x454
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x454
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:96
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x464
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x464
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:112
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x474
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x474
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:128
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x484
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x484
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:144
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x494
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x494
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:160
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x4a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x4a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:176
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x4b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x4b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:192
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x4c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x4c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:208
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x4d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x4d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:224
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x4e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x4e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:240
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x4f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x4f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:256
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x504
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x504
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:272
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x514
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x514
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:288
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x524
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x524
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:304
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x534
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x534
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:320
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x544
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x544
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:336
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x554
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x554
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:352
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x564
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x564
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:368
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x574
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x574
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:384
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x584
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x584
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:400
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x594
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x594
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:416
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x5a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x5a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:432
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x5b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x5b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:448
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x5c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x5c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:464
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x5d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x5d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:480
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x5e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x5e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:496
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x5f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x5f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:512
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x604
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x604
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:528
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x614
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x614
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:544
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x624
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x624
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:560
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x634
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x634
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:576
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x644
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x644
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:592
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x654
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x654
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:608
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x664
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x664
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:624
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x674
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x674
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:640
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x684
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x684
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:656
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x694
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x694
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:672
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x6a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x6a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:688
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x6b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x6b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:704
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x6c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x6c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:720
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x6d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x6d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:736
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x6e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x6e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:752
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x6f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x6f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:768
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x704
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x704
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:784
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x714
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x714
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:800
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x724
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x724
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:816
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x734
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x734
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:832
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x744
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x744
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:848
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x754
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x754
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:864
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x764
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x764
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:880
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x774
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x774
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:896
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x784
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x784
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:912
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x794
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x794
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:928
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x7a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x7a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:944
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x7b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x7b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:960
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x7c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x7c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:976
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x7d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x7d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:992
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x7e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x7e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1008
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x7f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x7f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1024
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x804
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x804
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1040
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x814
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x814
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1056
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x824
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x824
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1072
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x834
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x834
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1088
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x844
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x844
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1104
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x854
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x854
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1120
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x864
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x864
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1136
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x874
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x874
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1152
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x884
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x884
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1168
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x894
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x894
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1184
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x8a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x8a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1200
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x8b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x8b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1216
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x8c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x8c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1232
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x8d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x8d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1248
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x8e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x8e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1264
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x8f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x8f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1280
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x904
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x904
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1296
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x914
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x914
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1312
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x924
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x924
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1328
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x934
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x934
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1344
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x944
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x944
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1360
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x954
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x954
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1376
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x964
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x964
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1392
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x974
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x974
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1408
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x984
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x984
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1424
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x994
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x994
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1440
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x9a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x9a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1456
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x9b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x9b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1472
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x9c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x9c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1488
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x9d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x9d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1504
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x9e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x9e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1520
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x9f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x9f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1536
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa04
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa04
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1552
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa14
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa14
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1568
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa24
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa24
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1584
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa34
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa34
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1600
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa44
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa44
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1616
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa54
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa54
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1632
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa64
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa64
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1648
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa74
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa74
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1664
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa84
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa84
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1680
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa94
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa94
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1696
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xaa4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xaa4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1712
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xab4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xab4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1728
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xac4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xac4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1744
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xad4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xad4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1760
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xae4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xae4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1776
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xaf4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xaf4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1792
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb04
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb04
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1808
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb14
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb14
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1824
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb24
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb24
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1840
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb34
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb34
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1856
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb44
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb44
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1872
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb54
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb54
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1888
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb64
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb64
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1904
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb74
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb74
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1920
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb84
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb84
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1936
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb94
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb94
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1952
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xba4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xba4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1968
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xbb4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xbb4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xbc4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xbc4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xbd4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xbd4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xbe4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xbe4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xbf4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xbf4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc04
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc04
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc14
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc14
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc24
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc24
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2096
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc34
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc34
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2112
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc44
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc44
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2128
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc54
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc54
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2144
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc64
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc64
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2160
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc74
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc74
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2176
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc84
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc84
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2192
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc94
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc94
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2208
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xca4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xca4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2224
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xcb4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xcb4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2240
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xcc4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xcc4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2256
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xcd4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xcd4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2272
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xce4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xce4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2288
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xcf4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xcf4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2304
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd04
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd04
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2320
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd14
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd14
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2336
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd24
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd24
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2352
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd34
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd34
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2368
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd44
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd44
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2384
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd54
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd54
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2400
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd64
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd64
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2416
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd74
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd74
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2432
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd84
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd84
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2448
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd94
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd94
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2464
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xda4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xda4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2480
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xdb4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xdb4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2496
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xdc4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xdc4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2512
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xdd4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xdd4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2528
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xde4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xde4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2544
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xdf4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xdf4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2560
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe04
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe04
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2576
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe14
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe14
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2592
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe24
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe24
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2608
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe34
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe34
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2624
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe44
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe44
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2640
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe54
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe54
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2656
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe64
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe64
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2672
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe74
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe74
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2688
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe84
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe84
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2704
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe94
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe94
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2720
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xea4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xea4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2736
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xeb4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xeb4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2752
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xec4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xec4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2768
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xed4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xed4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2784
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xee4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xee4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2800
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xef4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xef4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2816
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf04
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf04
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2832
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf14
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf14
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2848
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf24
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf24
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2864
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf34
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf34
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2880
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf44
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf44
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2896
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf54
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf54
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2912
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf64
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf64
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2928
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf74
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf74
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2944
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf84
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf84
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2960
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf94
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf94
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2976
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xfa4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xfa4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2992
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xfb4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xfb4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3008
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xfc4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xfc4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3024
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xfd4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xfd4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3040
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xfe4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xfe4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3056
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xff4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xff4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3072
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1004
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1004
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3088
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1014
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1014
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3104
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1024
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1024
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3120
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1034
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1034
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3136
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1044
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1044
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3152
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1054
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1054
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3168
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1064
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1064
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3184
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1074
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1074
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3200
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1084
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1084
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3216
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1094
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1094
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3232
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x10a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x10a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3248
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x10b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x10b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3264
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x10c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x10c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3280
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x10d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x10d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3296
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x10e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x10e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3312
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x10f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x10f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3328
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1104
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1104
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3344
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1114
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1114
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3360
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1124
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1124
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3376
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1134
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1134
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3392
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1144
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1144
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3408
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1154
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1154
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3424
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1164
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1164
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3440
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1174
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1174
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3456
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1184
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1184
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3472
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1194
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1194
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3488
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x11a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x11a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3504
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x11b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x11b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3520
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x11c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x11c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3536
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x11d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x11d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3552
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x11e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x11e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3568
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x11f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x11f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3584
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1204
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1204
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3600
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1214
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1214
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3616
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1224
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1224
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3632
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1234
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1234
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3648
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1244
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1244
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3664
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1254
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1254
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3680
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1264
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1264
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3696
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1274
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1274
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3712
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1284
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1284
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3728
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1294
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1294
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3744
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x12a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x12a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3760
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x12b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x12b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3776
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x12c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x12c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3792
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x12d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x12d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3808
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x12e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x12e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3824
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x12f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x12f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3840
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1304
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1304
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3856
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1314
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1314
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3872
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1324
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1324
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3888
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1334
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1334
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3904
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1344
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1344
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3920
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1354
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1354
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3936
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1364
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1364
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3952
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1374
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1374
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3968
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1384
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1384
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1394
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1394
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x13a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x13a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x13b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x13b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x13c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x13c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x13d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x13d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:4064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x13e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x13e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:4080
; GFX9-FLATSCR-NEXT: s_movk_i32 s2, 0x13e4
; GFX9-FLATSCR-NEXT: ;;#ASMSTART
@@ -7346,7 +7338,7 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[0:3], s[0:1]
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x3f4
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s10, v4
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x400, v4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x3e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
@@ -7380,7 +7372,7 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[0:1], v[7:10], off offset:3968
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s9, v4
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x380, v4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x364
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
@@ -7414,7 +7406,7 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[0:1], v[7:10], off offset:3968
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s8, v4
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x300, v4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
@@ -7448,7 +7440,7 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[0:1], v[7:10], off offset:3968
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s7, v4
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x280, v4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x264
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
@@ -7482,7 +7474,7 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[0:1], v[7:10], off offset:3968
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x200, v4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x1e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
@@ -7516,7 +7508,7 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[0:1], v[7:10], off offset:3968
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s5, v4
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x180, v4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x164
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
@@ -7550,7 +7542,7 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[0:1], v[7:10], off offset:3968
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s4, v4
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x100, v4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0xe4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll
index 613349f32e2d5ad..f8898ddf9290bcd 100644
--- a/llvm/test/CodeGen/AMDGPU/srem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem64.ll
@@ -1583,8 +1583,7 @@ define i64 @v_test_srem_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3
-; GCN-IR-NEXT: s_movk_i32 s6, 0xffc5
-; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, s6, v6
+; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 0xffffffc5, v6
; GCN-IR-NEXT: v_addc_u32_e64 v4, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[3:4]
@@ -1774,8 +1773,7 @@ define i64 @v_test_srem_pow2_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3
-; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0
-; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, s6, v6
+; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 0xffffffd0, v6
; GCN-IR-NEXT: v_addc_u32_e64 v4, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[3:4]
@@ -1914,13 +1912,12 @@ define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
-; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: .LBB13_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
-; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, s12, v10
+; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 0x7fff, v10
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, 0, v11, vcc
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll
index c5ab44e31c0320d..ea938d5a121a24c 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll
@@ -1283,13 +1283,12 @@ define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
-; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4
-; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v6
+; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 0x7fff, v6
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll
index 894c96acbbcd6b1..c1119e0a9cc3336 100644
--- a/llvm/test/CodeGen/AMDGPU/urem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/urem64.ll
@@ -1307,13 +1307,12 @@ define i64 @v_test_urem_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
-; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
-; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v8
+; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 0x7fff, v8
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
>From d5fe529e16864f4305ff30362a0923d3843570eb Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: Sat, 30 Sep 2023 01:31:11 -0700
Subject: [PATCH 2/2] [AMDGPU] Add another SIFoldOperands instance after shrink
There is no fold operands pass past the shrink and at the same
time there are limited attempts to do shrinking right inside
folding. We seem to need to run shrinking before folding, hence
this patch. I can see some clear benefits in the tests we have.
I also need this for a future patch. We could extend our efforts
to do shrinkig inside folding, but at the end it will just result
in the recreation of the the shrinking pass there.
As an alternative I have tried to move previous instance of the
folding past the shrink, but the result is not as good as here and
there were few regressions. We may have some light compile time
regressions, hence it is disabled at -O1.
---
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 +
.../CodeGen/AMDGPU/GlobalISel/add.v2i16.ll | 5 +-
.../test/CodeGen/AMDGPU/GlobalISel/saddsat.ll | 161 +-
.../CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll | 8 +-
.../CodeGen/AMDGPU/GlobalISel/srem.i32.ll | 16 +-
.../CodeGen/AMDGPU/GlobalISel/srem.i64.ll | 4 +-
.../test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll | 161 +-
.../CodeGen/AMDGPU/GlobalISel/urem.i32.ll | 14 +-
.../CodeGen/AMDGPU/GlobalISel/urem.i64.ll | 6 +-
.../CodeGen/AMDGPU/ds-combine-large-stride.ll | 46 +-
.../CodeGen/AMDGPU/integer-mad-patterns.ll | 3 +-
llvm/test/CodeGen/AMDGPU/llc-pipeline.ll | 2 +
.../AMDGPU/promote-constOffset-to-imm.ll | 106 +-
llvm/test/CodeGen/AMDGPU/sdiv64.ll | 9 +-
.../CodeGen/AMDGPU/spill-scavenge-offset.ll | 1298 ++++++++---------
llvm/test/CodeGen/AMDGPU/srem64.ll | 9 +-
llvm/test/CodeGen/AMDGPU/udiv64.ll | 3 +-
llvm/test/CodeGen/AMDGPU/urem64.ll | 3 +-
18 files changed, 885 insertions(+), 971 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index bcbc03eb2559c4f..a674c52667c684b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1199,6 +1199,8 @@ void GCNPassConfig::addMachineSSAOptimization() {
}
addPass(&DeadMachineInstructionElimID);
addPass(createSIShrinkInstructionsPass());
+ if (TM->getOptLevel() > CodeGenOptLevel::Less)
+ addPass(&SIFoldOperandsID);
}
bool GCNPassConfig::addILPOpts() {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
index 26d1fbb09210c64..e9f30e8503b310e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
@@ -165,9 +165,8 @@ define <2 x i16> @v_add_v2i16_neg_inline_imm_splat(<2 x i16> %a) {
; GFX7-LABEL: v_add_v2i16_neg_inline_imm_splat:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_movk_i32 s4, 0xffc0
-; GFX7-NEXT: v_add_i32_e32 v0, vcc, s4, v0
-; GFX7-NEXT: v_add_i32_e32 v1, vcc, s4, v1
+; GFX7-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc0, v0
+; GFX7-NEXT: v_add_i32_e32 v1, vcc, 0xffffffc0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_add_v2i16_neg_inline_imm_splat:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
index cded5c94edf8cc3..c78d4533f4ddd3f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -231,14 +231,12 @@ define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v5, 0, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s5, v5
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x80000000, v5
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v1, v5, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v4
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
@@ -246,8 +244,8 @@ define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX6-NEXT: v_min_i32_e32 v4, 0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX6-NEXT: v_max_i32_e32 v3, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s5, v4
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x80000000, v4
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x7fffffff, v3
; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
@@ -512,15 +510,15 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, 0, v0
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, s5, v10
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s4, v8
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_max_i32_e32 v1, v10, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v8
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2
; GFX6-NEXT: v_min_i32_e32 v8, 0, v1
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v1
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s5, v8
@@ -1265,19 +1263,17 @@ define <2 x i32> @v_saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX6-LABEL: v_saddsat_v2i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v5, 0, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s5, v5
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x80000000, v5
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v2, v5, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_min_i32_e32 v4, 0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_max_i32_e32 v2, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s5, v4
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s4, v2
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x80000000, v4
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_max_i32_e32 v3, v4, v3
; GFX6-NEXT: v_min_i32_e32 v2, v3, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
@@ -1286,19 +1282,17 @@ define <2 x i32> @v_saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX8-LABEL: v_saddsat_v2i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s5, 1
; GFX8-NEXT: v_min_i32_e32 v5, 0, v0
-; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v4, 0, v0
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, s5, v5
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x80000000, v5
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_max_i32_e32 v2, v5, v2
; GFX8-NEXT: v_min_i32_e32 v2, v2, v4
; GFX8-NEXT: v_min_i32_e32 v4, 0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_max_i32_e32 v2, 0, v1
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, s5, v4
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s4, v2
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0x80000000, v4
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 0x7fffffff, v2
; GFX8-NEXT: v_max_i32_e32 v3, v4, v3
; GFX8-NEXT: v_min_i32_e32 v2, v3, v2
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v2
@@ -1383,26 +1377,25 @@ define <3 x i32> @v_saddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX6-LABEL: v_saddsat_v3i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v7, 0, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v6, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v7, vcc, s5, v7
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s4, v6
+; GFX6-NEXT: v_sub_i32_e32 v7, vcc, 0x80000000, v7
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x7fffffff, v6
; GFX6-NEXT: v_max_i32_e32 v3, v7, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v6
; GFX6-NEXT: v_min_i32_e32 v6, 0, v1
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GFX6-NEXT: v_max_i32_e32 v3, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s5, v6
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3
; GFX6-NEXT: v_max_i32_e32 v4, v6, v4
; GFX6-NEXT: v_min_i32_e32 v3, v4, v3
; GFX6-NEXT: v_min_i32_e32 v4, 0, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_max_i32_e32 v3, 0, v2
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s5, v4
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x80000000, v4
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x7fffffff, v3
; GFX6-NEXT: v_max_i32_e32 v4, v4, v5
; GFX6-NEXT: v_min_i32_e32 v3, v4, v3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
@@ -1411,26 +1404,25 @@ define <3 x i32> @v_saddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX8-LABEL: v_saddsat_v3i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s5, 1
; GFX8-NEXT: v_min_i32_e32 v7, 0, v0
-; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v6, 0, v0
-; GFX8-NEXT: v_sub_u32_e32 v7, vcc, s5, v7
-; GFX8-NEXT: v_sub_u32_e32 v6, vcc, s4, v6
+; GFX8-NEXT: v_sub_u32_e32 v7, vcc, 0x80000000, v7
+; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x7fffffff, v6
; GFX8-NEXT: v_max_i32_e32 v3, v7, v3
; GFX8-NEXT: v_min_i32_e32 v3, v3, v6
; GFX8-NEXT: v_min_i32_e32 v6, 0, v1
+; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_max_i32_e32 v3, 0, v1
-; GFX8-NEXT: v_sub_u32_e32 v6, vcc, s5, v6
+; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x80000000, v6
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s4, v3
; GFX8-NEXT: v_max_i32_e32 v4, v6, v4
; GFX8-NEXT: v_min_i32_e32 v3, v4, v3
; GFX8-NEXT: v_min_i32_e32 v4, 0, v2
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_max_i32_e32 v3, 0, v2
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, s5, v4
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s4, v3
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0x80000000, v4
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 0x7fffffff, v3
; GFX8-NEXT: v_max_i32_e32 v4, v4, v5
; GFX8-NEXT: v_min_i32_e32 v3, v4, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
@@ -1536,26 +1528,24 @@ define <4 x i32> @v_saddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX6-LABEL: v_saddsat_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v9, 0, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v9, vcc, s5, v9
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s4, v8
+; GFX6-NEXT: v_sub_i32_e32 v9, vcc, 0x80000000, v9
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_max_i32_e32 v4, v9, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v8
; GFX6-NEXT: v_min_i32_e32 v8, 0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_max_i32_e32 v4, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s5, v8
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x80000000, v8
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v5, v8, v5
; GFX6-NEXT: v_min_i32_e32 v4, v5, v4
; GFX6-NEXT: v_min_i32_e32 v5, 0, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_max_i32_e32 v4, 0, v2
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s5, v5
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x80000000, v5
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v5, v5, v6
; GFX6-NEXT: v_min_i32_e32 v4, v5, v4
; GFX6-NEXT: v_min_i32_e32 v5, 0, v3
@@ -1571,26 +1561,24 @@ define <4 x i32> @v_saddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX8-LABEL: v_saddsat_v4i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s5, 1
; GFX8-NEXT: v_min_i32_e32 v9, 0, v0
-; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v8, 0, v0
-; GFX8-NEXT: v_sub_u32_e32 v9, vcc, s5, v9
-; GFX8-NEXT: v_sub_u32_e32 v8, vcc, s4, v8
+; GFX8-NEXT: v_sub_u32_e32 v9, vcc, 0x80000000, v9
+; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 0x7fffffff, v8
; GFX8-NEXT: v_max_i32_e32 v4, v9, v4
; GFX8-NEXT: v_min_i32_e32 v4, v4, v8
; GFX8-NEXT: v_min_i32_e32 v8, 0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v4
; GFX8-NEXT: v_max_i32_e32 v4, 0, v1
-; GFX8-NEXT: v_sub_u32_e32 v8, vcc, s5, v8
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 0x80000000, v8
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_max_i32_e32 v5, v8, v5
; GFX8-NEXT: v_min_i32_e32 v4, v5, v4
; GFX8-NEXT: v_min_i32_e32 v5, 0, v2
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v4
; GFX8-NEXT: v_max_i32_e32 v4, 0, v2
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, s5, v5
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x80000000, v5
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_max_i32_e32 v5, v5, v6
; GFX8-NEXT: v_min_i32_e32 v4, v5, v4
; GFX8-NEXT: v_min_i32_e32 v5, 0, v3
@@ -1724,34 +1712,32 @@ define <5 x i32> @v_saddsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX6-LABEL: v_saddsat_v5i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_min_i32_e32 v12, 0, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
+; GFX6-NEXT: v_min_i32_e32 v11, 0, v0
; GFX6-NEXT: v_max_i32_e32 v10, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v12, vcc, s5, v12
-; GFX6-NEXT: v_sub_i32_e32 v10, vcc, s4, v10
-; GFX6-NEXT: v_max_i32_e32 v5, v12, v5
+; GFX6-NEXT: v_sub_i32_e32 v11, vcc, 0x80000000, v11
+; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 0x7fffffff, v10
+; GFX6-NEXT: v_max_i32_e32 v5, v11, v5
; GFX6-NEXT: v_min_i32_e32 v5, v5, v10
; GFX6-NEXT: v_min_i32_e32 v10, 0, v1
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v10, vcc, s5, v10
+; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 0x80000000, v10
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s4, v5
; GFX6-NEXT: v_max_i32_e32 v6, v10, v6
; GFX6-NEXT: v_min_i32_e32 v5, v6, v5
; GFX6-NEXT: v_min_i32_e32 v6, 0, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v2
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s5, v6
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s4, v5
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x7fffffff, v5
; GFX6-NEXT: v_max_i32_e32 v6, v6, v7
; GFX6-NEXT: v_min_i32_e32 v5, v6, v5
; GFX6-NEXT: v_min_i32_e32 v6, 0, v3
-; GFX6-NEXT: v_bfrev_b32_e32 v11, -2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v3
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v11, v5
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x7fffffff, v5
; GFX6-NEXT: v_max_i32_e32 v6, v6, v8
; GFX6-NEXT: v_min_i32_e32 v5, v6, v5
; GFX6-NEXT: v_min_i32_e32 v6, 0, v4
@@ -1767,34 +1753,32 @@ define <5 x i32> @v_saddsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX8-LABEL: v_saddsat_v5i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s5, 1
-; GFX8-NEXT: v_min_i32_e32 v12, 0, v0
-; GFX8-NEXT: s_brev_b32 s4, -2
+; GFX8-NEXT: v_min_i32_e32 v11, 0, v0
; GFX8-NEXT: v_max_i32_e32 v10, 0, v0
-; GFX8-NEXT: v_sub_u32_e32 v12, vcc, s5, v12
-; GFX8-NEXT: v_sub_u32_e32 v10, vcc, s4, v10
-; GFX8-NEXT: v_max_i32_e32 v5, v12, v5
+; GFX8-NEXT: v_sub_u32_e32 v11, vcc, 0x80000000, v11
+; GFX8-NEXT: v_sub_u32_e32 v10, vcc, 0x7fffffff, v10
+; GFX8-NEXT: v_max_i32_e32 v5, v11, v5
; GFX8-NEXT: v_min_i32_e32 v5, v5, v10
; GFX8-NEXT: v_min_i32_e32 v10, 0, v1
+; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v5
; GFX8-NEXT: v_max_i32_e32 v5, 0, v1
-; GFX8-NEXT: v_sub_u32_e32 v10, vcc, s5, v10
+; GFX8-NEXT: v_sub_u32_e32 v10, vcc, 0x80000000, v10
; GFX8-NEXT: v_sub_u32_e32 v5, vcc, s4, v5
; GFX8-NEXT: v_max_i32_e32 v6, v10, v6
; GFX8-NEXT: v_min_i32_e32 v5, v6, v5
; GFX8-NEXT: v_min_i32_e32 v6, 0, v2
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v5
; GFX8-NEXT: v_max_i32_e32 v5, 0, v2
-; GFX8-NEXT: v_sub_u32_e32 v6, vcc, s5, v6
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x80000000, v6
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x7fffffff, v5
; GFX8-NEXT: v_max_i32_e32 v6, v6, v7
; GFX8-NEXT: v_min_i32_e32 v5, v6, v5
; GFX8-NEXT: v_min_i32_e32 v6, 0, v3
-; GFX8-NEXT: v_bfrev_b32_e32 v11, -2
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_max_i32_e32 v5, 0, v3
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x80000000, v6
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v11, v5
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x7fffffff, v5
; GFX8-NEXT: v_max_i32_e32 v6, v6, v8
; GFX8-NEXT: v_min_i32_e32 v5, v6, v5
; GFX8-NEXT: v_min_i32_e32 v6, 0, v4
@@ -2766,13 +2750,11 @@ define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v5, 0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s5, v5
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x80000000, v5
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v2, v5, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
@@ -2780,8 +2762,8 @@ define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX6-NEXT: v_max_i32_e32 v3, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s5, v4
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x80000000, v4
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x7fffffff, v3
; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
@@ -2978,13 +2960,11 @@ define amdgpu_ps float @saddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: saddsat_v2i16_vs:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: s_brev_b32 s3, 1
; GFX6-NEXT: v_min_i32_e32 v3, 0, v0
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
-; GFX6-NEXT: s_brev_b32 s2, -2
; GFX6-NEXT: v_max_i32_e32 v2, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s3, v3
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x80000000, v3
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_max_i32_e32 v3, s0, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_min_i32_e32 v2, v3, v2
@@ -2992,8 +2972,8 @@ define amdgpu_ps float @saddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: s_lshl_b32 s0, s1, 16
; GFX6-NEXT: v_max_i32_e32 v2, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s3, v3
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x80000000, v3
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_max_i32_e32 v3, s0, v3
; GFX6-NEXT: v_min_i32_e32 v2, v3, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
@@ -3059,14 +3039,14 @@ define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v10, 0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, 0, v0
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, s5, v10
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s4, v8
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_max_i32_e32 v4, v10, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_min_i32_e32 v4, v4, v8
; GFX6-NEXT: v_min_i32_e32 v8, 0, v1
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v1
@@ -4847,8 +4827,7 @@ define <2 x i64> @v_saddsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[6:7], 0, v[4:5]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v9
-; GFX6-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, v0, v1
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0x80000000, v0
; GFX6-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
@@ -4871,8 +4850,7 @@ define <2 x i64> @v_saddsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[6:7], 0, v[4:5]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v9
-; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v0, v1
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0x80000000, v0
; GFX8-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
@@ -4895,8 +4873,7 @@ define <2 x i64> @v_saddsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[6:7], 0, v[4:5]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v9
-; GFX9-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v0, v1
+; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, 0x80000000, v0
; GFX9-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
index ab000d91a3ef23d..7f7788de6a7e1fe 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
@@ -295,7 +295,7 @@ define i32 @v_sdiv_i32_pow2k_denom(i32 %num) {
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0
; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[4:5]
-; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, s6, v0
+; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, 0x1000, v0
; CHECK-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[4:5]
; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v2
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
@@ -345,7 +345,7 @@ define <2 x i32> @v_sdiv_v2i32_pow2k_denom(<2 x i32> %num) {
; GISEL-NEXT: v_subrev_i32_e32 v7, vcc, s8, v0
; GISEL-NEXT: v_cmp_le_u32_e64 s[6:7], s8, v1
; GISEL-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[6:7]
-; GISEL-NEXT: v_subrev_i32_e32 v8, vcc, s8, v1
+; GISEL-NEXT: v_subrev_i32_e32 v8, vcc, 0x1000, v1
; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v7, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v5
; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[6:7]
@@ -437,7 +437,7 @@ define i32 @v_sdiv_i32_oddk_denom(i32 %num) {
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0
; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[4:5]
-; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, s6, v0
+; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, 0x12d8fb, v0
; CHECK-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[4:5]
; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v2
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
@@ -486,7 +486,7 @@ define <2 x i32> @v_sdiv_v2i32_oddk_denom(<2 x i32> %num) {
; GISEL-NEXT: v_subrev_i32_e32 v6, vcc, s8, v0
; GISEL-NEXT: v_cmp_le_u32_e64 s[6:7], s8, v1
; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, v9, s[6:7]
-; GISEL-NEXT: v_subrev_i32_e32 v7, vcc, s8, v1
+; GISEL-NEXT: v_subrev_i32_e32 v7, vcc, 0x12d8fb, v1
; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v4
; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[6:7]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
index 88ace1c51f5b023..6aff6200acff9f8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
@@ -268,10 +268,10 @@ define i32 @v_srem_i32_pow2k_denom(i32 %num) {
; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2
; CHECK-NEXT: v_lshlrev_b32_e32 v2, 12, v2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
-; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
+; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, 0x1000, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
+; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, 0x1000, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1
@@ -312,13 +312,13 @@ define <2 x i32> @v_srem_v2i32_pow2k_denom(<2 x i32> %num) {
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
-; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, s4, v1
+; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, 0x1000, v1
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
-; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, s4, v1
+; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, 0x1000, v1
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
@@ -399,10 +399,10 @@ define i32 @v_srem_i32_oddk_denom(i32 %num) {
; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2
; CHECK-NEXT: v_mul_lo_u32 v2, v2, s4
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
-; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
+; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, 0x12d8fb, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
+; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, 0x12d8fb, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1
@@ -443,13 +443,13 @@ define <2 x i32> @v_srem_v2i32_oddk_denom(<2 x i32> %num) {
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
-; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, s4, v1
+; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, 0x12d8fb, v1
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
-; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, s4, v1
+; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, 0x12d8fb, v1
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
index d0c55c69f508775..a89f01d62afa71f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
@@ -1078,7 +1078,7 @@ define i64 @v_srem_i64_pow2k_denom(i64 %num) {
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
-; CHECK-NEXT: v_sub_i32_e32 v4, vcc, v0, v6
+; CHECK-NEXT: v_subrev_i32_e32 v4, vcc, 0x1000, v0
; CHECK-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v4, v6
@@ -1699,7 +1699,7 @@ define i64 @v_srem_i64_oddk_denom(i64 %num) {
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
-; CHECK-NEXT: v_sub_i32_e32 v4, vcc, v0, v6
+; CHECK-NEXT: v_subrev_i32_e32 v4, vcc, 0x12d8fb, v0
; CHECK-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v4, v6
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index 65455d754be4f53..345982c1c693317 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -231,23 +231,21 @@ define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, -1, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_min_i32_e32 v5, -1, v0
-; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, 0x80000000, v5
; GFX6-NEXT: v_max_i32_e32 v1, v4, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v5
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX6-NEXT: v_max_i32_e32 v3, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x7fffffff, v3
; GFX6-NEXT: v_min_i32_e32 v4, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x80000000, v4
; GFX6-NEXT: v_max_i32_e32 v2, v3, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
@@ -506,20 +504,20 @@ define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, -1, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s4, v8
+; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_min_i32_e32 v10, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s5, v10
; GFX6-NEXT: v_max_i32_e32 v1, v8, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v10
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s4, v5
@@ -1265,19 +1263,17 @@ define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX6-LABEL: v_ssubsat_v2i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, -1, v0
-; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_min_i32_e32 v5, -1, v0
-; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, 0x80000000, v5
; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v5
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_max_i32_e32 v2, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s4, v2
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_min_i32_e32 v4, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x80000000, v4
; GFX6-NEXT: v_max_i32_e32 v2, v2, v3
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
@@ -1286,19 +1282,17 @@ define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX8-LABEL: v_ssubsat_v2i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v4, -1, v0
-; GFX8-NEXT: s_brev_b32 s5, 1
-; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_min_i32_e32 v5, -1, v0
-; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s5, v5
+; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, 0x80000000, v5
; GFX8-NEXT: v_max_i32_e32 v2, v4, v2
; GFX8-NEXT: v_min_i32_e32 v2, v2, v5
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_max_i32_e32 v2, -1, v1
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s4, v2
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 0x7fffffff, v2
; GFX8-NEXT: v_min_i32_e32 v4, -1, v1
-; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s5, v4
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 0x80000000, v4
; GFX8-NEXT: v_max_i32_e32 v2, v2, v3
; GFX8-NEXT: v_min_i32_e32 v2, v2, v4
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v2
@@ -1383,26 +1377,25 @@ define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX6-LABEL: v_ssubsat_v3i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v6, -1, v0
-; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s4, v6
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 0x7fffffff, v6
; GFX6-NEXT: v_min_i32_e32 v7, -1, v0
-; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, s5, v7
+; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 0x80000000, v7
; GFX6-NEXT: v_max_i32_e32 v3, v6, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v7
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; GFX6-NEXT: v_max_i32_e32 v3, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
; GFX6-NEXT: v_min_i32_e32 v6, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s5, v6
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v3, v3, v4
; GFX6-NEXT: v_min_i32_e32 v3, v3, v6
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_max_i32_e32 v3, -1, v2
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x7fffffff, v3
; GFX6-NEXT: v_min_i32_e32 v4, -1, v2
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x80000000, v4
; GFX6-NEXT: v_max_i32_e32 v3, v3, v5
; GFX6-NEXT: v_min_i32_e32 v3, v3, v4
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
@@ -1411,26 +1404,25 @@ define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX8-LABEL: v_ssubsat_v3i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v6, -1, v0
-; GFX8-NEXT: s_brev_b32 s5, 1
-; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s4, v6
+; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 0x7fffffff, v6
; GFX8-NEXT: v_min_i32_e32 v7, -1, v0
-; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, s5, v7
+; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 0x80000000, v7
; GFX8-NEXT: v_max_i32_e32 v3, v6, v3
; GFX8-NEXT: v_min_i32_e32 v3, v3, v7
+; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_max_i32_e32 v3, -1, v1
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s4, v3
; GFX8-NEXT: v_min_i32_e32 v6, -1, v1
-; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s5, v6
+; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 0x80000000, v6
; GFX8-NEXT: v_max_i32_e32 v3, v3, v4
; GFX8-NEXT: v_min_i32_e32 v3, v3, v6
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_max_i32_e32 v3, -1, v2
-; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s4, v3
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 0x7fffffff, v3
; GFX8-NEXT: v_min_i32_e32 v4, -1, v2
-; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s5, v4
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 0x80000000, v4
; GFX8-NEXT: v_max_i32_e32 v3, v3, v5
; GFX8-NEXT: v_min_i32_e32 v3, v3, v4
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v3
@@ -1536,26 +1528,24 @@ define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX6-LABEL: v_ssubsat_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, -1, v0
-; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s4, v8
+; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_min_i32_e32 v9, -1, v0
-; GFX6-NEXT: v_subrev_i32_e32 v9, vcc, s5, v9
+; GFX6-NEXT: v_subrev_i32_e32 v9, vcc, 0x80000000, v9
; GFX6-NEXT: v_max_i32_e32 v4, v8, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v9
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_max_i32_e32 v4, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_min_i32_e32 v8, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s5, v8
+; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, 0x80000000, v8
; GFX6-NEXT: v_max_i32_e32 v4, v4, v5
; GFX6-NEXT: v_min_i32_e32 v4, v4, v8
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_max_i32_e32 v4, -1, v2
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_min_i32_e32 v5, -1, v2
-; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, 0x80000000, v5
; GFX6-NEXT: v_max_i32_e32 v4, v4, v6
; GFX6-NEXT: v_min_i32_e32 v4, v4, v5
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v4
@@ -1571,26 +1561,24 @@ define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX8-LABEL: v_ssubsat_v4i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v8, -1, v0
-; GFX8-NEXT: s_brev_b32 s5, 1
-; GFX8-NEXT: v_subrev_u32_e32 v8, vcc, s4, v8
+; GFX8-NEXT: v_subrev_u32_e32 v8, vcc, 0x7fffffff, v8
; GFX8-NEXT: v_min_i32_e32 v9, -1, v0
-; GFX8-NEXT: v_subrev_u32_e32 v9, vcc, s5, v9
+; GFX8-NEXT: v_subrev_u32_e32 v9, vcc, 0x80000000, v9
; GFX8-NEXT: v_max_i32_e32 v4, v8, v4
; GFX8-NEXT: v_min_i32_e32 v4, v4, v9
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v4
; GFX8-NEXT: v_max_i32_e32 v4, -1, v1
-; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_min_i32_e32 v8, -1, v1
-; GFX8-NEXT: v_subrev_u32_e32 v8, vcc, s5, v8
+; GFX8-NEXT: v_subrev_u32_e32 v8, vcc, 0x80000000, v8
; GFX8-NEXT: v_max_i32_e32 v4, v4, v5
; GFX8-NEXT: v_min_i32_e32 v4, v4, v8
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v4
; GFX8-NEXT: v_max_i32_e32 v4, -1, v2
-; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_min_i32_e32 v5, -1, v2
-; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s5, v5
+; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, 0x80000000, v5
; GFX8-NEXT: v_max_i32_e32 v4, v4, v6
; GFX8-NEXT: v_min_i32_e32 v4, v4, v5
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v4
@@ -1724,32 +1712,30 @@ define <5 x i32> @v_ssubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX6-LABEL: v_ssubsat_v5i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v10, -1, v0
-; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s4, v10
-; GFX6-NEXT: v_min_i32_e32 v12, -1, v0
-; GFX6-NEXT: v_subrev_i32_e32 v12, vcc, s5, v12
+; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, 0x7fffffff, v10
+; GFX6-NEXT: v_min_i32_e32 v11, -1, v0
+; GFX6-NEXT: v_subrev_i32_e32 v11, vcc, 0x80000000, v11
; GFX6-NEXT: v_max_i32_e32 v5, v10, v5
-; GFX6-NEXT: v_min_i32_e32 v5, v5, v12
+; GFX6-NEXT: v_min_i32_e32 v5, v5, v11
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s4, v5
; GFX6-NEXT: v_min_i32_e32 v10, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s5, v10
+; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, 0x80000000, v10
; GFX6-NEXT: v_max_i32_e32 v5, v5, v6
; GFX6-NEXT: v_min_i32_e32 v5, v5, v10
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v2
-; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s4, v5
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, 0x7fffffff, v5
; GFX6-NEXT: v_min_i32_e32 v6, -1, v2
-; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s5, v6
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v5, v5, v7
; GFX6-NEXT: v_min_i32_e32 v5, v5, v6
-; GFX6-NEXT: v_bfrev_b32_e32 v11, -2
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v3
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v11
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, 0x7fffffff, v5
; GFX6-NEXT: v_min_i32_e32 v6, -1, v3
; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v5, v5, v8
@@ -1767,32 +1753,30 @@ define <5 x i32> @v_ssubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX8-LABEL: v_ssubsat_v5i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v10, -1, v0
-; GFX8-NEXT: s_brev_b32 s5, 1
-; GFX8-NEXT: v_subrev_u32_e32 v10, vcc, s4, v10
-; GFX8-NEXT: v_min_i32_e32 v12, -1, v0
-; GFX8-NEXT: v_subrev_u32_e32 v12, vcc, s5, v12
+; GFX8-NEXT: v_subrev_u32_e32 v10, vcc, 0x7fffffff, v10
+; GFX8-NEXT: v_min_i32_e32 v11, -1, v0
+; GFX8-NEXT: v_subrev_u32_e32 v11, vcc, 0x80000000, v11
; GFX8-NEXT: v_max_i32_e32 v5, v10, v5
-; GFX8-NEXT: v_min_i32_e32 v5, v5, v12
+; GFX8-NEXT: v_min_i32_e32 v5, v5, v11
+; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v5
; GFX8-NEXT: v_max_i32_e32 v5, -1, v1
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s4, v5
; GFX8-NEXT: v_min_i32_e32 v10, -1, v1
-; GFX8-NEXT: v_subrev_u32_e32 v10, vcc, s5, v10
+; GFX8-NEXT: v_subrev_u32_e32 v10, vcc, 0x80000000, v10
; GFX8-NEXT: v_max_i32_e32 v5, v5, v6
; GFX8-NEXT: v_min_i32_e32 v5, v5, v10
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v5
; GFX8-NEXT: v_max_i32_e32 v5, -1, v2
-; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, 0x7fffffff, v5
; GFX8-NEXT: v_min_i32_e32 v6, -1, v2
-; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s5, v6
+; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 0x80000000, v6
; GFX8-NEXT: v_max_i32_e32 v5, v5, v7
; GFX8-NEXT: v_min_i32_e32 v5, v5, v6
-; GFX8-NEXT: v_bfrev_b32_e32 v11, -2
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_max_i32_e32 v5, -1, v3
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v5, v11
+; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, 0x7fffffff, v5
; GFX8-NEXT: v_min_i32_e32 v6, -1, v3
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 0x80000000, v6
; GFX8-NEXT: v_max_i32_e32 v5, v5, v8
@@ -2766,22 +2750,20 @@ define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_min_i32_e32 v5, -1, v0
-; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, 0x80000000, v5
; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX6-NEXT: v_max_i32_e32 v3, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x7fffffff, v3
; GFX6-NEXT: v_min_i32_e32 v4, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x80000000, v4
; GFX6-NEXT: v_max_i32_e32 v2, v3, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
@@ -2978,22 +2960,20 @@ define amdgpu_ps float @ssubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: ssubsat_v2i16_vs:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: s_brev_b32 s2, -2
; GFX6-NEXT: v_max_i32_e32 v2, -1, v0
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
-; GFX6-NEXT: s_brev_b32 s3, 1
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_min_i32_e32 v3, -1, v0
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s3, v3
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_max_i32_e32 v2, s0, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_max_i32_e32 v2, -1, v1
; GFX6-NEXT: s_lshl_b32 s0, s1, 16
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_min_i32_e32 v3, -1, v1
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s3, v3
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_max_i32_e32 v2, s0, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
@@ -3056,16 +3036,16 @@ define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: s_brev_b32 s5, 1
-; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s4, v8
+; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_min_i32_e32 v10, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s5, v10
; GFX6-NEXT: v_max_i32_e32 v4, v8, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v10
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v1
@@ -4847,8 +4827,7 @@ define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]
; GFX6-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[4:5]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v9
-; GFX6-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, v0, v1
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0x80000000, v0
; GFX6-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
@@ -4871,8 +4850,7 @@ define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]
; GFX8-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[4:5]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v9
-; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v0, v1
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0x80000000, v0
; GFX8-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
@@ -4895,8 +4873,7 @@ define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[4:5]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v9
-; GFX9-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v0, v1
+; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, 0x80000000, v0
; GFX9-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
index 48f05a33f03649c..3af5ac98658ddac 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
@@ -222,10 +222,10 @@ define i32 @v_urem_i32_oddk_denom(i32 %num) {
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_mul_lo_u32 v1, v1, s4
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
-; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
+; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, 0x12d8fb, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
+; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, 0x12d8fb, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31]
@@ -253,13 +253,13 @@ define <2 x i32> @v_urem_v2i32_oddk_denom(<2 x i32> %num) {
; GISEL-NEXT: v_mul_lo_u32 v3, v3, v2
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
-; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
+; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, 0x12d8fb, v0
; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, 0x12d8fb, v1
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
+; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, 0x12d8fb, v0
; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, 0x12d8fb, v1
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
@@ -284,13 +284,13 @@ define <2 x i32> @v_urem_v2i32_oddk_denom(<2 x i32> %num) {
; CGP-NEXT: v_mul_lo_u32 v2, v2, s4
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
-; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
-; CGP-NEXT: v_subrev_i32_e32 v3, vcc, s4, v1
+; CGP-NEXT: v_subrev_i32_e32 v2, vcc, 0x12d8fb, v0
+; CGP-NEXT: v_subrev_i32_e32 v3, vcc, 0x12d8fb, v1
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
+; CGP-NEXT: v_subrev_i32_e32 v2, vcc, 0x12d8fb, v0
; CGP-NEXT: v_subrev_i32_e32 v3, vcc, 0x12d8fb, v1
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
index 097f6642cbc669b..f5b27906ed67ed8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
@@ -1068,7 +1068,7 @@ define i64 @v_urem_i64_oddk_denom(i64 %num) {
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
-; CHECK-NEXT: v_sub_i32_e32 v5, vcc, v0, v2
+; CHECK-NEXT: v_subrev_i32_e32 v5, vcc, 0x12d8fb, v0
; CHECK-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v4
; CHECK-NEXT: v_cndmask_b32_e64 v3, -1, v3, s[6:7]
; CHECK-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
@@ -1295,7 +1295,7 @@ define <2 x i64> @v_urem_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v3, v5
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4
; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
-; GISEL-NEXT: v_sub_i32_e32 v9, vcc, v2, v4
+; GISEL-NEXT: v_subrev_i32_e32 v9, vcc, 0x12d8fb, v2
; GISEL-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v7
; GISEL-NEXT: v_cndmask_b32_e64 v6, -1, v6, s[8:9]
; GISEL-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
@@ -1530,7 +1530,7 @@ define <2 x i64> @v_urem_v2i64_oddk_denom(<2 x i64> %num) {
; CGP-NEXT: v_sub_i32_e32 v3, vcc, v3, v6
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4
; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
-; CGP-NEXT: v_sub_i32_e32 v9, vcc, v2, v4
+; CGP-NEXT: v_subrev_i32_e32 v9, vcc, 0x12d8fb, v2
; CGP-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v7
; CGP-NEXT: v_cndmask_b32_e64 v5, -1, v5, s[8:9]
; CGP-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll b/llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
index aa1d44c31606b8f..726203c4156708b 100644
--- a/llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
@@ -5,9 +5,9 @@
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x200, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x400, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x800, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x200, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]
@@ -50,8 +50,8 @@ bb:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x400, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x800, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x400, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x800, [[BASE]]
@@ -94,9 +94,9 @@ bb:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x800, [[BASE]]
; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x200, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]
@@ -173,9 +173,9 @@ bb:
; GCN-LABEL: ds_read32_combine_stride_8192_shifted:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
-; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
+; GFX9: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
+; VI-DAG: v_add_u32_e64 [[B1:v[0-9]+]], vcc, [[ARG]], 8
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 8, [[BASE]]
; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:32
@@ -209,7 +209,7 @@ bb:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x800, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]
; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:50
@@ -247,9 +247,9 @@ bb:
; GCN-LABEL: ds_read64_combine_stride_8192_shifted:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
-; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
+; GFX9: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
+; VI-DAG: v_add_u32_e64 [[B1:v[0-9]+]], vcc, [[ARG]], 8
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 8, [[BASE]]
; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:16
@@ -283,9 +283,9 @@ bb:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x200, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x400, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x800, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x200, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]
@@ -319,9 +319,9 @@ bb:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
-; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x800, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x400, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x200, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]
@@ -380,9 +380,9 @@ bb:
; GCN-LABEL: ds_write32_combine_stride_8192_shifted:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
-; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
+; GFX9: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[BASE:v[0-9]+]], vcc, 4, [[BASE]]
+; VI-DAG: v_add_u32_e64 [[BASE:v[0-9]+]], vcc, [[ARG]], 4
; GFX9-DAG: v_add_u32_e32 [[BASE:v[0-9]+]], 4, [[BASE]]
; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
@@ -409,7 +409,7 @@ bb:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
+; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x800, [[BASE]]
; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]
; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:50
@@ -438,9 +438,9 @@ bb:
; GCN-LABEL: ds_write64_combine_stride_8192_shifted:
; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
-; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
+; GFX9: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
-; VI-DAG: v_add_u32_e32 [[BASE]], vcc, 8, [[BASE]]
+; VI-DAG: v_add_u32_e64 [[BASE:v[0-9]+]], vcc, [[ARG]], 8
; GFX9-DAG: v_add_u32_e32 [[BASE]], 8, [[BASE]]
; GCN-DAG: ds_write2st64_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16
diff --git a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
index 61017e809c86365..70a7f67f5b8d0d6 100644
--- a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+++ b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
@@ -3273,9 +3273,8 @@ define <2 x i8> @clpeak_imad_pat_v2i8(<2 x i8> %x, <2 x i8> %y) {
; GFX67-SDAG-NEXT: v_lshlrev_b32_e32 v4, 8, v6
; GFX67-SDAG-NEXT: v_mul_u32_u24_e32 v5, v0, v2
; GFX67-SDAG-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX67-SDAG-NEXT: s_movk_i32 s4, 0x100
; GFX67-SDAG-NEXT: v_mad_u32_u24 v0, v0, v2, 1
-; GFX67-SDAG-NEXT: v_add_i32_e32 v3, vcc, s4, v3
+; GFX67-SDAG-NEXT: v_add_i32_e32 v3, vcc, 0x100, v3
; GFX67-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX67-SDAG-NEXT: v_lshlrev_b32_e32 v2, 8, v1
; GFX67-SDAG-NEXT: v_or_b32_e32 v0, v2, v0
diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
index b939c8d2e339de4..25047121f31ff61 100644
--- a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
@@ -920,6 +920,7 @@
; GCN-O2-NEXT: SI Fold Operands
; GCN-O2-NEXT: Remove dead machine instructions
; GCN-O2-NEXT: SI Shrink Instructions
+; GCN-O2-NEXT: SI Fold Operands
; GCN-O2-NEXT: Register Usage Information Propagation
; GCN-O2-NEXT: Detect Dead Lanes
; GCN-O2-NEXT: Remove dead machine instructions
@@ -1238,6 +1239,7 @@
; GCN-O3-NEXT: SI Fold Operands
; GCN-O3-NEXT: Remove dead machine instructions
; GCN-O3-NEXT: SI Shrink Instructions
+; GCN-O3-NEXT: SI Fold Operands
; GCN-O3-NEXT: Register Usage Information Propagation
; GCN-O3-NEXT: Detect Dead Lanes
; GCN-O3-NEXT: Remove dead machine instructions
diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
index a462c19ce645d4a..c2b10c160bf586a 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
@@ -54,13 +54,11 @@ define amdgpu_kernel void @clmem_read_simplified(ptr addrspace(1) %buffer) {
; GFX8-NEXT: s_movk_i32 s0, 0x2000
; GFX8-NEXT: v_add_u32_e32 v13, vcc, s0, v0
; GFX8-NEXT: v_addc_u32_e32 v14, vcc, 0, v1, vcc
-; GFX8-NEXT: s_movk_i32 s0, 0x2800
-; GFX8-NEXT: v_add_u32_e32 v15, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v15, vcc, 0x2800, v0
; GFX8-NEXT: v_addc_u32_e32 v16, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx2 v[13:14], v[13:14]
; GFX8-NEXT: flat_load_dwordx2 v[15:16], v[15:16]
-; GFX8-NEXT: s_movk_i32 s0, 0x3000
-; GFX8-NEXT: v_add_u32_e32 v17, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v17, vcc, 0x3000, v0
; GFX8-NEXT: v_addc_u32_e32 v18, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx2 v[17:18], v[17:18]
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x3800, v0
@@ -132,8 +130,7 @@ define amdgpu_kernel void @clmem_read_simplified(ptr addrspace(1) %buffer) {
; GFX900-NEXT: global_load_dwordx2 v[12:13], v[10:11], off offset:2048
; GFX900-NEXT: global_load_dwordx2 v[14:15], v[6:7], off
; GFX900-NEXT: global_load_dwordx2 v[16:17], v[6:7], off offset:2048
-; GFX900-NEXT: s_movk_i32 s0, 0x3000
-; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
+; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, 0x3000, v0
; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX900-NEXT: global_load_dwordx2 v[6:7], v[0:1], off
; GFX900-NEXT: global_load_dwordx2 v[10:11], v[0:1], off offset:2048
@@ -276,8 +273,7 @@ define amdgpu_kernel void @clmem_read_simplified(ptr addrspace(1) %buffer) {
; GFX90A-NEXT: global_load_dwordx2 v[12:13], v[10:11], off offset:2048
; GFX90A-NEXT: global_load_dwordx2 v[14:15], v[6:7], off
; GFX90A-NEXT: global_load_dwordx2 v[16:17], v[6:7], off offset:2048
-; GFX90A-NEXT: s_movk_i32 s0, 0x3000
-; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, 0x3000, v0
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX90A-NEXT: global_load_dwordx2 v[6:7], v[0:1], off
; GFX90A-NEXT: global_load_dwordx2 v[10:11], v[0:1], off offset:2048
@@ -573,21 +569,17 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX900-NEXT: v_mov_b32_e32 v3, s35
; GFX900-NEXT: v_add_co_u32_e32 v1, vcc, s34, v1
; GFX900-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v3, vcc
-; GFX900-NEXT: s_movk_i32 s0, 0x5000
-; GFX900-NEXT: v_add_co_u32_e32 v1, vcc, s0, v1
+; GFX900-NEXT: v_add_co_u32_e32 v1, vcc, 0x5000, v1
; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
-; GFX900-NEXT: s_movk_i32 s2, 0x7f
; GFX900-NEXT: v_mov_b32_e32 v4, 0
-; GFX900-NEXT: s_movk_i32 s0, 0xd000
-; GFX900-NEXT: s_movk_i32 s1, 0xe000
-; GFX900-NEXT: s_movk_i32 s3, 0xf000
+; GFX900-NEXT: s_movk_i32 s0, 0x7f
; GFX900-NEXT: .LBB1_1: ; %for.cond.preheader
; GFX900-NEXT: ; =>This Loop Header: Depth=1
; GFX900-NEXT: ; Child Loop BB1_2 Depth 2
; GFX900-NEXT: v_mov_b32_e32 v6, v2
; GFX900-NEXT: v_mov_b32_e32 v5, v1
-; GFX900-NEXT: s_mov_b32 s4, 0
+; GFX900-NEXT: s_mov_b32 s1, 0
; GFX900-NEXT: .LBB1_2: ; %for.body
; GFX900-NEXT: ; Parent Loop BB1_1 Depth=1
; GFX900-NEXT: ; => This Inner Loop Header: Depth=2
@@ -599,23 +591,23 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX900-NEXT: global_load_dwordx2 v[7:8], v[7:8], off
; GFX900-NEXT: v_addc_co_u32_e32 v14, vcc, -1, v6, vcc
; GFX900-NEXT: global_load_dwordx2 v[17:18], v[13:14], off offset:-2048
-; GFX900-NEXT: v_add_co_u32_e32 v15, vcc, s0, v5
+; GFX900-NEXT: v_add_co_u32_e32 v15, vcc, 0xffffd000, v5
; GFX900-NEXT: v_addc_co_u32_e32 v16, vcc, -1, v6, vcc
; GFX900-NEXT: global_load_dwordx2 v[15:16], v[15:16], off offset:-2048
-; GFX900-NEXT: v_add_co_u32_e32 v19, vcc, s1, v5
+; GFX900-NEXT: v_add_co_u32_e32 v19, vcc, 0xffffe000, v5
; GFX900-NEXT: global_load_dwordx2 v[13:14], v[13:14], off
; GFX900-NEXT: v_addc_co_u32_e32 v20, vcc, -1, v6, vcc
; GFX900-NEXT: global_load_dwordx2 v[23:24], v[19:20], off offset:-4096
; GFX900-NEXT: global_load_dwordx2 v[25:26], v[19:20], off offset:-2048
; GFX900-NEXT: global_load_dwordx2 v[27:28], v[19:20], off
-; GFX900-NEXT: v_add_co_u32_e32 v21, vcc, s3, v5
+; GFX900-NEXT: v_add_co_u32_e32 v21, vcc, 0xfffff000, v5
; GFX900-NEXT: v_addc_co_u32_e32 v22, vcc, -1, v6, vcc
; GFX900-NEXT: global_load_dwordx2 v[19:20], v[21:22], off offset:-2048
; GFX900-NEXT: global_load_dwordx2 v[29:30], v[5:6], off
; GFX900-NEXT: v_add_co_u32_e32 v5, vcc, 0x10000, v5
; GFX900-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
-; GFX900-NEXT: s_addk_i32 s4, 0x2000
-; GFX900-NEXT: s_cmp_gt_u32 s4, 0x3fffff
+; GFX900-NEXT: s_addk_i32 s1, 0x2000
+; GFX900-NEXT: s_cmp_gt_u32 s1, 0x3fffff
; GFX900-NEXT: s_waitcnt vmcnt(8)
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, v7, v3
; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
@@ -649,11 +641,11 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX900-NEXT: s_cbranch_scc0 .LBB1_2
; GFX900-NEXT: ; %bb.3: ; %while.cond.loopexit
; GFX900-NEXT: ; in Loop: Header=BB1_1 Depth=1
-; GFX900-NEXT: s_add_i32 s4, s2, -1
-; GFX900-NEXT: s_cmp_eq_u32 s2, 0
+; GFX900-NEXT: s_add_i32 s1, s0, -1
+; GFX900-NEXT: s_cmp_eq_u32 s0, 0
; GFX900-NEXT: s_cbranch_scc1 .LBB1_5
; GFX900-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1
-; GFX900-NEXT: s_mov_b32 s2, s4
+; GFX900-NEXT: s_mov_b32 s0, s1
; GFX900-NEXT: s_branch .LBB1_1
; GFX900-NEXT: .LBB1_5: ; %while.end
; GFX900-NEXT: v_mov_b32_e32 v1, s35
@@ -805,19 +797,15 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX90A-NEXT: v_mov_b32_e32 v2, s35
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, s34, v1
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v2, vcc
-; GFX90A-NEXT: s_movk_i32 s0, 0x5000
-; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, s0, v1
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x5000, v1
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
-; GFX90A-NEXT: s_movk_i32 s2, 0x7f
+; GFX90A-NEXT: s_movk_i32 s0, 0x7f
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], 0, 0
-; GFX90A-NEXT: s_movk_i32 s0, 0xd000
-; GFX90A-NEXT: s_movk_i32 s1, 0xe000
-; GFX90A-NEXT: s_movk_i32 s3, 0xf000
; GFX90A-NEXT: .LBB1_1: ; %for.cond.preheader
; GFX90A-NEXT: ; =>This Loop Header: Depth=1
; GFX90A-NEXT: ; Child Loop BB1_2 Depth 2
; GFX90A-NEXT: v_pk_mov_b32 v[6:7], v[2:3], v[2:3] op_sel:[0,1]
-; GFX90A-NEXT: s_mov_b32 s4, 0
+; GFX90A-NEXT: s_mov_b32 s1, 0
; GFX90A-NEXT: .LBB1_2: ; %for.body
; GFX90A-NEXT: ; Parent Loop BB1_1 Depth=1
; GFX90A-NEXT: ; => This Inner Loop Header: Depth=2
@@ -829,23 +817,23 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX90A-NEXT: global_load_dwordx2 v[12:13], v[12:13], off
; GFX90A-NEXT: v_addc_co_u32_e32 v15, vcc, -1, v7, vcc
; GFX90A-NEXT: global_load_dwordx2 v[18:19], v[14:15], off offset:-2048
-; GFX90A-NEXT: v_add_co_u32_e32 v16, vcc, s0, v6
+; GFX90A-NEXT: v_add_co_u32_e32 v16, vcc, 0xffffd000, v6
; GFX90A-NEXT: v_addc_co_u32_e32 v17, vcc, -1, v7, vcc
; GFX90A-NEXT: global_load_dwordx2 v[16:17], v[16:17], off offset:-2048
-; GFX90A-NEXT: v_add_co_u32_e32 v20, vcc, s1, v6
+; GFX90A-NEXT: v_add_co_u32_e32 v20, vcc, 0xffffe000, v6
; GFX90A-NEXT: global_load_dwordx2 v[14:15], v[14:15], off
; GFX90A-NEXT: v_addc_co_u32_e32 v21, vcc, -1, v7, vcc
; GFX90A-NEXT: global_load_dwordx2 v[24:25], v[20:21], off offset:-4096
; GFX90A-NEXT: global_load_dwordx2 v[26:27], v[20:21], off offset:-2048
; GFX90A-NEXT: global_load_dwordx2 v[28:29], v[20:21], off
-; GFX90A-NEXT: v_add_co_u32_e32 v22, vcc, s3, v6
+; GFX90A-NEXT: v_add_co_u32_e32 v22, vcc, 0xfffff000, v6
; GFX90A-NEXT: v_addc_co_u32_e32 v23, vcc, -1, v7, vcc
; GFX90A-NEXT: global_load_dwordx2 v[20:21], v[22:23], off offset:-2048
; GFX90A-NEXT: global_load_dwordx2 v[30:31], v[6:7], off
; GFX90A-NEXT: v_add_co_u32_e32 v6, vcc, 0x10000, v6
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
-; GFX90A-NEXT: s_addk_i32 s4, 0x2000
-; GFX90A-NEXT: s_cmp_gt_u32 s4, 0x3fffff
+; GFX90A-NEXT: s_addk_i32 s1, 0x2000
+; GFX90A-NEXT: s_cmp_gt_u32 s1, 0x3fffff
; GFX90A-NEXT: s_waitcnt vmcnt(8)
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, v12, v4
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v13, v5, vcc
@@ -879,11 +867,11 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX90A-NEXT: s_cbranch_scc0 .LBB1_2
; GFX90A-NEXT: ; %bb.3: ; %while.cond.loopexit
; GFX90A-NEXT: ; in Loop: Header=BB1_1 Depth=1
-; GFX90A-NEXT: s_add_i32 s4, s2, -1
-; GFX90A-NEXT: s_cmp_eq_u32 s2, 0
+; GFX90A-NEXT: s_add_i32 s1, s0, -1
+; GFX90A-NEXT: s_cmp_eq_u32 s0, 0
; GFX90A-NEXT: s_cbranch_scc1 .LBB1_5
; GFX90A-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1
-; GFX90A-NEXT: s_mov_b32 s2, s4
+; GFX90A-NEXT: s_mov_b32 s0, s1
; GFX90A-NEXT: s_branch .LBB1_1
; GFX90A-NEXT: .LBB1_5: ; %while.end
; GFX90A-NEXT: v_mov_b32_e32 v1, s35
@@ -1163,10 +1151,8 @@ define amdgpu_kernel void @Address32(ptr addrspace(1) %buffer) {
; GFX8-NEXT: s_movk_i32 s0, 0x1800
; GFX8-NEXT: v_add_u32_e32 v15, vcc, s0, v0
; GFX8-NEXT: v_addc_u32_e32 v16, vcc, 0, v1, vcc
-; GFX8-NEXT: s_movk_i32 s0, 0x1c00
-; GFX8-NEXT: v_add_u32_e32 v17, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v17, vcc, 0x1c00, v0
; GFX8-NEXT: v_addc_u32_e32 v18, vcc, 0, v1, vcc
-; GFX8-NEXT: s_movk_i32 s0, 0x2000
; GFX8-NEXT: flat_load_dword v2, v[0:1]
; GFX8-NEXT: flat_load_dword v19, v[5:6]
; GFX8-NEXT: flat_load_dword v7, v[7:8]
@@ -1175,7 +1161,7 @@ define amdgpu_kernel void @Address32(ptr addrspace(1) %buffer) {
; GFX8-NEXT: flat_load_dword v10, v[13:14]
; GFX8-NEXT: flat_load_dword v11, v[15:16]
; GFX8-NEXT: flat_load_dword v12, v[17:18]
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x2000, v0
; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x2400, v0
; GFX8-NEXT: flat_load_dword v5, v[5:6]
@@ -1230,10 +1216,9 @@ define amdgpu_kernel void @Address32(ptr addrspace(1) %buffer) {
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v4
; GFX900-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v0, vcc
; GFX900-NEXT: v_lshlrev_b64 v[0:1], 2, v[1:2]
-; GFX900-NEXT: s_movk_i32 s0, 0x1000
; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0
; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v1, vcc
-; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, s0, v0
+; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, 0x1000, v0
; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX900-NEXT: global_load_dword v5, v[0:1], off
; GFX900-NEXT: global_load_dword v6, v[0:1], off offset:1024
@@ -1357,8 +1342,7 @@ define amdgpu_kernel void @Address32(ptr addrspace(1) %buffer) {
; GFX90A-NEXT: v_lshlrev_b64 v[0:1], 2, v[2:3]
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v5, v0
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v1, vcc
-; GFX90A-NEXT: s_movk_i32 s0, 0x1000
-; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, s0, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0x1000, v0
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX90A-NEXT: global_load_dword v5, v[0:1], off
; GFX90A-NEXT: global_load_dword v6, v[0:1], off offset:1024
@@ -1526,10 +1510,9 @@ define amdgpu_kernel void @Offset64(ptr addrspace(1) %buffer) {
; GFX8-NEXT: s_movk_i32 s0, 0xf000
; GFX8-NEXT: v_add_u32_e32 v5, vcc, s0, v0
; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc
-; GFX8-NEXT: s_movk_i32 s0, 0xf800
; GFX8-NEXT: flat_load_dwordx2 v[7:8], v[0:1]
; GFX8-NEXT: flat_load_dwordx2 v[5:6], v[5:6]
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0xfffff800, v0
; GFX8-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx2 v[9:10], v[9:10]
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0
@@ -1804,11 +1787,9 @@ define amdgpu_kernel void @p32Offset64(ptr addrspace(1) %buffer) {
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v3, v0
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
-; GFX8-NEXT: s_mov_b32 s0, 0x7ffff800
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7ffff800, v0
; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc
-; GFX8-NEXT: s_mov_b32 s0, 0x7ffffc00
-; GFX8-NEXT: v_add_u32_e32 v7, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, 0x7ffffc00, v0
; GFX8-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v2, v[0:1]
; GFX8-NEXT: flat_load_dword v5, v[5:6]
@@ -2348,13 +2329,11 @@ define amdgpu_kernel void @ReverseOrder(ptr addrspace(1) %buffer) {
; GFX8-NEXT: s_movk_i32 s0, 0x2000
; GFX8-NEXT: v_add_u32_e32 v13, vcc, s0, v0
; GFX8-NEXT: v_addc_u32_e32 v14, vcc, 0, v1, vcc
-; GFX8-NEXT: s_movk_i32 s0, 0x1800
-; GFX8-NEXT: v_add_u32_e32 v15, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v15, vcc, 0x1800, v0
; GFX8-NEXT: v_addc_u32_e32 v16, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx2 v[13:14], v[13:14]
; GFX8-NEXT: flat_load_dwordx2 v[15:16], v[15:16]
-; GFX8-NEXT: s_movk_i32 s0, 0x1000
-; GFX8-NEXT: v_add_u32_e32 v17, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e32 v17, vcc, 0x1000, v0
; GFX8-NEXT: v_addc_u32_e32 v18, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx2 v[17:18], v[17:18]
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x800, v0
@@ -2424,8 +2403,7 @@ define amdgpu_kernel void @ReverseOrder(ptr addrspace(1) %buffer) {
; GFX900-NEXT: v_add_co_u32_e32 v4, vcc, s0, v0
; GFX900-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
; GFX900-NEXT: global_load_dwordx2 v[10:11], v[4:5], off offset:2048
-; GFX900-NEXT: s_movk_i32 s0, 0x1000
-; GFX900-NEXT: v_add_co_u32_e32 v12, vcc, s0, v0
+; GFX900-NEXT: v_add_co_u32_e32 v12, vcc, 0x1000, v0
; GFX900-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v1, vcc
; GFX900-NEXT: global_load_dwordx2 v[14:15], v[12:13], off
; GFX900-NEXT: global_load_dwordx2 v[16:17], v[4:5], off
@@ -2571,8 +2549,7 @@ define amdgpu_kernel void @ReverseOrder(ptr addrspace(1) %buffer) {
; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, s0, v0
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
; GFX90A-NEXT: global_load_dwordx2 v[10:11], v[4:5], off offset:2048
-; GFX90A-NEXT: s_movk_i32 s0, 0x1000
-; GFX90A-NEXT: v_add_co_u32_e32 v12, vcc, s0, v0
+; GFX90A-NEXT: v_add_co_u32_e32 v12, vcc, 0x1000, v0
; GFX90A-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v1, vcc
; GFX90A-NEXT: global_load_dwordx2 v[14:15], v[12:13], off
; GFX90A-NEXT: global_load_dwordx2 v[16:17], v[4:5], off
@@ -2743,8 +2720,7 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v0
; GFX8-NEXT: v_addc_u32_e32 v6, vcc, v4, v1, vcc
-; GFX8-NEXT: s_movk_i32 s0, 0x800
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x800, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, -1, v6, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0, v2
; GFX8-NEXT: v_addc_u32_e32 v6, vcc, -1, v6, vcc
@@ -2784,10 +2760,9 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s34, v8
; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v0, vcc
; GFX900-NEXT: v_lshlrev_b64 v[0:1], 3, v[1:2]
-; GFX900-NEXT: s_movk_i32 s0, 0x1000
; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, v3, v0
; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v1, vcc
-; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2
+; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v2
; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v3, vcc
; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, 0, v2
; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc
@@ -2871,8 +2846,7 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf
; GFX90A-NEXT: v_lshlrev_b64 v[0:1], 3, v[2:3]
; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v4, v0
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v1, vcc
-; GFX90A-NEXT: s_movk_i32 s0, 0x1000
-; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2
+; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v3, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, 0, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
index 705a2af73959065..7361d9d9f795e39 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
@@ -1394,8 +1394,7 @@ define i64 @v_test_sdiv_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4
; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1
; GCN-IR-NEXT: v_min_u32_e32 v8, v4, v5
-; GCN-IR-NEXT: s_movk_i32 s6, 0xffc5
-; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, s6, v8
+; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, 0xffffffc5, v8
; GCN-IR-NEXT: v_addc_u32_e64 v6, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[5:6]
@@ -1587,8 +1586,7 @@ define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4
; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1
; GCN-IR-NEXT: v_min_u32_e32 v8, v4, v5
-; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0
-; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, s6, v8
+; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, 0xffffffd0, v8
; GCN-IR-NEXT: v_addc_u32_e64 v6, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[5:6]
@@ -1722,13 +1720,12 @@ define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
-; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: .LBB13_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[9:10], v[9:10], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v4
; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
-; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, s12, v0
+; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, 0x7fff, v0
; GCN-IR-NEXT: v_subb_u32_e32 v5, vcc, 0, v10, vcc
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v7
; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1
diff --git a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
index 08db1e7fee259d6..dd4eb0ae2a09ed6 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
@@ -5000,22 +5000,14 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
; GFX9-FLATSCR-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
; GFX9-FLATSCR-NEXT: v_lshlrev_b32_e32 v5, 13, v0
-; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x80
+; GFX9-FLATSCR-NEXT: s_mov_b32 s4, 4
; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v2, vcc, s2, v5
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, s3
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v0, vcc
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s4, v2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x80, v2
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
-; GFX9-FLATSCR-NEXT: s_mov_b32 s4, 4
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0x84
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x104
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x184
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x204
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x284
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x304
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x384
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
@@ -5043,1268 +5035,1268 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4080
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x100, v2
; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x74
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x100
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s4, v2
-; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x84
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0x94
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x94
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0xa4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0xb4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0xc4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0xd4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0xe4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0xf4
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s5 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s5, 0x180
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s5, v2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x180, v2
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x104
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x114
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x114
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x124
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x124
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x134
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x134
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x144
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x144
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x154
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x154
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x164
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x164
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x174
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s6 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s6, 0x200
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s6, v2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x200, v2
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x174
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x184
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x194
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x194
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x1a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x1b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x1c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x1d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x1e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x1f4
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s7 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s7, 0x280
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s7, v2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x280, v2
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1f4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x204
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x214
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x214
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x224
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x224
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x234
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x234
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x244
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x244
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x254
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x254
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x264
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x264
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x274
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s8 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s8, 0x300
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s8, v2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x300, v2
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x274
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x284
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x294
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x294
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x2a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x2a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x2b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x2b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x2c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x2c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x2d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x2d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x2e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x2e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x2f4
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s9 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s9, 0x380
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s9, v2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x380, v2
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x2f4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x304
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x314
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x314
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x324
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x324
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x334
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x334
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x344
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x344
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x354
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x354
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x364
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x364
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x374
-; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s10 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s10, 0x400
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s10, v2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x400, v2
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x374
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3968
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x384
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x394
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x394
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x3a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x3a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x3b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x3b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x3c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x3c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x3d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x3d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:4064
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:4080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x3e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x3e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(1)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s11 ; 16-byte Folded Spill
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x3f4
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s4 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x3f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(1)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3]
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x404
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x404
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, s1
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:16
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x414
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x414
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:32
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x424
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x424
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:48
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x434
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x434
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:64
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x444
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x444
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:80
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x454
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x454
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:96
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x464
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x464
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:112
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x474
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x474
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:128
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x484
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x484
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:144
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x494
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x494
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:160
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x4a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x4a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:176
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x4b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x4b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:192
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x4c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x4c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:208
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x4d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x4d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:224
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x4e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x4e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:240
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x4f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x4f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:256
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x504
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x504
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:272
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x514
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x514
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:288
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x524
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x524
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:304
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x534
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x534
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:320
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x544
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x544
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:336
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x554
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x554
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:352
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x564
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x564
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:368
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x574
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x574
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:384
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x584
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x584
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:400
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x594
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x594
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:416
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x5a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x5a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:432
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x5b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x5b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:448
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x5c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x5c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:464
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x5d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x5d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:480
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x5e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x5e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:496
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x5f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x5f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:512
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x604
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x604
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:528
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x614
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x614
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:544
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x624
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x624
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:560
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x634
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x634
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:576
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x644
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x644
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:592
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x654
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x654
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:608
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x664
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x664
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:624
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x674
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x674
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:640
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x684
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x684
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:656
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x694
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x694
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:672
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x6a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x6a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:688
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x6b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x6b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:704
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x6c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x6c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:720
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x6d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x6d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:736
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x6e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x6e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:752
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x6f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x6f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:768
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x704
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x704
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:784
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x714
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x714
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:800
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x724
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x724
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:816
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x734
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x734
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:832
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x744
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x744
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:848
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x754
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x754
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:864
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x764
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x764
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:880
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x774
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x774
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:896
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x784
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x784
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:912
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x794
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x794
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:928
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x7a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x7a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:944
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x7b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x7b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:960
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x7c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x7c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:976
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x7d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x7d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:992
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x7e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x7e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1008
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x7f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x7f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1024
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x804
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x804
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1040
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x814
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x814
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1056
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x824
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x824
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1072
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x834
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x834
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1088
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x844
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x844
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1104
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x854
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x854
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1120
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x864
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x864
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1136
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x874
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x874
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1152
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x884
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x884
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1168
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x894
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x894
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1184
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x8a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x8a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1200
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x8b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x8b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1216
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x8c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x8c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1232
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x8d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x8d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1248
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x8e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x8e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1264
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x8f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x8f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1280
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x904
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x904
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1296
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x914
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x914
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1312
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x924
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x924
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1328
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x934
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x934
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1344
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x944
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x944
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1360
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x954
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x954
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1376
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x964
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x964
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1392
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x974
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x974
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1408
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x984
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x984
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1424
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x994
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x994
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1440
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x9a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x9a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1456
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x9b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x9b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1472
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x9c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x9c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1488
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x9d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x9d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1504
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x9e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x9e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1520
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x9f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x9f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1536
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa04
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa04
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1552
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa14
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa14
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1568
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa24
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa24
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1584
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa34
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa34
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1600
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa44
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa44
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1616
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa54
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa54
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1632
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa64
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa64
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1648
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa74
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa74
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1664
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa84
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa84
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1680
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xa94
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xa94
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1696
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xaa4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xaa4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1712
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xab4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xab4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1728
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xac4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xac4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1744
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xad4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xad4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1760
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xae4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xae4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1776
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xaf4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xaf4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1792
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb04
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb04
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1808
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb14
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb14
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1824
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb24
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb24
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1840
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb34
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb34
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1856
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb44
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb44
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1872
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb54
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb54
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1888
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb64
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb64
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1904
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb74
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb74
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1920
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb84
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb84
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1936
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xb94
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xb94
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1952
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xba4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xba4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1968
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xbb4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xbb4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:1984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xbc4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xbc4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xbd4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xbd4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xbe4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xbe4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xbf4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xbf4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc04
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc04
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc14
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc14
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2080
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc24
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc24
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2096
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc34
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc34
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2112
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc44
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc44
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2128
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc54
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc54
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2144
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc64
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc64
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2160
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc74
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc74
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2176
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc84
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc84
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2192
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xc94
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xc94
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2208
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xca4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xca4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2224
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xcb4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xcb4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2240
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xcc4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xcc4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2256
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xcd4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xcd4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2272
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xce4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xce4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2288
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xcf4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xcf4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2304
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd04
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd04
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2320
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd14
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd14
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2336
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd24
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd24
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2352
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd34
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd34
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2368
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd44
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd44
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2384
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd54
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd54
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2400
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd64
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd64
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2416
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd74
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd74
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2432
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd84
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd84
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2448
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xd94
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xd94
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2464
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xda4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xda4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2480
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xdb4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xdb4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2496
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xdc4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xdc4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2512
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xdd4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xdd4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2528
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xde4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xde4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2544
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xdf4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xdf4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2560
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe04
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe04
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2576
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe14
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe14
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2592
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe24
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe24
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2608
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe34
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe34
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2624
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe44
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe44
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2640
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe54
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe54
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2656
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe64
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe64
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2672
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe74
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe74
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2688
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe84
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe84
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2704
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xe94
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xe94
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2720
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xea4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xea4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2736
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xeb4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xeb4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2752
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xec4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xec4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2768
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xed4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xed4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2784
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xee4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xee4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2800
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xef4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xef4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2816
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf04
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf04
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2832
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf14
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf14
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2848
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf24
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf24
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2864
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf34
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf34
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2880
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf44
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf44
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2896
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf54
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf54
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2912
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf64
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf64
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2928
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf74
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf74
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2944
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf84
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf84
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2960
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xf94
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xf94
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2976
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xfa4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xfa4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:2992
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xfb4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xfb4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3008
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xfc4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xfc4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3024
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xfd4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xfd4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3040
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xfe4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xfe4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3056
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0xff4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0xff4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3072
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1004
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1004
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3088
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1014
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1014
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3104
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1024
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1024
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3120
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1034
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1034
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3136
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1044
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1044
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3152
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1054
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1054
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3168
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1064
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1064
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3184
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1074
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1074
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3200
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1084
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1084
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3216
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1094
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1094
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3232
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x10a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x10a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3248
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x10b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x10b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3264
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x10c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x10c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3280
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x10d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x10d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3296
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x10e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x10e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3312
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x10f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x10f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3328
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1104
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1104
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3344
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1114
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1114
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3360
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1124
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1124
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3376
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1134
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1134
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3392
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1144
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1144
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3408
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1154
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1154
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3424
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1164
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1164
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3440
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1174
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1174
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3456
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1184
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1184
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3472
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1194
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1194
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3488
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x11a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x11a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3504
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x11b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x11b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3520
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x11c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x11c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3536
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x11d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x11d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3552
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x11e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x11e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3568
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x11f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x11f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3584
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1204
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1204
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3600
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1214
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1214
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3616
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1224
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1224
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3632
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1234
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1234
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3648
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1244
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1244
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3664
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1254
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1254
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3680
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1264
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1264
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3696
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1274
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1274
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3712
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1284
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1284
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3728
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1294
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1294
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3744
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x12a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x12a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3760
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x12b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x12b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3776
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x12c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x12c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3792
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x12d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x12d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3808
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x12e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x12e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3824
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x12f4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x12f4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3840
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1304
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1304
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3856
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1314
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1314
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3872
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1324
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1324
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3888
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1334
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1334
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3904
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1344
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1344
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3920
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1354
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1354
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3936
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1364
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1364
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3952
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1374
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1374
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3968
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1384
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1384
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:3984
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x1394
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x1394
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:4000
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x13a4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x13a4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:4016
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x13b4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x13b4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:4032
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x13c4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x13c4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:4048
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x13d4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x13d4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:4064
-; GFX9-FLATSCR-NEXT: s_movk_i32 s11, 0x13e4
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x13e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s11 ; 16-byte Folded Spill
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s4 ; 16-byte Folded Spill
; GFX9-FLATSCR-NEXT: global_load_dwordx4 v[0:3], v5, s[2:3] offset:4080
; GFX9-FLATSCR-NEXT: s_movk_i32 s2, 0x13e4
; GFX9-FLATSCR-NEXT: ;;#ASMSTART
@@ -7346,7 +7338,7 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v5, v[0:3], s[0:1]
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x3f4
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s10, v4
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x400, v4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x3e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
@@ -7380,7 +7372,7 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[0:1], v[7:10], off offset:3968
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s9, v4
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x380, v4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x364
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
@@ -7414,7 +7406,7 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[0:1], v[7:10], off offset:3968
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s8, v4
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x300, v4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x2e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
@@ -7448,7 +7440,7 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[0:1], v[7:10], off offset:3968
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s7, v4
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x280, v4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x264
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
@@ -7482,7 +7474,7 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[0:1], v[7:10], off offset:3968
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x200, v4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x1e4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
@@ -7516,7 +7508,7 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[0:1], v[7:10], off offset:3968
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s5, v4
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x180, v4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x164
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
@@ -7550,7 +7542,7 @@ define amdgpu_kernel void @test(ptr addrspace(1) %out, ptr addrspace(1) %in) {
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: global_store_dwordx4 v[0:1], v[7:10], off offset:3968
; GFX9-FLATSCR-NEXT: scratch_load_dwordx4 v[7:10], off, s0 ; 16-byte Folded Reload
-; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s4, v4
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x100, v4
; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0xe4
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll
index 613349f32e2d5ad..f8898ddf9290bcd 100644
--- a/llvm/test/CodeGen/AMDGPU/srem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem64.ll
@@ -1583,8 +1583,7 @@ define i64 @v_test_srem_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3
-; GCN-IR-NEXT: s_movk_i32 s6, 0xffc5
-; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, s6, v6
+; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 0xffffffc5, v6
; GCN-IR-NEXT: v_addc_u32_e64 v4, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[3:4]
@@ -1774,8 +1773,7 @@ define i64 @v_test_srem_pow2_k_num_i64(i64 %x) {
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3
-; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0
-; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, s6, v6
+; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 0xffffffd0, v6
; GCN-IR-NEXT: v_addc_u32_e64 v4, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[3:4]
@@ -1914,13 +1912,12 @@ define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
-; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: .LBB13_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
-; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, s12, v10
+; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 0x7fff, v10
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, 0, v11, vcc
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll
index c5ab44e31c0320d..ea938d5a121a24c 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll
@@ -1283,13 +1283,12 @@ define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
-; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4
-; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v6
+; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 0x7fff, v6
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll
index 894c96acbbcd6b1..c1119e0a9cc3336 100644
--- a/llvm/test/CodeGen/AMDGPU/urem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/urem64.ll
@@ -1307,13 +1307,12 @@ define i64 @v_test_urem_pow2_k_den_i64(i64 %x) {
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
-; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
-; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v8
+; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 0x7fff, v8
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
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