[PATCH] D155472: [DAG] Attempt shl narrowing in SimplifyDemandedBits

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 557530.
RKSimon added a comment.

rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155472/new/

https://reviews.llvm.org/D155472

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/AArch64/ushl_sat.ll
  llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
  llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
  llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
  llvm/test/CodeGen/AMDGPU/idiv-licm.ll
  llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
  llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
  llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
  llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
  llvm/test/CodeGen/AMDGPU/xnor.ll
  llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll
  llvm/test/CodeGen/X86/atomic-rm-bit-test-64.ll
  llvm/test/CodeGen/X86/avx512vnni-combine.ll
  llvm/test/CodeGen/X86/avxvnni-combine.ll
  llvm/test/CodeGen/X86/bswap.ll
  llvm/test/CodeGen/X86/buildvec-insertvec.ll
  llvm/test/CodeGen/X86/cmp-concat.ll
  llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness-reduced.ll
  llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
  llvm/test/CodeGen/X86/combine-bitreverse.ll
  llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
  llvm/test/CodeGen/X86/dagcombine-shifts.ll
  llvm/test/CodeGen/X86/divmod128.ll
  llvm/test/CodeGen/X86/extract-bits.ll
  llvm/test/CodeGen/X86/fold-and-shift.ll
  llvm/test/CodeGen/X86/fp128-i128.ll
  llvm/test/CodeGen/X86/lea-dagdag.ll
  llvm/test/CodeGen/X86/lea-opt2.ll
  llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
  llvm/test/CodeGen/X86/parity.ll
  llvm/test/CodeGen/X86/pr62653.ll
  llvm/test/CodeGen/X86/select.ll
  llvm/test/CodeGen/X86/select_const.ll
  llvm/test/CodeGen/X86/selectcc-to-shiftand.ll
  llvm/test/CodeGen/X86/setcc.ll
  llvm/test/CodeGen/X86/shift-combine.ll
  llvm/test/CodeGen/X86/vector-shuffle-variable-128.ll
  llvm/test/CodeGen/X86/vector-shuffle-variable-256.ll
  llvm/test/CodeGen/X86/vselect.ll
  llvm/test/CodeGen/X86/zext-logicop-shift-load.ll
  llvm/test/CodeGen/X86/zext-shl.ll