[llvm] [RISCV][GISel] Add ISel supports for SHXADD from Zba extension (PR #67863)

via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 29 15:39:03 PDT 2023


github-actions[bot] wrote:


<!--LLVM CODE FORMAT COMMENT: {clang-format}-->

:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff a3c11723d508efd59dbadcc078fec7513f99fdfd 08f77d6a53dadd4c136b92fcb60700fd7389eeb3 -- llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 3a98e84546f3..f264c041eaf9 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -177,8 +177,8 @@ RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root,
         }}};
       }
 
-      // Given (and (lshr y, c2), mask) in which mask has c2 leading zeros and c3
-      // trailing zeros. We can use an SRLI by c2 + c3 followed by a SHXADD.
+      // Given (and (lshr y, c2), mask) in which mask has c2 leading zeros and
+      // c3 trailing zeros. We can use an SRLI by c2 + c3 followed by a SHXADD.
       if (!*LeftShift && Leading == C2 && Trailing == ShAmt) {
         Register DstReg =
             MRI.createGenericVirtualRegister(MRI.getType(RootReg));

``````````

</details>


https://github.com/llvm/llvm-project/pull/67863


More information about the llvm-commits mailing list