[llvm] 305fbc1 - Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
Tobias Stadler via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 28 18:44:56 PDT 2023
Author: Tobias Stadler
Date: 2023-09-29T03:35:40+02:00
New Revision: 305fbc1b320364a4e70cea2d9987de2b0b14dcc5
URL: https://github.com/llvm/llvm-project/commit/305fbc1b320364a4e70cea2d9987de2b0b14dcc5
DIFF: https://github.com/llvm/llvm-project/commit/305fbc1b320364a4e70cea2d9987de2b0b14dcc5.diff
LOG: Revert "[GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND"
This reverts commit 3686a0b611c65f0d7190345b8e3e73cdca9fa657.
This seems to have broken some sanitizer tests:
https://lab.llvm.org/buildbot/#/builders/184/builds/7721
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-debugloc.mir
llvm/test/CodeGen/AArch64/GlobalISel/huge-switch.ll
llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-cse.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptrtoint.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir
llvm/test/CodeGen/AArch64/zext.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-cse-leaves-dead-cast.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctlz.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/cttz.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-abs.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-add.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-icmp.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-lshr.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul-ext.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-shl.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-store.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-sub.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ashr.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-icmp.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-lshr.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul-ext.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-shl.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-store.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir
llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-ext.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-trunc.mir
llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir
llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h b/llvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h
index ea75c2c7f6f4194..eff87c5617d997d 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h
@@ -118,7 +118,11 @@ class GISelKnownBitsAnalysis : public MachineFunctionPass {
GISelKnownBitsAnalysis() : MachineFunctionPass(ID) {
initializeGISelKnownBitsAnalysisPass(*PassRegistry::getPassRegistry());
}
- GISelKnownBits &get(MachineFunction &MF);
+ GISelKnownBits &get(MachineFunction &MF) {
+ if (!Info)
+ Info = std::make_unique<GISelKnownBits>(MF);
+ return *Info.get();
+ }
void getAnalysisUsage(AnalysisUsage &AU) const override;
bool runOnMachineFunction(MachineFunction &MF) override;
void releaseMemory() override { Info.reset(); }
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
index 90b627764d059f6..7ccb99d511fff46 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -35,7 +35,6 @@ class LegalizationArtifactCombiner {
MachineIRBuilder &Builder;
MachineRegisterInfo &MRI;
const LegalizerInfo &LI;
- GISelKnownBits *KB;
static bool isArtifactCast(unsigned Opc) {
switch (Opc) {
@@ -51,9 +50,8 @@ class LegalizationArtifactCombiner {
public:
LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI,
- const LegalizerInfo &LI,
- GISelKnownBits *KB = nullptr)
- : Builder(B), MRI(MRI), LI(LI), KB(KB) {}
+ const LegalizerInfo &LI)
+ : Builder(B), MRI(MRI), LI(LI) {}
bool tryCombineAnyExt(MachineInstr &MI,
SmallVectorImpl<MachineInstr *> &DeadInsts,
@@ -133,26 +131,13 @@ class LegalizationArtifactCombiner {
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
LLT SrcTy = MRI.getType(SrcReg);
APInt MaskVal = APInt::getAllOnes(SrcTy.getScalarSizeInBits());
+ auto Mask = Builder.buildConstant(
+ DstTy, MaskVal.zext(DstTy.getScalarSizeInBits()));
if (SextSrc && (DstTy != MRI.getType(SextSrc)))
SextSrc = Builder.buildSExtOrTrunc(DstTy, SextSrc).getReg(0);
if (TruncSrc && (DstTy != MRI.getType(TruncSrc)))
TruncSrc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrc).getReg(0);
- APInt ExtMaskVal = MaskVal.zext(DstTy.getScalarSizeInBits());
- Register AndSrc = SextSrc ? SextSrc : TruncSrc;
- // Elide G_AND and mask constant if possible.
- // The G_AND would also be removed by the post-legalize redundant_and
- // combine, but in this very common case, eliding early and regardless of
- // OptLevel results in significant compile-time and O0 code-size
- // improvements. Inserting unnecessary instructions between a boolean def
- // and use can also hinder ISel to detect e.g. that reloading a flags
- // register is unnecessary.
- if (KB && (KB->getKnownZeroes(AndSrc) | ExtMaskVal).isAllOnes()) {
- replaceRegOrBuildCopy(DstReg, AndSrc, MRI, Builder, UpdatedDefs,
- Observer);
- } else {
- auto Mask = Builder.buildConstant(DstTy, ExtMaskVal);
- Builder.buildAnd(DstReg, AndSrc, Mask);
- }
+ Builder.buildAnd(DstReg, SextSrc ? SextSrc : TruncSrc, Mask);
markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
return true;
}
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
index ea8c20cdcd45d66..bbe82e201366d59 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
@@ -19,7 +19,6 @@
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/IR/Module.h"
-#include "llvm/Target/TargetMachine.h"
#define DEBUG_TYPE "gisel-known-bits"
@@ -774,12 +773,3 @@ void GISelKnownBitsAnalysis::getAnalysisUsage(AnalysisUsage &AU) const {
bool GISelKnownBitsAnalysis::runOnMachineFunction(MachineFunction &MF) {
return false;
}
-
-GISelKnownBits &GISelKnownBitsAnalysis::get(MachineFunction &MF) {
- if (!Info) {
- unsigned MaxDepth =
- MF.getTarget().getOptLevel() == CodeGenOptLevel::None ? 2 : 6;
- Info = std::make_unique<GISelKnownBits>(MF, MaxDepth);
- }
- return *Info.get();
-}
diff --git a/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp b/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
index 6d75258c1041b1a..aecbe0b7604c074 100644
--- a/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
@@ -218,7 +218,7 @@ Legalizer::legalizeMachineFunction(MachineFunction &MF, const LegalizerInfo &LI,
// This will keep all the observers notified about new insertions/deletions.
RAIIMFObsDelInstaller Installer(MF, WrapperObserver);
LegalizerHelper Helper(MF, LI, WrapperObserver, MIRBuilder, KB);
- LegalizationArtifactCombiner ArtCombiner(MIRBuilder, MRI, LI, KB);
+ LegalizationArtifactCombiner ArtCombiner(MIRBuilder, MRI, LI);
bool Changed = false;
SmallVector<MachineInstr *, 128> RetryList;
do {
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
index 88061756d8feebb..0c52a8a683e3a06 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
@@ -926,6 +926,7 @@ define dso_local i64 @atomicrmw_add_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_add_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_monotonic:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -948,6 +949,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_acquire:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -970,6 +972,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_release:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -992,6 +995,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_acq_rel:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -1014,6 +1018,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_seq_cst:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -1301,6 +1306,7 @@ define dso_local i64 @atomicrmw_add_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_add_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_monotonic:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1315,6 +1321,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_add_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_acquire:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1329,6 +1336,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_release:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1343,6 +1351,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_acq_rel:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1357,6 +1366,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_seq_cst:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1696,6 +1706,7 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_sub_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_monotonic:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1717,6 +1728,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_acquire:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1738,6 +1750,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_release:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1759,6 +1772,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_acq_rel:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1780,6 +1794,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_seq_cst:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -2066,6 +2081,7 @@ define dso_local i64 @atomicrmw_sub_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_sub_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_monotonic:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_monotonic:
@@ -2079,6 +2095,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_sub_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_acquire:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_acquire:
@@ -2092,6 +2109,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_release:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_release:
@@ -2105,6 +2123,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_acq_rel:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_acq_rel:
@@ -2118,6 +2137,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_seq_cst:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_seq_cst:
@@ -5372,7 +5392,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5393,7 +5415,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5414,7 +5438,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5435,7 +5461,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5456,7 +5484,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5477,7 +5507,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_aligned_monotonic:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5497,7 +5529,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acquire:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5517,7 +5551,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_release:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5537,7 +5573,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acq_rel:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5557,7 +5595,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_seq_cst:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5576,7 +5616,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5594,7 +5636,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5612,7 +5656,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5630,7 +5676,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5648,7 +5696,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5666,7 +5716,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5684,7 +5736,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5702,7 +5756,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5720,7 +5776,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5738,7 +5796,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5756,11 +5816,15 @@ define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -5786,11 +5850,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -5816,11 +5884,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -5846,11 +5918,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -5876,11 +5952,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -5907,7 +5987,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5928,7 +6010,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5949,7 +6033,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5970,7 +6056,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5991,7 +6079,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6012,7 +6102,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0-LABEL: atomicrmw_max_i16_unaligned_monotonic:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
@@ -6028,7 +6120,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_acquire:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
@@ -6044,7 +6138,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_release:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
@@ -6060,7 +6156,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
@@ -6076,7 +6174,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
@@ -6091,7 +6191,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_monotonic:
@@ -6105,7 +6207,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_max_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_acquire:
@@ -6119,7 +6223,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_release:
@@ -6133,7 +6239,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_acq_rel:
@@ -6147,7 +6255,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_seq_cst:
@@ -6161,7 +6271,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_monotonic:
@@ -6175,7 +6287,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_max_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_acquire:
@@ -6189,7 +6303,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_release:
@@ -6203,7 +6319,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_acq_rel:
@@ -6217,7 +6335,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_seq_cst:
@@ -6231,11 +6351,15 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6253,11 +6377,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6275,11 +6403,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6297,11 +6429,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6319,11 +6455,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6342,7 +6482,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6363,7 +6505,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6384,7 +6528,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6405,7 +6551,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6426,7 +6574,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6447,7 +6597,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_aligned_monotonic:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6467,7 +6619,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acquire:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6487,7 +6641,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_release:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6507,7 +6663,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acq_rel:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6527,7 +6685,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_seq_cst:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6546,7 +6706,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6564,7 +6726,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6582,7 +6746,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6600,7 +6766,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6618,7 +6786,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6636,7 +6806,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6654,7 +6826,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6672,7 +6846,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6690,7 +6866,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6708,7 +6886,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6726,11 +6906,15 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -6756,11 +6940,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -6786,11 +6974,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -6816,11 +7008,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -6846,11 +7042,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -6877,7 +7077,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6898,7 +7100,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6919,7 +7123,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6940,7 +7146,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6961,7 +7169,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6982,7 +7192,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0-LABEL: atomicrmw_min_i16_unaligned_monotonic:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
@@ -6998,7 +7210,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_acquire:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
@@ -7014,7 +7228,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_release:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
@@ -7030,7 +7246,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
@@ -7046,7 +7264,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
@@ -7061,7 +7281,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
@@ -7075,7 +7297,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
@@ -7089,7 +7313,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
@@ -7103,7 +7329,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
@@ -7117,7 +7345,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
@@ -7131,7 +7361,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
@@ -7145,7 +7377,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
@@ -7159,7 +7393,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
@@ -7173,7 +7409,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
@@ -7187,7 +7425,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
@@ -7201,11 +7441,15 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7223,11 +7467,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7245,11 +7493,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7267,11 +7519,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7289,11 +7545,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7312,7 +7572,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7333,7 +7595,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7354,7 +7618,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7375,7 +7641,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7396,7 +7664,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7416,7 +7686,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_monotonic:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7435,7 +7707,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acquire:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7454,7 +7728,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_release:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7473,7 +7749,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7492,7 +7770,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7511,7 +7791,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7529,7 +7811,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7547,7 +7831,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7565,7 +7851,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7583,7 +7871,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7601,7 +7891,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7619,7 +7911,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7637,7 +7931,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7655,7 +7951,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7673,7 +7971,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7691,11 +7991,15 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -7721,11 +8025,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -7751,11 +8059,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -7781,11 +8093,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -7811,11 +8127,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -7842,7 +8162,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O0-LABEL: atomicrmw_umax_i8_unaligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7863,7 +8185,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7884,7 +8208,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7905,7 +8231,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7926,7 +8254,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7946,7 +8276,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
@@ -7961,7 +8293,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acquire:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
@@ -7976,7 +8310,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_release:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
@@ -7991,7 +8327,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
@@ -8006,7 +8344,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
@@ -8021,7 +8361,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_monotonic:
@@ -8035,7 +8377,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umax_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_acquire:
@@ -8049,7 +8393,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_release:
@@ -8063,7 +8409,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_acq_rel:
@@ -8077,7 +8425,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_seq_cst:
@@ -8091,7 +8441,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_monotonic:
@@ -8105,7 +8457,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umax_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_acquire:
@@ -8119,7 +8473,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_release:
@@ -8133,7 +8489,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_acq_rel:
@@ -8147,7 +8505,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_seq_cst:
@@ -8161,11 +8521,15 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8183,11 +8547,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8205,11 +8573,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8227,11 +8599,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8249,11 +8625,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8272,7 +8652,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8293,7 +8675,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8314,7 +8698,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8335,7 +8721,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8356,7 +8744,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8376,7 +8766,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_monotonic:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8395,7 +8787,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acquire:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8414,7 +8808,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_release:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8433,7 +8829,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8452,7 +8850,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8471,7 +8871,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8489,7 +8891,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8507,7 +8911,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8525,7 +8931,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8543,7 +8951,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8561,7 +8971,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8579,7 +8991,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8597,7 +9011,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8615,7 +9031,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8633,7 +9051,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8651,11 +9071,15 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -8681,11 +9105,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -8711,11 +9139,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -8741,11 +9173,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -8771,11 +9207,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -8802,7 +9242,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O0-LABEL: atomicrmw_umin_i8_unaligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8823,7 +9265,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8844,7 +9288,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8865,7 +9311,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8886,7 +9334,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8906,7 +9356,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
@@ -8921,7 +9373,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acquire:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
@@ -8936,7 +9390,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_release:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
@@ -8951,7 +9407,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
@@ -8966,7 +9424,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
@@ -8981,7 +9441,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
@@ -8995,7 +9457,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
@@ -9009,7 +9473,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
@@ -9023,7 +9489,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
@@ -9037,7 +9505,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
@@ -9051,7 +9521,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
@@ -9065,7 +9537,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
@@ -9079,7 +9553,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
@@ -9093,7 +9569,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
@@ -9107,7 +9585,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
@@ -9121,11 +9601,15 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9143,11 +9627,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9165,11 +9653,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9187,11 +9679,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9209,11 +9705,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
index a1712a5ec7a27cf..4b0371d23b5b895 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
@@ -511,6 +511,7 @@ define dso_local i64 @atomicrmw_add_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_add_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_monotonic:
; -O0: adds x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: subs w11, w11, #1
; -O0: casp x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
@@ -531,6 +532,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_acquire:
; -O0: adds x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: subs w11, w11, #1
; -O0: caspa x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
@@ -551,6 +553,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_release:
; -O0: adds x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: subs w11, w11, #1
; -O0: caspl x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
@@ -571,6 +574,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_acq_rel:
; -O0: adds x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: subs w11, w11, #1
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
@@ -591,6 +595,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_seq_cst:
; -O0: adds x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: subs w11, w11, #1
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
@@ -826,6 +831,7 @@ define dso_local i64 @atomicrmw_add_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_add_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_monotonic:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -840,6 +846,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_add_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_acquire:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -854,6 +861,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_release:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -868,6 +876,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_acq_rel:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -882,6 +891,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_seq_cst:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1036,6 +1046,7 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_sub_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_monotonic:
; -O0: subs x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: casp x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
@@ -1055,6 +1066,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_acquire:
; -O0: subs x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: caspa x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
@@ -1074,6 +1086,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_release:
; -O0: subs x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: caspl x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
@@ -1093,6 +1106,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_acq_rel:
; -O0: subs x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
@@ -1112,6 +1126,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_seq_cst:
; -O0: subs x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
@@ -1346,6 +1361,7 @@ define dso_local i64 @atomicrmw_sub_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_sub_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_monotonic:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_monotonic:
@@ -1359,6 +1375,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_sub_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_acquire:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_acquire:
@@ -1372,6 +1389,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_release:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_release:
@@ -1385,6 +1403,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_acq_rel:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_acq_rel:
@@ -1398,6 +1417,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_seq_cst:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_seq_cst:
@@ -3931,11 +3951,15 @@ define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_monotonic:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: casp x0, x1, x2, x3, [x8]
@@ -3959,11 +3983,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acquire:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspa x0, x1, x2, x3, [x8]
@@ -3987,11 +4015,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_release:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspl x0, x1, x2, x3, [x8]
@@ -4015,11 +4047,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acq_rel:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -4043,11 +4079,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_seq_cst:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -4107,7 +4147,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0-LABEL: atomicrmw_max_i16_unaligned_monotonic:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
@@ -4123,7 +4165,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_acquire:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
@@ -4139,7 +4183,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_release:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
@@ -4155,7 +4201,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
@@ -4171,7 +4219,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
@@ -4186,7 +4236,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_monotonic:
@@ -4200,7 +4252,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_max_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_acquire:
@@ -4214,7 +4268,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_release:
@@ -4228,7 +4284,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_acq_rel:
@@ -4242,7 +4300,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_seq_cst:
@@ -4256,7 +4316,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_monotonic:
@@ -4270,7 +4332,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_max_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_acquire:
@@ -4284,7 +4348,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_release:
@@ -4298,7 +4364,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_acq_rel:
@@ -4312,7 +4380,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_seq_cst:
@@ -4326,11 +4396,15 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -4348,11 +4422,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -4370,11 +4448,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -4392,11 +4474,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -4414,11 +4500,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -4576,11 +4666,15 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: casp x0, x1, x2, x3, [x8]
@@ -4604,11 +4698,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspa x0, x1, x2, x3, [x8]
@@ -4632,11 +4730,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspl x0, x1, x2, x3, [x8]
@@ -4660,11 +4762,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -4688,11 +4794,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -4752,7 +4862,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0-LABEL: atomicrmw_min_i16_unaligned_monotonic:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
@@ -4768,7 +4880,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_acquire:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
@@ -4784,7 +4898,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_release:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
@@ -4800,7 +4916,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
@@ -4816,7 +4934,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
@@ -4831,7 +4951,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
@@ -4845,7 +4967,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
@@ -4859,7 +4983,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
@@ -4873,7 +4999,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
@@ -4887,7 +5015,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
@@ -4901,7 +5031,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
@@ -4915,7 +5047,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
@@ -4929,7 +5063,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
@@ -4943,7 +5079,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
@@ -4957,7 +5095,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
@@ -4971,11 +5111,15 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -4993,11 +5137,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5015,11 +5163,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5037,11 +5189,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5059,11 +5215,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5221,11 +5381,15 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_monotonic:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: casp x0, x1, x2, x3, [x8]
@@ -5249,11 +5413,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acquire:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspa x0, x1, x2, x3, [x8]
@@ -5277,11 +5445,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_release:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspl x0, x1, x2, x3, [x8]
@@ -5305,11 +5477,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acq_rel:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -5333,11 +5509,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_seq_cst:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -5396,7 +5576,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
@@ -5411,7 +5593,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acquire:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
@@ -5426,7 +5610,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_release:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
@@ -5441,7 +5627,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
@@ -5456,7 +5644,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
@@ -5471,7 +5661,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_monotonic:
@@ -5485,7 +5677,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umax_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_acquire:
@@ -5499,7 +5693,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_release:
@@ -5513,7 +5709,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_acq_rel:
@@ -5527,7 +5725,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_seq_cst:
@@ -5541,7 +5741,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_monotonic:
@@ -5555,7 +5757,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umax_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_acquire:
@@ -5569,7 +5773,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_release:
@@ -5583,7 +5789,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_acq_rel:
@@ -5597,7 +5805,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_seq_cst:
@@ -5611,11 +5821,15 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5633,11 +5847,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5655,11 +5873,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5677,11 +5899,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5699,11 +5925,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5861,11 +6091,15 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: casp x0, x1, x2, x3, [x8]
@@ -5889,11 +6123,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspa x0, x1, x2, x3, [x8]
@@ -5917,11 +6155,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspl x0, x1, x2, x3, [x8]
@@ -5945,11 +6187,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -5973,11 +6219,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -6036,7 +6286,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
@@ -6051,7 +6303,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acquire:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
@@ -6066,7 +6320,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_release:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
@@ -6081,7 +6337,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
@@ -6096,7 +6354,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
@@ -6111,7 +6371,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
@@ -6125,7 +6387,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
@@ -6139,7 +6403,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
@@ -6153,7 +6419,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
@@ -6167,7 +6435,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
@@ -6181,7 +6451,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
@@ -6195,7 +6467,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
@@ -6209,7 +6483,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
@@ -6223,7 +6499,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
@@ -6237,7 +6515,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
@@ -6251,11 +6531,15 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6273,11 +6557,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6295,11 +6583,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6317,11 +6609,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6339,11 +6635,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
index c660c139e35d44c..89d22c59e630b42 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
@@ -556,6 +556,7 @@ define dso_local i64 @atomicrmw_add_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_add_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_monotonic:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -578,6 +579,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_acquire:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -600,6 +602,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_release:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -622,6 +625,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_acq_rel:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -644,6 +648,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_seq_cst:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -881,6 +886,7 @@ define dso_local i64 @atomicrmw_add_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_add_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_monotonic:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -895,6 +901,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_add_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_acquire:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -909,6 +916,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_release:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -923,6 +931,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_acq_rel:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -937,6 +946,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_seq_cst:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1171,6 +1181,7 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_sub_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_monotonic:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1192,6 +1203,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_acquire:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1213,6 +1225,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_release:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1234,6 +1247,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_acq_rel:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1255,6 +1269,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_seq_cst:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1511,6 +1526,7 @@ define dso_local i64 @atomicrmw_sub_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_sub_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_monotonic:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_monotonic:
@@ -1524,6 +1540,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_sub_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_acquire:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_acquire:
@@ -1537,6 +1554,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_release:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_release:
@@ -1550,6 +1568,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_acq_rel:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_acq_rel:
@@ -1563,6 +1582,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_seq_cst:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_seq_cst:
@@ -4237,7 +4257,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -4258,7 +4280,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -4279,7 +4303,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -4300,7 +4326,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -4321,7 +4349,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -4342,7 +4372,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_aligned_monotonic:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -4362,7 +4394,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acquire:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -4382,7 +4416,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_release:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -4402,7 +4438,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acq_rel:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -4422,7 +4460,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_seq_cst:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -4441,7 +4481,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -4459,7 +4501,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -4477,7 +4521,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -4495,7 +4541,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -4513,7 +4561,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -4531,7 +4581,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -4549,7 +4601,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -4567,7 +4621,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -4585,7 +4641,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -4603,7 +4661,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -4621,11 +4681,15 @@ define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -4651,11 +4715,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -4681,11 +4749,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -4711,11 +4783,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -4741,11 +4817,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -4772,7 +4852,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -4793,7 +4875,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -4814,7 +4898,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -4835,7 +4921,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -4856,7 +4944,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -4877,7 +4967,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0-LABEL: atomicrmw_max_i16_unaligned_monotonic:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
@@ -4893,7 +4985,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_acquire:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
@@ -4909,7 +5003,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_release:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
@@ -4925,7 +5021,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
@@ -4941,7 +5039,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
@@ -4956,7 +5056,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_monotonic:
@@ -4970,7 +5072,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_max_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_acquire:
@@ -4984,7 +5088,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_release:
@@ -4998,7 +5104,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_acq_rel:
@@ -5012,7 +5120,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_seq_cst:
@@ -5026,7 +5136,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_monotonic:
@@ -5040,7 +5152,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_max_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_acquire:
@@ -5054,7 +5168,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_release:
@@ -5068,7 +5184,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_acq_rel:
@@ -5082,7 +5200,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_seq_cst:
@@ -5096,11 +5216,15 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5118,11 +5242,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5140,11 +5268,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5162,11 +5294,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5184,11 +5320,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5207,7 +5347,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5228,7 +5370,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5249,7 +5393,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5270,7 +5416,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5291,7 +5439,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5312,7 +5462,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_aligned_monotonic:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5332,7 +5484,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acquire:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5352,7 +5506,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_release:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5372,7 +5528,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acq_rel:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5392,7 +5550,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_seq_cst:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5411,7 +5571,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5429,7 +5591,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5447,7 +5611,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5465,7 +5631,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5483,7 +5651,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5501,7 +5671,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5519,7 +5691,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5537,7 +5711,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5555,7 +5731,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5573,7 +5751,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5591,11 +5771,15 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -5621,11 +5805,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -5651,11 +5839,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -5681,11 +5873,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -5711,11 +5907,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -5742,7 +5942,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5763,7 +5965,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5784,7 +5988,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5805,7 +6011,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5826,7 +6034,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5847,7 +6057,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0-LABEL: atomicrmw_min_i16_unaligned_monotonic:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
@@ -5863,7 +6075,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_acquire:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
@@ -5879,7 +6093,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_release:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
@@ -5895,7 +6111,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
@@ -5911,7 +6129,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
@@ -5926,7 +6146,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
@@ -5940,7 +6162,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
@@ -5954,7 +6178,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
@@ -5968,7 +6194,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
@@ -5982,7 +6210,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
@@ -5996,7 +6226,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
@@ -6010,7 +6242,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
@@ -6024,7 +6258,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
@@ -6038,7 +6274,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
@@ -6052,7 +6290,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
@@ -6066,11 +6306,15 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6088,11 +6332,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6110,11 +6358,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6132,11 +6384,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6154,11 +6410,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6177,7 +6437,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6198,7 +6460,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6219,7 +6483,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6240,7 +6506,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6261,7 +6529,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6281,7 +6551,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_monotonic:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6300,7 +6572,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acquire:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6319,7 +6593,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_release:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6338,7 +6614,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6357,7 +6635,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6376,7 +6656,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6394,7 +6676,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6412,7 +6696,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6430,7 +6716,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6448,7 +6736,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6466,7 +6756,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6484,7 +6776,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6502,7 +6796,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6520,7 +6816,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6538,7 +6836,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6556,11 +6856,15 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -6586,11 +6890,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -6616,11 +6924,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -6646,11 +6958,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -6676,11 +6992,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -6707,7 +7027,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O0-LABEL: atomicrmw_umax_i8_unaligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6728,7 +7050,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6749,7 +7073,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6770,7 +7096,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6791,7 +7119,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6811,7 +7141,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
@@ -6826,7 +7158,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acquire:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
@@ -6841,7 +7175,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_release:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
@@ -6856,7 +7192,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
@@ -6871,7 +7209,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
@@ -6886,7 +7226,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_monotonic:
@@ -6900,7 +7242,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umax_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_acquire:
@@ -6914,7 +7258,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_release:
@@ -6928,7 +7274,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_acq_rel:
@@ -6942,7 +7290,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_seq_cst:
@@ -6956,7 +7306,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_monotonic:
@@ -6970,7 +7322,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umax_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_acquire:
@@ -6984,7 +7338,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_release:
@@ -6998,7 +7354,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_acq_rel:
@@ -7012,7 +7370,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_seq_cst:
@@ -7026,11 +7386,15 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7048,11 +7412,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7070,11 +7438,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7092,11 +7464,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7114,11 +7490,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7137,7 +7517,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7158,7 +7540,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7179,7 +7563,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7200,7 +7586,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7221,7 +7609,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7241,7 +7631,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_monotonic:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7260,7 +7652,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acquire:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7279,7 +7673,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_release:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7298,7 +7694,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7317,7 +7715,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7336,7 +7736,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7354,7 +7756,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7372,7 +7776,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7390,7 +7796,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7408,7 +7816,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7426,7 +7836,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7444,7 +7856,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7462,7 +7876,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7480,7 +7896,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7498,7 +7916,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7516,11 +7936,15 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -7546,11 +7970,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -7576,11 +8004,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -7606,11 +8038,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -7636,11 +8072,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -7667,7 +8107,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O0-LABEL: atomicrmw_umin_i8_unaligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7688,7 +8130,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7709,7 +8153,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7730,7 +8176,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7751,7 +8199,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7771,7 +8221,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
@@ -7786,7 +8238,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acquire:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
@@ -7801,7 +8255,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_release:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
@@ -7816,7 +8272,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
@@ -7831,7 +8289,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
@@ -7846,7 +8306,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
@@ -7860,7 +8322,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
@@ -7874,7 +8338,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
@@ -7888,7 +8354,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
@@ -7902,7 +8370,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
@@ -7916,7 +8386,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
@@ -7930,7 +8402,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
@@ -7944,7 +8418,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
@@ -7958,7 +8434,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
@@ -7972,7 +8450,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
@@ -7986,11 +8466,15 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8008,11 +8492,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8030,11 +8518,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8052,11 +8544,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8074,11 +8570,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
index 4f9e520997a22f0..bb6163f5bc38754 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
@@ -926,6 +926,7 @@ define dso_local i64 @atomicrmw_add_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_add_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_monotonic:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -948,6 +949,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_acquire:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -970,6 +972,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_release:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -992,6 +995,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_acq_rel:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -1014,6 +1018,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_seq_cst:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -1301,6 +1306,7 @@ define dso_local i64 @atomicrmw_add_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_add_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_monotonic:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1315,6 +1321,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_add_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_acquire:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1329,6 +1336,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_release:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1343,6 +1351,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_acq_rel:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1357,6 +1366,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_seq_cst:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1696,6 +1706,7 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_sub_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_monotonic:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1717,6 +1728,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_acquire:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1738,6 +1750,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_release:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1759,6 +1772,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_acq_rel:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1780,6 +1794,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_seq_cst:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -2066,6 +2081,7 @@ define dso_local i64 @atomicrmw_sub_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_sub_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_monotonic:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_monotonic:
@@ -2079,6 +2095,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_sub_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_acquire:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_acquire:
@@ -2092,6 +2109,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_release:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_release:
@@ -2105,6 +2123,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_acq_rel:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_acq_rel:
@@ -2118,6 +2137,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_seq_cst:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_seq_cst:
@@ -5372,7 +5392,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5393,7 +5415,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5414,7 +5438,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5435,7 +5461,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5456,7 +5484,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5477,7 +5507,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_aligned_monotonic:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5497,7 +5529,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acquire:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5517,7 +5551,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_release:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5537,7 +5573,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acq_rel:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5557,7 +5595,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_seq_cst:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5576,7 +5616,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5594,7 +5636,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5612,7 +5656,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5630,7 +5676,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5648,7 +5696,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5666,7 +5716,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5684,7 +5736,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5702,7 +5756,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5720,7 +5776,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5738,7 +5796,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5756,11 +5816,15 @@ define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -5786,11 +5850,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -5816,11 +5884,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -5846,11 +5918,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -5876,11 +5952,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -5907,7 +5987,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5928,7 +6010,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5949,7 +6033,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5970,7 +6056,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5991,7 +6079,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6012,7 +6102,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0-LABEL: atomicrmw_max_i16_unaligned_monotonic:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
@@ -6028,7 +6120,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_acquire:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
@@ -6044,7 +6138,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_release:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
@@ -6060,7 +6156,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
@@ -6076,7 +6174,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
@@ -6091,7 +6191,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_monotonic:
@@ -6105,7 +6207,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_max_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_acquire:
@@ -6119,7 +6223,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_release:
@@ -6133,7 +6239,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_acq_rel:
@@ -6147,7 +6255,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_seq_cst:
@@ -6161,7 +6271,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_monotonic:
@@ -6175,7 +6287,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_max_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_acquire:
@@ -6189,7 +6303,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_release:
@@ -6203,7 +6319,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_acq_rel:
@@ -6217,7 +6335,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_seq_cst:
@@ -6231,11 +6351,15 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6253,11 +6377,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6275,11 +6403,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6297,11 +6429,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6319,11 +6455,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6342,7 +6482,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6363,7 +6505,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6384,7 +6528,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6405,7 +6551,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6426,7 +6574,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6447,7 +6597,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_aligned_monotonic:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6467,7 +6619,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acquire:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6487,7 +6641,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_release:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6507,7 +6663,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acq_rel:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6527,7 +6685,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_seq_cst:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6546,7 +6706,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6564,7 +6726,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6582,7 +6746,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6600,7 +6766,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6618,7 +6786,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6636,7 +6806,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6654,7 +6826,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6672,7 +6846,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6690,7 +6866,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6708,7 +6886,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6726,11 +6906,15 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -6756,11 +6940,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -6786,11 +6974,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -6816,11 +7008,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -6846,11 +7042,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -6877,7 +7077,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6898,7 +7100,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6919,7 +7123,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6940,7 +7146,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6961,7 +7169,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6982,7 +7192,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0-LABEL: atomicrmw_min_i16_unaligned_monotonic:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
@@ -6998,7 +7210,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_acquire:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
@@ -7014,7 +7228,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_release:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
@@ -7030,7 +7246,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
@@ -7046,7 +7264,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
@@ -7061,7 +7281,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
@@ -7075,7 +7297,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
@@ -7089,7 +7313,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
@@ -7103,7 +7329,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
@@ -7117,7 +7345,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
@@ -7131,7 +7361,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
@@ -7145,7 +7377,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
@@ -7159,7 +7393,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
@@ -7173,7 +7409,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
@@ -7187,7 +7425,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
@@ -7201,11 +7441,15 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7223,11 +7467,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7245,11 +7493,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7267,11 +7519,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7289,11 +7545,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7312,7 +7572,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7333,7 +7595,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7354,7 +7618,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7375,7 +7641,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7396,7 +7664,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7416,7 +7686,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_monotonic:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7435,7 +7707,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acquire:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7454,7 +7728,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_release:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7473,7 +7749,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7492,7 +7770,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7511,7 +7791,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7529,7 +7811,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7547,7 +7831,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7565,7 +7851,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7583,7 +7871,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7601,7 +7891,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7619,7 +7911,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7637,7 +7931,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7655,7 +7951,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7673,7 +7971,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7691,11 +7991,15 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -7721,11 +8025,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -7751,11 +8059,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -7781,11 +8093,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -7811,11 +8127,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -7842,7 +8162,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O0-LABEL: atomicrmw_umax_i8_unaligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7863,7 +8185,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7884,7 +8208,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7905,7 +8231,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7926,7 +8254,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7946,7 +8276,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
@@ -7961,7 +8293,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acquire:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
@@ -7976,7 +8310,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_release:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
@@ -7991,7 +8327,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
@@ -8006,7 +8344,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
@@ -8021,7 +8361,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_monotonic:
@@ -8035,7 +8377,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umax_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_acquire:
@@ -8049,7 +8393,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_release:
@@ -8063,7 +8409,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_acq_rel:
@@ -8077,7 +8425,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_seq_cst:
@@ -8091,7 +8441,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_monotonic:
@@ -8105,7 +8457,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umax_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_acquire:
@@ -8119,7 +8473,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_release:
@@ -8133,7 +8489,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_acq_rel:
@@ -8147,7 +8505,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_seq_cst:
@@ -8161,11 +8521,15 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8183,11 +8547,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8205,11 +8573,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8227,11 +8599,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8249,11 +8625,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8272,7 +8652,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8293,7 +8675,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8314,7 +8698,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8335,7 +8721,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8356,7 +8744,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8376,7 +8766,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_monotonic:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8395,7 +8787,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acquire:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8414,7 +8808,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_release:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8433,7 +8829,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8452,7 +8850,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8471,7 +8871,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8489,7 +8891,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8507,7 +8911,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8525,7 +8931,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8543,7 +8951,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8561,7 +8971,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8579,7 +8991,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8597,7 +9011,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8615,7 +9031,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8633,7 +9051,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8651,11 +9071,15 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -8681,11 +9105,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -8711,11 +9139,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -8741,11 +9173,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -8771,11 +9207,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -8802,7 +9242,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O0-LABEL: atomicrmw_umin_i8_unaligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8823,7 +9265,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8844,7 +9288,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8865,7 +9311,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8886,7 +9334,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8906,7 +9356,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
@@ -8921,7 +9373,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acquire:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
@@ -8936,7 +9390,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_release:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
@@ -8951,7 +9407,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
@@ -8966,7 +9424,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
@@ -8981,7 +9441,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
@@ -8995,7 +9457,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
@@ -9009,7 +9473,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
@@ -9023,7 +9489,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
@@ -9037,7 +9505,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
@@ -9051,7 +9521,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
@@ -9065,7 +9537,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
@@ -9079,7 +9553,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
@@ -9093,7 +9569,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
@@ -9107,7 +9585,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
@@ -9121,11 +9601,15 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9143,11 +9627,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9165,11 +9653,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9187,11 +9679,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9209,11 +9705,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
index 3437ccc8be40d70..635620bb5ae11b1 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
@@ -926,6 +926,7 @@ define dso_local i64 @atomicrmw_add_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_add_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_monotonic:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -948,6 +949,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_acquire:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -970,6 +972,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_release:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -992,6 +995,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_acq_rel:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -1014,6 +1018,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_seq_cst:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -1301,6 +1306,7 @@ define dso_local i64 @atomicrmw_add_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_add_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_monotonic:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1315,6 +1321,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_add_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_acquire:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1329,6 +1336,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_release:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1343,6 +1351,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_acq_rel:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1357,6 +1366,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_seq_cst:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1696,6 +1706,7 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_sub_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_monotonic:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1717,6 +1728,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_acquire:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1738,6 +1750,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_release:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1759,6 +1772,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_acq_rel:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1780,6 +1794,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_seq_cst:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -2066,6 +2081,7 @@ define dso_local i64 @atomicrmw_sub_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_sub_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_monotonic:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_monotonic:
@@ -2079,6 +2095,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_sub_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_acquire:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_acquire:
@@ -2092,6 +2109,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_release:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_release:
@@ -2105,6 +2123,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_acq_rel:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_acq_rel:
@@ -2118,6 +2137,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_seq_cst:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_seq_cst:
@@ -5372,7 +5392,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5393,7 +5415,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5414,7 +5438,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5435,7 +5461,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5456,7 +5484,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5477,7 +5507,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_aligned_monotonic:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5497,7 +5529,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acquire:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5517,7 +5551,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_release:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5537,7 +5573,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acq_rel:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5557,7 +5595,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_seq_cst:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5576,7 +5616,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5594,7 +5636,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5612,7 +5656,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5630,7 +5676,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5648,7 +5696,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5666,7 +5716,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5684,7 +5736,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5702,7 +5756,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5720,7 +5776,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5738,7 +5796,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5756,11 +5816,15 @@ define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -5786,11 +5850,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -5816,11 +5884,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -5846,11 +5918,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -5876,11 +5952,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -5907,7 +5987,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5928,7 +6010,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5949,7 +6033,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5970,7 +6056,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5991,7 +6079,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6012,7 +6102,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0-LABEL: atomicrmw_max_i16_unaligned_monotonic:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
@@ -6028,7 +6120,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_acquire:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
@@ -6044,7 +6138,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_release:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
@@ -6060,7 +6156,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
@@ -6076,7 +6174,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
@@ -6091,7 +6191,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_monotonic:
@@ -6105,7 +6207,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_max_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_acquire:
@@ -6119,7 +6223,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_release:
@@ -6133,7 +6239,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_acq_rel:
@@ -6147,7 +6255,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_seq_cst:
@@ -6161,7 +6271,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_monotonic:
@@ -6175,7 +6287,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_max_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_acquire:
@@ -6189,7 +6303,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_release:
@@ -6203,7 +6319,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_acq_rel:
@@ -6217,7 +6335,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_seq_cst:
@@ -6231,11 +6351,15 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6253,11 +6377,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6275,11 +6403,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6297,11 +6429,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6319,11 +6455,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6342,7 +6482,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6363,7 +6505,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6384,7 +6528,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6405,7 +6551,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6426,7 +6574,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6447,7 +6597,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_aligned_monotonic:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6467,7 +6619,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acquire:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6487,7 +6641,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_release:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6507,7 +6663,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acq_rel:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6527,7 +6685,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_seq_cst:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6546,7 +6706,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6564,7 +6726,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6582,7 +6746,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6600,7 +6766,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6618,7 +6786,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6636,7 +6806,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6654,7 +6826,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6672,7 +6846,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6690,7 +6866,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6708,7 +6886,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6726,11 +6906,15 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -6756,11 +6940,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -6786,11 +6974,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -6816,11 +7008,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -6846,11 +7042,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -6877,7 +7077,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6898,7 +7100,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6919,7 +7123,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6940,7 +7146,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6961,7 +7169,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6982,7 +7192,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0-LABEL: atomicrmw_min_i16_unaligned_monotonic:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
@@ -6998,7 +7210,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_acquire:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
@@ -7014,7 +7228,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_release:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
@@ -7030,7 +7246,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
@@ -7046,7 +7264,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
@@ -7061,7 +7281,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
@@ -7075,7 +7297,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
@@ -7089,7 +7313,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
@@ -7103,7 +7329,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
@@ -7117,7 +7345,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
@@ -7131,7 +7361,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
@@ -7145,7 +7377,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
@@ -7159,7 +7393,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
@@ -7173,7 +7409,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
@@ -7187,7 +7425,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
@@ -7201,11 +7441,15 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7223,11 +7467,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7245,11 +7493,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7267,11 +7519,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7289,11 +7545,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7312,7 +7572,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7333,7 +7595,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7354,7 +7618,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7375,7 +7641,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7396,7 +7664,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7416,7 +7686,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_monotonic:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7435,7 +7707,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acquire:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7454,7 +7728,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_release:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7473,7 +7749,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7492,7 +7770,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7511,7 +7791,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7529,7 +7811,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7547,7 +7831,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7565,7 +7851,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7583,7 +7871,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7601,7 +7891,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7619,7 +7911,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7637,7 +7931,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7655,7 +7951,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7673,7 +7971,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7691,11 +7991,15 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -7721,11 +8025,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -7751,11 +8059,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -7781,11 +8093,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -7811,11 +8127,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -7842,7 +8162,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O0-LABEL: atomicrmw_umax_i8_unaligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7863,7 +8185,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7884,7 +8208,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7905,7 +8231,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7926,7 +8254,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7946,7 +8276,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
@@ -7961,7 +8293,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acquire:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
@@ -7976,7 +8310,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_release:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
@@ -7991,7 +8327,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
@@ -8006,7 +8344,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
@@ -8021,7 +8361,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_monotonic:
@@ -8035,7 +8377,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umax_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_acquire:
@@ -8049,7 +8393,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_release:
@@ -8063,7 +8409,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_acq_rel:
@@ -8077,7 +8425,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_seq_cst:
@@ -8091,7 +8441,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_monotonic:
@@ -8105,7 +8457,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umax_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_acquire:
@@ -8119,7 +8473,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_release:
@@ -8133,7 +8489,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_acq_rel:
@@ -8147,7 +8505,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_seq_cst:
@@ -8161,11 +8521,15 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8183,11 +8547,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8205,11 +8573,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8227,11 +8599,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8249,11 +8625,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8272,7 +8652,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8293,7 +8675,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8314,7 +8698,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8335,7 +8721,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8356,7 +8744,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8376,7 +8766,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_monotonic:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8395,7 +8787,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acquire:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8414,7 +8808,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_release:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8433,7 +8829,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8452,7 +8850,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8471,7 +8871,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8489,7 +8891,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8507,7 +8911,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8525,7 +8931,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8543,7 +8951,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8561,7 +8971,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8579,7 +8991,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8597,7 +9011,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8615,7 +9031,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8633,7 +9051,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8651,11 +9071,15 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -8681,11 +9105,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -8711,11 +9139,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -8741,11 +9173,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -8771,11 +9207,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -8802,7 +9242,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O0-LABEL: atomicrmw_umin_i8_unaligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8823,7 +9265,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8844,7 +9288,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8865,7 +9311,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8886,7 +9334,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8906,7 +9356,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
@@ -8921,7 +9373,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acquire:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
@@ -8936,7 +9390,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_release:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
@@ -8951,7 +9407,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
@@ -8966,7 +9424,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
@@ -8981,7 +9441,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
@@ -8995,7 +9457,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
@@ -9009,7 +9473,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
@@ -9023,7 +9489,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
@@ -9037,7 +9505,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
@@ -9051,7 +9521,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
@@ -9065,7 +9537,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
@@ -9079,7 +9553,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
@@ -9093,7 +9569,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
@@ -9107,7 +9585,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
@@ -9121,11 +9601,15 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9143,11 +9627,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9165,11 +9653,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9187,11 +9679,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9209,11 +9705,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
index ee5fbe39b4492cd..7fc733a13bf07f9 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
@@ -546,6 +546,7 @@ define dso_local i64 @atomicrmw_add_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_add_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_monotonic:
; -O0: adds x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: subs w11, w11, #1
; -O0: casp x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
@@ -566,6 +567,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_acquire:
; -O0: adds x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: subs w11, w11, #1
; -O0: caspa x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
@@ -586,6 +588,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_release:
; -O0: adds x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: subs w11, w11, #1
; -O0: caspl x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
@@ -606,6 +609,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_acq_rel:
; -O0: adds x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: subs w11, w11, #1
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
@@ -626,6 +630,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_seq_cst:
; -O0: adds x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: subs w11, w11, #1
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
@@ -861,6 +866,7 @@ define dso_local i64 @atomicrmw_add_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_add_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_monotonic:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -875,6 +881,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_add_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_acquire:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -889,6 +896,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_release:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -903,6 +911,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_acq_rel:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -917,6 +926,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_seq_cst:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1071,6 +1081,7 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_sub_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_monotonic:
; -O0: subs x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: casp x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
@@ -1090,6 +1101,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_acquire:
; -O0: subs x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: caspa x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
@@ -1109,6 +1121,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_release:
; -O0: subs x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: caspl x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
@@ -1128,6 +1141,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_acq_rel:
; -O0: subs x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
@@ -1147,6 +1161,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_seq_cst:
; -O0: subs x2, x9, x11
+; -O0: and w11, w9, #0x1
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: eor x8, x10, x8
; -O0: eor x11, x9, x11
@@ -1381,6 +1396,7 @@ define dso_local i64 @atomicrmw_sub_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_sub_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_monotonic:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_monotonic:
@@ -1394,6 +1410,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_sub_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_acquire:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_acquire:
@@ -1407,6 +1424,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_release:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_release:
@@ -1420,6 +1438,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_acq_rel:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_acq_rel:
@@ -1433,6 +1452,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_seq_cst:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_seq_cst:
@@ -4056,11 +4076,15 @@ define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_monotonic:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: casp x0, x1, x2, x3, [x8]
@@ -4084,11 +4108,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acquire:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspa x0, x1, x2, x3, [x8]
@@ -4112,11 +4140,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_release:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspl x0, x1, x2, x3, [x8]
@@ -4140,11 +4172,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acq_rel:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -4168,11 +4204,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_seq_cst:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -4232,7 +4272,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0-LABEL: atomicrmw_max_i16_unaligned_monotonic:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
@@ -4248,7 +4290,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_acquire:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
@@ -4264,7 +4308,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_release:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
@@ -4280,7 +4326,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
@@ -4296,7 +4344,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
@@ -4311,7 +4361,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_monotonic:
@@ -4325,7 +4377,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_max_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_acquire:
@@ -4339,7 +4393,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_release:
@@ -4353,7 +4409,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_acq_rel:
@@ -4367,7 +4425,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_seq_cst:
@@ -4381,7 +4441,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_monotonic:
@@ -4395,7 +4457,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_max_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_acquire:
@@ -4409,7 +4473,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_release:
@@ -4423,7 +4489,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_acq_rel:
@@ -4437,7 +4505,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_seq_cst:
@@ -4451,11 +4521,15 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -4473,11 +4547,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -4495,11 +4573,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -4517,11 +4599,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -4539,11 +4625,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -4701,11 +4791,15 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: casp x0, x1, x2, x3, [x8]
@@ -4729,11 +4823,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspa x0, x1, x2, x3, [x8]
@@ -4757,11 +4855,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspl x0, x1, x2, x3, [x8]
@@ -4785,11 +4887,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -4813,11 +4919,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -4877,7 +4987,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0-LABEL: atomicrmw_min_i16_unaligned_monotonic:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
@@ -4893,7 +5005,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_acquire:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
@@ -4909,7 +5023,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_release:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
@@ -4925,7 +5041,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
@@ -4941,7 +5059,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
@@ -4956,7 +5076,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
@@ -4970,7 +5092,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
@@ -4984,7 +5108,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
@@ -4998,7 +5124,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
@@ -5012,7 +5140,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
@@ -5026,7 +5156,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
@@ -5040,7 +5172,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
@@ -5054,7 +5188,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
@@ -5068,7 +5204,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
@@ -5082,7 +5220,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
@@ -5096,11 +5236,15 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5118,11 +5262,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5140,11 +5288,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5162,11 +5314,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5184,11 +5340,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5346,11 +5506,15 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_monotonic:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: casp x0, x1, x2, x3, [x8]
@@ -5374,11 +5538,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acquire:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspa x0, x1, x2, x3, [x8]
@@ -5402,11 +5570,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_release:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspl x0, x1, x2, x3, [x8]
@@ -5430,11 +5602,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acq_rel:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -5458,11 +5634,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_seq_cst:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -5521,7 +5701,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
@@ -5536,7 +5718,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acquire:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
@@ -5551,7 +5735,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_release:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
@@ -5566,7 +5752,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
@@ -5581,7 +5769,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
@@ -5596,7 +5786,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_monotonic:
@@ -5610,7 +5802,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umax_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_acquire:
@@ -5624,7 +5818,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_release:
@@ -5638,7 +5834,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_acq_rel:
@@ -5652,7 +5850,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_seq_cst:
@@ -5666,7 +5866,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_monotonic:
@@ -5680,7 +5882,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umax_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_acquire:
@@ -5694,7 +5898,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_release:
@@ -5708,7 +5914,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_acq_rel:
@@ -5722,7 +5930,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_seq_cst:
@@ -5736,11 +5946,15 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5758,11 +5972,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5780,11 +5998,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5802,11 +6024,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5824,11 +6050,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -5986,11 +6216,15 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: casp x0, x1, x2, x3, [x8]
@@ -6014,11 +6248,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspa x0, x1, x2, x3, [x8]
@@ -6042,11 +6280,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspl x0, x1, x2, x3, [x8]
@@ -6070,11 +6312,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -6098,11 +6344,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O0: subs x9, x9, x10
+; -O0: subs x9, x9, x10
; -O0: subs x9, x9, x12
-; -O0: subs x13, x13, x10
-; -O0: csel w11, w9, w11, eq
-; -O0: ands w13, w11, #0x1
-; -O0: csel x2, x9, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w9, w9, w11, ne
+; -O0: and w13, w9, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x2, x11, x12, ne
+; -O0: and w11, w9, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x9, x9, x10, ne
; -O0: caspal x0, x1, x2, x3, [x8]
@@ -6161,7 +6411,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
@@ -6176,7 +6428,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acquire:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
@@ -6191,7 +6445,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_release:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
@@ -6206,7 +6462,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
@@ -6221,7 +6479,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
@@ -6236,7 +6496,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
@@ -6250,7 +6512,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
@@ -6264,7 +6528,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
@@ -6278,7 +6544,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
@@ -6292,7 +6560,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
@@ -6306,7 +6576,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
@@ -6320,7 +6592,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
@@ -6334,7 +6608,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
@@ -6348,7 +6624,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
@@ -6362,7 +6640,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
@@ -6376,11 +6656,15 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6398,11 +6682,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6420,11 +6708,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6442,11 +6734,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6464,11 +6760,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
index 2473147509dc874..0ea04d18788f689 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
@@ -926,6 +926,7 @@ define dso_local i64 @atomicrmw_add_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_add_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_monotonic:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -948,6 +949,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_acquire:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -970,6 +972,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_release:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -992,6 +995,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_acq_rel:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -1014,6 +1018,7 @@ define dso_local i128 @atomicrmw_add_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_add_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_aligned_seq_cst:
; -O0: adds x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: subs w10, w10, #1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
@@ -1301,6 +1306,7 @@ define dso_local i64 @atomicrmw_add_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_add_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_monotonic:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1315,6 +1321,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_add_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_acquire:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1329,6 +1336,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_release:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1343,6 +1351,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_acq_rel:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1357,6 +1366,7 @@ define dso_local i128 @atomicrmw_add_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_add_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_add_i128_unaligned_seq_cst:
; -O0: adds x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: subs w11, w11, #1
; -O0: bl __atomic_compare_exchange
;
@@ -1696,6 +1706,7 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_sub_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_monotonic:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1717,6 +1728,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_acquire:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1738,6 +1750,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_release:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1759,6 +1772,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_acq_rel:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -1780,6 +1794,7 @@ define dso_local i128 @atomicrmw_sub_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_sub_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_aligned_seq_cst:
; -O0: subs x14, x8, x10
+; -O0: and w10, w8, #0x1
; -O0: ldaxp x10, x9, [x11]
; -O0: cmp x10, x12
; -O0: cmp x9, x13
@@ -2066,6 +2081,7 @@ define dso_local i64 @atomicrmw_sub_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_sub_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_monotonic:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_monotonic:
@@ -2079,6 +2095,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_sub_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_acquire:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_acquire:
@@ -2092,6 +2109,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_release:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_release:
@@ -2105,6 +2123,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_acq_rel:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_acq_rel:
@@ -2118,6 +2137,7 @@ define dso_local i128 @atomicrmw_sub_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_sub_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_sub_i128_unaligned_seq_cst:
; -O0: subs x9, x8, x9
+; -O0: and w11, w8, #0x1
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_sub_i128_unaligned_seq_cst:
@@ -5372,7 +5392,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5393,7 +5415,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5414,7 +5438,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5435,7 +5461,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5456,7 +5484,9 @@ define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5477,7 +5507,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_aligned_monotonic:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5497,7 +5529,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acquire:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5517,7 +5551,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_release:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5537,7 +5573,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acq_rel:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5557,7 +5595,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_seq_cst:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -5576,7 +5616,9 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5594,7 +5636,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5612,7 +5656,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5630,7 +5676,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5648,7 +5696,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -5666,7 +5716,9 @@ define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5684,7 +5736,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5702,7 +5756,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5720,7 +5776,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5738,7 +5796,9 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -5756,11 +5816,15 @@ define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -5786,11 +5850,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -5816,11 +5884,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -5846,11 +5918,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -5876,11 +5952,15 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -5907,7 +5987,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5928,7 +6010,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5949,7 +6033,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5970,7 +6056,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -5991,7 +6079,9 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, gt
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6012,7 +6102,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0-LABEL: atomicrmw_max_i16_unaligned_monotonic:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
@@ -6028,7 +6120,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_acquire:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
@@ -6044,7 +6138,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_release:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
@@ -6060,7 +6156,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
@@ -6076,7 +6174,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
@@ -6091,7 +6191,9 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_monotonic:
@@ -6105,7 +6207,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_max_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_acquire:
@@ -6119,7 +6223,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_release:
@@ -6133,7 +6239,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_acq_rel:
@@ -6147,7 +6255,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i32_unaligned_seq_cst:
@@ -6161,7 +6271,9 @@ define dso_local i32 @atomicrmw_max_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_monotonic:
@@ -6175,7 +6287,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_max_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_acquire:
@@ -6189,7 +6303,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_release:
@@ -6203,7 +6319,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_acq_rel:
@@ -6217,7 +6335,9 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, gt
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i64_unaligned_seq_cst:
@@ -6231,11 +6351,15 @@ define dso_local i64 @atomicrmw_max_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6253,11 +6377,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6275,11 +6403,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6297,11 +6429,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6319,11 +6455,15 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_max_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -6342,7 +6482,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6363,7 +6505,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6384,7 +6528,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6405,7 +6551,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6426,7 +6574,9 @@ define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6447,7 +6597,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_aligned_monotonic:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6467,7 +6619,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acquire:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6487,7 +6641,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_release:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6507,7 +6663,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acq_rel:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6527,7 +6685,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_seq_cst:
; -O0: sxth w10, w8
; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -6546,7 +6706,9 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6564,7 +6726,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6582,7 +6746,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6600,7 +6766,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6618,7 +6786,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -6636,7 +6806,9 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6654,7 +6826,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6672,7 +6846,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6690,7 +6866,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6708,7 +6886,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -6726,11 +6906,15 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -6756,11 +6940,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -6786,11 +6974,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -6816,11 +7008,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -6846,11 +7042,15 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -6877,7 +7077,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_monotonic:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6898,7 +7100,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acquire:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6919,7 +7123,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_release:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6940,7 +7146,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6961,7 +7169,9 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
; -O0: sxtb w9, w10
; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w12, w10, w8, le
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -6982,7 +7192,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0-LABEL: atomicrmw_min_i16_unaligned_monotonic:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
@@ -6998,7 +7210,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_acquire:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
@@ -7014,7 +7228,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_release:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
@@ -7030,7 +7246,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
@@ -7046,7 +7264,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
; -O0: sxth w10, w9
; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
@@ -7061,7 +7281,9 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
@@ -7075,7 +7297,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
@@ -7089,7 +7313,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
@@ -7103,7 +7329,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
@@ -7117,7 +7345,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
@@ -7131,7 +7361,9 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
@@ -7145,7 +7377,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
@@ -7159,7 +7393,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
@@ -7173,7 +7409,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
@@ -7187,7 +7425,9 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
@@ -7201,11 +7441,15 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7223,11 +7467,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7245,11 +7493,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7267,11 +7519,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7289,11 +7545,15 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -7312,7 +7572,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7333,7 +7595,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7354,7 +7618,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7375,7 +7641,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7396,7 +7664,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7416,7 +7686,9 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_monotonic:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7435,7 +7707,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acquire:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7454,7 +7728,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_release:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7473,7 +7749,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7492,7 +7770,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -7511,7 +7791,9 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7529,7 +7811,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7547,7 +7831,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7565,7 +7851,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7583,7 +7871,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -7601,7 +7891,9 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7619,7 +7911,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7637,7 +7931,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7655,7 +7951,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7673,7 +7971,9 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -7691,11 +7991,15 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -7721,11 +8025,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -7751,11 +8059,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -7781,11 +8093,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -7811,11 +8127,15 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -7842,7 +8162,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O0-LABEL: atomicrmw_umax_i8_unaligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7863,7 +8185,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7884,7 +8208,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7905,7 +8231,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7926,7 +8254,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, hi
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -7946,7 +8276,9 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
@@ -7961,7 +8293,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acquire:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
@@ -7976,7 +8310,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_release:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
@@ -7991,7 +8327,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
@@ -8006,7 +8344,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
@@ -8021,7 +8361,9 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_monotonic:
@@ -8035,7 +8377,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umax_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_acquire:
@@ -8049,7 +8393,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_release:
@@ -8063,7 +8409,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_acq_rel:
@@ -8077,7 +8425,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i32_unaligned_seq_cst:
@@ -8091,7 +8441,9 @@ define dso_local i32 @atomicrmw_umax_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_monotonic:
@@ -8105,7 +8457,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umax_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_acquire:
@@ -8119,7 +8473,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_release:
@@ -8133,7 +8489,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_acq_rel:
@@ -8147,7 +8505,9 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, hi
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i64_unaligned_seq_cst:
@@ -8161,11 +8521,15 @@ define dso_local i64 @atomicrmw_umax_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8183,11 +8547,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8205,11 +8573,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8227,11 +8599,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8249,11 +8625,15 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umax_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -8272,7 +8652,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8293,7 +8675,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8314,7 +8698,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8335,7 +8721,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8356,7 +8744,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8376,7 +8766,9 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_monotonic:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8395,7 +8787,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acquire:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8414,7 +8808,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_release:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8433,7 +8829,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8452,7 +8850,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxrh w9, [x11]
; -O0: cmp w9, w8, uxth
; -O0: stlxrh w10, w12, [x11]
@@ -8471,7 +8871,9 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8489,7 +8891,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8507,7 +8911,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_release:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8525,7 +8931,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8543,7 +8951,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O0: subs w10, w8, w9
-; -O0: csel w12, w8, w9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w12, w8, w9, ne
; -O0: ldaxr w9, [x11]
; -O0: cmp w9, w8
; -O0: stlxr w10, w12, [x11]
@@ -8561,7 +8971,9 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8579,7 +8991,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8597,7 +9011,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_release:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8615,7 +9031,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8633,7 +9051,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O0: subs x10, x8, x9
-; -O0: csel x12, x8, x9, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x12, x8, x9, ne
; -O0: ldaxr x9, [x11]
; -O0: cmp x9, x8
; -O0: stlxr w10, x12, [x11]
@@ -8651,11 +9071,15 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -8681,11 +9105,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -8711,11 +9139,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldxp x10, x9, [x11]
@@ -8741,11 +9173,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -8771,11 +9207,15 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O0: subs x8, x8, x9
+; -O0: subs x8, x8, x9
; -O0: subs x8, x8, x12
-; -O0: subs x13, x13, x9
-; -O0: csel w10, w8, w10, eq
-; -O0: ands w13, w10, #0x1
-; -O0: csel x14, x8, x12, ne
+; -O0: and w13, w13, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel w8, w8, w10, ne
+; -O0: and w13, w8, #0x1
+; -O0: ands w13, w13, #0x1
+; -O0: csel x14, x10, x12, ne
+; -O0: and w10, w8, #0x1
; -O0: ands w10, w10, #0x1
; -O0: csel x15, x8, x9, ne
; -O0: ldaxp x10, x9, [x11]
@@ -8802,7 +9242,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O0-LABEL: atomicrmw_umin_i8_unaligned_monotonic:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8823,7 +9265,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acquire:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8844,7 +9288,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_release:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8865,7 +9311,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acq_rel:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8886,7 +9334,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_seq_cst:
; -O0: and w9, w10, #0xff
; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w12, w10, w8, ls
+; -O0: and w9, w9, #0x1
+; -O0: ands w9, w9, #0x1
+; -O0: csel w12, w10, w8, ne
; -O0: ldaxrb w9, [x11]
; -O0: cmp w9, w10, uxtb
; -O0: stlxrb w8, w12, [x11]
@@ -8906,7 +9356,9 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
@@ -8921,7 +9373,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acquire:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
@@ -8936,7 +9390,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_release:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
@@ -8951,7 +9407,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
@@ -8966,7 +9424,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
@@ -8981,7 +9441,9 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
@@ -8995,7 +9457,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
@@ -9009,7 +9473,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
@@ -9023,7 +9489,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
@@ -9037,7 +9505,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel w8, w9, w8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
@@ -9051,7 +9521,9 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
@@ -9065,7 +9537,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
@@ -9079,7 +9553,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
@@ -9093,7 +9569,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
@@ -9107,7 +9585,9 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: and w10, w10, #0x1
+; -O0: ands w10, w10, #0x1
+; -O0: csel x8, x9, x8, ne
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
@@ -9121,11 +9601,15 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9143,11 +9627,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9165,11 +9653,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9187,11 +9679,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
@@ -9209,11 +9705,15 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O0: subs x8, x8, x10
-; -O0: subs x8, x8, x9
-; -O0: subs x12, x12, x10
-; -O0: csel w11, w8, w11, eq
-; -O0: ands w12, w11, #0x1
-; -O0: csel x9, x8, x9, ne
+; -O0: subs x8, x8, x10
+; -O0: subs x8, x8, x11
+; -O0: and w12, w12, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel w8, w8, w9, ne
+; -O0: and w12, w8, #0x1
+; -O0: ands w12, w12, #0x1
+; -O0: csel x9, x9, x11, ne
+; -O0: and w11, w8, #0x1
; -O0: ands w11, w11, #0x1
; -O0: csel x8, x8, x10, ne
; -O0: bl __atomic_compare_exchange
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
index d03647f8b294efe..aa5e54992f486fb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
@@ -1770,7 +1770,10 @@ define i8 @atomicrmw_min_i8(ptr %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: sxtb w9, w10
; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, sxtb
-; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, le
+; CHECK-NOLSE-O0-NEXT: cset w9, le
+; CHECK-NOLSE-O0-NEXT: and w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT: ands w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, ne
; CHECK-NOLSE-O0-NEXT: LBB33_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB33_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
@@ -1840,7 +1843,10 @@ define i8 @atomicrmw_max_i8(ptr %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: sxtb w9, w10
; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, sxtb
-; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, gt
+; CHECK-NOLSE-O0-NEXT: cset w9, gt
+; CHECK-NOLSE-O0-NEXT: and w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT: ands w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, ne
; CHECK-NOLSE-O0-NEXT: LBB34_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB34_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
@@ -1911,7 +1917,10 @@ define i8 @atomicrmw_umin_i8(ptr %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: and w9, w10, #0xff
; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxtb
-; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, ls
+; CHECK-NOLSE-O0-NEXT: cset w9, ls
+; CHECK-NOLSE-O0-NEXT: and w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT: ands w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, ne
; CHECK-NOLSE-O0-NEXT: LBB35_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB35_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
@@ -1982,7 +1991,10 @@ define i8 @atomicrmw_umax_i8(ptr %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: and w9, w10, #0xff
; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxtb
-; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, hi
+; CHECK-NOLSE-O0-NEXT: cset w9, hi
+; CHECK-NOLSE-O0-NEXT: and w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT: ands w9, w9, #0x1
+; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, ne
; CHECK-NOLSE-O0-NEXT: LBB36_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB36_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
@@ -2451,7 +2463,10 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: sxth w10, w8
; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, sxth
-; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, le
+; CHECK-NOLSE-O0-NEXT: cset w10, le
+; CHECK-NOLSE-O0-NEXT: and w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT: ands w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, ne
; CHECK-NOLSE-O0-NEXT: LBB43_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB43_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
@@ -2521,7 +2536,10 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: sxth w10, w8
; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, sxth
-; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, gt
+; CHECK-NOLSE-O0-NEXT: cset w10, gt
+; CHECK-NOLSE-O0-NEXT: and w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT: ands w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, ne
; CHECK-NOLSE-O0-NEXT: LBB44_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB44_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
@@ -2592,7 +2610,10 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: uxth w10, w8
; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, uxth
-; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, ls
+; CHECK-NOLSE-O0-NEXT: cset w10, ls
+; CHECK-NOLSE-O0-NEXT: and w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT: ands w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, ne
; CHECK-NOLSE-O0-NEXT: LBB45_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB45_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
@@ -2663,7 +2684,10 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: uxth w10, w8
; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, uxth
-; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, hi
+; CHECK-NOLSE-O0-NEXT: cset w10, hi
+; CHECK-NOLSE-O0-NEXT: and w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT: ands w10, w10, #0x1
+; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, ne
; CHECK-NOLSE-O0-NEXT: LBB46_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB46_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
@@ -2739,7 +2763,8 @@ define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
; CHECK-NOLSE-O0-NEXT: LBB47_3:
; CHECK-NOLSE-O0-NEXT: and w8, w0, #0xff
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w1, uxtb
-; CHECK-NOLSE-O0-NEXT: cset w1, eq
+; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: and w1, w8, #0x1
; CHECK-NOLSE-O0-NEXT: ret
;
; CHECK-LSE-O1-LABEL: cmpxchg_i8:
@@ -2759,7 +2784,8 @@ define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
; CHECK-LSE-O0-NEXT: casb w0, w2, [x8]
; CHECK-LSE-O0-NEXT: and w8, w0, #0xff
; CHECK-LSE-O0-NEXT: subs w8, w8, w1, uxtb
-; CHECK-LSE-O0-NEXT: cset w1, eq
+; CHECK-LSE-O0-NEXT: cset w8, eq
+; CHECK-LSE-O0-NEXT: and w1, w8, #0x1
; CHECK-LSE-O0-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %desired, i8 %new monotonic monotonic
ret { i8, i1 } %res
@@ -2803,7 +2829,8 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
; CHECK-NOLSE-O0-NEXT: LBB48_3:
; CHECK-NOLSE-O0-NEXT: and w8, w0, #0xffff
; CHECK-NOLSE-O0-NEXT: subs w8, w8, w1, uxth
-; CHECK-NOLSE-O0-NEXT: cset w1, eq
+; CHECK-NOLSE-O0-NEXT: cset w8, eq
+; CHECK-NOLSE-O0-NEXT: and w1, w8, #0x1
; CHECK-NOLSE-O0-NEXT: ret
;
; CHECK-LSE-O1-LABEL: cmpxchg_i16:
@@ -2823,7 +2850,8 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
; CHECK-LSE-O0-NEXT: cash w0, w2, [x8]
; CHECK-LSE-O0-NEXT: and w8, w0, #0xffff
; CHECK-LSE-O0-NEXT: subs w8, w8, w1, uxth
-; CHECK-LSE-O0-NEXT: cset w1, eq
+; CHECK-LSE-O0-NEXT: cset w8, eq
+; CHECK-LSE-O0-NEXT: and w1, w8, #0x1
; CHECK-LSE-O0-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %desired, i16 %new monotonic monotonic
ret { i16, i1 } %res
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
index 860df510b21187d..02d27e556fd5889 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
@@ -2,7 +2,7 @@
# Check that when we combine ZEXT/ANYEXT we assign the correct location.
# CHECK: !8 = !DILocation(line: 23, column: 5, scope: !4)
-# CHECK: G_AND %15, %16, debug-location !8
+# CHECK: G_AND %16, %15, debug-location !8
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-debugloc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-debugloc.mir
index b0d7b04ed50a940..4f44badb8e38c02 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-debugloc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-debugloc.mir
@@ -2,7 +2,7 @@
# Check that when we combine SEXT we assign the correct debug location.
# CHECK: !9 = !DILocation(line: 36, column: 21, scope: !4)
-# CHECK: G_AND %4, %5, debug-location !9
+# CHECK: G_AND %5, %4, debug-location !9
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/huge-switch.ll b/llvm/test/CodeGen/AArch64/GlobalISel/huge-switch.ll
index 8742a848c4af106..3c193307a863ed5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/huge-switch.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/huge-switch.ll
@@ -1,7 +1,9 @@
; RUN: llc -mtriple=arm64-apple-ios %s -o - -O0 -global-isel=1 | FileCheck %s
define void @foo(i512 %in) {
; CHECK-LABEL: foo:
-; CHECK: cbz
+; CHECK: subs
+; CHECK-NEXT: cset
+; CHECK-NEXT: tbnz
switch i512 %in, label %default [
i512 3923188584616675477397368389504791510063972152790021570560, label %l1
i512 3923188584616675477397368389504791510063972152790021570561, label %l2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll b/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
index 007e1fb3d63dad9..291eb5e22ca142c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
@@ -38,8 +38,8 @@ define i1 @test_lpad_phi_widen_into_pred() personality ptr @__gxx_personality_v0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[C2]](s16), %bb.1, [[C3]](s16), %bb.2
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
; CHECK-NEXT: $w0 = COPY [[AND]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -95,8 +95,8 @@ define i1 @test_lpad_phi_widen_into_pred_ext(ptr %ptr) personality ptr @__gxx_pe
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue:
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[ANYEXT]](s16), %bb.1, [[C2]](s16), %bb.2
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]]
; CHECK-NEXT: $w0 = COPY [[AND]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
index a7d7a1e81617e4f..fa3074a554944cb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
@@ -38,7 +38,6 @@ define i32 @test(i32 %a, i1 %c) {
; TRANSLATED-NEXT: BL @callee, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; TRANSLATED-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; TRANSLATED-NEXT: G_BR %bb.2
- ;
; PRESELECTION-LABEL: name: test
; PRESELECTION: bb.1.entry:
; PRESELECTION-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
@@ -51,8 +50,8 @@ define i32 @test(i32 %a, i1 %c) {
; PRESELECTION-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
; PRESELECTION-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 100000
; PRESELECTION-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:gpr(s32) = G_CONSTANT_FOLD_BARRIER [[C1]]
- ; PRESELECTION-NEXT: [[ANYEXT:%[0-9]+]]:gpr(s32) = G_ANYEXT [[ASSERT_ZEXT]](s8)
; PRESELECTION-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
+ ; PRESELECTION-NEXT: [[ANYEXT:%[0-9]+]]:gpr(s32) = G_ANYEXT [[ASSERT_ZEXT]](s8)
; PRESELECTION-NEXT: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[ANYEXT]], [[C2]]
; PRESELECTION-NEXT: G_BRCOND [[AND]](s32), %bb.3
; PRESELECTION-NEXT: G_BR %bb.2
@@ -70,7 +69,6 @@ define i32 @test(i32 %a, i1 %c) {
; PRESELECTION-NEXT: BL @callee, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; PRESELECTION-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; PRESELECTION-NEXT: G_BR %bb.2
- ;
; POSTSELECTION-LABEL: name: test
; POSTSELECTION: bb.1.entry:
; POSTSELECTION-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
index ceddb4bca725596..02f96cbe997898b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
@@ -10,7 +10,9 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY2]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], [[AND]]
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
%0:_(s64) = COPY $x0
@@ -35,8 +37,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
- ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], [[AND]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDE1]], [[C]]
+ ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY2]], [[COPY3]], [[AND1]]
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
; CHECK-NEXT: $x2 = COPY [[UADDE2]](s64)
@@ -84,7 +89,9 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY2]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], [[AND]]
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
%0:_(s64) = COPY $x0
@@ -112,7 +119,9 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY2]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], [[AND]]
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
%0:_(s64) = COPY $x0
@@ -358,15 +367,15 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
+ ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[DEF]](s16)
+ ; CHECK-NEXT: [[IMPLICIT_DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT0]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[IMPLICIT_DEF]](s16)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s16>) = G_ADD [[BUILD_VECTOR]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[ADD]](<4 x s16>)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s16)
- ; CHECK-NEXT: $b0 = COPY [[TRUNC]](s8)
+ ; CHECK-NEXT: [[VAL0:%[0-9]+]]:_(s16), [[VAL1:%[0-9]+]]:_(s16), [[VAL2:%[0-9]+]]:_(s16), [[VAL3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[ADD]](<4 x s16>)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[VAL0]](s16)
+ ; CHECK-NEXT: $b0 = COPY [[TRUNC3]](s8)
; CHECK-NEXT: RET_ReallyLR implicit $b0
%1:_(s8) = COPY $b0
%2:_(s8) = COPY $b1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
index 91f9dc0283dea5d..6111f4966028939 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
@@ -145,8 +145,8 @@ body: |
; CHECK: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[DEF]]
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 28
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s64)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32)
; CHECK: %ext:_(s64) = G_AND [[ANYEXT]], [[C1]]
; CHECK: $x0 = COPY %ext(s64)
; CHECK: RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
index e9b3aa0a3a8fd83..c7c061a15a2f98d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
@@ -9,8 +9,8 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s64), [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[ICMP]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
@@ -50,8 +50,11 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[DEF]](s64), [[C1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
- ; CHECK-NEXT: G_BRCOND [[SELECT]](s32), %bb.1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[AND1]](s32), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -88,7 +91,9 @@ body: |
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -127,7 +132,9 @@ body: |
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: G_BRCOND [[AND4]](s32), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -166,7 +173,9 @@ body: |
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s64), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: G_BRCOND [[AND4]](s32), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -205,7 +214,9 @@ body: |
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[AND1]], [[AND3]]
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[XOR]], [[XOR1]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s64), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: G_BRCOND [[AND4]](s32), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -267,7 +278,9 @@ body: |
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[XOR6]]
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[OR5]], [[XOR7]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR6]](s64), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND16:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: G_BRCOND [[AND16]](s32), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -313,7 +326,9 @@ body: |
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[XOR2]]
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[XOR3]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR2]](s64), [[C2]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: G_BRCOND [[AND8]](s32), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir
index 1cd1ab4a22e180e..35261d26fbb4e9f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir
@@ -292,13 +292,18 @@ body: |
; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[AND]](s64)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[CTLZ]], [[C3]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[C2]], [[C2]], [[UADDO1]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C4]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[C2]], [[C2]], [[AND2]]
; CHECK-NEXT: [[CTLZ1:%[0-9]+]]:_(s64) = G_CTLZ [[AND1]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDO]], [[CTLZ1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDE]], [[C2]]
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
- ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[SELECT]], [[C4]]
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[SELECT1]], [[C2]], [[USUBO1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C4]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND3]](s32), [[UADDO]], [[CTLZ1]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C4]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s32), [[UADDE]], [[C2]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
+ ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[SELECT]], [[C5]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C4]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[SELECT1]], [[C2]], [[AND5]]
; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
index ae0c29927afa6d4..472b09a3d78cb3b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
@@ -172,8 +172,8 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT %copy(s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT %copy(s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[AND]](s64)
; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
@@ -211,8 +211,8 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT %copy(s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT %copy(s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[AND]](s64)
; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
@@ -250,8 +250,8 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT %copy(s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT %copy(s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[AND]](s64)
; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
@@ -288,8 +288,8 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:_(s32) = COPY $w0
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT %copy(s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT %copy(s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s8>) = G_BITCAST [[AND]](s64)
; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
index 94ac5146006b166..17b80e03df7e2c8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
@@ -19,7 +19,6 @@ body: |
; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
; CHECK-NEXT: $w0 = COPY [[CTLZ]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- ;
; CHECK-CSSC-LABEL: name: s8
; CHECK-CSSC: liveins: $w0
; CHECK-CSSC-NEXT: {{ $}}
@@ -52,7 +51,6 @@ body: |
; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
; CHECK-NEXT: $w0 = COPY [[CTLZ]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- ;
; CHECK-CSSC-LABEL: name: s16
; CHECK-CSSC: liveins: $w0
; CHECK-CSSC-NEXT: {{ $}}
@@ -85,7 +83,6 @@ body: |
; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
; CHECK-NEXT: $w0 = COPY [[CTLZ]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- ;
; CHECK-CSSC-LABEL: name: s32
; CHECK-CSSC: liveins: $w0
; CHECK-CSSC-NEXT: {{ $}}
@@ -115,7 +112,6 @@ body: |
; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[BITREVERSE]](s64)
; CHECK-NEXT: $x0 = COPY [[CTLZ]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- ;
; CHECK-CSSC-LABEL: name: s64
; CHECK-CSSC: liveins: $x0
; CHECK-CSSC-NEXT: {{ $}}
@@ -148,7 +144,6 @@ body: |
; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<4 x s32>) = G_CTPOP [[AND]](<4 x s32>)
; CHECK-NEXT: $q0 = COPY [[CTPOP]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- ;
; CHECK-CSSC-LABEL: name: v4s32
; CHECK-CSSC: liveins: $q0
; CHECK-CSSC-NEXT: {{ $}}
@@ -185,7 +180,6 @@ body: |
; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[BITREVERSE]](s64)
; CHECK-NEXT: $x0 = COPY [[CTLZ]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
- ;
; CHECK-CSSC-LABEL: name: s35
; CHECK-CSSC: liveins: $x0
; CHECK-CSSC-NEXT: {{ $}}
@@ -224,15 +218,17 @@ body: |
; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[BITREVERSE]](s64)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[CTLZ]], [[C2]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[C]], [[C]], [[UADDO1]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C3]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[C]], [[C]], [[AND]]
; CHECK-NEXT: [[BITREVERSE1:%[0-9]+]]:_(s64) = G_BITREVERSE [[OR]]
; CHECK-NEXT: [[CTLZ1:%[0-9]+]]:_(s64) = G_CTLZ [[BITREVERSE1]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDO]], [[CTLZ1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDE]], [[C]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[UADDO]], [[CTLZ1]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[UADDE]], [[C]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: $x1 = COPY [[SELECT1]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
- ;
; CHECK-CSSC-LABEL: name: s65
; CHECK-CSSC: liveins: $x0, $x1
; CHECK-CSSC-NEXT: {{ $}}
@@ -246,10 +242,13 @@ body: |
; CHECK-CSSC-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[OR1]](s64)
; CHECK-CSSC-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK-CSSC-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[CTTZ]], [[C2]]
- ; CHECK-CSSC-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[C]], [[C]], [[UADDO1]]
+ ; CHECK-CSSC-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-CSSC-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C3]]
+ ; CHECK-CSSC-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[C]], [[C]], [[AND]]
; CHECK-CSSC-NEXT: [[CTTZ1:%[0-9]+]]:_(s64) = G_CTTZ [[OR]](s64)
- ; CHECK-CSSC-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDO]], [[CTTZ1]]
- ; CHECK-CSSC-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDE]], [[C]]
+ ; CHECK-CSSC-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-CSSC-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[UADDO]], [[CTTZ1]]
+ ; CHECK-CSSC-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[UADDE]], [[C]]
; CHECK-CSSC-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-CSSC-NEXT: $x1 = COPY [[SELECT1]](s64)
; CHECK-CSSC-NEXT: RET_ReallyLR implicit $x0, implicit $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
index d0089bba68bec8c..7fec515fe3fb07a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
@@ -6,20 +6,20 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_div
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
- ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
- ; CHECK-NEXT: $w0 = COPY [[SDIV]](s32)
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]
- ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C]]
- ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
- ; CHECK-NEXT: $w0 = COPY [[UDIV]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
+ ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
+ ; CHECK: $w0 = COPY [[SDIV]](s32)
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]
+ ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C]]
+ ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
+ ; CHECK: $w0 = COPY [[UDIV]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)
@@ -43,18 +43,17 @@ body: |
; CHECK-LABEL: name: sdiv_v4s32
; CHECK: liveins: $q0, $q1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
- ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[UV]], [[UV4]]
- ; CHECK-NEXT: [[SDIV1:%[0-9]+]]:_(s32) = G_SDIV [[UV1]], [[UV5]]
- ; CHECK-NEXT: [[SDIV2:%[0-9]+]]:_(s32) = G_SDIV [[UV2]], [[UV6]]
- ; CHECK-NEXT: [[SDIV3:%[0-9]+]]:_(s32) = G_SDIV [[UV3]], [[UV7]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SDIV]](s32), [[SDIV1]](s32), [[SDIV2]](s32), [[SDIV3]](s32)
- ; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
+ ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[UV]], [[UV4]]
+ ; CHECK: [[SDIV1:%[0-9]+]]:_(s32) = G_SDIV [[UV1]], [[UV5]]
+ ; CHECK: [[SDIV2:%[0-9]+]]:_(s32) = G_SDIV [[UV2]], [[UV6]]
+ ; CHECK: [[SDIV3:%[0-9]+]]:_(s32) = G_SDIV [[UV3]], [[UV7]]
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SDIV]](s32), [[SDIV1]](s32), [[SDIV2]](s32), [[SDIV3]](s32)
+ ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>)
+ ; CHECK: RET_ReallyLR implicit $q0
%0:_(<4 x s32>) = COPY $q0
%1:_(<4 x s32>) = COPY $q1
%2:_(<4 x s32>) = G_SDIV %0, %1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-cse.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-cse.mir
index f105b2e934d3c09..98e6cbbda593c47 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-cse.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-cse.mir
@@ -6,12 +6,12 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_cse_in_legalizer
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)
- ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
+ ; CHECK: $w0 = COPY [[COPY1]](s32)
+ ; CHECK: $w0 = COPY [[AND]](s32)
%0:_(s64) = COPY $x0
%1:_(s8) = G_TRUNC %0(s64)
%19:_(s32) = G_ZEXT %1(s8)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir
index 2a45a05b2e5a0a9..fe6f4a1344c7733 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir
@@ -10,11 +10,11 @@ body: |
; CHECK: CSEInfo::Add MI: %{{[0-9]+}}:_(s32) = G_ZEXT
; CHECK: CSEInfo::Add MI: %{{[0-9]+}}:_(s8) = G_TRUNC
; CHECK: CSEInfo::Add MI: %{{[0-9]+}}:_(s32) = G_ZEXT
- ; CHECK: CSEInfo::Recording new MI G_TRUNC
; CHECK: CSEInfo::Recording new MI G_CONSTANT
+ ; CHECK: CSEInfo::Recording new MI G_TRUNC
; CHECK: CSEInfo::Recording new MI G_AND
- ; CHECK: CSEInfo::Found Instr %{{[0-9]+}}:_(s32) = G_TRUNC
; CHECK: CSEInfo::Found Instr %{{[0-9]+}}:_(s32) = G_CONSTANT
+ ; CHECK: CSEInfo::Found Instr %{{[0-9]+}}:_(s32) = G_TRUNC
; CHECK: CSEInfo::Found Instr %{{[0-9]+}}:_(s32) = G_AND
; CHECK: CSEInfo::CSE Hit for Opc {{[0-9]+}} : 1
; CHECK: CSEInfo::CSE Hit for Opc {{[0-9]+}} : 1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
index 74401a2f1ceace5..8275ed81d3e1ff5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
@@ -24,14 +24,14 @@ body: |
; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC4]], 1
; CHECK-NEXT: $w0 = COPY [[SEXT_INREG1]](s32)
- ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC5]], [[C1]]
; CHECK-NEXT: $w0 = COPY [[AND1]](s32)
; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: $w0 = COPY [[TRUNC6]](s32)
- ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC7]], [[C2]]
; CHECK-NEXT: $w0 = COPY [[AND2]](s32)
; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
index 68302f5f1869588..62a0c92004f7f87 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
@@ -291,8 +291,8 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
; CHECK-NEXT: %ext:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
index be674d79b54f1de..57bd3e761f81d08 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
@@ -7,9 +7,7 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_freeze_s64
- ; CHECK: liveins: $x0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x0:_(s64) = COPY $x0
+ ; CHECK: %x0:_(s64) = COPY $x0
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE %x0
; CHECK-NEXT: $x0 = COPY [[FREEZE]](s64)
%x0:_(s64) = COPY $x0
@@ -23,9 +21,7 @@ body: |
liveins: $q0
; CHECK-LABEL: name: test_freeze_v4s32
- ; CHECK: liveins: $q0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %q0:_(<4 x s32>) = COPY $q0
+ ; CHECK: %q0:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<4 x s32>) = G_FREEZE %q0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[FREEZE]](<4 x s32>)
; CHECK-NEXT: $x0 = COPY [[UV]](<2 x s32>)
@@ -60,9 +56,7 @@ body: |
liveins: $d0
; CHECK-LABEL: name: test_freeze_v2s32
- ; CHECK: liveins: $d0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %d0:_(<2 x s32>) = COPY $d0
+ ; CHECK: %d0:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<2 x s32>) = G_FREEZE %d0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[FREEZE]](<2 x s32>)
; CHECK-NEXT: $w0 = COPY [[UV]](s32)
@@ -80,9 +74,7 @@ body: |
liveins: $d0
; CHECK-LABEL: name: test_freeze_v8s8
- ; CHECK: liveins: $d0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %d0:_(<8 x s8>) = COPY $d0
+ ; CHECK: %d0:_(<8 x s8>) = COPY $d0
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<8 x s8>) = G_FREEZE %d0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s8>), [[UV1:%[0-9]+]]:_(<4 x s8>) = G_UNMERGE_VALUES [[FREEZE]](<8 x s8>)
; CHECK-NEXT: $w0 = COPY [[UV]](<4 x s8>)
@@ -99,12 +91,10 @@ body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_freeze_s1
- ; CHECK: liveins: $x0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+ ; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s8) = G_FREEZE [[DEF]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FREEZE]](s8)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FREEZE]](s8)
; CHECK-NEXT: %ext:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: $x0 = COPY %ext(s64)
%x:_(s1) = G_IMPLICIT_DEF
@@ -118,12 +108,10 @@ body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_freeze_s2
- ; CHECK: liveins: $x0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+ ; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s8) = G_FREEZE [[DEF]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FREEZE]](s8)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FREEZE]](s8)
; CHECK-NEXT: %ext:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: $x0 = COPY %ext(s64)
%x:_(s2) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir
index c3c23aecc161f0c..80617314ce0e546 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir
@@ -21,13 +21,15 @@ body: |
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[COPY3]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND2]](s32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s64)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND1]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C3]](s64)
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C2]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[AND4]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -64,13 +66,15 @@ body: |
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[COPY3]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND2]](s32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s64)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND1]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C3]](s64)
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C2]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[AND4]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir
index 09520445b71d98d..81bf4332b456d58 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir
@@ -23,10 +23,12 @@ body: |
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[COPY3]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND]](s32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C3]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND2]](s32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C3]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -65,10 +67,12 @@ body: |
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[COPY3]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s64)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND]](s32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C3]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND2]](s32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C3]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
; CHECK-NEXT: $w0 = COPY [[OR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
index 942bb60f5c06230..c49e62e53f07bb1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
@@ -66,9 +66,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
index fafaa4646fa2298..3ad54ba3f17fb50 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
@@ -18,7 +18,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -45,7 +47,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
@@ -72,7 +76,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -99,7 +105,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
@@ -128,7 +136,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -155,7 +165,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
@@ -182,7 +194,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -209,7 +223,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
index fc417b2eca61892..8c6a30aaed04836 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
@@ -274,12 +274,12 @@ body: |
; CHECK-LABEL: name: test_uitofp_v2s64_v2i1
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[DEF]](s64)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[COPY]](s64)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[COPY]](s64)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(<2 x s64>) = G_UITOFP [[AND]](<2 x s64>)
; CHECK-NEXT: $q0 = COPY [[UITOFP]](<2 x s64>)
%0:_(<2 x s1>) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
index 5cbb8649d158b0e..1040a5d6ff4d993 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
@@ -688,8 +688,8 @@ body: |
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[LOAD]], 1
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASSERT_ZEXT]](s8)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASSERT_ZEXT]](s8)
; CHECK-NEXT: %ext:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: $x0 = COPY %ext(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
index 8fc2ad3e41789b4..6e399d8a3883506 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
@@ -6,11 +6,14 @@ name: test_merge_s4
body: |
bb.0:
; CHECK-LABEL: name: test_merge_s4
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C1]](s64)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[SHL]]
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[C1]], [[C]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
; CHECK-NEXT: $x0 = COPY [[ANYEXT]](s64)
%0:_(s64) = G_CONSTANT i64 0
@@ -26,6 +29,7 @@ name: test_merge_s16_s8
body: |
bb.0:
+ ; This isn't legal but we don't support widening the destination type.
; CHECK-LABEL: name: test_merge_s16_s8
; CHECK: %a:_(s32) = COPY $w0
; CHECK-NEXT: %b:_(s32) = COPY $w1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
index b29670a89c8cf67..0e895c49eff0991 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
@@ -131,8 +131,8 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %lhs_wide, [[C]]
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %rhs_wide, [[C]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT %lhs_wide(s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16777215
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT %lhs_wide(s32)
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]]
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT %rhs_wide(s32)
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C1]]
@@ -223,8 +223,8 @@ body: |
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[LOAD]], [[LOAD1]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s64), [[C]]
; CHECK-NEXT: G_STORE [[C]](s64), [[FRAME_INDEX2]](p0) :: (store (s64), align 1)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]]
; CHECK-NEXT: $x0 = COPY [[MUL]](s64)
; CHECK-NEXT: $x1 = COPY [[AND]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
index f1aee90bb07ddeb..60d7af273eb5e31 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
@@ -52,8 +52,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(p0) = G_PHI %6(p0), %bb.2, [[DEF]](p0), %bb.0
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI %22(s16), %bb.2, [[DEF1]](s16), %bb.0
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.3
; CHECK-NEXT: {{ $}}
@@ -71,8 +71,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT1]](s32), [[COPY]]
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PHI]], [[C2]](s64)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C4]]
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ICMP1]](s32)
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.3
+ ; CHECK-NEXT: G_BRCOND [[AND1]](s32), %bb.3
; CHECK-NEXT: G_BR %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.bb10:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
index 4154ab7039c2f3f..3c952cb779d230e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
@@ -32,7 +32,8 @@ body: |
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+ ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -50,10 +51,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.1, [[TRUNC1]](s16), %bb.2
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
- ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+ ; CHECK-NEXT: $w0 = COPY [[AND1]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
bb.0:
; Test that we insert legalization artifacts(Truncs here) into the correct BBs
@@ -184,7 +185,8 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -201,10 +203,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.1, [[TRUNC1]](s16), %bb.2
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
- ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+ ; CHECK-NEXT: $w0 = COPY [[AND1]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -279,13 +281,14 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.1
+ ; CHECK-NEXT: G_BRCOND [[AND1]](s32), %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C3]]
- ; CHECK-NEXT: $w0 = COPY [[AND1]](s32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C3]]
+ ; CHECK-NEXT: $w0 = COPY [[AND2]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
bb.0:
successors: %bb.1(0x80000000)
@@ -339,11 +342,13 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[C]](s16), %bb.0, [[PHI]](s16), %bb.1
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[AND1]](s32), %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: $w0 = COPY [[AND]](s32)
@@ -407,7 +412,8 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -427,12 +433,12 @@ body: |
; CHECK-NEXT: bb.3:
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC2]](s16), %bb.2
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.1, [[C3]](s16), %bb.2
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C4]]
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C4]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]]
; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
bb.0:
@@ -518,28 +524,31 @@ body: |
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
- ; CHECK-NEXT: G_BRCOND [[ICMP]](s32), %bb.1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.1
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.0, %22(s16), %bb.1
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[C2]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[C2]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ADD1]](s32), [[C3]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 43
- ; CHECK-NEXT: G_BRCOND [[ICMP1]](s32), %bb.2
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C5]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 43
+ ; CHECK-NEXT: G_BRCOND [[AND2]](s32), %bb.2
; CHECK-NEXT: G_BR %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[PHI]](s16), %bb.1, [[TRUNC]](s16), %bb.0
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C6]]
- ; CHECK-NEXT: $w0 = COPY [[AND1]](s32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C7]]
+ ; CHECK-NEXT: $w0 = COPY [[AND3]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
bb.0:
successors: %bb.1(0x40000000), %bb.3(0x40000000)
@@ -662,8 +671,8 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C]]
; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.1
; CHECK-NEXT: G_BR %bb.2
@@ -718,8 +727,8 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr1, [[C]](s64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C1]]
; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.2
; CHECK-NEXT: G_BR %bb.1
@@ -769,8 +778,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.2
; CHECK-NEXT: G_BR %bb.1
@@ -815,8 +824,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF1]], [[C]]
; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.2
; CHECK-NEXT: G_BR %bb.1
@@ -910,8 +919,8 @@ body: |
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr1, [[C]](s64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD1]](<2 x s64>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C1]]
; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.2
; CHECK-NEXT: G_BR %bb.1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptrtoint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptrtoint.mir
index dbc538a21afda4a..f62a948a4b36e2d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptrtoint.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptrtoint.mir
@@ -83,8 +83,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT %ptr(p0)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
; CHECK-NEXT: %ext:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
index 7a8f42b43787a3f..b707e3ce2a3d50b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
@@ -96,8 +96,8 @@ body: |
; CHECK-LABEL: name: test_urem_1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
index bbb6fda40dd512c..6e72e749eaef785 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
@@ -11,11 +11,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY]], [[COPY2]], [[AND]]
- ; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY1]], [[COPY3]], [[UADDE1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDE1]], [[C]]
+ ; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY1]], [[COPY3]], [[AND1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SADDE1]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
; CHECK-NEXT: $x1 = COPY [[SADDE]](s64)
@@ -46,12 +47,14 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY]], [[COPY1]], [[AND]]
- ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], [[UADDE1]]
- ; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY2]], [[COPY3]], [[UADDE3]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDE1]], [[C]]
+ ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], [[AND1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UADDE3]], [[C]]
+ ; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY2]], [[COPY3]], [[AND2]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SADDE1]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
; CHECK-NEXT: $x1 = COPY [[UADDE2]](s64)
@@ -86,8 +89,8 @@ body: |
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], [[AND]]
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UADDE]], 8
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
index bf0af67e56f8740..0b04b45cddf3ec0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
@@ -11,7 +11,9 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY2]]
- ; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
+ ; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY1]], [[COPY3]], [[AND]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SADDE1]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
; CHECK-NEXT: $x1 = COPY [[SADDE]](s64)
@@ -40,8 +42,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
- ; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY2]], [[COPY3]], [[UADDE1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], [[AND]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDE1]], [[C]]
+ ; CHECK-NEXT: [[SADDE:%[0-9]+]]:_(s64), [[SADDE1:%[0-9]+]]:_(s32) = G_SADDE [[COPY2]], [[COPY3]], [[AND1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SADDE1]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
index b8bdef06cac6d16..b2fb18733b7cb6b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
@@ -18,7 +18,9 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SADDO]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
- ; CHECK-NEXT: %saddsat:_(s32) = G_SELECT [[SADDO1]](s32), [[ADD]], [[SADDO]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SADDO1]], [[C2]]
+ ; CHECK-NEXT: %saddsat:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[SADDO]]
; CHECK-NEXT: $w0 = COPY %saddsat(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
@@ -44,7 +46,9 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SADDO]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
- ; CHECK-NEXT: %saddsat:_(s64) = G_SELECT [[SADDO1]](s32), [[ADD]], [[SADDO]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SADDO1]], [[C2]]
+ ; CHECK-NEXT: %saddsat:_(s64) = G_SELECT [[AND]](s32), [[ADD]], [[SADDO]]
; CHECK-NEXT: $x0 = COPY %saddsat(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%x:_(s64) = COPY $x0
@@ -76,7 +80,9 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD1]], [[ADD]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD1]], [[ADD]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
@@ -111,7 +117,8 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD1]], [[ADD]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD1]], [[ADD]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
@@ -146,7 +153,9 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD1]], [[ADD]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD1]], [[ADD]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
@@ -178,10 +187,13 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s64), [[SEXT_INREG2]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 35
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[SEXT_INREG2]](s64)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[ADD1]], [[ADD]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[ADD1]], [[ADD]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%copy_1:_(s64) = COPY $x0
@@ -215,7 +227,9 @@ body: |
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 24
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 24
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], [[UADDO1]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C1]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], [[AND]]
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UADDE]], 24
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UADDE]](s32)
@@ -226,10 +240,11 @@ body: |
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV8]](s8), [[UV9]](s8), [[UV10]](s8), [[UV8]](s8)
; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](s32), [[MV1]](s32)
; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[MV2]], 24
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[C2]](s64)
; CHECK-NEXT: [[UADDO2:%[0-9]+]]:_(s64), [[UADDO3:%[0-9]+]]:_(s32) = G_UADDO [[ASHR]], [[C]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDO2]], [[UADDO]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[UADDO2]], [[UADDO]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%copy_1:_(s128) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
index 4879ffd28784c16..31b87a04a6dc170 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
@@ -125,18 +125,20 @@ body: |
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[AND]], 1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY2]](s32), [[C2]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY2]](s32), [[C3]](s64)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s32>), [[DEF]], shufflemask(0, 0, 0, 0)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32), [[C3]](s32), [[C3]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C4]](s32), [[C4]](s32), [[C4]](s32), [[C4]](s32)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY1]], [[SHUF]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[BUILD_VECTOR]], [[XOR]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY1]], [[SHUF]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<4 x s32>) = G_AND [[BUILD_VECTOR]], [[XOR]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[AND1]], [[AND2]]
; CHECK-NEXT: $q0 = COPY [[OR]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(s32) = COPY $w0
@@ -164,7 +166,9 @@ body: |
; CHECK-NEXT: %b:_(s32) = COPY $w1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), %a(s32), %b
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[DEF]], [[DEF]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[DEF]], [[DEF]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s32) = COPY $w0
@@ -307,17 +311,17 @@ body: |
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[BUILD_VECTOR1]](<4 x s1>)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s16>) = G_XOR [[ANYEXT]], [[ANYEXT1]]
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[XOR]](<4 x s16>)
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT %vec_cond0(<4 x s1>)
- ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[SHUF]](<4 x s1>)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[ANYEXT2]], [[ANYEXT3]]
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT %vec_cond0(<4 x s1>)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[SHUF]](<4 x s1>)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[ANYEXT3]], [[ANYEXT4]]
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[AND]](<4 x s16>)
- ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT %vec_cond1(<4 x s1>)
- ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC2]](<4 x s1>)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s16>) = G_AND [[ANYEXT4]], [[ANYEXT5]]
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT %vec_cond1(<4 x s1>)
+ ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC2]](<4 x s1>)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s16>) = G_AND [[ANYEXT5]], [[ANYEXT6]]
; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[AND1]](<4 x s16>)
- ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC3]](<4 x s1>)
- ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC4]](<4 x s1>)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s16>) = G_OR [[ANYEXT6]], [[ANYEXT7]]
+ ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC3]](<4 x s1>)
+ ; CHECK-NEXT: [[ANYEXT8:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC4]](<4 x s1>)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s16>) = G_OR [[ANYEXT7]], [[ANYEXT8]]
; CHECK-NEXT: %select:_(<4 x s1>) = G_TRUNC [[OR]](<4 x s16>)
; CHECK-NEXT: %zext_select:_(<4 x s32>) = G_ZEXT %select(<4 x s1>)
; CHECK-NEXT: $q0 = COPY %zext_select(<4 x s32>)
@@ -355,20 +359,22 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[C]](p0), [[C]](p0)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[COPY1]](<2 x p0>)
; CHECK-NEXT: [[PTRTOINT1:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BUILD_VECTOR]](<2 x p0>)
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[AND]], 1
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXT_INREG]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT]](s64), [[C1]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT]](s64), [[C2]](s64)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[IVEC]](<2 x s64>), [[DEF]], shufflemask(0, 0)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C2]](s64), [[C2]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C3]](s64), [[C3]](s64)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT]], [[SHUF]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT1]], [[XOR]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT]], [[SHUF]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT1]], [[XOR]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND2]]
; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(<2 x p0>) = G_INTTOPTR [[OR]](<2 x s64>)
; CHECK-NEXT: $q0 = COPY [[INTTOPTR]](<2 x p0>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
index 9a9b35cf293da1c..e7073bdc3d68589 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
@@ -7,8 +7,8 @@ body: |
; CHECK-LABEL: name: test_shift
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
@@ -109,9 +109,13 @@ body: |
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[TRUNC]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]]
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[SUB]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[SHL]], [[C1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[OR]], [[SHL2]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s32), [[UV1]], [[SELECT1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[SHL]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[OR]], [[SHL2]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s32), [[UV1]], [[SELECT1]]
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; CHECK-NEXT: $q0 = COPY [[MV]](s128)
%0:_(s128) = COPY $q0
@@ -141,9 +145,13 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[SUB1]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[SUB]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[OR]], [[LSHR2]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s32), [[UV]], [[SELECT]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[OR]], [[LSHR2]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[UV]], [[SELECT]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s32), [[LSHR]], [[C1]]
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; CHECK-NEXT: $q0 = COPY [[MV]](s128)
%0:_(s128) = COPY $q0
@@ -175,9 +183,13 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C2]](s64)
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[SUB]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[OR]], [[ASHR2]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s32), [[UV]], [[SELECT]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[ASHR]], [[ASHR1]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[OR]], [[ASHR2]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C3]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[UV]], [[SELECT]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s32), [[ASHR]], [[ASHR1]]
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; CHECK-NEXT: $q0 = COPY [[MV]](s128)
%0:_(s128) = COPY $q0
@@ -224,9 +236,7 @@ body: |
liveins: $w0
; CHECK-LABEL: name: shl_cimm_32
- ; CHECK: liveins: $w0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s64)
; CHECK-NEXT: $w0 = COPY [[SHL]](s32)
@@ -245,9 +255,7 @@ body: |
liveins: $w0
; CHECK-LABEL: name: lshr_cimm_32
- ; CHECK: liveins: $w0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s64)
; CHECK-NEXT: $w0 = COPY [[LSHR]](s32)
@@ -266,9 +274,7 @@ body: |
liveins: $w0
; CHECK-LABEL: name: ashr_cimm_32
- ; CHECK: liveins: $w0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s64)
; CHECK-NEXT: $w0 = COPY [[ASHR]](s32)
@@ -490,8 +496,11 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[SUB1]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[MV1]], [[SUB]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[OR]], [[LSHR1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s32), [[MV]], [[SELECT]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[OR]], [[LSHR1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C3]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[MV]], [[SELECT]]
; CHECK-NEXT: %d1:_(s32), %d2:_(s32) = G_UNMERGE_VALUES [[SELECT1]](s64)
; CHECK-NEXT: $w0 = COPY %d2(s32)
%0:_(s64) = COPY $x0
@@ -520,6 +529,7 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[C2]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s64), [[C1]]
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[C3]]
; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s64) = G_SUB [[C3]], [[COPY]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[C3]]
@@ -528,11 +538,14 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[SUB3]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[MV1]], [[SUB2]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s32), [[OR]], [[LSHR1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s32), [[MV]], [[SELECT]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C4]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[OR]], [[LSHR1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[C4]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[MV]], [[SELECT]]
; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB1]](s64), [[C3]]
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[MV2]], [[SUB1]](s64)
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s32), [[SHL1]], [[C1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[C4]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s32), [[SHL1]], [[C1]]
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SELECT1]], [[SELECT2]]
; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB [[SUB]], [[C3]]
; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s64) = G_SUB [[C3]], [[SUB]]
@@ -542,10 +555,14 @@ body: |
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[C1]], [[SUB5]](s64)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[SHL2]]
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[C1]], [[SUB4]](s64)
- ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s32), [[OR2]], [[LSHR3]]
- ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s32), [[MV2]], [[SELECT3]]
- ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[OR1]], [[SELECT4]]
- ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s32), [[MV]], [[SELECT5]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP5]], [[C4]]
+ ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[AND3]](s32), [[OR2]], [[LSHR3]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP6]], [[C4]]
+ ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s32), [[MV2]], [[SELECT3]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C4]]
+ ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[AND5]](s32), [[OR1]], [[SELECT4]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C4]]
+ ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[AND6]](s32), [[MV]], [[SELECT5]]
; CHECK-NEXT: %d1:_(s32), %d2:_(s32) = G_UNMERGE_VALUES [[SELECT6]](s64)
; CHECK-NEXT: $w0 = COPY %d2(s32)
%0:_(s64) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
index 62865bcfdf081e8..c1bf5cd33bea431 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
@@ -12,16 +12,16 @@ body: |
; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[INTTOPTR]](p0)
; CHECK-NEXT: $x0 = COPY [[PTRTOINT]](s64)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC4]], [[C1]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[TRUNC2]], [[TRUNC3]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
@@ -101,9 +101,7 @@ body: |
liveins: $x0, $x1
; CHECK-LABEL: name: bitcast128
- ; CHECK: liveins: $x0, $x1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[MV]](s128)
@@ -124,9 +122,7 @@ body: |
liveins: $x0
; CHECK-LABEL: name: testExtOfCopyOfTrunc
- ; CHECK: liveins: $x0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
@@ -144,9 +140,7 @@ body: |
liveins: $x0
; CHECK-LABEL: name: testExtOf2CopyOfTrunc
- ; CHECK: liveins: $x0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
index e7d1f8e7a50f97a..fa372217c88350c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
@@ -11,11 +11,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY]], [[COPY2]], [[AND]]
- ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY1]], [[COPY3]], [[USUBE1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[USUBE1]], [[C]]
+ ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY1]], [[COPY3]], [[AND1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SSUBE1]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
; CHECK-NEXT: $x1 = COPY [[SSUBE]](s64)
@@ -46,12 +47,14 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY]], [[COPY1]], [[AND]]
- ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], [[USUBE1]]
- ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY2]], [[COPY3]], [[USUBE3]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[USUBE1]], [[C]]
+ ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], [[AND1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[USUBE3]], [[C]]
+ ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY2]], [[COPY3]], [[AND2]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SSUBE1]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
; CHECK-NEXT: $x1 = COPY [[USUBE2]](s64)
@@ -86,8 +89,8 @@ body: |
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]
; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], [[AND]]
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[USUBE]], 8
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
index 5e8d96a4b6d689b..cc53b387940b2d2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
@@ -11,7 +11,9 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY2]]
- ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY1]], [[COPY3]], [[USUBO1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C]]
+ ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY1]], [[COPY3]], [[AND]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SSUBE1]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
; CHECK-NEXT: $x1 = COPY [[SSUBE]](s64)
@@ -40,8 +42,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
- ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY2]], [[COPY3]], [[USUBE1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], [[AND]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[USUBE1]], [[C]]
+ ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:_(s64), [[SSUBE1:%[0-9]+]]:_(s32) = G_SSUBE [[COPY2]], [[COPY3]], [[AND1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[SSUBE1]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
index 2311be6b425cb9d..8baa96bc564d5a2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
@@ -18,7 +18,9 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SSUBO]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
- ; CHECK-NEXT: %ssubsat:_(s32) = G_SELECT [[SSUBO1]](s32), [[ADD]], [[SSUBO]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSUBO1]], [[C2]]
+ ; CHECK-NEXT: %ssubsat:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[SSUBO]]
; CHECK-NEXT: $w0 = COPY %ssubsat(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
@@ -44,7 +46,9 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SSUBO]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
- ; CHECK-NEXT: %ssubsat:_(s64) = G_SELECT [[SSUBO1]](s32), [[ADD]], [[SSUBO]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSUBO1]], [[C2]]
+ ; CHECK-NEXT: %ssubsat:_(s64) = G_SELECT [[AND]](s32), [[ADD]], [[SSUBO]]
; CHECK-NEXT: $x0 = COPY %ssubsat(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%x:_(s64) = COPY $x0
@@ -76,7 +80,9 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD]], [[SUB]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[SUB]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
@@ -111,7 +117,8 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD]], [[SUB]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[SUB]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
@@ -146,7 +153,9 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD]], [[SUB]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[SUB]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
@@ -178,10 +187,13 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s64), [[SEXT_INREG2]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 35
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[SEXT_INREG2]](s64)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[ADD]], [[SUB]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[ADD]], [[SUB]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%copy_1:_(s64) = COPY $x0
@@ -215,7 +227,9 @@ body: |
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 24
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 24
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], [[USUBO1]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C1]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], [[AND]]
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[USUBE]], 24
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[SEXT_INREG2]]
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[USUBE]](s32)
@@ -226,10 +240,11 @@ body: |
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV8]](s8), [[UV9]](s8), [[UV10]](s8), [[UV8]](s8)
; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](s32), [[MV1]](s32)
; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[MV2]], 24
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[C2]](s64)
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[ASHR]], [[C]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s32), [[UADDO]], [[USUBO]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s32), [[UADDO]], [[USUBO]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%copy_1:_(s128) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
index 205c32f6971acc7..3de25d98f00c91f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
@@ -11,7 +11,9 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY2]]
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY3]], [[USUBO1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY3]], [[AND]]
; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
%0:_(s64) = COPY $x0
@@ -36,8 +38,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
- ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], [[AND]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[USUBE1]], [[C]]
+ ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY2]], [[COPY3]], [[AND1]]
; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
; CHECK-NEXT: $x2 = COPY [[USUBE2]](s64)
@@ -131,8 +136,8 @@ body: |
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $d3
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[COPY3]]
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<2 x s32>) = G_SUB [[ICMP]], [[ICMP1]]
- ; CHECK-NEXT: $d0 = COPY [[SUB]](<2 x s32>)
+ ; CHECK-NEXT: [[sub:%[0-9]+]]:_(<2 x s32>) = G_SUB [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[sub]](<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@@ -158,15 +163,15 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
+ ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[DEF]](s16)
+ ; CHECK-NEXT: [[IMPLICIT_DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT0]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[IMPLICIT_DEF]](s16)
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s16>) = G_SUB [[BUILD_VECTOR]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[SUB]](<4 x s16>)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s16)
- ; CHECK-NEXT: $b0 = COPY [[TRUNC]](s8)
+ ; CHECK-NEXT: [[VAL0:%[0-9]+]]:_(s16), [[VAL1:%[0-9]+]]:_(s16), [[VAL2:%[0-9]+]]:_(s16), [[VAL3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[SUB]](<4 x s16>)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[VAL0]](s16)
+ ; CHECK-NEXT: $b0 = COPY [[TRUNC3]](s8)
; CHECK-NEXT: RET_ReallyLR implicit $b0
%1:_(s8) = COPY $b0
%2:_(s8) = COPY $b1
@@ -195,8 +200,8 @@ body: |
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s16>) = COPY $d3
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY2]](<4 x s16>), [[COPY3]]
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s16>) = G_SUB [[ICMP]], [[ICMP1]]
- ; CHECK-NEXT: $d0 = COPY [[SUB]](<4 x s16>)
+ ; CHECK-NEXT: [[sub:%[0-9]+]]:_(<4 x s16>) = G_SUB [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[sub]](<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@@ -225,8 +230,8 @@ body: |
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x s8>) = COPY $d3
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY2]](<8 x s8>), [[COPY3]]
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s8>) = G_SUB [[ICMP]], [[ICMP1]]
- ; CHECK-NEXT: $d0 = COPY [[SUB]](<8 x s8>)
+ ; CHECK-NEXT: [[sub:%[0-9]+]]:_(<8 x s8>) = G_SUB [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[sub]](<8 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@@ -255,8 +260,8 @@ body: |
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY $q3
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY2]](<16 x s8>), [[COPY3]]
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[ICMP]], [[ICMP1]]
- ; CHECK-NEXT: $q0 = COPY [[SUB]](<16 x s8>)
+ ; CHECK-NEXT: [[sub:%[0-9]+]]:_(<16 x s8>) = G_SUB [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $q0 = COPY [[sub]](<16 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
index e6293e72f547fb2..9dbbd1454154620 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
@@ -18,7 +18,9 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY1]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[UADDO1]](s32), [[C]], [[UADDO]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[C]], [[UADDO]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -46,7 +48,9 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY1]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[UADDO1]](s32), [[C]], [[UADDO]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[C]], [[UADDO]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
@@ -79,7 +83,9 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C1]], [[ADD]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[ADD]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
@@ -115,7 +121,9 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C1]], [[ADD]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[ADD]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
@@ -154,7 +162,9 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY2]], [[ADD]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[COPY2]], [[ADD]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
index 11f1f09cbbe0f31..fcd50131dc75e98 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
@@ -11,11 +11,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY]], [[COPY2]], [[AND]]
- ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDE1]], [[C]]
+ ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], [[AND1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[UADDE3]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
; CHECK-NEXT: $x1 = COPY [[UADDE2]](s64)
@@ -46,12 +47,14 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY]], [[COPY1]], [[AND]]
- ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], [[UADDE1]]
- ; CHECK-NEXT: [[UADDE4:%[0-9]+]]:_(s64), [[UADDE5:%[0-9]+]]:_(s32) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE3]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDE1]], [[C]]
+ ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], [[AND1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UADDE3]], [[C]]
+ ; CHECK-NEXT: [[UADDE4:%[0-9]+]]:_(s64), [[UADDE5:%[0-9]+]]:_(s32) = G_UADDE [[COPY2]], [[COPY3]], [[AND2]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[UADDE5]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDE]](s64)
; CHECK-NEXT: $x1 = COPY [[UADDE2]](s64)
@@ -82,13 +85,13 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C1]]
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[AND]], [[AND1]], [[AND2]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UADDE]], [[C]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
index 7628233a6addc6a..f646c6b053f173e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
@@ -11,7 +11,9 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY2]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], [[UADDO1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY3]], [[AND]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[UADDE1]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
@@ -40,8 +42,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], [[UADDO1]]
- ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UADDO1]], [[C]]
+ ; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[COPY1]], [[COPY2]], [[AND]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UADDE1]], [[C]]
+ ; CHECK-NEXT: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s32) = G_UADDE [[COPY2]], [[COPY3]], [[AND1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[UADDE3]](s32)
; CHECK-NEXT: $x0 = COPY [[UADDO]](s64)
; CHECK-NEXT: $x1 = COPY [[UADDE]](s64)
@@ -69,8 +74,8 @@ body: |
; CHECK-LABEL: name: test_scalar_uaddo_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
index 784dc389af58b9b..5fc30343b42f995 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
@@ -18,7 +18,9 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY1]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[USUBO1]](s32), [[C]], [[USUBO]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[C]], [[USUBO]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
@@ -46,7 +48,9 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY1]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[USUBO1]](s32), [[C]], [[USUBO]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[C]], [[USUBO]]
; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
@@ -79,7 +83,9 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C1]], [[SUB]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[SUB]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
@@ -115,7 +121,9 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C1]], [[SUB]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[SUB]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
@@ -151,7 +159,9 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C1]], [[SUB]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[SUB]]
; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
index a9c0f3135b4205f..ca9fef41e45b54f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
@@ -11,11 +11,12 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY]], [[COPY2]], [[AND]]
- ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY3]], [[USUBE1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[USUBE1]], [[C]]
+ ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY3]], [[AND1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[USUBE3]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
; CHECK-NEXT: $x1 = COPY [[USUBE2]](s64)
@@ -46,12 +47,14 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY]], [[COPY1]], [[AND]]
- ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], [[USUBE1]]
- ; CHECK-NEXT: [[USUBE4:%[0-9]+]]:_(s64), [[USUBE5:%[0-9]+]]:_(s32) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE3]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[USUBE1]], [[C]]
+ ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], [[AND1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[USUBE3]], [[C]]
+ ; CHECK-NEXT: [[USUBE4:%[0-9]+]]:_(s64), [[USUBE5:%[0-9]+]]:_(s32) = G_USUBE [[COPY2]], [[COPY3]], [[AND2]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[USUBE5]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBE]](s64)
; CHECK-NEXT: $x1 = COPY [[USUBE2]](s64)
@@ -82,13 +85,13 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C1]]
; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[AND]], [[AND1]], [[AND2]]
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[USUBE]], [[C]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
index 30faa53d89362e5..34eabeebe5169d5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
@@ -11,7 +11,9 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY2]]
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY3]], [[USUBO1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY3]], [[AND]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[USUBE1]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
@@ -40,8 +42,11 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s32) = G_USUBO [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
- ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[USUBO1]], [[C]]
+ ; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s32) = G_USUBE [[COPY1]], [[COPY2]], [[AND]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[USUBE1]], [[C]]
+ ; CHECK-NEXT: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s32) = G_USUBE [[COPY2]], [[COPY3]], [[AND1]]
; CHECK-NEXT: %carry_out_ext:_(s64) = G_ANYEXT [[USUBE3]](s32)
; CHECK-NEXT: $x0 = COPY [[USUBO]](s64)
; CHECK-NEXT: $x1 = COPY [[USUBE]](s64)
@@ -69,8 +74,8 @@ body: |
; CHECK-LABEL: name: test_scalar_usubo_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
index 0982d9a0218b722..3fc7505e44e04ea 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
@@ -17,8 +17,8 @@ body: |
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI %33(s16), %bb.2, [[DEF]](s16), %bb.0
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 46
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[C1]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir b/llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir
index 242b09546522b32..b39cdabb03f268a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir
@@ -10,7 +10,8 @@ body: |
; CHECK: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ogt), [[COPY]](s32), [[COPY1]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C]]
- ; CHECK: $w0 = COPY [[AND]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
+ ; CHECK: $w0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s1) = G_FCMP floatpred(ogt), %0(s32), %1
diff --git a/llvm/test/CodeGen/AArch64/zext.ll b/llvm/test/CodeGen/AArch64/zext.ll
index f43f31efc9a7135..8b30ee257ad2055 100644
--- a/llvm/test/CodeGen/AArch64/zext.ll
+++ b/llvm/test/CodeGen/AArch64/zext.ll
@@ -1200,7 +1200,7 @@ define <16 x i64> @zext_v16i10_v16i64(<16 x i10> %a) {
;
; CHECK-GI-LABEL: zext_v16i10_v16i64:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: fmov s16, w0
+; CHECK-GI-NEXT: fmov s7, w0
; CHECK-GI-NEXT: fmov s17, w2
; CHECK-GI-NEXT: ldr s0, [sp]
; CHECK-GI-NEXT: fmov s18, w4
@@ -1211,33 +1211,33 @@ define <16 x i64> @zext_v16i10_v16i64(<16 x i10> %a) {
; CHECK-GI-NEXT: ldr s4, [sp, #32]
; CHECK-GI-NEXT: ldr s5, [sp, #40]
; CHECK-GI-NEXT: ldr s6, [sp, #48]
-; CHECK-GI-NEXT: ldr s7, [sp, #56]
-; CHECK-GI-NEXT: mov v16.s[1], w1
+; CHECK-GI-NEXT: ldr s16, [sp, #56]
+; CHECK-GI-NEXT: mov v7.s[1], w1
; CHECK-GI-NEXT: mov v17.s[1], w3
; CHECK-GI-NEXT: mov v18.s[1], w5
; CHECK-GI-NEXT: mov v19.s[1], w7
; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
; CHECK-GI-NEXT: mov v2.s[1], v3.s[0]
; CHECK-GI-NEXT: mov v4.s[1], v5.s[0]
-; CHECK-GI-NEXT: mov v6.s[1], v7.s[0]
+; CHECK-GI-NEXT: mov v6.s[1], v16.s[0]
; CHECK-GI-NEXT: adrp x8, .LCPI54_0
-; CHECK-GI-NEXT: ushll v1.2d, v16.2s, #0
+; CHECK-GI-NEXT: ldr q16, [x8, :lo12:.LCPI54_0]
+; CHECK-GI-NEXT: ushll v1.2d, v7.2s, #0
; CHECK-GI-NEXT: ushll v3.2d, v17.2s, #0
; CHECK-GI-NEXT: ushll v5.2d, v18.2s, #0
; CHECK-GI-NEXT: ushll v7.2d, v19.2s, #0
-; CHECK-GI-NEXT: ushll v16.2d, v0.2s, #0
+; CHECK-GI-NEXT: ushll v17.2d, v0.2s, #0
; CHECK-GI-NEXT: ushll v18.2d, v2.2s, #0
; CHECK-GI-NEXT: ushll v19.2d, v4.2s, #0
; CHECK-GI-NEXT: ushll v20.2d, v6.2s, #0
-; CHECK-GI-NEXT: ldr q17, [x8, :lo12:.LCPI54_0]
-; CHECK-GI-NEXT: and v0.16b, v1.16b, v17.16b
-; CHECK-GI-NEXT: and v1.16b, v3.16b, v17.16b
-; CHECK-GI-NEXT: and v2.16b, v5.16b, v17.16b
-; CHECK-GI-NEXT: and v3.16b, v7.16b, v17.16b
-; CHECK-GI-NEXT: and v4.16b, v16.16b, v17.16b
-; CHECK-GI-NEXT: and v5.16b, v18.16b, v17.16b
-; CHECK-GI-NEXT: and v6.16b, v19.16b, v17.16b
-; CHECK-GI-NEXT: and v7.16b, v20.16b, v17.16b
+; CHECK-GI-NEXT: and v0.16b, v1.16b, v16.16b
+; CHECK-GI-NEXT: and v1.16b, v3.16b, v16.16b
+; CHECK-GI-NEXT: and v2.16b, v5.16b, v16.16b
+; CHECK-GI-NEXT: and v3.16b, v7.16b, v16.16b
+; CHECK-GI-NEXT: and v4.16b, v17.16b, v16.16b
+; CHECK-GI-NEXT: and v5.16b, v18.16b, v16.16b
+; CHECK-GI-NEXT: and v6.16b, v19.16b, v16.16b
+; CHECK-GI-NEXT: and v7.16b, v20.16b, v16.16b
; CHECK-GI-NEXT: ret
entry:
%c = zext <16 x i10> %a to <16 x i64>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-cse-leaves-dead-cast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-cse-leaves-dead-cast.mir
index bd2f5181fd525de..b99b4cf54c5b3dd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-cse-leaves-dead-cast.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-cse-leaves-dead-cast.mir
@@ -50,8 +50,8 @@ body: |
; CHECK-NEXT: %and5:_(s1) = G_XOR %unmerge3_5, %negone
; CHECK-NEXT: %and6:_(s1) = G_XOR %unmerge3_6, %negone
; CHECK-NEXT: %and7:_(s1) = G_XOR %unmerge3_7, %negone
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT %and0(s1)
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT %and0(s1)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT]], [[C10]]
; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT %and1(s1)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SEXT1]], [[C10]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
index 3b456ed248b3af9..2ff6433b362d69c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
@@ -139,7 +139,8 @@ body: |
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[LSHR]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr0_vgpr1
@@ -548,9 +549,11 @@ body: |
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[LSHR]](s32)
- ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND1]](s32), [[LSHR1]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
+ ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND2]](s32), [[AND3]](s32)
; CHECK-NEXT: S_ENDPGM 0, implicit [[MV]](s64), implicit [[MV1]](s64)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
@@ -1302,8 +1305,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[COPY]](<4 x s64>)
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](<2 x s64>)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV2]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV2]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
@@ -1450,8 +1453,8 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY2]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY2]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s1)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s1)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP1]](s1)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
index 7334ae71d63cf9b..6f866ea47856968 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
@@ -31,10 +31,10 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C]]
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[AND]](s64), [[AND1]](s64)
@@ -55,13 +55,13 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C1]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[SHL]]
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[TRUNC]], [[BITCAST]]
; CHECK-NEXT: $vgpr0 = COPY [[AND]](<2 x s16>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
@@ -134,8 +134,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT]], [[C]]
; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
@@ -158,8 +158,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT]], [[C]]
; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
@@ -181,8 +181,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 8
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 8
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C]]
; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
@@ -209,12 +209,12 @@ body: |
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV1]](s32), [[UV3]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
@@ -241,12 +241,12 @@ body: |
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV1]](s32), [[UV3]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
@@ -269,12 +269,12 @@ body: |
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 8
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 8
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<2 x s8>) = G_LOAD %0 :: (load (<2 x s8>), addrspace 1)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index dd13b257ea67b95..139bb40daa930a8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -1327,9 +1327,9 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v2
; GFX9-NEXT: v_and_b32_e32 v8, 7, v2
; GFX9-NEXT: v_not_b32_e32 v2, v2
-; GFX9-NEXT: s_mov_b32 s4, 1
+; GFX9-NEXT: s_mov_b32 s5, 1
; GFX9-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX9-NEXT: v_lshrrev_b16_sdwa v10, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshrrev_b16_sdwa v10, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_lshlrev_b16_e32 v8, v8, v0
; GFX9-NEXT: v_lshrrev_b16_e32 v2, v2, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 8, v1
@@ -1338,7 +1338,7 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX9-NEXT: v_not_b32_e32 v5, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v0
; GFX9-NEXT: v_and_b32_e32 v5, 7, v5
-; GFX9-NEXT: v_lshrrev_b16_sdwa v4, s4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshrrev_b16_sdwa v4, s5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_mov_b32_e32 v9, 0xff
; GFX9-NEXT: v_lshlrev_b16_e32 v3, v8, v3
; GFX9-NEXT: v_lshrrev_b16_e32 v4, v5, v4
@@ -1360,9 +1360,9 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX9-NEXT: v_lshrrev_b16_e32 v1, v6, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 8
-; GFX9-NEXT: s_movk_i32 s5, 0xff
+; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_and_or_b32 v1, v2, s5, v1
+; GFX9-NEXT: v_and_or_b32 v1, v2, s4, v1
; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
@@ -1807,47 +1807,48 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 inreg %amt.arg) {
; GFX6-LABEL: s_fshl_v2i24:
; GFX6: ; %bb.0:
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_lshr_b32 s6, s0, 16
; GFX6-NEXT: s_lshr_b32 s7, s0, 24
; GFX6-NEXT: s_and_b32 s9, s0, 0xff
; GFX6-NEXT: s_bfe_u32 s0, s0, 0x80008
-; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX6-NEXT: s_lshl_b32 s0, s0, 8
; GFX6-NEXT: s_and_b32 s6, s6, 0xff
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_or_b32 s0, s9, s0
; GFX6-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: s_lshr_b32 s8, s1, 8
; GFX6-NEXT: s_and_b32 s0, 0xffff, s0
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_and_b32 s1, s1, 0xff
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_or_b32 s0, s0, s6
; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_and_b32 s6, s8, 0xff
; GFX6-NEXT: s_or_b32 s1, s7, s1
; GFX6-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX6-NEXT: s_and_b32 s1, 0xffff, s1
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX6-NEXT: s_or_b32 s1, s1, s6
; GFX6-NEXT: s_lshr_b32 s6, s2, 16
; GFX6-NEXT: s_lshr_b32 s7, s2, 24
; GFX6-NEXT: s_and_b32 s9, s2, 0xff
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x80008
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, v1
; GFX6-NEXT: s_lshl_b32 s2, s2, 8
; GFX6-NEXT: s_and_b32 s6, s6, 0xff
; GFX6-NEXT: s_or_b32 s2, s9, s2
; GFX6-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX6-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX6-NEXT: s_lshr_b32 s8, s3, 8
; GFX6-NEXT: s_and_b32 s2, 0xffff, s2
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_and_b32 s3, s3, 0xff
-; GFX6-NEXT: v_mul_lo_u32 v3, v1, v2
; GFX6-NEXT: s_or_b32 s2, s2, s6
; GFX6-NEXT: s_lshl_b32 s3, s3, 8
; GFX6-NEXT: s_and_b32 s6, s8, 0xff
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: s_or_b32 s3, s7, s3
; GFX6-NEXT: s_and_b32 s6, 0xffff, s6
; GFX6-NEXT: s_and_b32 s3, 0xffff, s3
@@ -1857,77 +1858,78 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_lshr_b32 s7, s4, 24
; GFX6-NEXT: s_and_b32 s9, s4, 0xff
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x80008
-; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: s_lshl_b32 s4, s4, 8
; GFX6-NEXT: s_and_b32 s6, s6, 0xff
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX6-NEXT: s_or_b32 s4, s9, s4
; GFX6-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX6-NEXT: s_and_b32 s4, 0xffff, s4
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_or_b32 s4, s4, s6
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT: v_mul_hi_u32 v1, s4, v1
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX6-NEXT: s_lshr_b32 s8, s5, 8
-; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX6-NEXT: s_and_b32 s5, s5, 0xff
-; GFX6-NEXT: v_mul_lo_u32 v2, v0, v2
+; GFX6-NEXT: v_mul_lo_u32 v1, v2, v1
; GFX6-NEXT: s_lshl_b32 s5, s5, 8
-; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s4, v1
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v1
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX6-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX6-NEXT: s_and_b32 s6, s8, 0xff
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: s_or_b32 s5, s7, s5
; GFX6-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v1
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v0
; GFX6-NEXT: s_and_b32 s5, 0xffff, s5
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX6-NEXT: s_or_b32 s5, s5, s6
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v1
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffffff, v1
-; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX6-NEXT: v_lshl_b32_e32 v1, s0, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0
; GFX6-NEXT: s_lshr_b32 s0, s2, 1
; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v3
; GFX6-NEXT: v_lshr_b32_e32 v2, s0, v2
-; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
-; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v0
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v1
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX6-NEXT: s_lshr_b32 s0, s3, 1
; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX6-NEXT: v_lshl_b32_e32 v0, s1, v0
+; GFX6-NEXT: v_lshl_b32_e32 v1, s1, v1
; GFX6-NEXT: v_lshr_b32_e32 v2, s0, v2
-; GFX6-NEXT: v_bfe_u32 v3, v1, 8, 8
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; GFX6-NEXT: v_bfe_u32 v3, v0, 8, 8
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_bfe_u32 v2, v0, 8, 8
+; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v1
-; GFX6-NEXT: v_readfirstlane_b32 s1, v0
+; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: v_bfe_u32 v2, v1, 8, 8
+; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_fshl_v2i24:
@@ -1940,7 +1942,9 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_lshl_b32 s6, s6, 8
; GFX8-NEXT: s_or_b32 s0, s0, s6
; GFX8-NEXT: s_and_b32 s6, s7, 0xff
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_lshr_b32 s9, s1, 8
; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
@@ -1948,24 +1952,24 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_or_b32 s0, s0, s6
; GFX8-NEXT: s_lshl_b32 s1, s1, 8
; GFX8-NEXT: s_and_b32 s6, s9, 0xff
-; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX8-NEXT: s_or_b32 s1, s8, s1
; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
+; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: s_or_b32 s1, s1, s6
; GFX8-NEXT: s_lshr_b32 s6, s2, 8
+; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_and_b32 s6, s6, 0xff
; GFX8-NEXT: s_lshr_b32 s7, s2, 16
; GFX8-NEXT: s_lshr_b32 s8, s2, 24
; GFX8-NEXT: s_and_b32 s2, s2, 0xff
; GFX8-NEXT: s_lshl_b32 s6, s6, 8
-; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX8-NEXT: s_or_b32 s2, s2, s6
; GFX8-NEXT: s_and_b32 s6, s7, 0xff
-; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX8-NEXT: v_mul_lo_u32 v2, v0, v1
; GFX8-NEXT: s_lshr_b32 s9, s3, 8
; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
@@ -1973,12 +1977,11 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_or_b32 s2, s2, s6
; GFX8-NEXT: s_lshl_b32 s3, s3, 8
; GFX8-NEXT: s_and_b32 s6, s9, 0xff
-; GFX8-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX8-NEXT: s_or_b32 s3, s8, s3
; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX8-NEXT: v_mul_lo_u32 v3, v1, v2
; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
+; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX8-NEXT: s_or_b32 s3, s3, s6
; GFX8-NEXT: s_lshr_b32 s6, s4, 8
; GFX8-NEXT: s_and_b32 s6, s6, 0xff
@@ -1986,207 +1989,212 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_lshr_b32 s8, s4, 24
; GFX8-NEXT: s_and_b32 s4, s4, 0xff
; GFX8-NEXT: s_lshl_b32 s6, s6, 8
-; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX8-NEXT: s_or_b32 s4, s4, s6
; GFX8-NEXT: s_and_b32 s6, s7, 0xff
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX8-NEXT: s_and_b32 s4, 0xffff, s4
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
; GFX8-NEXT: s_or_b32 s4, s4, s6
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
-; GFX8-NEXT: v_mul_hi_u32 v1, s4, v1
-; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX8-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX8-NEXT: s_lshr_b32 s9, s5, 8
-; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX8-NEXT: s_and_b32 s5, s5, 0xff
-; GFX8-NEXT: v_mul_lo_u32 v2, v0, v2
+; GFX8-NEXT: v_mul_lo_u32 v1, v2, v1
; GFX8-NEXT: s_lshl_b32 s5, s5, 8
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s4, v1
-; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v1
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v0
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX8-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX8-NEXT: s_and_b32 s6, s9, 0xff
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: s_or_b32 s5, s8, s5
; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v1
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v0
; GFX8-NEXT: s_and_b32 s5, 0xffff, s5
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX8-NEXT: s_or_b32 s5, s5, s6
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
-; GFX8-NEXT: v_mul_hi_u32 v0, s5, v0
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v1
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1
-; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX8-NEXT: v_lshlrev_b32_e64 v1, v1, s0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1
+; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX8-NEXT: v_lshlrev_b32_e64 v0, v0, s0
; GFX8-NEXT: s_lshr_b32 s0, s2, 1
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v3
; GFX8-NEXT: v_lshrrev_b32_e64 v2, v2, s0
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s5, v0
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v0
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX8-NEXT: s_lshr_b32 s0, s3, 1
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX8-NEXT: v_lshlrev_b32_e64 v0, v0, s1
+; GFX8-NEXT: v_lshlrev_b32_e64 v1, v1, s1
; GFX8-NEXT: v_lshrrev_b32_e64 v2, v2, s0
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_mov_b32_e32 v2, 8
-; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX8-NEXT: v_mov_b32_e32 v4, 16
-; GFX8-NEXT: v_or_b32_sdwa v3, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-; GFX8-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX8-NEXT: v_and_b32_e32 v3, 0xff, v0
+; GFX8-NEXT: v_or_b32_sdwa v3, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX8-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX8-NEXT: v_and_b32_e32 v3, 0xff, v1
; GFX8-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX8-NEXT: v_readfirstlane_b32 s0, v1
-; GFX8-NEXT: v_readfirstlane_b32 s1, v0
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
+; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_fshl_v2i24:
; GFX9: ; %bb.0:
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_lshr_b32 s7, s0, 8
; GFX9-NEXT: s_and_b32 s7, s7, 0xff
; GFX9-NEXT: s_lshr_b32 s9, s0, 16
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_lshr_b32 s10, s0, 24
; GFX9-NEXT: s_and_b32 s0, s0, 0xff
; GFX9-NEXT: s_lshl_b32 s7, s7, 8
; GFX9-NEXT: s_or_b32 s0, s0, s7
; GFX9-NEXT: s_and_b32 s7, s9, 0xff
; GFX9-NEXT: s_and_b32 s7, 0xffff, s7
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX9-NEXT: s_lshr_b32 s11, s1, 8
; GFX9-NEXT: s_and_b32 s0, 0xffff, s0
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: v_mul_lo_u32 v2, v0, v1
; GFX9-NEXT: s_or_b32 s0, s0, s7
; GFX9-NEXT: s_lshl_b32 s1, s1, 8
; GFX9-NEXT: s_and_b32 s7, s11, 0xff
-; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX9-NEXT: s_or_b32 s1, s10, s1
; GFX9-NEXT: s_and_b32 s7, 0xffff, s7
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
; GFX9-NEXT: s_or_b32 s1, s1, s7
; GFX9-NEXT: s_lshr_b32 s7, s2, 8
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: s_and_b32 s7, s7, 0xff
; GFX9-NEXT: s_lshr_b32 s9, s2, 16
; GFX9-NEXT: s_lshr_b32 s10, s2, 24
; GFX9-NEXT: s_and_b32 s2, s2, 0xff
; GFX9-NEXT: s_lshl_b32 s7, s7, 8
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX9-NEXT: s_or_b32 s2, s2, s7
; GFX9-NEXT: s_and_b32 s7, s9, 0xff
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_and_b32 s7, 0xffff, s7
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX9-NEXT: s_lshr_b32 s11, s3, 8
; GFX9-NEXT: s_and_b32 s2, 0xffff, s2
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
; GFX9-NEXT: s_and_b32 s3, s3, 0xff
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX9-NEXT: s_or_b32 s2, s2, s7
; GFX9-NEXT: s_lshl_b32 s3, s3, 8
; GFX9-NEXT: s_and_b32 s7, s11, 0xff
-; GFX9-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX9-NEXT: s_or_b32 s3, s10, s3
; GFX9-NEXT: s_and_b32 s7, 0xffff, s7
-; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
; GFX9-NEXT: s_and_b32 s3, 0xffff, s3
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
; GFX9-NEXT: s_or_b32 s3, s3, s7
; GFX9-NEXT: s_lshr_b32 s7, s4, 8
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX9-NEXT: s_and_b32 s7, s7, 0xff
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT: s_lshr_b32 s9, s4, 16
; GFX9-NEXT: s_lshr_b32 s10, s4, 24
; GFX9-NEXT: s_and_b32 s4, s4, 0xff
; GFX9-NEXT: s_lshl_b32 s7, s7, 8
-; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: s_or_b32 s4, s4, s7
; GFX9-NEXT: s_and_b32 s7, s9, 0xff
; GFX9-NEXT: s_and_b32 s7, 0xffff, s7
; GFX9-NEXT: s_and_b32 s4, 0xffff, s4
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
-; GFX9-NEXT: v_mul_lo_u32 v2, v0, v2
+; GFX9-NEXT: v_mul_lo_u32 v1, v2, v1
; GFX9-NEXT: s_or_b32 s4, s4, s7
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT: v_mul_hi_u32 v1, s4, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX9-NEXT: s_lshr_b32 s11, s5, 8
; GFX9-NEXT: s_and_b32 s5, s5, 0xff
-; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX9-NEXT: s_lshl_b32 s5, s5, 8
; GFX9-NEXT: s_and_b32 s7, s11, 0xff
; GFX9-NEXT: s_or_b32 s5, s10, s5
; GFX9-NEXT: s_and_b32 s7, 0xffff, s7
-; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX9-NEXT: s_and_b32 s5, 0xffff, s5
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
; GFX9-NEXT: s_or_b32 s5, s5, s7
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
-; GFX9-NEXT: v_mul_hi_u32 v0, s5, v0
-; GFX9-NEXT: v_sub_u32_e32 v1, s4, v1
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX9-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX9-NEXT: v_sub_u32_e32 v2, 23, v1
-; GFX9-NEXT: s_lshr_b32 s2, s2, 1
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1
-; GFX9-NEXT: v_lshrrev_b32_e64 v2, v2, s2
-; GFX9-NEXT: v_sub_u32_e32 v0, s5, v0
-; GFX9-NEXT: v_lshl_or_b32 v1, s0, v1, v2
-; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v0
+; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
+; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_sub_u32_e32 v2, 23, v0
-; GFX9-NEXT: s_lshr_b32 s0, s3, 1
+; GFX9-NEXT: s_lshr_b32 s2, s2, 1
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX9-NEXT: v_lshrrev_b32_e64 v2, v2, s2
+; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, s0, v0, v2
+; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_sub_u32_e32 v2, 23, v1
+; GFX9-NEXT: s_lshr_b32 s0, s3, 1
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX9-NEXT: v_lshrrev_b32_e64 v2, v2, s0
; GFX9-NEXT: s_mov_b32 s6, 8
-; GFX9-NEXT: v_lshl_or_b32 v0, s1, v0, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, s1, v1, v2
; GFX9-NEXT: s_mov_b32 s8, 16
; GFX9-NEXT: s_movk_i32 s0, 0xff
-; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX9-NEXT: v_and_b32_e32 v3, 0xff, v0
-; GFX9-NEXT: v_and_or_b32 v2, v1, s0, v2
-; GFX9-NEXT: v_lshlrev_b32_sdwa v1, s8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX9-NEXT: v_and_b32_e32 v3, 0xff, v1
+; GFX9-NEXT: v_and_or_b32 v2, v0, s0, v2
+; GFX9-NEXT: v_lshlrev_b32_sdwa v0, s8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX9-NEXT: v_or3_b32 v1, v2, v1, v3
-; GFX9-NEXT: v_bfe_u32 v2, v0, 8, 8
-; GFX9-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v2
-; GFX9-NEXT: v_readfirstlane_b32 s0, v1
-; GFX9-NEXT: v_readfirstlane_b32 s1, v0
+; GFX9-NEXT: v_or3_b32 v0, v2, v0, v3
+; GFX9-NEXT: v_bfe_u32 v2, v1, 8, 8
+; GFX9-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 8, v2
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_fshl_v2i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
; GFX10-NEXT: s_lshr_b32 s6, s0, 8
; GFX10-NEXT: s_lshr_b32 s7, s0, 16
; GFX10-NEXT: s_and_b32 s6, s6, 0xff
-; GFX10-NEXT: s_lshr_b32 s8, s0, 24
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX10-NEXT: s_lshr_b32 s8, s0, 24
; GFX10-NEXT: s_and_b32 s0, s0, 0xff
; GFX10-NEXT: s_lshl_b32 s6, s6, 8
; GFX10-NEXT: s_and_b32 s7, s7, 0xff
@@ -2194,251 +2202,244 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX10-NEXT: s_and_b32 s6, 0xffff, s7
; GFX10-NEXT: s_lshr_b32 s7, s4, 8
; GFX10-NEXT: s_lshr_b32 s10, s4, 16
+; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: s_and_b32 s7, s7, 0xff
; GFX10-NEXT: s_lshr_b32 s11, s4, 24
-; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: s_and_b32 s4, s4, 0xff
+; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: s_lshl_b32 s7, s7, 8
; GFX10-NEXT: s_lshr_b32 s12, s5, 8
-; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: s_or_b32 s4, s4, s7
+; GFX10-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v0
+; GFX10-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v1
; GFX10-NEXT: s_and_b32 s7, s10, 0xff
; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX10-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v1
-; GFX10-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v0
; GFX10-NEXT: s_and_b32 s7, 0xffff, s7
; GFX10-NEXT: s_and_b32 s5, s5, 0xff
; GFX10-NEXT: s_lshl_b32 s7, s7, 16
; GFX10-NEXT: s_lshl_b32 s5, s5, 8
+; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX10-NEXT: s_or_b32 s4, s4, s7
; GFX10-NEXT: s_and_b32 s7, s12, 0xff
-; GFX10-NEXT: v_mul_hi_u32 v2, v1, v2
-; GFX10-NEXT: v_mul_hi_u32 v3, v0, v3
; GFX10-NEXT: s_or_b32 s5, s11, s5
; GFX10-NEXT: s_and_b32 s7, 0xffff, s7
; GFX10-NEXT: s_and_b32 s5, 0xffff, s5
; GFX10-NEXT: s_lshl_b32 s7, s7, 16
-; GFX10-NEXT: s_lshr_b32 s9, s1, 8
+; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
+; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3
; GFX10-NEXT: s_or_b32 s5, s5, s7
-; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; GFX10-NEXT: s_lshr_b32 s9, s1, 8
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
-; GFX10-NEXT: s_and_b32 s7, s9, 0xff
+; GFX10-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX10-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX10-NEXT: s_lshl_b32 s1, s1, 8
-; GFX10-NEXT: v_mul_hi_u32 v1, s4, v1
-; GFX10-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX10-NEXT: s_and_b32 s7, s9, 0xff
; GFX10-NEXT: s_or_b32 s1, s8, s1
; GFX10-NEXT: s_lshr_b32 s8, s2, 8
; GFX10-NEXT: s_lshr_b32 s9, s2, 16
; GFX10-NEXT: s_and_b32 s8, s8, 0xff
+; GFX10-NEXT: v_mul_lo_u32 v0, v0, 24
+; GFX10-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX10-NEXT: s_lshr_b32 s10, s2, 24
; GFX10-NEXT: s_and_b32 s2, s2, 0xff
-; GFX10-NEXT: v_mul_lo_u32 v1, v1, 24
-; GFX10-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX10-NEXT: s_lshl_b32 s8, s8, 8
; GFX10-NEXT: s_and_b32 s7, 0xffff, s7
; GFX10-NEXT: s_or_b32 s2, s2, s8
; GFX10-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX10-NEXT: s_and_b32 s2, 0xffff, s2
-; GFX10-NEXT: s_lshl_b32 s6, s6, 16
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, s4, v1
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, s5, v0
+; GFX10-NEXT: v_sub_nc_u32_e32 v0, s4, v0
+; GFX10-NEXT: v_sub_nc_u32_e32 v1, s5, v1
; GFX10-NEXT: s_lshr_b32 s4, s3, 8
; GFX10-NEXT: s_and_b32 s5, s9, 0xff
; GFX10-NEXT: s_and_b32 s3, s3, 0xff
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
-; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v0
+; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
+; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v1
; GFX10-NEXT: s_and_b32 s5, 0xffff, s5
; GFX10-NEXT: s_lshl_b32 s3, s3, 8
; GFX10-NEXT: s_and_b32 s4, s4, 0xff
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
+; GFX10-NEXT: s_and_b32 s2, 0xffff, s2
; GFX10-NEXT: s_lshl_b32 s5, s5, 16
; GFX10-NEXT: s_or_b32 s3, s10, s3
+; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX10-NEXT: s_or_b32 s2, s2, s5
; GFX10-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX10-NEXT: s_lshl_b32 s4, s4, 16
-; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
-; GFX10-NEXT: s_or_b32 s3, s3, s4
; GFX10-NEXT: s_lshr_b32 s2, s2, 1
+; GFX10-NEXT: s_or_b32 s3, s3, s4
+; GFX10-NEXT: v_sub_nc_u32_e32 v2, 23, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX10-NEXT: s_lshl_b32 s6, s6, 16
; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX10-NEXT: v_sub_nc_u32_e32 v2, 23, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v1
; GFX10-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX10-NEXT: s_lshl_b32 s7, s7, 16
; GFX10-NEXT: s_or_b32 s0, s0, s6
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v0
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffffff, v0
-; GFX10-NEXT: s_or_b32 s1, s1, s7
; GFX10-NEXT: v_lshrrev_b32_e64 v2, v2, s2
; GFX10-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX10-NEXT: s_lshr_b32 s2, s3, 1
-; GFX10-NEXT: v_lshl_or_b32 v1, s0, v1, v2
+; GFX10-NEXT: s_or_b32 s1, s1, s7
+; GFX10-NEXT: v_lshl_or_b32 v0, s0, v0, v2
; GFX10-NEXT: v_lshrrev_b32_e64 v3, v3, s2
; GFX10-NEXT: s_mov_b32 s0, 8
-; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX10-NEXT: v_lshl_or_b32 v0, s1, v0, v3
+; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX10-NEXT: v_lshl_or_b32 v1, s1, v1, v3
; GFX10-NEXT: s_mov_b32 s0, 16
-; GFX10-NEXT: v_and_or_b32 v2, v1, 0xff, v2
-; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v0
-; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-; GFX10-NEXT: v_bfe_u32 v4, v0, 8, 8
-; GFX10-NEXT: v_bfe_u32 v0, v0, 16, 8
+; GFX10-NEXT: v_and_or_b32 v2, v0, 0xff, v2
+; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v1
+; GFX10-NEXT: v_lshlrev_b32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX10-NEXT: v_bfe_u32 v4, v1, 8, 8
+; GFX10-NEXT: v_bfe_u32 v1, v1, 16, 8
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v4
-; GFX10-NEXT: v_or3_b32 v1, v2, v1, v3
-; GFX10-NEXT: v_readfirstlane_b32 s1, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v1
+; GFX10-NEXT: v_lshl_or_b32 v1, v1, 8, v4
+; GFX10-NEXT: v_or3_b32 v0, v2, v0, v3
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_fshl_v2i24:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
; GFX11-NEXT: s_lshr_b32 s6, s0, 8
; GFX11-NEXT: s_lshr_b32 s7, s0, 16
; GFX11-NEXT: s_and_b32 s6, s6, 0xff
-; GFX11-NEXT: s_lshr_b32 s8, s0, 24
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX11-NEXT: s_lshr_b32 s8, s0, 24
; GFX11-NEXT: s_and_b32 s0, s0, 0xff
; GFX11-NEXT: s_lshl_b32 s6, s6, 8
-; GFX11-NEXT: s_and_b32 s7, s7, 0xff
+; GFX11-NEXT: s_lshr_b32 s10, s4, 24
; GFX11-NEXT: s_or_b32 s0, s0, s6
-; GFX11-NEXT: s_and_b32 s6, 0xffff, s7
+; GFX11-NEXT: s_and_b32 s6, s7, 0xff
; GFX11-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX11-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_mul_f32 v1, 0x4f7ffffe, v1
; GFX11-NEXT: s_lshl_b32 s6, s6, 16
-; GFX11-NEXT: s_lshr_b32 s9, s4, 16
+; GFX11-NEXT: s_lshr_b32 s7, s4, 16
; GFX11-NEXT: s_or_b32 s0, s0, s6
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
-; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX11-NEXT: s_lshr_b32 s6, s4, 8
-; GFX11-NEXT: s_lshr_b32 s10, s4, 24
-; GFX11-NEXT: s_and_b32 s6, s6, 0xff
; GFX11-NEXT: s_and_b32 s4, s4, 0xff
-; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-NEXT: s_and_b32 s6, s6, 0xff
+; GFX11-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v0
+; GFX11-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v1
; GFX11-NEXT: s_lshl_b32 s6, s6, 8
-; GFX11-NEXT: s_lshr_b32 s11, s5, 8
+; GFX11-NEXT: s_and_b32 s7, s7, 0xff
; GFX11-NEXT: s_or_b32 s4, s4, s6
-; GFX11-NEXT: s_and_b32 s6, s9, 0xff
-; GFX11-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v0
-; GFX11-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX11-NEXT: s_and_b32 s6, 0xffff, s7
+; GFX11-NEXT: s_lshr_b32 s11, s5, 8
; GFX11-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX11-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX11-NEXT: s_lshl_b32 s6, s6, 16
; GFX11-NEXT: s_and_b32 s5, s5, 0xff
; GFX11-NEXT: s_or_b32 s4, s4, s6
; GFX11-NEXT: s_lshl_b32 s5, s5, 8
; GFX11-NEXT: s_and_b32 s6, s11, 0xff
-; GFX11-NEXT: v_mul_hi_u32 v3, v0, v3
; GFX11-NEXT: s_or_b32 s5, s10, s5
; GFX11-NEXT: s_and_b32 s6, 0xffff, s6
+; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v2
+; GFX11-NEXT: v_mul_hi_u32 v2, v1, v3
; GFX11-NEXT: s_and_b32 s5, 0xffff, s5
; GFX11-NEXT: s_lshl_b32 s6, s6, 16
-; GFX11-NEXT: s_lshr_b32 s7, s1, 8
+; GFX11-NEXT: s_lshr_b32 s9, s1, 8
+; GFX11-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX11-NEXT: s_or_b32 s5, s5, s6
; GFX11-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v3
-; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX11-NEXT: s_and_b32 s7, s9, 0xff
+; GFX11-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX11-NEXT: s_lshl_b32 s1, s1, 8
-; GFX11-NEXT: s_and_b32 s6, s7, 0xff
+; GFX11-NEXT: s_and_b32 s6, 0xffff, s7
; GFX11-NEXT: s_lshr_b32 s7, s2, 8
-; GFX11-NEXT: v_mul_hi_u32 v0, s5, v0
-; GFX11-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v1
+; GFX11-NEXT: v_mul_lo_u32 v0, v0, 24
+; GFX11-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX11-NEXT: s_or_b32 s1, s8, s1
; GFX11-NEXT: s_lshr_b32 s8, s2, 16
; GFX11-NEXT: s_and_b32 s7, s7, 0xff
-; GFX11-NEXT: s_lshr_b32 s9, s2, 24
-; GFX11-NEXT: s_and_b32 s2, s2, 0xff
+; GFX11-NEXT: s_lshr_b32 s9, s3, 8
; GFX11-NEXT: s_lshl_b32 s7, s7, 8
-; GFX11-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX11-NEXT: v_mul_hi_u32 v2, v1, v2
+; GFX11-NEXT: s_and_b32 s3, s3, 0xff
+; GFX11-NEXT: v_sub_nc_u32_e32 v0, s4, v0
+; GFX11-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX11-NEXT: s_lshr_b32 s4, s2, 24
+; GFX11-NEXT: s_and_b32 s2, s2, 0xff
+; GFX11-NEXT: s_lshl_b32 s3, s3, 8
+; GFX11-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX11-NEXT: s_or_b32 s2, s2, s7
-; GFX11-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX11-NEXT: s_and_b32 s2, 0xffff, s2
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_sub_nc_u32_e32 v0, s5, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v1, v1, v2
+; GFX11-NEXT: s_or_b32 s3, s4, s3
+; GFX11-NEXT: v_sub_nc_u32_e32 v1, s5, v1
; GFX11-NEXT: s_and_b32 s5, s8, 0xff
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX11-NEXT: s_and_b32 s5, 0xffff, s5
+; GFX11-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX11-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX11-NEXT: v_subrev_nc_u32_e32 v3, 24, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX11-NEXT: s_lshl_b32 s5, s5, 16
+; GFX11-NEXT: s_and_b32 s4, s9, 0xff
; GFX11-NEXT: s_or_b32 s2, s2, s5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: s_lshr_b32 s2, s2, 1
-; GFX11-NEXT: v_mul_lo_u32 v1, v1, 24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_sub_nc_u32_e32 v1, s4, v1
-; GFX11-NEXT: s_lshr_b32 s4, s3, 8
-; GFX11-NEXT: s_and_b32 s3, s3, 0xff
-; GFX11-NEXT: s_and_b32 s4, s4, 0xff
-; GFX11-NEXT: s_lshl_b32 s3, s3, 8
-; GFX11-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
-; GFX11-NEXT: s_or_b32 s3, s9, s3
-; GFX11-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX11-NEXT: s_and_b32 s3, 0xffff, s3
-; GFX11-NEXT: s_lshl_b32 s4, s4, 16
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
-; GFX11-NEXT: s_or_b32 s3, s3, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: s_lshr_b32 s3, s3, 1
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX11-NEXT: s_lshr_b32 s2, s2, 1
+; GFX11-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
; GFX11-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
-; GFX11-NEXT: v_subrev_nc_u32_e32 v3, 24, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_sub_nc_u32_e32 v2, 23, v1
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
+; GFX11-NEXT: s_lshl_b32 s6, s6, 16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_sub_nc_u32_e32 v3, 23, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffffff, v0
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffffff, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_and_b32 v0, 0xffffff, v0
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_sub_nc_u32_e32 v3, 23, v1
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX11-NEXT: v_lshrrev_b32_e64 v2, v2, s2
-; GFX11-NEXT: s_lshl_b32 s2, s6, 16
-; GFX11-NEXT: v_lshrrev_b32_e64 v3, v3, s3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_lshl_or_b32 v1, s0, v1, v2
-; GFX11-NEXT: s_or_b32 s0, s1, s2
+; GFX11-NEXT: s_and_b32 s2, 0xffff, s3
+; GFX11-NEXT: s_lshl_b32 s3, s4, 16
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffffff, v3
+; GFX11-NEXT: s_or_b32 s2, s2, s3
+; GFX11-NEXT: v_lshl_or_b32 v0, s0, v0, v2
+; GFX11-NEXT: s_lshr_b32 s0, s2, 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_lshl_or_b32 v0, s0, v0, v3
+; GFX11-NEXT: v_lshrrev_b32_e64 v2, v3, s0
+; GFX11-NEXT: s_or_b32 s0, s1, s6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v3, v0, 8, 8
+; GFX11-NEXT: v_lshl_or_b32 v1, s0, v1, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_bfe_u32 v2, v1, 8, 8
-; GFX11-NEXT: v_bfe_u32 v3, v1, 16, 8
-; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v3
+; GFX11-NEXT: v_bfe_u32 v3, v0, 16, 8
+; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 24, v4
-; GFX11-NEXT: v_and_or_b32 v1, v1, 0xff, v2
-; GFX11-NEXT: v_bfe_u32 v2, v0, 8, 8
-; GFX11-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or3_b32 v1, v1, v3, v4
-; GFX11-NEXT: v_lshl_or_b32 v0, v0, 8, v2
+; GFX11-NEXT: v_and_or_b32 v0, v0, 0xff, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 24, v4
+; GFX11-NEXT: v_bfe_u32 v4, v1, 8, 8
+; GFX11-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT: v_or3_b32 v0, v0, v2, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v1
-; GFX11-NEXT: v_readfirstlane_b32 s1, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v1, 8, v4
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: ; return to shader part epilog
%lhs = bitcast i48 %lhs.arg to <2 x i24>
%rhs = bitcast i48 %rhs.arg to <2 x i24>
@@ -2454,35 +2455,37 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX6-NEXT: v_mov_b32_e32 v8, 0xffffffe8
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX6-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX6-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
-; GFX6-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX6-NEXT: v_mov_b32_e32 v7, 0xffffffe8
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v9, v9
; GFX6-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX6-NEXT: v_bfe_u32 v2, v2, 1, 23
-; GFX6-NEXT: v_mul_lo_u32 v9, v7, v8
-; GFX6-NEXT: v_mul_lo_u32 v8, v6, v8
-; GFX6-NEXT: v_mul_hi_u32 v9, v7, v9
+; GFX6-NEXT: v_mul_lo_u32 v8, v6, v7
; GFX6-NEXT: v_mul_hi_u32 v8, v6, v8
-; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v9
-; GFX6-NEXT: v_mul_hi_u32 v7, v4, v7
-; GFX6-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v7
-; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 24, v4
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8
+; GFX6-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX6-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v9
+; GFX6-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX6-NEXT: v_mul_lo_u32 v7, v8, v7
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 24, v4
+; GFX6-NEXT: v_mul_hi_u32 v7, v8, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8
-; GFX6-NEXT: v_mul_hi_u32 v6, v5, v6
-; GFX6-NEXT: v_sub_i32_e32 v7, vcc, 23, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GFX6-NEXT: v_mul_hi_u32 v7, v5, v7
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 23, v4
; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v4, v0
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v7
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v6
+; GFX6-NEXT: v_mul_lo_u32 v6, v7, 24
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v5, v6
@@ -2506,35 +2509,37 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX8-NEXT: v_mov_b32_e32 v8, 0xffffffe8
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX8-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
-; GFX8-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX8-NEXT: v_mov_b32_e32 v7, 0xffffffe8
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v9, v9
; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX8-NEXT: v_bfe_u32 v2, v2, 1, 23
-; GFX8-NEXT: v_mul_lo_u32 v9, v7, v8
-; GFX8-NEXT: v_mul_lo_u32 v8, v6, v8
-; GFX8-NEXT: v_mul_hi_u32 v9, v7, v9
+; GFX8-NEXT: v_mul_lo_u32 v8, v6, v7
; GFX8-NEXT: v_mul_hi_u32 v8, v6, v8
-; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v9
-; GFX8-NEXT: v_mul_hi_u32 v7, v4, v7
-; GFX8-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v7
-; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 24, v4
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8
+; GFX8-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX8-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v9
+; GFX8-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX8-NEXT: v_mul_lo_u32 v7, v8, v7
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v6
+; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 24, v4
+; GFX8-NEXT: v_mul_hi_u32 v7, v8, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8
-; GFX8-NEXT: v_mul_hi_u32 v6, v5, v6
-; GFX8-NEXT: v_sub_u32_e32 v7, vcc, 23, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, v8, v7
+; GFX8-NEXT: v_mul_hi_u32 v7, v5, v7
+; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 23, v4
; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v4, v0
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v7
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v6
+; GFX8-NEXT: v_mul_lo_u32 v6, v7, 24
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v5, v6
@@ -2558,35 +2563,37 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX9-NEXT: v_mov_b32_e32 v8, 0xffffffe8
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX9-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
-; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX9-NEXT: v_mov_b32_e32 v7, 0xffffffe8
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v9, v9
; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX9-NEXT: v_mul_f32_e32 v9, 0x4f7ffffe, v9
+; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GFX9-NEXT: v_mul_lo_u32 v8, v6, v7
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX9-NEXT: v_bfe_u32 v2, v2, 1, 23
-; GFX9-NEXT: v_mul_lo_u32 v9, v7, v8
-; GFX9-NEXT: v_bfe_u32 v3, v3, 1, 23
-; GFX9-NEXT: v_mul_lo_u32 v8, v6, v8
-; GFX9-NEXT: v_mul_hi_u32 v9, v7, v9
+; GFX9-NEXT: v_mul_lo_u32 v7, v9, v7
; GFX9-NEXT: v_mul_hi_u32 v8, v6, v8
-; GFX9-NEXT: v_add_u32_e32 v7, v7, v9
-; GFX9-NEXT: v_mul_hi_u32 v7, v4, v7
+; GFX9-NEXT: v_bfe_u32 v3, v3, 1, 23
+; GFX9-NEXT: v_mul_hi_u32 v7, v9, v7
; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
-; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6
-; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX9-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX9-NEXT: v_add_u32_e32 v7, v9, v7
; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX9-NEXT: v_sub_u32_e32 v4, v4, v7
-; GFX9-NEXT: v_subrev_u32_e32 v7, 24, v4
+; GFX9-NEXT: v_sub_u32_e32 v4, v4, v6
+; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v7, 24, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX9-NEXT: v_mul_hi_u32 v6, v5, v7
; GFX9-NEXT: v_sub_u32_e32 v7, 23, v4
; GFX9-NEXT: v_and_b32_e32 v7, 0xffffff, v7
; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX9-NEXT: v_lshrrev_b32_e32 v2, v7, v2
; GFX9-NEXT: v_lshl_or_b32 v0, v0, v4, v2
; GFX9-NEXT: v_sub_u32_e32 v2, v5, v6
@@ -2607,27 +2614,29 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v7, 24
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX10-NEXT: v_bfe_u32 v2, v2, 1, 23
-; GFX10-NEXT: v_bfe_u32 v3, v3, 1, 23
; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v7, v7
+; GFX10-NEXT: v_bfe_u32 v3, v3, 1, 23
; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
-; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX10-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v7
-; GFX10-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v6
-; GFX10-NEXT: v_mul_hi_u32 v8, v7, v8
-; GFX10-NEXT: v_mul_hi_u32 v9, v6, v9
-; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v8
-; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v9
-; GFX10-NEXT: v_mul_hi_u32 v7, v4, v7
-; GFX10-NEXT: v_mul_hi_u32 v6, v5, v6
-; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX10-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v6
+; GFX10-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v7
+; GFX10-NEXT: v_mul_hi_u32 v8, v6, v8
+; GFX10-NEXT: v_mul_hi_u32 v9, v7, v9
+; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v8
+; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v9
+; GFX10-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX10-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX10-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v7
-; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v6
+; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v6
+; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v7
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 24, v4
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, 24, v5
@@ -2656,63 +2665,64 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v7, 24
; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX11-NEXT: v_bfe_u32 v2, v2, 1, 23
; GFX11-NEXT: v_bfe_u32 v3, v3, 1, 23
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
-; GFX11-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
+; GFX11-NEXT: v_dual_mul_f32 v6, 0x4f7ffffe, v6 :: v_dual_mul_f32 v7, 0x4f7ffffe, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v6
-; GFX11-NEXT: v_mul_hi_u32 v9, v6, v9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_nc_u32_e32 v6, v6, v9
; GFX11-NEXT: v_cvt_u32_f32_e32 v7, v7
-; GFX11-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v7
-; GFX11-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX11-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v6
+; GFX11-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mul_hi_u32 v8, v7, v8
-; GFX11-NEXT: v_sub_nc_u32_e32 v5, v5, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v7, v7, v8
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX11-NEXT: v_mul_hi_u32 v7, v4, v7
+; GFX11-NEXT: v_mul_hi_u32 v8, v6, v8
+; GFX11-NEXT: v_mul_hi_u32 v9, v7, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_nc_u32_e32 v6, v6, v8
+; GFX11-NEXT: v_add_nc_u32_e32 v7, v7, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX11-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX11-NEXT: v_sub_nc_u32_e32 v4, v4, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_sub_nc_u32_e32 v5, v5, v7
; GFX11-NEXT: v_subrev_nc_u32_e32 v7, 24, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX11-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_sub_nc_u32_e32 v4, v4, v6
; GFX11-NEXT: v_subrev_nc_u32_e32 v6, 24, v4
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_subrev_nc_u32_e32 v6, 24, v4
; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_subrev_nc_u32_e32 v7, 24, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_sub_nc_u32_e32 v6, 23, v4
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX11-NEXT: v_sub_nc_u32_e32 v7, 23, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v7 :: v_dual_and_b32 v4, 0xffffff, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_b32_e32 v6, 0xffffff, v6
+; GFX11-NEXT: v_sub_nc_u32_e32 v7, 23, v5
; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffffff, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshrrev_b32_e32 v2, v6, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, v7, v3
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffffff, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshl_or_b32 v0, v0, v4, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, v7, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_lshl_or_b32 v1, v1, v5, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i24> @llvm.fshl.v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index a922464210867cc..25d845f2f9922ac 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -1371,48 +1371,48 @@ define i32 @v_fshr_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX10-LABEL: v_fshr_v4i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_not_b32_e32 v5, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v7, 8, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 8, v0
+; GFX10-NEXT: v_not_b32_e32 v8, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v11, 24, v2
+; GFX10-NEXT: v_not_b32_e32 v12, v7
+; GFX10-NEXT: v_lshlrev_b16 v3, 1, v3
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX10-NEXT: v_lshrrev_b32_e32 v6, 24, v0
-; GFX10-NEXT: v_and_b32_e32 v5, 7, v5
+; GFX10-NEXT: v_lshrrev_b32_e32 v5, 24, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v6, 8, v1
+; GFX10-NEXT: v_and_b32_e32 v12, 7, v12
+; GFX10-NEXT: v_and_b32_e32 v8, 7, v8
; GFX10-NEXT: v_lshlrev_b16 v0, 1, v0
-; GFX10-NEXT: v_not_b32_e32 v10, v7
-; GFX10-NEXT: v_lshrrev_b32_e32 v8, 8, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v2
-; GFX10-NEXT: v_lshrrev_b32_e32 v12, 24, v2
-; GFX10-NEXT: v_lshlrev_b16 v0, v5, v0
-; GFX10-NEXT: v_and_b32_e32 v5, 7, v10
-; GFX10-NEXT: v_lshlrev_b16 v3, 1, v3
-; GFX10-NEXT: v_not_b32_e32 v13, v11
+; GFX10-NEXT: v_not_b32_e32 v13, v10
; GFX10-NEXT: s_movk_i32 s4, 0xff
+; GFX10-NEXT: v_lshlrev_b16 v3, v12, v3
+; GFX10-NEXT: v_not_b32_e32 v12, v11
; GFX10-NEXT: v_lshrrev_b32_e32 v9, 24, v1
-; GFX10-NEXT: v_and_b32_e32 v10, 0xff, v1
-; GFX10-NEXT: v_lshlrev_b16 v3, v5, v3
-; GFX10-NEXT: v_and_b32_e32 v5, 0xff, v8
-; GFX10-NEXT: v_not_b32_e32 v8, v12
+; GFX10-NEXT: v_lshlrev_b16 v0, v8, v0
+; GFX10-NEXT: v_and_b32_e32 v8, 0xff, v1
; GFX10-NEXT: v_and_b32_e32 v7, 7, v7
-; GFX10-NEXT: v_and_b32_e32 v11, 7, v11
+; GFX10-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX10-NEXT: v_and_b32_e32 v10, 7, v10
; GFX10-NEXT: v_and_b32_e32 v13, 7, v13
; GFX10-NEXT: v_lshlrev_b16 v4, 1, v4
; GFX10-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-NEXT: v_and_b32_e32 v8, 7, v8
-; GFX10-NEXT: v_lshlrev_b16 v6, 1, v6
; GFX10-NEXT: v_and_b32_e32 v12, 7, v12
+; GFX10-NEXT: v_lshlrev_b16 v5, 1, v5
+; GFX10-NEXT: v_and_b32_e32 v11, 7, v11
; GFX10-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX10-NEXT: v_lshrrev_b16 v5, v7, v5
+; GFX10-NEXT: v_lshrrev_b16 v6, v7, v6
; GFX10-NEXT: v_lshlrev_b16 v4, v13, v4
-; GFX10-NEXT: v_lshrrev_b16 v1, v11, v1
-; GFX10-NEXT: v_lshlrev_b16 v6, v8, v6
-; GFX10-NEXT: v_lshrrev_b16 v7, v12, v9
-; GFX10-NEXT: v_lshrrev_b16 v2, v2, v10
-; GFX10-NEXT: v_or_b32_e32 v3, v3, v5
-; GFX10-NEXT: v_mov_b32_e32 v5, 8
+; GFX10-NEXT: v_lshrrev_b16 v1, v10, v1
+; GFX10-NEXT: v_lshlrev_b16 v5, v12, v5
+; GFX10-NEXT: v_lshrrev_b16 v7, v11, v9
+; GFX10-NEXT: v_lshrrev_b16 v2, v2, v8
+; GFX10-NEXT: v_or_b32_e32 v3, v3, v6
+; GFX10-NEXT: v_mov_b32_e32 v6, 8
; GFX10-NEXT: v_or_b32_e32 v1, v4, v1
-; GFX10-NEXT: v_or_b32_e32 v4, v6, v7
+; GFX10-NEXT: v_or_b32_e32 v4, v5, v7
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v4
; GFX10-NEXT: v_and_or_b32 v0, v0, 0xff, v2
@@ -1820,13 +1820,14 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_lshr_b32 s6, s0, 16
; GFX6-NEXT: s_lshr_b32 s7, s0, 24
; GFX6-NEXT: s_lshr_b32 s8, s1, 8
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_and_b32 s9, s0, 0xff
; GFX6-NEXT: s_bfe_u32 s0, s0, 0x80008
; GFX6-NEXT: s_and_b32 s1, s1, 0xff
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX6-NEXT: s_lshl_b32 s0, s0, 8
; GFX6-NEXT: s_lshl_b32 s1, s1, 8
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX6-NEXT: s_or_b32 s0, s9, s0
; GFX6-NEXT: s_or_b32 s1, s7, s1
; GFX6-NEXT: s_and_b32 s7, s8, 0xff
@@ -1834,19 +1835,19 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_lshr_b32 s9, s2, 24
; GFX6-NEXT: s_and_b32 s11, s2, 0xff
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x80008
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, v1
; GFX6-NEXT: s_lshl_b32 s2, s2, 8
; GFX6-NEXT: s_and_b32 s8, s8, 0xff
; GFX6-NEXT: s_or_b32 s2, s11, s2
; GFX6-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX6-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX6-NEXT: s_lshr_b32 s10, s3, 8
; GFX6-NEXT: s_and_b32 s2, 0xffff, s2
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
; GFX6-NEXT: s_and_b32 s3, s3, 0xff
-; GFX6-NEXT: v_mul_lo_u32 v3, v1, v2
; GFX6-NEXT: s_or_b32 s2, s2, s8
; GFX6-NEXT: s_lshl_b32 s3, s3, 8
; GFX6-NEXT: s_and_b32 s8, s10, 0xff
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: s_or_b32 s3, s9, s3
; GFX6-NEXT: s_and_b32 s8, 0xffff, s8
; GFX6-NEXT: s_and_b32 s3, 0xffff, s3
@@ -1856,100 +1857,103 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_lshr_b32 s9, s4, 24
; GFX6-NEXT: s_and_b32 s11, s4, 0xff
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x80008
-; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: s_lshl_b32 s4, s4, 8
; GFX6-NEXT: s_and_b32 s8, s8, 0xff
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX6-NEXT: s_or_b32 s4, s11, s4
; GFX6-NEXT: s_and_b32 s8, 0xffff, s8
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX6-NEXT: s_and_b32 s4, 0xffff, s4
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
; GFX6-NEXT: s_or_b32 s4, s4, s8
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT: v_mul_hi_u32 v1, s4, v1
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX6-NEXT: s_lshr_b32 s10, s5, 8
-; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX6-NEXT: s_and_b32 s5, s5, 0xff
-; GFX6-NEXT: v_mul_lo_u32 v2, v0, v2
+; GFX6-NEXT: v_mul_lo_u32 v1, v2, v1
; GFX6-NEXT: s_lshl_b32 s5, s5, 8
-; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s4, v1
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v1
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX6-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX6-NEXT: s_and_b32 s8, s10, 0xff
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: s_or_b32 s5, s9, s5
; GFX6-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v1
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v0
; GFX6-NEXT: s_and_b32 s5, 0xffff, s5
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX6-NEXT: s_or_b32 s5, s5, s8
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX6-NEXT: s_and_b32 s6, s6, 0xff
; GFX6-NEXT: s_and_b32 s0, 0xffff, s0
; GFX6-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v0
; GFX6-NEXT: s_lshl_b32 s4, s6, 17
; GFX6-NEXT: s_lshl_b32 s0, s0, 1
; GFX6-NEXT: s_or_b32 s0, s4, s0
; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v3
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2
-; GFX6-NEXT: v_lshr_b32_e32 v1, s2, v1
-; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX6-NEXT: v_lshr_b32_e32 v0, s2, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
+; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX6-NEXT: s_and_b32 s1, 0xffff, s1
; GFX6-NEXT: s_and_b32 s7, 0xffff, s7
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v1
; GFX6-NEXT: s_lshl_b32 s0, s7, 17
; GFX6-NEXT: s_lshl_b32 s1, s1, 1
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2
-; GFX6-NEXT: v_lshr_b32_e32 v0, s3, v0
-; GFX6-NEXT: v_bfe_u32 v3, v1, 8, 8
-; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_lshr_b32_e32 v1, s3, v1
+; GFX6-NEXT: v_bfe_u32 v3, v0, 8, 8
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
-; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_bfe_u32 v2, v0, 8, 8
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v1
-; GFX6-NEXT: v_readfirstlane_b32 s1, v0
+; GFX6-NEXT: v_and_b32_e32 v2, 0xff, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: v_bfe_u32 v2, v1, 8, 8
+; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_fshr_v2i24:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_lshr_b32 s9, s1, 8
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_lshr_b32 s6, s0, 8
; GFX8-NEXT: s_lshr_b32 s8, s0, 24
; GFX8-NEXT: s_lshl_b32 s1, s1, 8
+; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: s_and_b32 s6, s6, 0xff
; GFX8-NEXT: s_or_b32 s1, s8, s1
; GFX8-NEXT: s_lshr_b32 s8, s2, 8
+; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_lshr_b32 s7, s0, 16
; GFX8-NEXT: s_and_b32 s0, s0, 0xff
; GFX8-NEXT: s_lshl_b32 s6, s6, 8
@@ -1961,11 +1965,11 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_lshr_b32 s10, s2, 24
; GFX8-NEXT: s_and_b32 s2, s2, 0xff
; GFX8-NEXT: s_lshl_b32 s8, s8, 8
-; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX8-NEXT: s_or_b32 s2, s2, s8
; GFX8-NEXT: s_and_b32 s8, s9, 0xff
-; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX8-NEXT: s_and_b32 s8, 0xffff, s8
+; GFX8-NEXT: v_mul_lo_u32 v2, v0, v1
; GFX8-NEXT: s_lshr_b32 s11, s3, 8
; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
@@ -1973,12 +1977,11 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_or_b32 s2, s2, s8
; GFX8-NEXT: s_lshl_b32 s3, s3, 8
; GFX8-NEXT: s_and_b32 s8, s11, 0xff
-; GFX8-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX8-NEXT: s_or_b32 s3, s10, s3
; GFX8-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX8-NEXT: v_mul_lo_u32 v3, v1, v2
; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
+; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX8-NEXT: s_or_b32 s3, s3, s8
; GFX8-NEXT: s_lshr_b32 s8, s4, 8
; GFX8-NEXT: s_and_b32 s8, s8, 0xff
@@ -1986,95 +1989,101 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_lshr_b32 s10, s4, 24
; GFX8-NEXT: s_and_b32 s4, s4, 0xff
; GFX8-NEXT: s_lshl_b32 s8, s8, 8
-; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX8-NEXT: s_or_b32 s4, s4, s8
; GFX8-NEXT: s_and_b32 s8, s9, 0xff
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX8-NEXT: s_and_b32 s8, 0xffff, s8
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX8-NEXT: s_and_b32 s4, 0xffff, s4
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
; GFX8-NEXT: s_or_b32 s4, s4, s8
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
-; GFX8-NEXT: v_mul_hi_u32 v1, s4, v1
-; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX8-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX8-NEXT: s_lshr_b32 s11, s5, 8
-; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX8-NEXT: s_and_b32 s5, s5, 0xff
-; GFX8-NEXT: v_mul_lo_u32 v2, v0, v2
+; GFX8-NEXT: v_mul_lo_u32 v1, v2, v1
; GFX8-NEXT: s_lshl_b32 s5, s5, 8
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s4, v1
-; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v1
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v0
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX8-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX8-NEXT: s_and_b32 s8, s11, 0xff
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: s_or_b32 s5, s10, s5
; GFX8-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v1
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v0
; GFX8-NEXT: s_and_b32 s5, 0xffff, s5
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX8-NEXT: s_or_b32 s5, s5, s8
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
-; GFX8-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1
+; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v1
-; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v0
+; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX8-NEXT: s_lshl_b32 s4, s6, 17
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: s_or_b32 s0, s4, s0
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v3
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GFX8-NEXT: v_lshlrev_b32_e64 v2, v2, s0
-; GFX8-NEXT: v_lshrrev_b32_e64 v1, v1, s2
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s5, v0
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s2
+; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_and_b32 s7, 0xffff, s7
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v1
; GFX8-NEXT: s_lshl_b32 s0, s7, 17
; GFX8-NEXT: s_lshl_b32 s1, s1, 1
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX8-NEXT: v_lshlrev_b32_e64 v2, v2, s0
-; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s3
-; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_lshrrev_b32_e64 v1, v1, s3
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: v_mov_b32_e32 v2, 8
-; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX8-NEXT: v_mov_b32_e32 v4, 16
-; GFX8-NEXT: v_or_b32_sdwa v3, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-; GFX8-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX8-NEXT: v_and_b32_e32 v3, 0xff, v0
+; GFX8-NEXT: v_or_b32_sdwa v3, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX8-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX8-NEXT: v_and_b32_e32 v3, 0xff, v1
; GFX8-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX8-NEXT: v_readfirstlane_b32 s0, v1
-; GFX8-NEXT: v_readfirstlane_b32 s1, v0
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
+; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_fshr_v2i24:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX9-NEXT: s_lshr_b32 s11, s1, 8
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_lshr_b32 s7, s0, 8
; GFX9-NEXT: s_lshr_b32 s10, s0, 24
; GFX9-NEXT: s_lshl_b32 s1, s1, 8
+; GFX9-NEXT: v_mul_lo_u32 v2, v0, v1
; GFX9-NEXT: s_and_b32 s7, s7, 0xff
; GFX9-NEXT: s_or_b32 s1, s10, s1
; GFX9-NEXT: s_lshr_b32 s10, s2, 8
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: s_lshr_b32 s9, s0, 16
; GFX9-NEXT: s_and_b32 s0, s0, 0xff
; GFX9-NEXT: s_lshl_b32 s7, s7, 8
@@ -2086,11 +2095,12 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_lshr_b32 s12, s2, 24
; GFX9-NEXT: s_and_b32 s2, s2, 0xff
; GFX9-NEXT: s_lshl_b32 s10, s10, 8
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX9-NEXT: s_or_b32 s2, s2, s10
; GFX9-NEXT: s_and_b32 s10, s11, 0xff
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX9-NEXT: s_and_b32 s10, 0xffff, s10
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX9-NEXT: s_lshr_b32 s13, s3, 8
; GFX9-NEXT: s_and_b32 s2, 0xffff, s2
; GFX9-NEXT: s_lshl_b32 s10, s10, 16
@@ -2098,103 +2108,101 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_or_b32 s2, s2, s10
; GFX9-NEXT: s_lshl_b32 s3, s3, 8
; GFX9-NEXT: s_and_b32 s10, s13, 0xff
-; GFX9-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX9-NEXT: s_or_b32 s3, s12, s3
; GFX9-NEXT: s_and_b32 s10, 0xffff, s10
-; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2
; GFX9-NEXT: s_and_b32 s3, 0xffff, s3
; GFX9-NEXT: s_lshl_b32 s10, s10, 16
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX9-NEXT: s_or_b32 s3, s3, s10
; GFX9-NEXT: s_lshr_b32 s10, s4, 8
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT: s_and_b32 s10, s10, 0xff
; GFX9-NEXT: s_lshr_b32 s11, s4, 16
; GFX9-NEXT: s_lshr_b32 s12, s4, 24
; GFX9-NEXT: s_and_b32 s4, s4, 0xff
; GFX9-NEXT: s_lshl_b32 s10, s10, 8
-; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: s_or_b32 s4, s4, s10
; GFX9-NEXT: s_and_b32 s10, s11, 0xff
; GFX9-NEXT: s_and_b32 s10, 0xffff, s10
-; GFX9-NEXT: v_mul_lo_u32 v2, v0, v2
+; GFX9-NEXT: v_mul_lo_u32 v1, v2, v1
; GFX9-NEXT: s_and_b32 s4, 0xffff, s4
; GFX9-NEXT: s_lshl_b32 s10, s10, 16
; GFX9-NEXT: s_or_b32 s4, s4, s10
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT: v_mul_hi_u32 v1, s4, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX9-NEXT: s_lshr_b32 s13, s5, 8
; GFX9-NEXT: s_and_b32 s5, s5, 0xff
-; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX9-NEXT: s_lshl_b32 s5, s5, 8
; GFX9-NEXT: s_and_b32 s10, s13, 0xff
; GFX9-NEXT: s_or_b32 s5, s12, s5
; GFX9-NEXT: s_and_b32 s10, 0xffff, s10
; GFX9-NEXT: s_and_b32 s5, 0xffff, s5
; GFX9-NEXT: s_lshl_b32 s10, s10, 16
-; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24
-; GFX9-NEXT: s_or_b32 s5, s5, s10
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
-; GFX9-NEXT: v_mul_hi_u32 v0, s5, v0
-; GFX9-NEXT: v_sub_u32_e32 v1, s4, v1
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX9-NEXT: s_or_b32 s5, s5, s10
+; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
+; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX9-NEXT: s_and_b32 s0, 0xffff, s0
; GFX9-NEXT: s_and_b32 s7, 0xffff, s7
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX9-NEXT: v_sub_u32_e32 v3, 23, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_sub_u32_e32 v3, 23, v0
; GFX9-NEXT: s_lshl_b32 s4, s7, 17
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GFX9-NEXT: s_or_b32 s0, s4, s0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v3
-; GFX9-NEXT: v_lshrrev_b32_e64 v1, v1, s2
-; GFX9-NEXT: v_sub_u32_e32 v0, s5, v0
-; GFX9-NEXT: v_lshl_or_b32 v1, s0, v2, v1
-; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v0
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v0
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s2
+; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, s0, v2, v0
+; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_and_b32 s9, 0xffff, s9
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT: v_sub_u32_e32 v2, 23, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_sub_u32_e32 v2, 23, v1
; GFX9-NEXT: s_lshl_b32 s0, s9, 17
; GFX9-NEXT: s_lshl_b32 s1, s1, 1
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s3
+; GFX9-NEXT: v_lshrrev_b32_e64 v1, v1, s3
; GFX9-NEXT: s_mov_b32 s6, 8
-; GFX9-NEXT: v_lshl_or_b32 v0, s0, v2, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, s0, v2, v1
; GFX9-NEXT: s_mov_b32 s8, 16
; GFX9-NEXT: s_movk_i32 s0, 0xff
-; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX9-NEXT: v_and_b32_e32 v3, 0xff, v0
-; GFX9-NEXT: v_and_or_b32 v2, v1, s0, v2
-; GFX9-NEXT: v_lshlrev_b32_sdwa v1, s8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX9-NEXT: v_and_b32_e32 v3, 0xff, v1
+; GFX9-NEXT: v_and_or_b32 v2, v0, s0, v2
+; GFX9-NEXT: v_lshlrev_b32_sdwa v0, s8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX9-NEXT: v_or3_b32 v1, v2, v1, v3
-; GFX9-NEXT: v_bfe_u32 v2, v0, 8, 8
-; GFX9-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v2
-; GFX9-NEXT: v_readfirstlane_b32 s0, v1
-; GFX9-NEXT: v_readfirstlane_b32 s1, v0
+; GFX9-NEXT: v_or3_b32 v0, v2, v0, v3
+; GFX9-NEXT: v_bfe_u32 v2, v1, 8, 8
+; GFX9-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 8, v2
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_fshr_v2i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
; GFX10-NEXT: s_lshr_b32 s9, s1, 8
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_lshr_b32 s6, s0, 8
-; GFX10-NEXT: s_lshr_b32 s8, s0, 24
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX10-NEXT: s_lshr_b32 s8, s0, 24
; GFX10-NEXT: s_lshl_b32 s1, s1, 8
; GFX10-NEXT: s_and_b32 s6, s6, 0xff
; GFX10-NEXT: s_or_b32 s1, s8, s1
@@ -2202,121 +2210,123 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX10-NEXT: s_lshr_b32 s7, s0, 16
; GFX10-NEXT: s_and_b32 s0, s0, 0xff
; GFX10-NEXT: s_lshl_b32 s6, s6, 8
+; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: s_and_b32 s8, s8, 0xff
; GFX10-NEXT: s_or_b32 s0, s0, s6
-; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: s_and_b32 s6, s7, 0xff
+; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: s_and_b32 s7, s9, 0xff
; GFX10-NEXT: s_lshr_b32 s9, s4, 16
-; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: s_lshr_b32 s10, s4, 24
+; GFX10-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v0
+; GFX10-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v1
; GFX10-NEXT: s_and_b32 s4, s4, 0xff
; GFX10-NEXT: s_lshl_b32 s8, s8, 8
-; GFX10-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v1
-; GFX10-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v0
+; GFX10-NEXT: s_lshr_b32 s11, s5, 8
; GFX10-NEXT: s_or_b32 s4, s4, s8
; GFX10-NEXT: s_and_b32 s8, s9, 0xff
-; GFX10-NEXT: s_lshr_b32 s11, s5, 8
-; GFX10-NEXT: s_and_b32 s8, 0xffff, s8
; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX10-NEXT: s_and_b32 s8, 0xffff, s8
; GFX10-NEXT: s_and_b32 s5, s5, 0xff
-; GFX10-NEXT: v_mul_hi_u32 v2, v1, v2
-; GFX10-NEXT: v_mul_hi_u32 v3, v0, v3
; GFX10-NEXT: s_lshl_b32 s8, s8, 16
; GFX10-NEXT: s_lshl_b32 s5, s5, 8
; GFX10-NEXT: s_or_b32 s4, s4, s8
; GFX10-NEXT: s_and_b32 s8, s11, 0xff
+; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT: s_or_b32 s5, s10, s5
; GFX10-NEXT: s_and_b32 s8, 0xffff, s8
-; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3
; GFX10-NEXT: s_and_b32 s5, 0xffff, s5
+; GFX10-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX10-NEXT: s_lshl_b32 s8, s8, 16
; GFX10-NEXT: s_lshr_b32 s9, s2, 8
-; GFX10-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX10-NEXT: s_or_b32 s5, s5, s8
; GFX10-NEXT: s_lshr_b32 s8, s2, 16
-; GFX10-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX10-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX10-NEXT: s_and_b32 s9, s9, 0xff
; GFX10-NEXT: s_lshr_b32 s10, s2, 24
+; GFX10-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX10-NEXT: s_lshr_b32 s11, s3, 8
; GFX10-NEXT: s_and_b32 s2, s2, 0xff
-; GFX10-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX10-NEXT: s_lshl_b32 s9, s9, 8
; GFX10-NEXT: s_and_b32 s8, s8, 0xff
-; GFX10-NEXT: v_mul_lo_u32 v0, v0, 24
+; GFX10-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX10-NEXT: s_and_b32 s3, s3, 0xff
; GFX10-NEXT: s_or_b32 s2, s2, s9
+; GFX10-NEXT: v_sub_nc_u32_e32 v0, s4, v0
+; GFX10-NEXT: s_and_b32 s4, 0xffff, s8
; GFX10-NEXT: s_lshl_b32 s3, s3, 8
; GFX10-NEXT: s_and_b32 s2, 0xffff, s2
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, s4, v1
-; GFX10-NEXT: s_and_b32 s4, 0xffff, s8
-; GFX10-NEXT: s_or_b32 s3, s10, s3
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, s5, v0
-; GFX10-NEXT: s_and_b32 s5, s11, 0xff
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX10-NEXT: s_lshl_b32 s4, s4, 16
+; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
+; GFX10-NEXT: v_sub_nc_u32_e32 v1, s5, v1
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
+; GFX10-NEXT: s_and_b32 s5, s11, 0xff
+; GFX10-NEXT: s_or_b32 s3, s10, s3
; GFX10-NEXT: s_and_b32 s5, 0xffff, s5
; GFX10-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX10-NEXT: s_lshl_b32 s5, s5, 16
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX10-NEXT: s_or_b32 s2, s2, s4
+; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v0
; GFX10-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX10-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX10-NEXT: s_or_b32 s3, s3, s5
; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX10-NEXT: s_and_b32 s7, 0xffff, s7
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX10-NEXT: s_lshl_b32 s4, s6, 17
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
-; GFX10-NEXT: s_lshl_b32 s1, s1, 1
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GFX10-NEXT: s_or_b32 s0, s4, s0
+; GFX10-NEXT: s_lshl_b32 s1, s1, 1
; GFX10-NEXT: v_and_b32_e32 v3, 0xffffff, v3
-; GFX10-NEXT: v_sub_nc_u32_e32 v2, 23, v0
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffffff, v0
-; GFX10-NEXT: v_lshrrev_b32_e64 v1, v1, s2
+; GFX10-NEXT: v_sub_nc_u32_e32 v2, 23, v1
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, s2
; GFX10-NEXT: s_lshl_b32 s2, s7, 17
; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, s3
-; GFX10-NEXT: v_lshl_or_b32 v1, s0, v3, v1
+; GFX10-NEXT: v_lshrrev_b32_e64 v1, v1, s3
+; GFX10-NEXT: v_lshl_or_b32 v0, s0, v3, v0
; GFX10-NEXT: s_or_b32 s0, s2, s1
-; GFX10-NEXT: v_lshl_or_b32 v0, s0, v2, v0
+; GFX10-NEXT: v_lshl_or_b32 v1, s0, v2, v1
; GFX10-NEXT: s_mov_b32 s0, 8
-; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-NEXT: s_mov_b32 s0, 16
-; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v0
-; GFX10-NEXT: v_bfe_u32 v4, v0, 8, 8
-; GFX10-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX10-NEXT: v_and_or_b32 v2, v1, 0xff, v2
-; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v1
+; GFX10-NEXT: v_bfe_u32 v4, v1, 8, 8
+; GFX10-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX10-NEXT: v_and_or_b32 v2, v0, 0xff, v2
+; GFX10-NEXT: v_lshlrev_b32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v4
-; GFX10-NEXT: v_or3_b32 v1, v2, v1, v3
-; GFX10-NEXT: v_readfirstlane_b32 s1, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v1
+; GFX10-NEXT: v_lshl_or_b32 v1, v1, 8, v4
+; GFX10-NEXT: v_or3_b32 v0, v2, v0, v3
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_fshr_v2i24:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
; GFX11-NEXT: s_lshr_b32 s6, s0, 8
; GFX11-NEXT: s_lshr_b32 s7, s0, 16
; GFX11-NEXT: s_and_b32 s6, s6, 0xff
-; GFX11-NEXT: s_lshr_b32 s8, s0, 24
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX11-NEXT: s_lshr_b32 s8, s0, 24
; GFX11-NEXT: s_and_b32 s0, s0, 0xff
; GFX11-NEXT: s_lshl_b32 s6, s6, 8
; GFX11-NEXT: s_lshr_b32 s9, s1, 8
@@ -2324,124 +2334,122 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX11-NEXT: s_and_b32 s6, s7, 0xff
; GFX11-NEXT: s_and_b32 s7, s9, 0xff
; GFX11-NEXT: s_lshr_b32 s9, s4, 8
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_mul_f32 v1, 0x4f7ffffe, v1
; GFX11-NEXT: s_lshr_b32 s10, s4, 16
; GFX11-NEXT: s_and_b32 s9, s9, 0xff
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX11-NEXT: s_and_b32 s11, s4, 0xff
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX11-NEXT: s_lshl_b32 s9, s9, 8
; GFX11-NEXT: s_and_b32 s10, s10, 0xff
; GFX11-NEXT: s_or_b32 s9, s11, s9
-; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX11-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v0
+; GFX11-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v1
; GFX11-NEXT: s_and_b32 s10, 0xffff, s10
; GFX11-NEXT: s_and_b32 s9, 0xffff, s9
; GFX11-NEXT: s_lshl_b32 s10, s10, 16
; GFX11-NEXT: s_lshr_b32 s11, s5, 8
-; GFX11-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v1
+; GFX11-NEXT: s_or_b32 s9, s9, s10
; GFX11-NEXT: s_and_b32 s5, s5, 0xff
+; GFX11-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX11-NEXT: s_lshr_b32 s4, s4, 24
-; GFX11-NEXT: s_or_b32 s9, s9, s10
; GFX11-NEXT: s_lshl_b32 s5, s5, 8
; GFX11-NEXT: s_and_b32 s10, s11, 0xff
; GFX11-NEXT: s_or_b32 s4, s4, s5
; GFX11-NEXT: s_and_b32 s5, 0xffff, s10
-; GFX11-NEXT: v_mul_hi_u32 v2, v1, v2
-; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: s_and_b32 s4, 0xffff, s4
; GFX11-NEXT: s_lshl_b32 s5, s5, 16
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v2
+; GFX11-NEXT: v_mul_hi_u32 v2, v1, v3
; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_lshl_b32 s1, s1, 8
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshr_b32 s10, s2, 16
-; GFX11-NEXT: v_add_nc_u32_e32 v1, v1, v2
-; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX11-NEXT: v_mul_hi_u32 v0, s9, v0
+; GFX11-NEXT: s_lshl_b32 s1, s1, 8
+; GFX11-NEXT: s_lshr_b32 s5, s2, 24
; GFX11-NEXT: s_or_b32 s1, s8, s1
+; GFX11-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX11-NEXT: s_lshr_b32 s8, s2, 8
-; GFX11-NEXT: s_lshr_b32 s5, s2, 24
-; GFX11-NEXT: v_mul_hi_u32 v1, s9, v1
-; GFX11-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v0
-; GFX11-NEXT: s_and_b32 s8, s8, 0xff
; GFX11-NEXT: s_and_b32 s2, s2, 0xff
+; GFX11-NEXT: s_and_b32 s8, s8, 0xff
+; GFX11-NEXT: v_mul_lo_u32 v0, v0, 24
+; GFX11-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX11-NEXT: s_lshl_b32 s8, s8, 8
; GFX11-NEXT: s_and_b32 s0, 0xffff, s0
; GFX11-NEXT: s_or_b32 s2, s2, s8
; GFX11-NEXT: s_and_b32 s8, s10, 0xff
-; GFX11-NEXT: v_mul_lo_u32 v1, v1, 24
-; GFX11-NEXT: v_mul_hi_u32 v2, v0, v3
-; GFX11-NEXT: s_and_b32 s8, 0xffff, s8
; GFX11-NEXT: s_and_b32 s2, 0xffff, s2
-; GFX11-NEXT: s_lshl_b32 s8, s8, 16
-; GFX11-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX11-NEXT: s_or_b32 s2, s2, s8
-; GFX11-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-NEXT: v_sub_nc_u32_e32 v1, s9, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v2
+; GFX11-NEXT: s_and_b32 s8, 0xffff, s8
+; GFX11-NEXT: v_sub_nc_u32_e32 v0, s9, v0
+; GFX11-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX11-NEXT: s_lshr_b32 s9, s3, 8
; GFX11-NEXT: s_and_b32 s3, s3, 0xff
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
-; GFX11-NEXT: v_mul_hi_u32 v0, s4, v0
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
+; GFX11-NEXT: s_lshl_b32 s8, s8, 16
+; GFX11-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX11-NEXT: s_lshl_b32 s3, s3, 8
-; GFX11-NEXT: s_and_b32 s7, 0xffff, s7
+; GFX11-NEXT: s_or_b32 s2, s2, s8
+; GFX11-NEXT: v_sub_nc_u32_e32 v1, s4, v1
+; GFX11-NEXT: s_and_b32 s4, s9, 0xff
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX11-NEXT: s_and_b32 s6, 0xffff, s6
; GFX11-NEXT: s_or_b32 s3, s5, s3
-; GFX11-NEXT: s_lshl_b32 s5, s6, 17
+; GFX11-NEXT: v_subrev_nc_u32_e32 v3, 24, v1
+; GFX11-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX11-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX11-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX11-NEXT: s_lshl_b32 s4, s4, 16
+; GFX11-NEXT: s_lshl_b32 s5, s6, 17
+; GFX11-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX11-NEXT: s_or_b32 s0, s5, s0
-; GFX11-NEXT: v_mul_lo_u32 v0, v0, 24
+; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX11-NEXT: s_and_b32 s7, 0xffff, s7
; GFX11-NEXT: s_lshl_b32 s1, s1, 1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_sub_nc_u32_e32 v0, s4, v0
-; GFX11-NEXT: s_and_b32 s4, s9, 0xff
-; GFX11-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_subrev_nc_u32_e32 v3, 24, v0
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX11-NEXT: s_lshl_b32 s4, s4, 16
-; GFX11-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_subrev_nc_u32_e32 v3, 24, v1
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX11-NEXT: v_subrev_nc_u32_e32 v3, 24, v0
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX11-NEXT: v_sub_nc_u32_e32 v2, 23, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_nc_u32_e32 v3, 23, v1
; GFX11-NEXT: v_and_b32_e32 v1, 0xffffff, v1
-; GFX11-NEXT: v_sub_nc_u32_e32 v3, 23, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX11-NEXT: v_lshrrev_b32_e64 v1, v1, s2
+; GFX11-NEXT: v_sub_nc_u32_e32 v2, 23, v0
; GFX11-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_lshrrev_b32_e64 v0, v0, s2
; GFX11-NEXT: s_or_b32 s2, s3, s4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshl_or_b32 v1, s0, v2, v1
+; GFX11-NEXT: v_lshrrev_b32_e64 v1, v1, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_lshl_or_b32 v0, s0, v2, v0
; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v3
-; GFX11-NEXT: v_lshrrev_b32_e64 v0, v0, s2
; GFX11-NEXT: s_lshl_b32 s0, s7, 17
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: v_bfe_u32 v3, v1, 8, 8
-; GFX11-NEXT: v_lshl_or_b32 v0, s0, v2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v3, v0, 8, 8
+; GFX11-NEXT: v_lshl_or_b32 v1, s0, v2, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v3
-; GFX11-NEXT: v_bfe_u32 v3, v1, 16, 8
-; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v0
+; GFX11-NEXT: v_bfe_u32 v3, v0, 16, 8
+; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_and_or_b32 v1, v1, 0xff, v2
+; GFX11-NEXT: v_and_or_b32 v0, v0, 0xff, v2
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 24, v4
-; GFX11-NEXT: v_bfe_u32 v4, v0, 8, 8
-; GFX11-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX11-NEXT: v_or3_b32 v1, v1, v2, v3
+; GFX11-NEXT: v_bfe_u32 v4, v1, 8, 8
+; GFX11-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX11-NEXT: v_or3_b32 v0, v0, v2, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshl_or_b32 v0, v0, 8, v4
-; GFX11-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v1, 8, v4
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_readfirstlane_b32 s1, v0
+; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: ; return to shader part epilog
%lhs = bitcast i48 %lhs.arg to <2 x i24>
%rhs = bitcast i48 %rhs.arg to <2 x i24>
@@ -2457,40 +2465,42 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX6-NEXT: v_mov_b32_e32 v8, 0xffffffe8
+; GFX6-NEXT: v_mov_b32_e32 v7, 0xffffffe8
; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX6-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX6-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
-; GFX6-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
; GFX6-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX6-NEXT: v_mul_lo_u32 v9, v7, v8
; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX6-NEXT: v_mul_lo_u32 v8, v6, v8
+; GFX6-NEXT: v_mul_lo_u32 v8, v6, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 1, v1
-; GFX6-NEXT: v_mul_hi_u32 v9, v7, v9
; GFX6-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX6-NEXT: v_mul_hi_u32 v8, v6, v8
-; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v9
-; GFX6-NEXT: v_mul_hi_u32 v7, v4, v7
-; GFX6-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v7
-; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 24, v4
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8
+; GFX6-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v8, v9
+; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX6-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX6-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 24, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8
-; GFX6-NEXT: v_mul_hi_u32 v6, v5, v6
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX6-NEXT: v_mul_lo_u32 v6, v8, v7
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, 23, v4
; GFX6-NEXT: v_and_b32_e32 v7, 0xffffff, v7
-; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX6-NEXT: v_mul_hi_u32 v6, v8, v6
; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v7, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; GFX6-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v5, v6
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 24, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
@@ -2511,40 +2521,42 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX8-NEXT: v_mov_b32_e32 v8, 0xffffffe8
+; GFX8-NEXT: v_mov_b32_e32 v7, 0xffffffe8
; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX8-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
-; GFX8-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX8-NEXT: v_mul_lo_u32 v9, v7, v8
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX8-NEXT: v_mul_lo_u32 v8, v6, v8
+; GFX8-NEXT: v_mul_lo_u32 v8, v6, v7
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 1, v1
-; GFX8-NEXT: v_mul_hi_u32 v9, v7, v9
; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX8-NEXT: v_mul_hi_u32 v8, v6, v8
-; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v9
-; GFX8-NEXT: v_mul_hi_u32 v7, v4, v7
-; GFX8-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v7
-; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 24, v4
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8
+; GFX8-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v8, v9
+; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX8-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX8-NEXT: v_cvt_u32_f32_e32 v8, v8
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v6
+; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 24, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8
-; GFX8-NEXT: v_mul_hi_u32 v6, v5, v6
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX8-NEXT: v_mul_lo_u32 v6, v8, v7
; GFX8-NEXT: v_sub_u32_e32 v7, vcc, 23, v4
; GFX8-NEXT: v_and_b32_e32 v7, 0xffffff, v7
-; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX8-NEXT: v_mul_hi_u32 v6, v8, v6
; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v7, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, v8, v6
+; GFX8-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v5, v6
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 24, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
@@ -2565,40 +2577,42 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX9-NEXT: v_mov_b32_e32 v8, 0xffffffe8
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX9-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
-; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v9, v9
+; GFX9-NEXT: v_mov_b32_e32 v7, 0xffffffe8
; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT: v_mul_f32_e32 v9, 0x4f7ffffe, v9
+; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX9-NEXT: v_mul_lo_u32 v8, v6, v7
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v5
+; GFX9-NEXT: v_mul_lo_u32 v7, v9, v7
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX9-NEXT: v_mul_lo_u32 v9, v7, v8
+; GFX9-NEXT: v_mul_hi_u32 v8, v6, v8
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX9-NEXT: v_mul_lo_u32 v8, v6, v8
+; GFX9-NEXT: v_mul_hi_u32 v7, v9, v7
; GFX9-NEXT: v_and_b32_e32 v3, 0xffffff, v3
-; GFX9-NEXT: v_mul_hi_u32 v9, v7, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1
-; GFX9-NEXT: v_mul_hi_u32 v8, v6, v8
-; GFX9-NEXT: v_add_u32_e32 v7, v7, v9
-; GFX9-NEXT: v_mul_hi_u32 v7, v4, v7
; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
-; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6
-; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX9-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX9-NEXT: v_add_u32_e32 v7, v9, v7
+; GFX9-NEXT: v_mul_hi_u32 v7, v5, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX9-NEXT: v_sub_u32_e32 v4, v4, v7
-; GFX9-NEXT: v_subrev_u32_e32 v7, 24, v4
+; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX9-NEXT: v_sub_u32_e32 v4, v4, v6
+; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v7, 24, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX9-NEXT: v_sub_u32_e32 v7, 23, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX9-NEXT: v_sub_u32_e32 v6, 23, v4
; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffffff, v7
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffffff, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v2, v4, v2
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, v7, v2
-; GFX9-NEXT: v_sub_u32_e32 v2, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, v6, v2
+; GFX9-NEXT: v_sub_u32_e32 v2, v5, v7
; GFX9-NEXT: v_subrev_u32_e32 v4, 24, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
@@ -2616,29 +2630,31 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v7, 24
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v7, v7
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 1, v1
-; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
-; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX10-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v7
-; GFX10-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v6
-; GFX10-NEXT: v_mul_hi_u32 v8, v7, v8
-; GFX10-NEXT: v_mul_hi_u32 v9, v6, v9
-; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v8
-; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v9
-; GFX10-NEXT: v_mul_hi_u32 v7, v4, v7
-; GFX10-NEXT: v_mul_hi_u32 v6, v5, v6
-; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX10-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v6
+; GFX10-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v7
+; GFX10-NEXT: v_mul_hi_u32 v8, v6, v8
+; GFX10-NEXT: v_mul_hi_u32 v9, v7, v9
+; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v8
+; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v9
+; GFX10-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX10-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX10-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v7
-; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v6
+; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v6
+; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v7
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 24, v4
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, 24, v5
@@ -2667,37 +2683,40 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v7, 24
; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; GFX11-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX11-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v7, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
-; GFX11-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
-; GFX11-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mul_f32 v6, 0x4f7ffffe, v6 :: v_dual_lshlrev_b32 v1, 1, v1
+; GFX11-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX11-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_hi_u32 v9, v6, v9
-; GFX11-NEXT: v_add_nc_u32_e32 v6, v6, v9
; GFX11-NEXT: v_cvt_u32_f32_e32 v7, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mul_hi_u32 v6, v5, v6
-; GFX11-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v7
+; GFX11-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v6
+; GFX11-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX11-NEXT: v_mul_hi_u32 v8, v7, v8
+; GFX11-NEXT: v_mul_hi_u32 v8, v6, v8
+; GFX11-NEXT: v_mul_hi_u32 v9, v7, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_sub_nc_u32_e32 v5, v5, v6
-; GFX11-NEXT: v_add_nc_u32_e32 v7, v7, v8
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX11-NEXT: v_add_nc_u32_e32 v6, v6, v8
+; GFX11-NEXT: v_add_nc_u32_e32 v7, v7, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_hi_u32 v7, v4, v7
+; GFX11-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX11-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_sub_nc_u32_e32 v4, v4, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_sub_nc_u32_e32 v5, v5, v7
; GFX11-NEXT: v_subrev_nc_u32_e32 v7, 24, v5
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX11-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_sub_nc_u32_e32 v4, v4, v6
; GFX11-NEXT: v_subrev_nc_u32_e32 v6, 24, v4
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
@@ -2710,20 +2729,20 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX11-NEXT: v_subrev_nc_u32_e32 v7, 24, v5
; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_sub_nc_u32_e32 v6, 23, v4
; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v7 :: v_dual_and_b32 v4, 0xffffff, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_b32_e32 v6, 0xffffff, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_sub_nc_u32_e32 v7, 23, v5
; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshrrev_b32_e32 v2, v4, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshrrev_b32_e32 v3, v5, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshl_or_b32 v0, v0, v6, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_lshl_or_b32 v1, v1, v4, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i24> @llvm.fshr.v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
index ebd5e2e085632cf..4bf6b6a623d8269 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
@@ -25,14 +25,12 @@ body: |
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -65,14 +63,12 @@ body: |
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[BUFFER_LOAD_USHORT_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN [[COPY]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_USHORT_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[BUFFER_LOAD_USHORT_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN [[COPY]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s16), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_USHORT_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -105,14 +101,12 @@ body: |
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[COPY]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[COPY]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -145,14 +139,12 @@ body: |
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (p3), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_p3_from_4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (p3), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_p3_from_4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -185,14 +177,12 @@ body: |
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (p5), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_p5_from_4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (p5), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_p5_from_4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -226,14 +216,12 @@ body: |
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (<2 x s16>), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_v2s16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (<2 x s16>), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_v2s16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -272,14 +260,12 @@ body: |
; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_CO_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_gep_2047
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[COPY]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 2047, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_gep_2047
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -310,6 +296,14 @@ body: |
bb.0:
liveins: $vgpr0
+ ; GFX6-LABEL: name: load_private_s32_from_1_gep_2047_known_bits
+ ; GFX6: liveins: $vgpr0
+ ; GFX6-NEXT: {{ $}}
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
+ ; GFX6-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+ ; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_AND_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 2047, 0, 0, implicit $exec :: (load (s8), addrspace 5)
+ ; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
; GFX9-LABEL: name: load_private_s32_from_1_gep_2047_known_bits
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -318,7 +312,6 @@ body: |
; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_AND_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 2047, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_gep_2047_known_bits
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -360,14 +353,12 @@ body: |
; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_CO_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_gep_2048
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[COPY]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 2048, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_gep_2048
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -406,7 +397,6 @@ body: |
; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_CO_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_gep_m2047
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -415,7 +405,6 @@ body: |
; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_gep_m2047
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -454,7 +443,6 @@ body: |
; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_CO_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_gep_m2048
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -463,7 +451,6 @@ body: |
; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_gep_m2048
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -502,14 +489,12 @@ body: |
; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_CO_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_gep_4095
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[COPY]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4095, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_gep_4095
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -548,7 +533,6 @@ body: |
; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_CO_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_gep_4096
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -557,7 +541,6 @@ body: |
; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_gep_4096
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -596,7 +579,6 @@ body: |
; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_CO_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_gep_m4095
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -605,7 +587,6 @@ body: |
; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_gep_m4095
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -644,7 +625,6 @@ body: |
; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_CO_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_gep_m4096
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -653,7 +633,6 @@ body: |
; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_gep_m4096
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -692,7 +671,6 @@ body: |
; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_CO_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_gep_8191
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -701,7 +679,6 @@ body: |
; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_gep_8191
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -740,7 +717,6 @@ body: |
; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_CO_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_gep_8192
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -749,7 +725,6 @@ body: |
; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_gep_8192
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -788,7 +763,6 @@ body: |
; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_CO_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_gep_m8191
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -797,7 +771,6 @@ body: |
; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_gep_m8191
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -836,7 +809,6 @@ body: |
; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_CO_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_gep_m8192
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -845,7 +817,6 @@ body: |
; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_gep_m8192
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -878,11 +849,9 @@ body: |
; GFX6-LABEL: name: load_private_s32_from_4_constant_0
; GFX6: [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
- ;
; GFX9-LABEL: name: load_private_s32_from_4_constant_0
; GFX9: [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
- ;
; GFX11-LABEL: name: load_private_s32_from_4_constant_0
; GFX11: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX11-NEXT: [[SCRATCH_LOAD_DWORD:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_DWORD [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32), addrspace 5)
@@ -909,11 +878,9 @@ body: |
; GFX6-LABEL: name: load_private_s32_from_4_constant_sgpr_16
; GFX6: [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 16, 0, 0, implicit $exec :: (load (s32), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
- ;
; GFX9-LABEL: name: load_private_s32_from_4_constant_sgpr_16
; GFX9: [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 16, 0, 0, implicit $exec :: (load (s32), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
- ;
; GFX11-LABEL: name: load_private_s32_from_4_constant_sgpr_16
; GFX11: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xexec_hi = S_MOV_B32 16
; GFX11-NEXT: [[SCRATCH_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_DWORD_SADDR [[S_MOV_B32_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32), addrspace 5)
@@ -940,11 +907,9 @@ body: |
; GFX6-LABEL: name: load_private_s32_from_1_constant_4095
; GFX6: [[BUFFER_LOAD_UBYTE_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4095, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFSET]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_constant_4095
; GFX9: [[BUFFER_LOAD_UBYTE_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4095, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFSET]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_constant_4095
; GFX11: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec
; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
@@ -972,12 +937,10 @@ body: |
; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_MOV_B32_e32_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_constant_4096
; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_MOV_B32_e32_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_constant_4096
; GFX11: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
@@ -1006,11 +969,9 @@ body: |
; GFX6-LABEL: name: load_private_s32_from_fi
; GFX6: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_fi
; GFX9: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_fi
; GFX11: [[SCRATCH_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_DWORD_SADDR %stack.0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32), addrspace 5)
; GFX11-NEXT: $vgpr0 = COPY [[SCRATCH_LOAD_DWORD_SADDR]]
@@ -1037,11 +998,9 @@ body: |
; GFX6-LABEL: name: load_private_s32_from_1_fi_offset_4095
; GFX6: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4095, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_fi_offset_4095
; GFX9: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4095, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_fi_offset_4095
; GFX11: [[SCRATCH_LOAD_UBYTE_SADDR:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE_SADDR %stack.0, 4095, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
; GFX11-NEXT: $vgpr0 = COPY [[SCRATCH_LOAD_UBYTE_SADDR]]
@@ -1071,11 +1030,9 @@ body: |
; GFX6-LABEL: name: load_private_s32_from_1_fi_offset_sgpr_4095
; GFX6: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4095, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_fi_offset_sgpr_4095
; GFX9: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4095, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_fi_offset_sgpr_4095
; GFX11: [[SCRATCH_LOAD_UBYTE_SADDR:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE_SADDR %stack.0, 4095, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
; GFX11-NEXT: $vgpr0 = COPY [[SCRATCH_LOAD_UBYTE_SADDR]]
@@ -1109,14 +1066,12 @@ body: |
; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], 0, implicit $exec
; GFX6-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_CO_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_1_fi_offset_4096
; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX9-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], 0, implicit $exec
; GFX9-NEXT: [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[V_ADD_U32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_1_fi_offset_4096
; GFX11: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
; GFX11-NEXT: [[SCRATCH_LOAD_UBYTE_SVS:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_UBYTE_SVS [[V_MOV_B32_e32_]], %stack.0, 0, 0, implicit $exec, implicit $flat_scr :: (load (s8), addrspace 5)
@@ -1147,12 +1102,10 @@ body: |
; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
; GFX6-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_MOV_B32_e32_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, -1, 0, 0, implicit $exec :: (load (s32), addrspace 5)
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
- ;
; GFX9-LABEL: name: load_private_s32_from_neg1
; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
; GFX9-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_MOV_B32_e32_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, -1, 0, 0, implicit $exec :: (load (s32), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
- ;
; GFX11-LABEL: name: load_private_s32_from_neg1
; GFX11: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
; GFX11-NEXT: [[SCRATCH_LOAD_DWORD:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_DWORD [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32), addrspace 5)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
index 7faf05e0aaf3096..98b29199dcc6d47 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
@@ -18,7 +18,6 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; GFX6-NEXT: $vgpr0 = COPY [[ADD]](s32)
- ;
; GFX8-LABEL: name: test_add_s32
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -26,7 +25,6 @@ body: |
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; GFX8-NEXT: $vgpr0 = COPY [[ADD]](s32)
- ;
; GFX9-LABEL: name: test_add_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -57,7 +55,6 @@ body: |
; GFX6-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UV3]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX8-LABEL: name: test_add_v2s32
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -69,7 +66,6 @@ body: |
; GFX8-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UV3]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_add_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -102,7 +98,6 @@ body: |
; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; GFX6-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX8-LABEL: name: test_add_s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -113,7 +108,6 @@ body: |
; GFX8-NEXT: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC1]]
; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ADD]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ZEXT]](s32)
- ;
; GFX9-LABEL: name: test_add_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -158,7 +152,6 @@ body: |
; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX8-LABEL: name: test_add_v2s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -181,7 +174,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_add_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -216,7 +208,6 @@ body: |
; GFX6-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY5]]
; GFX6-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD2]](s32)
; GFX6-NEXT: S_ENDPGM 0, implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16)
- ;
; GFX8-LABEL: name: test_add_v3s16
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; GFX8-NEXT: {{ $}}
@@ -236,7 +227,6 @@ body: |
; GFX8-NEXT: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[TRUNC4]]
; GFX8-NEXT: [[ADD2:%[0-9]+]]:_(s16) = G_ADD [[TRUNC2]], [[TRUNC5]]
; GFX8-NEXT: S_ENDPGM 0, implicit [[ADD]](s16), implicit [[ADD1]](s16), implicit [[ADD2]](s16)
- ;
; GFX9-LABEL: name: test_add_v3s16
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; GFX9-NEXT: {{ $}}
@@ -325,7 +315,6 @@ body: |
; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX8-LABEL: name: test_add_v4s16
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -366,7 +355,6 @@ body: |
; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_add_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -401,7 +389,6 @@ body: |
; GFX6-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX8-LABEL: name: test_add_s64
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -413,7 +400,6 @@ body: |
; GFX8-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX9-LABEL: name: test_add_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -446,7 +432,6 @@ body: |
; GFX6-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; GFX6-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX8-LABEL: name: test_add_s7
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -455,11 +440,10 @@ body: |
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8-NEXT: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC1]]
- ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
+ ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
; GFX8-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX9-LABEL: name: test_add_s7
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -468,8 +452,8 @@ body: |
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
; GFX9-NEXT: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
@@ -494,7 +478,6 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; GFX6-NEXT: $vgpr0 = COPY [[ADD]](s32)
- ;
; GFX8-LABEL: name: test_add_s24
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -502,7 +485,6 @@ body: |
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; GFX8-NEXT: $vgpr0 = COPY [[ADD]](s32)
- ;
; GFX9-LABEL: name: test_add_s24
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -535,7 +517,6 @@ body: |
; GFX6-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX8-LABEL: name: test_add_s33
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -547,7 +528,6 @@ body: |
; GFX8-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX9-LABEL: name: test_add_s33
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -586,7 +566,6 @@ body: |
; GFX6-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV2]], [[UV5]], [[UADDE1]]
; GFX6-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32), [[UADDE2]](s32)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
- ;
; GFX8-LABEL: name: test_add_s96
; GFX8: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX8-NEXT: {{ $}}
@@ -599,7 +578,6 @@ body: |
; GFX8-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV2]], [[UV5]], [[UADDE1]]
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32), [[UADDE2]](s32)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
- ;
; GFX9-LABEL: name: test_add_s96
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
index 66e95921679e504..60f626491c6b4c7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
@@ -469,9 +469,10 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL1]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV6]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS2]](<6 x s16>)
@@ -530,9 +531,10 @@ body: |
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
@@ -541,34 +543,38 @@ body: |
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[SHL1]]
; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL2]]
; CHECK-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL3]]
; CHECK-NEXT: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS3:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST8]](<2 x s16>), [[BITCAST9]](<2 x s16>)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<4 x s16>) = G_AND [[CONCAT_VECTORS2]], [[CONCAT_VECTORS3]]
- ; CHECK-NEXT: [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[AND3]](<4 x s16>)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(<4 x s16>) = G_AND [[CONCAT_VECTORS2]], [[CONCAT_VECTORS3]]
+ ; CHECK-NEXT: [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[AND5]](<4 x s16>)
; CHECK-NEXT: [[BITCAST10:%[0-9]+]]:_(s32) = G_BITCAST [[UV8]](<2 x s16>)
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST10]], [[C]](s32)
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>), [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF2]](<8 x s16>)
; CHECK-NEXT: [[BITCAST11:%[0-9]+]]:_(s32) = G_BITCAST [[UV12]](<2 x s16>)
; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST11]], [[C]](s32)
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C]](s32)
- ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL4]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL4]]
; CHECK-NEXT: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST10]], [[C1]]
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
- ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL5]]
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[BITCAST10]], [[C1]]
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL5]]
; CHECK-NEXT: [[BITCAST13:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[LSHR4]], [[C]](s32)
- ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL6]]
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C]](s32)
+ ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL6]]
; CHECK-NEXT: [[BITCAST14:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS4:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST12]](<2 x s16>), [[BITCAST13]](<2 x s16>), [[BITCAST14]](<2 x s16>), [[UV13]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS4]](<8 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
index 59adc212386a202..023617350e52f80 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
@@ -620,8 +620,8 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
@@ -631,12 +631,13 @@ body: |
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C4]](s16)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C3]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C4]](s16)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C3]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C4]](s16)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[SHL2]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C3]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND4]], [[C4]](s16)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL2]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY [[OR2]](s16)
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
@@ -684,7 +685,8 @@ body: |
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
index f4aaab745e03b57..68ce57cf51c6f24 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
@@ -18,7 +18,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; VI-LABEL: name: test_ashr_s32_s32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -26,7 +25,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
; VI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s32_s32
; GFX9PLUS: liveins: $vgpr0, $vgpr1
; GFX9PLUS-NEXT: {{ $}}
@@ -53,7 +51,6 @@ body: |
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[TRUNC]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
- ;
; VI-LABEL: name: test_ashr_s64_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -62,7 +59,6 @@ body: |
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[TRUNC]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s64_s64
; GFX9PLUS: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9PLUS-NEXT: {{ $}}
@@ -89,7 +85,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
- ;
; VI-LABEL: name: test_ashr_s64_s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -97,7 +92,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s64_s32
; GFX9PLUS: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9PLUS-NEXT: {{ $}}
@@ -125,7 +119,6 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
- ;
; VI-LABEL: name: test_ashr_s64_s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -135,7 +128,6 @@ body: |
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s64_s16
; GFX9PLUS: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9PLUS-NEXT: {{ $}}
@@ -166,7 +158,6 @@ body: |
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; VI-LABEL: name: test_ashr_s16_s32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -177,7 +168,6 @@ body: |
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s16_s32
; GFX9PLUS: liveins: $vgpr0, $vgpr1
; GFX9PLUS-NEXT: {{ $}}
@@ -212,7 +202,6 @@ body: |
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; VI-LABEL: name: test_ashr_s16_s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -223,7 +212,6 @@ body: |
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s16_s16
; GFX9PLUS: liveins: $vgpr0, $vgpr1
; GFX9PLUS-NEXT: {{ $}}
@@ -259,28 +247,26 @@ body: |
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; VI-LABEL: name: test_ashr_s16_i8
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s16_i8
; GFX9PLUS: liveins: $vgpr0, $vgpr1
; GFX9PLUS-NEXT: {{ $}}
; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9PLUS-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9PLUS-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9PLUS-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9PLUS-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s16)
; GFX9PLUS-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
@@ -310,14 +296,13 @@ body: |
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; VI-LABEL: name: test_ashr_i8_i8
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
@@ -326,14 +311,13 @@ body: |
; VI-NEXT: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[AND]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR1]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9PLUS-LABEL: name: test_ashr_i8_i8
; GFX9PLUS: liveins: $vgpr0, $vgpr1
; GFX9PLUS-NEXT: {{ $}}
; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9PLUS-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9PLUS-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9PLUS-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9PLUS-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX9PLUS-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
@@ -365,14 +349,13 @@ body: |
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; VI-LABEL: name: test_ashr_s7_s7
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 127
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
@@ -381,14 +364,13 @@ body: |
; VI-NEXT: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[AND]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR1]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s7_s7
; GFX9PLUS: liveins: $vgpr0, $vgpr1
; GFX9PLUS-NEXT: {{ $}}
; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9PLUS-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 127
+ ; GFX9PLUS-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9PLUS-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9PLUS-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
; GFX9PLUS-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
@@ -420,7 +402,6 @@ body: |
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 24
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; VI-LABEL: name: test_ashr_s24_s24
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -431,7 +412,6 @@ body: |
; VI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 24
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; VI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s24_s24
; GFX9PLUS: liveins: $vgpr0, $vgpr1
; GFX9PLUS-NEXT: {{ $}}
@@ -466,7 +446,6 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[AND]](s32)
; SI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; VI-LABEL: name: test_ashr_s32_s24
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -476,7 +455,6 @@ body: |
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[AND]](s32)
; VI-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s32_s24
; GFX9PLUS: liveins: $vgpr0, $vgpr1
; GFX9PLUS-NEXT: {{ $}}
@@ -510,7 +488,6 @@ body: |
; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[UV3]](s32)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_ashr_v2s32_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -522,7 +499,6 @@ body: |
; VI-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[UV3]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9PLUS-LABEL: name: test_ashr_v2s32_v2s32
; GFX9PLUS: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9PLUS-NEXT: {{ $}}
@@ -558,7 +534,6 @@ body: |
; SI-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[UV2]], [[UV5]](s32)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_ashr_v3s32_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -571,7 +546,6 @@ body: |
; VI-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[UV2]], [[UV5]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9PLUS-LABEL: name: test_ashr_v3s32_v3s32
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9PLUS-NEXT: {{ $}}
@@ -607,7 +581,6 @@ body: |
; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[UV3]](s32)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ASHR]](s64), [[ASHR1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_ashr_v2s64_v2s32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -619,7 +592,6 @@ body: |
; VI-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[UV3]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ASHR]](s64), [[ASHR1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9PLUS-LABEL: name: test_ashr_v2s64_v2s32
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
; GFX9PLUS-NEXT: {{ $}}
@@ -657,7 +629,6 @@ body: |
; SI-NEXT: [[UV7:%[0-9]+]]:_(s64), [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64), [[UV10:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[ASHR]](s64), [[ASHR1]](s64), [[ASHR2]](s64), [[UV10]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_ashr_v3s64_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; VI-NEXT: {{ $}}
@@ -672,7 +643,6 @@ body: |
; VI-NEXT: [[UV7:%[0-9]+]]:_(s64), [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64), [[UV10:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[ASHR]](s64), [[ASHR1]](s64), [[ASHR2]](s64), [[UV10]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9PLUS-LABEL: name: test_ashr_v3s64_v3s32
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; GFX9PLUS-NEXT: {{ $}}
@@ -716,15 +686,15 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; SI-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
- ; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[LSHR1]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
+ ; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[AND1]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; VI-LABEL: name: test_ashr_v2s16_v2s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -747,7 +717,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9PLUS-LABEL: name: test_ashr_v2s16_v2s16
; GFX9PLUS: liveins: $vgpr0, $vgpr1
; GFX9PLUS-NEXT: {{ $}}
@@ -787,7 +756,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; VI-LABEL: name: test_ashr_v2s16_v2s32
; VI: liveins: $vgpr0, $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -809,7 +777,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; GFX9PLUS-LABEL: name: test_ashr_v2s16_v2s32
; GFX9PLUS: liveins: $vgpr0, $vgpr0_vgpr1
; GFX9PLUS-NEXT: {{ $}}
@@ -856,33 +823,34 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; SI-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
- ; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[LSHR1]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[AND1]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; SI-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
- ; SI-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[AND1]](s32)
+ ; SI-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[AND2]](s32)
; SI-NEXT: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; SI-NEXT: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>)
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL]]
; SI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ASHR2]], [[C1]]
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL1]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ASHR2]], [[C1]]
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL1]]
; SI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL2]]
; SI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_ashr_v3s16_v3s16
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -922,13 +890,13 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9PLUS-LABEL: name: test_ashr_v3s16_v3s16
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9PLUS-NEXT: {{ $}}
@@ -999,26 +967,27 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; SI-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
- ; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[LSHR2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[AND1]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; SI-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
- ; SI-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[AND1]](s32)
+ ; SI-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[AND2]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
; SI-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
- ; SI-NEXT: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[LSHR3]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
+ ; SI-NEXT: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[AND3]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ASHR2]], [[C1]]
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C1]]
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL1]]
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ASHR2]], [[C1]]
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C1]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL1]]
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_ashr_v4s16_v4s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -1059,7 +1028,6 @@ body: |
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9PLUS-LABEL: name: test_ashr_v4s16_v4s16
; GFX9PLUS: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9PLUS-NEXT: {{ $}}
@@ -1088,13 +1056,13 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C1]]
+ ; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[COPY1]]
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C1]]
+ ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[COPY1]](s32)
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[COPY1]](s32)
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[SUB1]](s32)
@@ -1107,19 +1075,18 @@ body: |
; SI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[ASHR]], [[ASHR1]]
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_ashr_s128_s128
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; VI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C1]]
+ ; VI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[COPY1]]
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C1]]
+ ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[COPY1]](s32)
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[COPY1]](s32)
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[SUB1]](s32)
@@ -1132,19 +1099,18 @@ body: |
; VI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[ASHR]], [[ASHR1]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s128_s128
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9PLUS-NEXT: {{ $}}
; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; GFX9PLUS-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9PLUS-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; GFX9PLUS-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; GFX9PLUS-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; GFX9PLUS-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9PLUS-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; GFX9PLUS-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; GFX9PLUS-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C1]]
+ ; GFX9PLUS-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[COPY1]]
+ ; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX9PLUS-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C1]]
+ ; GFX9PLUS-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[COPY1]](s32)
; GFX9PLUS-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[COPY1]](s32)
; GFX9PLUS-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[SUB1]](s32)
@@ -1194,7 +1160,6 @@ body: |
; SI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[ASHR]], [[ASHR1]]
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_ashr_s128_s132
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1219,7 +1184,6 @@ body: |
; VI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[ASHR]], [[ASHR1]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s128_s132
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9PLUS-NEXT: {{ $}}
@@ -1261,13 +1225,11 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY]](s128)
- ;
; VI-LABEL: name: test_ashr_s128_s32_0
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY]](s128)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s128_s32_0
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9PLUS-NEXT: {{ $}}
@@ -1299,7 +1261,6 @@ body: |
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_ashr_s128_s32_23
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1313,7 +1274,6 @@ body: |
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s128_s32_23
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9PLUS-NEXT: {{ $}}
@@ -1352,7 +1312,6 @@ body: |
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_ashr_s128_s32_31
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1366,7 +1325,6 @@ body: |
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s128_s32_31
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9PLUS-NEXT: {{ $}}
@@ -1404,7 +1362,6 @@ body: |
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_ashr_s128_s32_32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1417,7 +1374,6 @@ body: |
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s128_s32_32
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9PLUS-NEXT: {{ $}}
@@ -1455,7 +1411,6 @@ body: |
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_ashr_s128_s32_33
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1469,7 +1424,6 @@ body: |
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[ASHR]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s128_s32_33
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9PLUS-NEXT: {{ $}}
@@ -1505,7 +1459,6 @@ body: |
; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_ashr_s128_s32_127
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1516,7 +1469,6 @@ body: |
; VI-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s128_s32_127
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9PLUS-NEXT: {{ $}}
@@ -1544,71 +1496,71 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
+ ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; SI-NEXT: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](s256)
- ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
- ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
+ ; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
+ ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; SI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; SI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; SI-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; SI-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; SI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; SI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; SI-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; SI-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; SI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[COPY1]](s32)
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[COPY1]](s32)
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[SUB3]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
- ; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
- ; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C3]](s32)
+ ; SI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
+ ; SI-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C4]](s32)
; SI-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[SUB2]](s32)
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[ASHR2]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]]
; SI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[ASHR]], [[ASHR1]]
; SI-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
- ; SI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; SI-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; SI-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; SI-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; SI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; SI-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; SI-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; SI-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[COPY1]](s32)
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[COPY1]](s32)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[SHL1]]
- ; SI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
; SI-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR3]]
; SI-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]]
- ; SI-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR1]], [[C4]]
+ ; SI-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR1]], [[C1]]
; SI-NEXT: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; SI-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
- ; SI-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
- ; SI-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
- ; SI-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
+ ; SI-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C3]]
+ ; SI-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB1]]
+ ; SI-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C3]]
+ ; SI-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C]]
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB1]](s32)
; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB7]](s32)
; SI-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL3]]
; SI-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB6]](s32)
- ; SI-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C4]]
+ ; SI-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C1]]
; SI-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[SHL4]]
; SI-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV7]], [[SELECT7]]
; SI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT6]]
; SI-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; SI-NEXT: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; SI-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C3]](s32)
- ; SI-NEXT: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C3]](s32)
+ ; SI-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C4]](s32)
+ ; SI-NEXT: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C4]](s32)
; SI-NEXT: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; SI-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
- ; SI-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
- ; SI-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
- ; SI-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
+ ; SI-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C3]]
+ ; SI-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB]]
+ ; SI-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C3]]
+ ; SI-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C]]
; SI-NEXT: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB]](s32)
; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV10]], [[SUB]](s32)
; SI-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV11]], [[SUB9]](s32)
; SI-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR5]], [[SHL5]]
- ; SI-NEXT: [[ASHR6:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[C3]](s32)
+ ; SI-NEXT: [[ASHR6:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[C4]](s32)
; SI-NEXT: [[ASHR7:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB8]](s32)
; SI-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[ASHR7]]
; SI-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV10]], [[SELECT9]]
@@ -1624,77 +1576,76 @@ body: |
; SI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64)
; SI-NEXT: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV2]](s256)
- ;
; VI-LABEL: name: test_ashr_s256_s256
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
+ ; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; VI-NEXT: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](s256)
- ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; VI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
- ; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
+ ; VI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
+ ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; VI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; VI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; VI-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; VI-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; VI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; VI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; VI-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; VI-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; VI-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[COPY1]](s32)
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[COPY1]](s32)
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[SUB3]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
- ; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
- ; VI-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C3]](s32)
+ ; VI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
+ ; VI-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C4]](s32)
; VI-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[SUB2]](s32)
; VI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[ASHR2]]
; VI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]]
; VI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[ASHR]], [[ASHR1]]
; VI-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
- ; VI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; VI-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; VI-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; VI-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; VI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; VI-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; VI-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; VI-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[COPY1]](s32)
; VI-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[COPY1]](s32)
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[SHL1]]
- ; VI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
; VI-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR3]]
; VI-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]]
- ; VI-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR1]], [[C4]]
+ ; VI-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR1]], [[C1]]
; VI-NEXT: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; VI-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
- ; VI-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
- ; VI-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
- ; VI-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
+ ; VI-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C3]]
+ ; VI-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB1]]
+ ; VI-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C3]]
+ ; VI-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C]]
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB1]](s32)
; VI-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB7]](s32)
; VI-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL3]]
; VI-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB6]](s32)
- ; VI-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C4]]
+ ; VI-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C1]]
; VI-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[SHL4]]
; VI-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV7]], [[SELECT7]]
; VI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT6]]
; VI-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; VI-NEXT: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; VI-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C3]](s32)
- ; VI-NEXT: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C3]](s32)
+ ; VI-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C4]](s32)
+ ; VI-NEXT: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C4]](s32)
; VI-NEXT: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; VI-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
- ; VI-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
- ; VI-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
- ; VI-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
+ ; VI-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C3]]
+ ; VI-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB]]
+ ; VI-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C3]]
+ ; VI-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C]]
; VI-NEXT: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB]](s32)
; VI-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV10]], [[SUB]](s32)
; VI-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV11]], [[SUB9]](s32)
; VI-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR5]], [[SHL5]]
- ; VI-NEXT: [[ASHR6:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[C3]](s32)
+ ; VI-NEXT: [[ASHR6:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[C4]](s32)
; VI-NEXT: [[ASHR7:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB8]](s32)
; VI-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[ASHR7]]
; VI-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV10]], [[SELECT9]]
@@ -1710,77 +1661,76 @@ body: |
; VI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64)
; VI-NEXT: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV2]](s256)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s256_s256
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8
; GFX9PLUS-NEXT: {{ $}}
; GFX9PLUS-NEXT: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9PLUS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
+ ; GFX9PLUS-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; GFX9PLUS-NEXT: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](s256)
- ; GFX9PLUS-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; GFX9PLUS-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; GFX9PLUS-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9PLUS-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; GFX9PLUS-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
- ; GFX9PLUS-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; GFX9PLUS-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
+ ; GFX9PLUS-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
+ ; GFX9PLUS-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX9PLUS-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
+ ; GFX9PLUS-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; GFX9PLUS-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9PLUS-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; GFX9PLUS-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; GFX9PLUS-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; GFX9PLUS-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; GFX9PLUS-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; GFX9PLUS-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; GFX9PLUS-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; GFX9PLUS-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; GFX9PLUS-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GFX9PLUS-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[COPY1]](s32)
; GFX9PLUS-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[COPY1]](s32)
; GFX9PLUS-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[SUB3]](s32)
; GFX9PLUS-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
- ; GFX9PLUS-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
- ; GFX9PLUS-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C3]](s32)
+ ; GFX9PLUS-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
+ ; GFX9PLUS-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C4]](s32)
; GFX9PLUS-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[SUB2]](s32)
; GFX9PLUS-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[ASHR2]]
; GFX9PLUS-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]]
; GFX9PLUS-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[ASHR]], [[ASHR1]]
; GFX9PLUS-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
- ; GFX9PLUS-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; GFX9PLUS-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; GFX9PLUS-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; GFX9PLUS-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; GFX9PLUS-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; GFX9PLUS-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; GFX9PLUS-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; GFX9PLUS-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GFX9PLUS-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[COPY1]](s32)
; GFX9PLUS-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[COPY1]](s32)
; GFX9PLUS-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32)
; GFX9PLUS-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[SHL1]]
- ; GFX9PLUS-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; GFX9PLUS-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9PLUS-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
; GFX9PLUS-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR3]]
; GFX9PLUS-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]]
- ; GFX9PLUS-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR1]], [[C4]]
+ ; GFX9PLUS-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR1]], [[C1]]
; GFX9PLUS-NEXT: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; GFX9PLUS-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
- ; GFX9PLUS-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
- ; GFX9PLUS-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
- ; GFX9PLUS-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
+ ; GFX9PLUS-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C3]]
+ ; GFX9PLUS-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB1]]
+ ; GFX9PLUS-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C3]]
+ ; GFX9PLUS-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C]]
; GFX9PLUS-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB1]](s32)
; GFX9PLUS-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB7]](s32)
; GFX9PLUS-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32)
; GFX9PLUS-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL3]]
; GFX9PLUS-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB6]](s32)
- ; GFX9PLUS-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C4]]
+ ; GFX9PLUS-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C1]]
; GFX9PLUS-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[SHL4]]
; GFX9PLUS-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV7]], [[SELECT7]]
; GFX9PLUS-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT6]]
; GFX9PLUS-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; GFX9PLUS-NEXT: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; GFX9PLUS-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C3]](s32)
- ; GFX9PLUS-NEXT: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C3]](s32)
+ ; GFX9PLUS-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C4]](s32)
+ ; GFX9PLUS-NEXT: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[UV9]], [[C4]](s32)
; GFX9PLUS-NEXT: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; GFX9PLUS-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
- ; GFX9PLUS-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
- ; GFX9PLUS-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
- ; GFX9PLUS-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
+ ; GFX9PLUS-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C3]]
+ ; GFX9PLUS-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB]]
+ ; GFX9PLUS-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C3]]
+ ; GFX9PLUS-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C]]
; GFX9PLUS-NEXT: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB]](s32)
; GFX9PLUS-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV10]], [[SUB]](s32)
; GFX9PLUS-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV11]], [[SUB9]](s32)
; GFX9PLUS-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR5]], [[SHL5]]
- ; GFX9PLUS-NEXT: [[ASHR6:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[C3]](s32)
+ ; GFX9PLUS-NEXT: [[ASHR6:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[C4]](s32)
; GFX9PLUS-NEXT: [[ASHR7:%[0-9]+]]:_(s64) = G_ASHR [[UV11]], [[SUB8]](s32)
; GFX9PLUS-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[ASHR7]]
; GFX9PLUS-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV10]], [[SELECT9]]
@@ -1851,7 +1801,6 @@ body: |
; SI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
- ;
; VI-LABEL: name: test_ashr_v2s128_v2s32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -1894,7 +1843,6 @@ body: |
; VI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
- ;
; GFX9PLUS-LABEL: name: test_ashr_v2s128_v2s32
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr4_vgpr5
; GFX9PLUS-NEXT: {{ $}}
@@ -1979,7 +1927,6 @@ body: |
; SI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
- ;
; VI-LABEL: name: test_ashr_s65_s32
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; VI-NEXT: {{ $}}
@@ -2010,7 +1957,6 @@ body: |
; VI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s65_s32
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; GFX9PLUS-NEXT: {{ $}}
@@ -2084,7 +2030,6 @@ body: |
; SI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
- ;
; VI-LABEL: name: test_ashr_s65_s32_constant8
; VI: liveins: $vgpr0_vgpr1_vgpr2
; VI-NEXT: {{ $}}
@@ -2114,7 +2059,6 @@ body: |
; VI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s65_s32_constant8
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2
; GFX9PLUS-NEXT: {{ $}}
@@ -2189,7 +2133,6 @@ body: |
; SI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
- ;
; VI-LABEL: name: test_ashr_s65_s32_known_pow2
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; VI-NEXT: {{ $}}
@@ -2221,7 +2164,6 @@ body: |
; VI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
- ;
; GFX9PLUS-LABEL: name: test_ashr_s65_s32_known_pow2
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; GFX9PLUS-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
index 8b5c27288453e6d..18a7032300afe49 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
@@ -440,8 +440,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -529,8 +529,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -968,8 +968,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<8 x s32>)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -1645,8 +1645,8 @@ body: |
; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[UV5]](s32)
; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[UV6]](s32)
; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[UV7]](s32)
- ; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C]]
; CHECK-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC9]], [[C]]
@@ -2018,8 +2018,8 @@ body: |
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<16 x s32>)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[UV1]](s32)
- ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C]]
@@ -2285,54 +2285,60 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[LSHR3]](s16)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C2]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C2]]
; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[LSHR4]](s16)
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT2]], [[C]](s32)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL2]]
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[LSHR5]](s16)
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32)
- ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL3]]
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL3]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C2]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C2]]
; CHECK-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[LSHR8]](s16)
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT4]], [[C]](s32)
- ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL4]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C2]]
; CHECK-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[LSHR9]](s16)
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ZEXT5]], [[C]](s32)
- ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR6]], [[SHL5]]
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL5]]
; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[C2]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[C2]]
; CHECK-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[LSHR10]](s16)
; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT6]], [[C]](s32)
- ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL6]]
+ ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL6]]
; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C2]]
; CHECK-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[LSHR11]](s16)
; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[ZEXT7]], [[C]](s32)
- ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[LSHR7]], [[SHL7]]
+ ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL7]]
; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR7]](s32)
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[C2]]
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[C2]]
; CHECK-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[LSHR14]](s16)
; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[ZEXT8]], [[C]](s32)
- ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL8]]
+ ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL8]]
; CHECK-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR8]](s32)
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C2]]
; CHECK-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[LSHR15]](s16)
; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[ZEXT9]], [[C]](s32)
- ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[LSHR12]], [[SHL9]]
+ ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SHL9]]
; CHECK-NEXT: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR9]](s32)
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UV8]], [[C2]]
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[UV8]], [[C2]]
; CHECK-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[LSHR16]](s16)
; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[ZEXT10]], [[C]](s32)
- ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL10]]
+ ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL10]]
; CHECK-NEXT: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR10]](s32)
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C2]]
; CHECK-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[LSHR17]](s16)
; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[ZEXT11]], [[C]](s32)
- ; CHECK-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[LSHR13]], [[SHL11]]
+ ; CHECK-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[AND11]], [[SHL11]]
; CHECK-NEXT: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR11]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<24 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>), [[BITCAST9]](<2 x s16>), [[BITCAST10]](<2 x s16>), [[BITCAST11]](<2 x s16>)
; CHECK-NEXT: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<24 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
index 92eb440fbd8ea61..5a147ca27d34009 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
@@ -98,8 +98,11 @@ body: |
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
; CHECK-NEXT: [[BITREVERSE1:%[0-9]+]]:_(s32) = G_BITREVERSE [[LSHR]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE1]], [[C]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
index a98ac9967185cbf..2b855e33e96d4d5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
@@ -13,13 +13,14 @@ body: |
; GFX7-NEXT: {{ $}}
; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX7-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; GFX7-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX7-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; GFX7-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
+ ; GFX7-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
; GFX7-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
; GFX7-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX8-LABEL: name: bswap_s8
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
@@ -58,7 +59,6 @@ body: |
; GFX7-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC1]], [[TRUNC]]
; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX7-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX8-LABEL: name: bswap_s16
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
@@ -85,13 +85,14 @@ body: |
; GFX7-NEXT: {{ $}}
; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; GFX7-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; GFX7-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX7-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; GFX7-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
+ ; GFX7-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
; GFX7-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
; GFX7-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX8-LABEL: name: bswap_s24
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
@@ -119,7 +120,6 @@ body: |
; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; GFX7-NEXT: $vgpr0 = COPY [[BSWAP]](s32)
- ;
; GFX8-LABEL: name: bswap_s32
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
@@ -157,7 +157,8 @@ body: |
; GFX7-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[COPY2]](s32)
; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; GFX7-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX7-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; GFX7-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX7-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; GFX7-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
; GFX7-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC3]], [[TRUNC2]]
; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -166,7 +167,6 @@ body: |
; GFX7-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; GFX7-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX7-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; GFX8-LABEL: name: bswap_v2s16
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
@@ -221,7 +221,6 @@ body: |
; GFX7-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX7-NEXT: $vgpr1 = COPY [[ANYEXT1]](s32)
; GFX7-NEXT: $vgpr2 = COPY [[ANYEXT2]](s32)
- ;
; GFX8-LABEL: name: bswap_v3s16
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8-NEXT: {{ $}}
@@ -295,22 +294,24 @@ body: |
; GFX7-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[COPY2]](s32)
; GFX7-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; GFX7-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX7-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; GFX7-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX7-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; GFX7-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; GFX7-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC3]], [[TRUNC2]]
; GFX7-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[COPY4]](s32)
; GFX7-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; GFX7-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX7-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
- ; GFX7-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
+ ; GFX7-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
+ ; GFX7-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; GFX7-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
; GFX7-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[TRUNC5]], [[TRUNC4]]
; GFX7-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[COPY6]](s32)
; GFX7-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; GFX7-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX7-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[COPY7]](s32)
+ ; GFX7-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; GFX7-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY7]](s32)
; GFX7-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](s32)
; GFX7-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[TRUNC7]], [[TRUNC6]]
; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -325,7 +326,6 @@ body: |
; GFX7-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; GFX7-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX8-LABEL: name: bswap_v4s16
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
@@ -355,7 +355,6 @@ body: |
; GFX7-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[UV1]]
; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[BSWAP]](s32), [[BSWAP1]](s32)
; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX8-LABEL: name: bswap_v2s32
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
@@ -385,7 +384,6 @@ body: |
; GFX7-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[UV]]
; GFX7-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[BSWAP]](s32), [[BSWAP1]](s32)
; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX8-LABEL: name: bswap_s64
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
@@ -421,7 +419,6 @@ body: |
; GFX7-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[BSWAP2]](s32), [[BSWAP3]](s32)
; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; GFX7-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX8-LABEL: name: bswap_v2s64
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
index e9f8180aae66bb0..c82de08bb6e50dc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
@@ -156,13 +156,14 @@ body: |
; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32)
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF]], [[C]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[LSHR]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND1]](s32)
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF1]], [[C]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
@@ -213,8 +214,8 @@ body: |
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[CTLZ_ZERO_UNDEF]], [[UV]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[USUBO]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[USUBO]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT1]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CTLZ_ZERO_UNDEF %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
index dd116927779b5fb..318960e578f4477 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
@@ -72,7 +72,9 @@ body: |
; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]]
- ; CHECK-NEXT: $vgpr0 = COPY [[UMIN]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UMIN]], [[C1]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_CTLZ %0
%2:_(s32) = G_ZEXT %1
@@ -172,14 +174,15 @@ body: |
; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C2]]
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK-NEXT: [[AMDGPU_FFBH_U32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[LSHR]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AMDGPU_FFBH_U32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND1]](s32)
; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_1]], [[C2]]
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UMIN1]], [[C]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
@@ -234,8 +237,8 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)
; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UMIN]], [[UV]]
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[USUBO]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[USUBO]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT1]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CTLZ %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
index f183271cd5f2792..cacf2f449a62331 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
@@ -14,7 +14,8 @@ body: |
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s8) = G_CTPOP %1
@@ -35,7 +36,8 @@ body: |
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s9) = G_TRUNC %0
%2:_(s9) = G_CTPOP %1
@@ -106,7 +108,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[CTPOP]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[CTPOP]], [[C]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_CTPOP %0
%2:_(s32) = G_ZEXT %1
@@ -127,7 +131,8 @@ body: |
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s16) = G_CTPOP %1
@@ -192,10 +197,13 @@ body: |
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
- ; CHECK-NEXT: [[CTPOP1:%[0-9]+]]:_(s32) = G_CTPOP [[LSHR]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[CTPOP1:%[0-9]+]]:_(s32) = G_CTPOP [[AND1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP1]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[SHL]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
@@ -218,7 +226,8 @@ body: |
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
%2:_(s7) = G_CTPOP %1
@@ -258,12 +267,12 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C]]
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C1]]
; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s64)
@@ -286,12 +295,12 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C]]
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C1]]
; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s64)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
index 0ef31a602961cb4..39d51cdd6a74313 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
@@ -72,7 +72,9 @@ body: |
; CHECK-NEXT: [[AMDGPU_FFBL_B32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[COPY]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[C]]
- ; CHECK-NEXT: $vgpr0 = COPY [[UMIN]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UMIN]], [[C1]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_CTTZ %0
%2:_(s32) = G_ZEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
index 801d2e918f0877d..4a85edd75a9dc5f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
@@ -18,14 +18,12 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
; SI-NEXT: $vgpr0 = COPY [[FABS]](s32)
- ;
; VI-LABEL: name: test_fabs_s32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
; VI-NEXT: $vgpr0 = COPY [[FABS]](s32)
- ;
; GFX9-LABEL: name: test_fabs_s32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -49,14 +47,12 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[FABS]](s64)
- ;
; VI-LABEL: name: test_fabs_s64
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[FABS]](s64)
- ;
; GFX9-LABEL: name: test_fabs_s64
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -81,7 +77,6 @@ body: |
; SI-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[TRUNC]]
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FABS]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; VI-LABEL: name: test_fabs_s16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -90,7 +85,6 @@ body: |
; VI-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[TRUNC]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FABS]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_fabs_s16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -121,7 +115,6 @@ body: |
; SI-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FABS]](s32), [[FABS1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_fabs_v2s32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -131,7 +124,6 @@ body: |
; VI-NEXT: [[FABS1:%[0-9]+]]:_(s32) = G_FABS [[UV1]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FABS]](s32), [[FABS1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_fabs_v2s32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -162,7 +154,6 @@ body: |
; SI-NEXT: [[FABS2:%[0-9]+]]:_(s32) = G_FABS [[UV2]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FABS]](s32), [[FABS1]](s32), [[FABS2]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_fabs_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2
; VI-NEXT: {{ $}}
@@ -173,7 +164,6 @@ body: |
; VI-NEXT: [[FABS2:%[0-9]+]]:_(s32) = G_FABS [[UV2]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FABS]](s32), [[FABS1]](s32), [[FABS2]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_fabs_v3s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
@@ -204,7 +194,6 @@ body: |
; SI-NEXT: [[FABS1:%[0-9]+]]:_(s64) = G_FABS [[UV1]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FABS]](s64), [[FABS1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_fabs_v2s64
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -214,7 +203,6 @@ body: |
; VI-NEXT: [[FABS1:%[0-9]+]]:_(s64) = G_FABS [[UV1]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FABS]](s64), [[FABS1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_fabs_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -241,14 +229,12 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; SI-NEXT: [[FABS:%[0-9]+]]:_(<2 x s16>) = G_FABS [[COPY]]
; SI-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
- ;
; VI-LABEL: name: test_fabs_v2s16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; VI-NEXT: [[FABS:%[0-9]+]]:_(<2 x s16>) = G_FABS [[COPY]]
; VI-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_fabs_v2s16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -282,19 +268,19 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[FABS1]](<2 x s16>)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL2]]
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL2]]
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; SI-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL3]]
+ ; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; SI-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL3]]
; SI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
; SI-NEXT: S_NOP 0, implicit [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_fabs_v3s16
; VI: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
@@ -312,19 +298,19 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[FABS1]](<2 x s16>)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL2]]
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL2]]
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; VI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; VI-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL3]]
+ ; VI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; VI-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL3]]
; VI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
; VI-NEXT: S_NOP 0, implicit [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_fabs_v3s16
; GFX9: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
@@ -367,7 +353,6 @@ body: |
; SI-NEXT: [[FABS1:%[0-9]+]]:_(<2 x s16>) = G_FABS [[UV1]]
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[FABS]](<2 x s16>), [[FABS1]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_fabs_v4s16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -377,7 +362,6 @@ body: |
; VI-NEXT: [[FABS1:%[0-9]+]]:_(<2 x s16>) = G_FABS [[UV1]]
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[FABS]](<2 x s16>), [[FABS1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_fabs_v4s16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
index 8b6e53cb7826772..92cde9de38cb792 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
@@ -18,7 +18,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
; SI-NEXT: $vgpr0 = COPY [[FADD]](s32)
- ;
; VI-LABEL: name: test_fadd_s32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -26,7 +25,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
; VI-NEXT: $vgpr0 = COPY [[FADD]](s32)
- ;
; GFX9-LABEL: name: test_fadd_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -53,7 +51,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
- ;
; VI-LABEL: name: test_fadd_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -61,7 +58,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; VI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
- ;
; GFX9-LABEL: name: test_fadd_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -94,7 +90,6 @@ body: |
; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; VI-LABEL: name: test_fadd_s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -105,7 +100,6 @@ body: |
; VI-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[TRUNC]], [[TRUNC1]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_fadd_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -143,7 +137,6 @@ body: |
; SI-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[UV1]], [[UV3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_fadd_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -155,7 +148,6 @@ body: |
; VI-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[UV1]], [[UV3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_fadd_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -190,7 +182,6 @@ body: |
; SI-NEXT: [[FADD1:%[0-9]+]]:_(s32) = nnan G_FADD [[UV1]], [[UV3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_fadd_v2s32_flags
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -202,7 +193,6 @@ body: |
; VI-NEXT: [[FADD1:%[0-9]+]]:_(s32) = nnan G_FADD [[UV1]], [[UV3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_fadd_v2s32_flags
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -238,7 +228,6 @@ body: |
; SI-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[UV2]], [[UV5]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32), [[FADD2]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_fadd_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -251,7 +240,6 @@ body: |
; VI-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[UV2]], [[UV5]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32), [[FADD2]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_fadd_v3s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -287,7 +275,6 @@ body: |
; SI-NEXT: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[UV1]], [[UV3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD]](s64), [[FADD1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_fadd_v2s64
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: {{ $}}
@@ -299,7 +286,6 @@ body: |
; VI-NEXT: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[UV1]], [[UV3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD]](s64), [[FADD1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_fadd_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: {{ $}}
@@ -351,7 +337,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; VI-LABEL: name: test_fadd_v2s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -374,7 +359,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_fadd_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -441,13 +425,13 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_fadd_v3s16
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -487,13 +471,13 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_fadd_v3s16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -599,7 +583,6 @@ body: |
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_fadd_v4s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -640,7 +623,6 @@ body: |
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_fadd_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
index ac72bf1dbbb6fa7..6f086c613eba8e2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
@@ -25,7 +25,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; VI-LABEL: name: test_copysign_s16_s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -40,7 +39,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_copysign_s16_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -81,7 +79,6 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND1]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_copysign_s32_s32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -93,7 +90,6 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND1]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_copysign_s32_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -128,7 +124,6 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
- ;
; VI-LABEL: name: test_copysign_s64_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -140,7 +135,6 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
- ;
; GFX9-LABEL: name: test_copysign_s64_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -178,7 +172,6 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
- ;
; VI-LABEL: name: test_copysign_s64_s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -193,7 +186,6 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
- ;
; GFX9-LABEL: name: test_copysign_s64_s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -234,7 +226,6 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND1]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_copysign_s32_s64
; VI: liveins: $vgpr0, $vgpr1_vgpr2
; VI-NEXT: {{ $}}
@@ -249,7 +240,6 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND1]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_copysign_s32_s64
; GFX9: liveins: $vgpr0, $vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
@@ -292,7 +282,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; VI-LABEL: name: test_copysign_s16_s32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -309,7 +298,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_copysign_s16_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -355,7 +343,6 @@ body: |
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND2]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_copysign_s32_s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -371,7 +358,6 @@ body: |
; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND2]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_copysign_s32_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -408,15 +394,14 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
; SI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
; SI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
- ;
; VI-LABEL: name: test_copysign_s64_s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -425,15 +410,14 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
; VI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
; VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]
; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
- ;
; GFX9-LABEL: name: test_copysign_s64_s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -442,8 +426,8 @@ body: |
; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)
@@ -479,7 +463,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; VI-LABEL: name: test_copysign_s16_s64
; VI: liveins: $vgpr0, $vgpr1_vgpr2
; VI-NEXT: {{ $}}
@@ -496,7 +479,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_copysign_s16_s64
; GFX9: liveins: $vgpr0, $vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
@@ -545,7 +527,6 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY1]], [[BITCAST]]
; SI-NEXT: [[OR2:%[0-9]+]]:_(<2 x s16>) = G_OR [[AND]], [[AND1]]
; SI-NEXT: $vgpr0 = COPY [[OR2]](<2 x s16>)
- ;
; VI-LABEL: name: test_copysign_v2s16_v2s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -564,7 +545,6 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY1]], [[BITCAST]]
; VI-NEXT: [[OR2:%[0-9]+]]:_(<2 x s16>) = G_OR [[AND]], [[AND1]]
; VI-NEXT: $vgpr0 = COPY [[OR2]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_copysign_v2s16_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -603,7 +583,6 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
; SI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = G_OR [[AND]], [[AND1]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
- ;
; VI-LABEL: name: test_copysign_v2s32_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -617,7 +596,6 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
; VI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = G_OR [[AND]], [[AND1]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_copysign_v2s32_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -660,7 +638,6 @@ body: |
; SI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[AND3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_copysign_v2s64_v2s64
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: {{ $}}
@@ -678,7 +655,6 @@ body: |
; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[AND3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_copysign_v2s64_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: {{ $}}
@@ -731,7 +707,6 @@ body: |
; SI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[AND3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_copysign_v2s64_v2s32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -755,7 +730,6 @@ body: |
; VI-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[AND3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_copysign_v2s64_v2s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -813,7 +787,6 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR2]], [[BUILD_VECTOR]]
; SI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = G_OR [[AND]], [[AND1]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
- ;
; VI-LABEL: name: test_copysign_v2s32_v2s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -835,7 +808,6 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR2]], [[BUILD_VECTOR]]
; VI-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = G_OR [[AND]], [[AND1]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_copysign_v2s32_v2s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -880,7 +852,6 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND1]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_copysign_s32_s32_flagss
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -892,7 +863,6 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND1]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_copysign_s32_s32_flagss
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -931,7 +901,6 @@ body: |
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND2]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_copysign_s32_s16_flags
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -947,7 +916,6 @@ body: |
; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND2]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_copysign_s32_s16_flags
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -993,7 +961,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = nnan G_OR [[AND]], [[AND1]]
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; VI-LABEL: name: test_copysign_s16_s32_flags
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -1010,7 +977,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s16) = nnan G_OR [[AND]], [[AND1]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_copysign_s16_s32_flags
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
index 2ccdc5d9c6b73d3..77a3e47d6deee67 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
@@ -19,7 +19,6 @@ body: |
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; SI-NEXT: $vgpr0 = COPY [[FMA]](s32)
- ;
; VI-LABEL: name: test_fma_s32
; VI: liveins: $vgpr0, $vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -28,7 +27,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; VI-NEXT: $vgpr0 = COPY [[FMA]](s32)
- ;
; GFX9-LABEL: name: test_fma_s32
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -57,7 +55,6 @@ body: |
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
; SI-NEXT: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[FMA]](s64)
- ;
; VI-LABEL: name: test_fma_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -66,7 +63,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
; VI-NEXT: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[FMA]](s64)
- ;
; GFX9-LABEL: name: test_fma_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -104,7 +100,6 @@ body: |
; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMA]](s32)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; VI-LABEL: name: test_fma_s16
; VI: liveins: $vgpr0, $vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -117,7 +112,6 @@ body: |
; VI-NEXT: [[FMA:%[0-9]+]]:_(s16) = G_FMA [[TRUNC]], [[TRUNC1]], [[TRUNC2]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMA]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_fma_s16
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -161,7 +155,6 @@ body: |
; SI-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[UV1]], [[UV3]], [[UV5]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMA]](s32), [[FMA1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_fma_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -175,7 +168,6 @@ body: |
; VI-NEXT: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[UV1]], [[UV3]], [[UV5]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMA]](s32), [[FMA1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_fma_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -216,7 +208,6 @@ body: |
; SI-NEXT: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[UV2]], [[UV5]], [[UV8]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMA]](s32), [[FMA1]](s32), [[FMA2]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_fma_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; VI-NEXT: {{ $}}
@@ -231,7 +222,6 @@ body: |
; VI-NEXT: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[UV2]], [[UV5]], [[UV8]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMA]](s32), [[FMA1]](s32), [[FMA2]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_fma_v3s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; GFX9-NEXT: {{ $}}
@@ -274,7 +264,6 @@ body: |
; SI-NEXT: [[FMA3:%[0-9]+]]:_(s32) = G_FMA [[UV3]], [[UV7]], [[UV11]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[FMA]](s32), [[FMA1]](s32), [[FMA2]](s32), [[FMA3]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; VI-LABEL: name: test_fma_v4s32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; VI-NEXT: {{ $}}
@@ -290,7 +279,6 @@ body: |
; VI-NEXT: [[FMA3:%[0-9]+]]:_(s32) = G_FMA [[UV3]], [[UV7]], [[UV11]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[FMA]](s32), [[FMA1]](s32), [[FMA2]](s32), [[FMA3]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_fma_v4s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; GFX9-NEXT: {{ $}}
@@ -332,7 +320,6 @@ body: |
; SI-NEXT: [[FMA1:%[0-9]+]]:_(s64) = G_FMA [[UV1]], [[UV3]], [[UV5]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FMA]](s64), [[FMA1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_fma_v2s64
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; VI-NEXT: {{ $}}
@@ -346,7 +333,6 @@ body: |
; VI-NEXT: [[FMA1:%[0-9]+]]:_(s64) = G_FMA [[UV1]], [[UV3]], [[UV5]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FMA]](s64), [[FMA1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_fma_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
; GFX9-NEXT: {{ $}}
@@ -408,7 +394,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x s16>)
- ;
; VI-LABEL: name: test_fma_v2s16
; VI: liveins: $vgpr0, $vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -436,7 +421,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST3]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_fma_v2s16
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -517,13 +501,13 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI-NEXT: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C1]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL2]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C1]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI-NEXT: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST8]](<2 x s16>), [[BITCAST9]](<2 x s16>), [[BITCAST10]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_fma_v3s16
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; VI-NEXT: {{ $}}
@@ -571,13 +555,13 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI-NEXT: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C1]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL2]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C1]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI-NEXT: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST8]](<2 x s16>), [[BITCAST9]](<2 x s16>), [[BITCAST10]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_fma_v3s16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
; GFX9-NEXT: {{ $}}
@@ -704,7 +688,6 @@ body: |
; SI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_fma_v4s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -755,7 +738,6 @@ body: |
; VI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_fma_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
index 78bed9e19c65e9a..2b42ee80b45e61b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
@@ -23,7 +23,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fmaxnum_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -33,7 +32,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fmaxnum_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -65,7 +63,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
; SI-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
- ;
; VI-LABEL: name: test_fmaxnum_s32_ieee_mode_off
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -73,7 +70,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
; VI-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
- ;
; GFX9-LABEL: name: test_fmaxnum_s32_ieee_mode_off
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -100,7 +96,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fmaxnum_s32_nnan
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -108,7 +103,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fmaxnum_s32_nnan
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -137,7 +131,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[FCANONICALIZE]]
; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fmaxnum_s32_nnan_lhs
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -146,7 +139,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[FCANONICALIZE]]
; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fmaxnum_s32_nnan_lhs
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -176,7 +168,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fmaxnum_s32_nnan_rhs
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -185,7 +176,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fmaxnum_s32_nnan_rhs
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -213,7 +203,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fmaxnum_s32_nnan_lhs_rhs
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -221,7 +210,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fmaxnum_s32_nnan_lhs_rhs
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -250,7 +238,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY1]]
; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s64) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[FMAXNUM_IEEE]](s64)
- ;
; VI-LABEL: name: test_fmaxnum_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -260,7 +247,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY1]]
; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s64) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[FMAXNUM_IEEE]](s64)
- ;
; GFX9-LABEL: name: test_fmaxnum_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -295,7 +281,6 @@ body: |
; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMAXNUM_IEEE]](s32)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; VI-LABEL: name: test_fmaxnum_s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -308,7 +293,6 @@ body: |
; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s16) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMAXNUM_IEEE]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_fmaxnum_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -351,7 +335,6 @@ body: |
; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMAXNUM_IEEE]](s32), [[FMAXNUM_IEEE1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_fmaxnum_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -367,7 +350,6 @@ body: |
; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMAXNUM_IEEE]](s32), [[FMAXNUM_IEEE1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_fmaxnum_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -423,7 +405,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; VI-LABEL: name: test_fmaxnum_v2s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -450,7 +431,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_fmaxnum_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -519,13 +499,13 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_fmaxnum_v3s16
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -571,13 +551,13 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_fmaxnum_v3s16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -687,7 +667,6 @@ body: |
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_fmaxnum_v4s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -736,7 +715,6 @@ body: |
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_fmaxnum_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -780,7 +758,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](s32)
- ;
; VI-LABEL: name: test_fmaxnum_with_fmaxnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -794,7 +771,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](s32)
- ;
; GFX9-LABEL: name: test_fmaxnum_with_fmaxnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -836,7 +812,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; SI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](s32)
- ;
; VI-LABEL: name: test_fmaxnum_with_nonNaN_fmaxnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -848,7 +823,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; VI-NEXT: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE1]](s32)
- ;
; GFX9-LABEL: name: test_fmaxnum_with_nonNaN_fmaxnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -890,7 +864,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fmaxnum_with_fminnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -904,7 +877,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fmaxnum_with_fminnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -946,7 +918,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fmaxnum_with_nonNaN_fminnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -958,7 +929,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fmaxnum_with_nonNaN_fminnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -995,7 +965,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
; SI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
; SI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fmaxnum_with_constant_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -1004,7 +973,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[C]]
; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fmaxnum_with_constant_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -1052,7 +1020,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; VI-LABEL: name: test_fmaxnum_with_constant_vector_argument_v2s16_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -1075,7 +1042,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_fmaxnum_with_constant_vector_argument_v2s16_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
index a20c2fa21eb1e25..d32be74e2c99635 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
@@ -23,7 +23,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fminnum_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -33,7 +32,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fminnum_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -65,7 +63,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
; SI-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)
- ;
; VI-LABEL: name: test_fminnum_s32_ieee_mode_off
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -73,7 +70,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
; VI-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)
- ;
; GFX9-LABEL: name: test_fminnum_s32_ieee_mode_off
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -100,7 +96,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fminnum_s32_nnan
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -108,7 +103,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fminnum_s32_nnan
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -137,7 +131,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fminnum_s32_nnan_lhs
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -146,7 +139,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fminnum_s32_nnan_lhs
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -176,7 +168,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fminnum_s32_nnan_rhs
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -185,7 +176,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fminnum_s32_nnan_rhs
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -213,7 +203,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fminnum_s32_nnan_lhs_rhs
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -221,7 +210,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fminnum_s32_nnan_lhs_rhs
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -250,7 +238,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY1]]
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[FMINNUM_IEEE]](s64)
- ;
; VI-LABEL: name: test_fminnum_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -260,7 +247,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s64) = G_FCANONICALIZE [[COPY1]]
; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[FMINNUM_IEEE]](s64)
- ;
; GFX9-LABEL: name: test_fminnum_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -295,7 +281,6 @@ body: |
; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMINNUM_IEEE]](s32)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; VI-LABEL: name: test_fminnum_s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -308,7 +293,6 @@ body: |
; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s16) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMINNUM_IEEE]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_fminnum_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -351,7 +335,6 @@ body: |
; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMINNUM_IEEE]](s32), [[FMINNUM_IEEE1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_fminnum_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -367,7 +350,6 @@ body: |
; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMINNUM_IEEE]](s32), [[FMINNUM_IEEE1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_fminnum_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -423,7 +405,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; VI-LABEL: name: test_fminnum_v2s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -450,7 +431,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_fminnum_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -519,13 +499,13 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_fminnum_v3s16
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -571,13 +551,13 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_fminnum_v3s16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -687,7 +667,6 @@ body: |
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_fminnum_v4s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -736,7 +715,6 @@ body: |
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_fminnum_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -780,7 +758,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](s32)
- ;
; VI-LABEL: name: test_fminnum_with_fminnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -794,7 +771,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](s32)
- ;
; GFX9-LABEL: name: test_fminnum_with_fminnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -836,7 +812,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](s32)
- ;
; VI-LABEL: name: test_fminnum_with_nonNaN_fminnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -848,7 +823,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; VI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMINNUM_IEEE]], [[FCANONICALIZE1]]
; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE1]](s32)
- ;
; GFX9-LABEL: name: test_fminnum_with_nonNaN_fminnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -890,7 +864,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fminnum_with_fmaxnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -904,7 +877,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE3:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY2]]
; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE2]], [[FCANONICALIZE3]]
; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fminnum_with_fmaxnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -946,7 +918,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fminnum_with_nonNaN_fmaxnum_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -958,7 +929,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE1:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[FCANONICALIZE1]]
; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fminnum_with_nonNaN_fmaxnum_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -995,7 +965,6 @@ body: |
; SI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
; SI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; VI-LABEL: name: test_fminnum_with_constant_argument_s32_ieee_mode_on
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -1004,7 +973,6 @@ body: |
; VI-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[C]]
; VI-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
- ;
; GFX9-LABEL: name: test_fminnum_with_constant_argument_s32_ieee_mode_on
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -1052,7 +1020,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; VI-LABEL: name: test_fminnum_with_constant_vector_argument_v2s16_ieee_mode_on
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -1075,7 +1042,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_fminnum_with_constant_vector_argument_v2s16_ieee_mode_on
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
index acfc6f69d8f796d..74c8ff83f318e1f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
@@ -18,7 +18,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
; SI-NEXT: $vgpr0 = COPY [[FMUL]](s32)
- ;
; VI-LABEL: name: test_fmul_s32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -26,7 +25,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
; VI-NEXT: $vgpr0 = COPY [[FMUL]](s32)
- ;
; GFX9PLUS-LABEL: name: test_fmul_s32
; GFX9PLUS: liveins: $vgpr0, $vgpr1
; GFX9PLUS-NEXT: {{ $}}
@@ -52,7 +50,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[FMUL]](s64)
- ;
; VI-LABEL: name: test_fmul_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -60,7 +57,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[FMUL]](s64)
- ;
; GFX9PLUS-LABEL: name: test_fmul_s64
; GFX9PLUS: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9PLUS-NEXT: {{ $}}
@@ -93,7 +89,6 @@ body: |
; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; VI-LABEL: name: test_fmul_s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -104,7 +99,6 @@ body: |
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[TRUNC1]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMUL]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9PLUS-LABEL: name: test_fmul_s16
; GFX9PLUS: liveins: $vgpr0, $vgpr1
; GFX9PLUS-NEXT: {{ $}}
@@ -142,7 +136,6 @@ body: |
; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_fmul_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -154,7 +147,6 @@ body: |
; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[UV3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9PLUS-LABEL: name: test_fmul_v2s32
; GFX9PLUS: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9PLUS-NEXT: {{ $}}
@@ -189,7 +181,6 @@ body: |
; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[UV1]], [[UV3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_fmul_v2s32_flags
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -201,7 +192,6 @@ body: |
; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[UV1]], [[UV3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9PLUS-LABEL: name: test_fmul_v2s32_flags
; GFX9PLUS: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9PLUS-NEXT: {{ $}}
@@ -237,7 +227,6 @@ body: |
; SI-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[UV5]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32), [[FMUL2]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_fmul_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -250,7 +239,6 @@ body: |
; VI-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[UV2]], [[UV5]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32), [[FMUL2]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9PLUS-LABEL: name: test_fmul_v3s32
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9PLUS-NEXT: {{ $}}
@@ -286,7 +274,6 @@ body: |
; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[UV1]], [[UV3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FMUL]](s64), [[FMUL1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_fmul_v2s64
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: {{ $}}
@@ -298,7 +285,6 @@ body: |
; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[UV1]], [[UV3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FMUL]](s64), [[FMUL1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9PLUS-LABEL: name: test_fmul_v2s64
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9PLUS-NEXT: {{ $}}
@@ -350,7 +336,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; VI-LABEL: name: test_fmul_v2s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -373,7 +358,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9PLUS-LABEL: name: test_fmul_v2s16
; GFX9PLUS: liveins: $vgpr0, $vgpr1
; GFX9PLUS-NEXT: {{ $}}
@@ -441,13 +425,13 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_fmul_v3s16
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -487,13 +471,13 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9PLUS-LABEL: name: test_fmul_v3s16
; GFX9PLUS: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9PLUS-NEXT: {{ $}}
@@ -599,7 +583,6 @@ body: |
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_fmul_v4s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -640,7 +623,6 @@ body: |
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9PLUS-LABEL: name: test_fmul_v4s16
; GFX9PLUS: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9PLUS-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
index 49cd1f798612900..eddc0cdbc61224d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
@@ -17,14 +17,12 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
; SI-NEXT: $vgpr0 = COPY [[FNEG]](s32)
- ;
; VI-LABEL: name: test_fneg_s32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
; VI-NEXT: $vgpr0 = COPY [[FNEG]](s32)
- ;
; GFX9-LABEL: name: test_fneg_s32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -47,14 +45,12 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[FNEG]](s64)
- ;
; VI-LABEL: name: test_fneg_s64
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[FNEG]](s64)
- ;
; GFX9-LABEL: name: test_fneg_s64
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -79,7 +75,6 @@ body: |
; SI-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[TRUNC]]
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FNEG]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; VI-LABEL: name: test_fneg_s16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -88,7 +83,6 @@ body: |
; VI-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[TRUNC]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FNEG]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_fneg_s16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -119,7 +113,6 @@ body: |
; SI-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[UV1]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FNEG]](s32), [[FNEG1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_fneg_v2s32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -129,7 +122,6 @@ body: |
; VI-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[UV1]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FNEG]](s32), [[FNEG1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_fneg_v2s32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -160,7 +152,6 @@ body: |
; SI-NEXT: [[FNEG2:%[0-9]+]]:_(s32) = G_FNEG [[UV2]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FNEG]](s32), [[FNEG1]](s32), [[FNEG2]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_fneg_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2
; VI-NEXT: {{ $}}
@@ -171,7 +162,6 @@ body: |
; VI-NEXT: [[FNEG2:%[0-9]+]]:_(s32) = G_FNEG [[UV2]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FNEG]](s32), [[FNEG1]](s32), [[FNEG2]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_fneg_v3s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
@@ -202,7 +192,6 @@ body: |
; SI-NEXT: [[FNEG1:%[0-9]+]]:_(s64) = G_FNEG [[UV1]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FNEG]](s64), [[FNEG1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_fneg_v2s64
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -212,7 +201,6 @@ body: |
; VI-NEXT: [[FNEG1:%[0-9]+]]:_(s64) = G_FNEG [[UV1]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FNEG]](s64), [[FNEG1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_fneg_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -239,14 +227,12 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; SI-NEXT: [[FNEG:%[0-9]+]]:_(<2 x s16>) = G_FNEG [[COPY]]
; SI-NEXT: $vgpr0 = COPY [[FNEG]](<2 x s16>)
- ;
; VI-LABEL: name: test_fneg_v2s16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; VI-NEXT: [[FNEG:%[0-9]+]]:_(<2 x s16>) = G_FNEG [[COPY]]
; VI-NEXT: $vgpr0 = COPY [[FNEG]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_fneg_v2s16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -280,10 +266,10 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[FNEG1]](<2 x s16>)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND1]](s32), [[LSHR]](s32), [[AND2]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; SI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_fneg_v3s16
; VI: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
@@ -301,10 +287,10 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[FNEG1]](<2 x s16>)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND1]](s32), [[LSHR]](s32), [[AND2]](s32)
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; VI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_fneg_v3s16
; GFX9: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
@@ -320,8 +306,9 @@ body: |
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[FNEG1]](<2 x s16>)
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[LSHR]](s32), [[AND1]](s32)
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; GFX9-NEXT: S_NOP 0, implicit [[BUILD_VECTOR1]](<3 x s32>)
%0:_(<3 x s16>) = G_IMPLICIT_DEF
%1:_(<3 x s16>) = G_FNEG %0
@@ -344,7 +331,6 @@ body: |
; SI-NEXT: [[FNEG1:%[0-9]+]]:_(<2 x s16>) = G_FNEG [[UV1]]
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[FNEG]](<2 x s16>), [[FNEG1]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_fneg_v4s16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -354,7 +340,6 @@ body: |
; VI-NEXT: [[FNEG1:%[0-9]+]]:_(<2 x s16>) = G_FNEG [[UV1]]
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[FNEG]](<2 x s16>), [[FNEG1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_fneg_v4s16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
index 70ed6ffcd2aa911..a6ebd27c6b03b1d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
@@ -256,19 +256,22 @@ body: |
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C4]]
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[ZEXT1]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC2]], [[TRUNC3]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
; SI-NEXT: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C2]]
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND3]](s16)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[COPY3]](s32)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LSHR5]], [[ZEXT3]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY3]](s32)
+ ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C4]]
+ ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT3]](s32)
; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR6]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC4]], [[TRUNC5]]
; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -438,12 +441,15 @@ body: |
; SI-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32)
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
- ; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND1]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C3]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND2]](s32)
+ ; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C3]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[AND4]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
@@ -458,19 +464,20 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; VI-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
; VI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND2]](s16)
; VI-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[C3]], [[C2]]
; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND3]], [[C3]](s16)
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
+ ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND4]], [[AND3]](s16)
; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C2]]
- ; VI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C2]]
- ; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND5]], [[AND4]](s16)
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C2]]
+ ; VI-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C2]]
+ ; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND6]], [[AND5]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
@@ -487,19 +494,20 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND2]](s16)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[C3]], [[C2]]
; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND3]], [[C3]](s16)
+ ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
+ ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND4]], [[AND3]](s16)
; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
- ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C2]]
- ; GFX9-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C2]]
- ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND5]], [[AND4]](s16)
+ ; GFX9-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C2]]
+ ; GFX9-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C2]]
+ ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND6]], [[AND5]](s16)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
@@ -531,31 +539,33 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; SI-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
+ ; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY3]](s32)
; SI-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; SI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[C1]]
+ ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY3]]
; SI-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; SI-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; SI-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; SI-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
- ; SI-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[C1]]
+ ; SI-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY3]]
; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; SI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[C1]]
- ; SI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C1]]
+ ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY3]]
+ ; SI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY3]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
- ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[C1]]
- ; SI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[C1]]
+ ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY3]]
+ ; SI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY3]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; SI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
+ ; SI-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C5]](s32)
+ ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
@@ -572,31 +582,33 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; VI-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
+ ; VI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; VI-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY3]](s32)
; VI-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; VI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[C1]]
+ ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY3]]
; VI-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; VI-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; VI-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; VI-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
- ; VI-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[C1]]
+ ; VI-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY3]]
; VI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; VI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[C1]]
- ; VI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C1]]
+ ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY3]]
+ ; VI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY3]]
; VI-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
- ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[C1]]
- ; VI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[C1]]
+ ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY3]]
+ ; VI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY3]]
; VI-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; VI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
+ ; VI-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C5]](s32)
+ ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
; VI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
@@ -613,31 +625,33 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
+ ; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY3]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[C1]]
+ ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY3]]
; GFX9-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; GFX9-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; GFX9-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; GFX9-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
- ; GFX9-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[C1]]
+ ; GFX9-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY3]]
; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[C1]]
- ; GFX9-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C1]]
+ ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY3]]
+ ; GFX9-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY3]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
- ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[C1]]
- ; GFX9-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[C1]]
+ ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY3]]
+ ; GFX9-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY3]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX9-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
+ ; GFX9-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C5]](s32)
+ ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
; GFX9-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
@@ -695,32 +709,36 @@ body: |
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C4]]
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[ZEXT1]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC3]], [[TRUNC4]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
; SI-NEXT: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C2]]
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND3]](s16)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[COPY6]](s32)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LSHR5]], [[ZEXT3]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY6]](s32)
+ ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C4]]
+ ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT3]](s32)
; SI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR6]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC5]], [[TRUNC6]]
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
; SI-NEXT: [[XOR2:%[0-9]+]]:_(s16) = G_XOR [[TRUNC2]], [[C2]]
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[XOR2]], [[C1]]
- ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s16) = G_AND [[XOR2]], [[C1]]
+ ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[ZEXT4]](s32)
; SI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]]
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY7]](s32)
- ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND6]](s16)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR7]], [[ZEXT5]](s32)
+ ; SI-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY7]](s32)
+ ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
+ ; SI-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C4]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[ZEXT5]](s32)
; SI-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR8]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[TRUNC7]], [[TRUNC8]]
; SI-NEXT: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -734,13 +752,14 @@ body: |
; SI-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT6]], [[SHL3]]
; SI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; SI-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
- ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C4]]
- ; SI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
+ ; SI-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C4]]
+ ; SI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C]](s32)
; SI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT8]], [[SHL4]]
; SI-NEXT: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; SI-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C4]]
- ; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
- ; SI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR9]], [[SHL5]]
+ ; SI-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C4]]
+ ; SI-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C4]]
+ ; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C]](s32)
+ ; SI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND13]], [[SHL5]]
; SI-NEXT: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST8]](<2 x s16>)
; SI-NEXT: $vgpr1 = COPY [[BITCAST9]](<2 x s16>)
@@ -814,9 +833,10 @@ body: |
; VI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; VI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; VI-NEXT: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; VI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C4]]
- ; VI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
- ; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR9]], [[SHL5]]
+ ; VI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C4]]
+ ; VI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C4]]
+ ; VI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
+ ; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; VI-NEXT: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST8]](<2 x s16>)
; VI-NEXT: $vgpr1 = COPY [[BITCAST9]](<2 x s16>)
@@ -937,44 +957,50 @@ body: |
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C4]]
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[ZEXT1]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C4]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR7]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC4]], [[TRUNC5]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
; SI-NEXT: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C2]]
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND3]](s16)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
; SI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR2]], [[COPY3]](s32)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[LSHR8]], [[ZEXT3]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY3]](s32)
+ ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C4]]
+ ; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT3]](s32)
; SI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR9]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC6]], [[TRUNC7]]
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
; SI-NEXT: [[XOR2:%[0-9]+]]:_(s16) = G_XOR [[TRUNC2]], [[C2]]
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[XOR2]], [[C1]]
- ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s16) = G_AND [[XOR2]], [[C1]]
+ ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[ZEXT4]](s32)
; SI-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]]
- ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY4]](s32)
- ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND6]](s16)
- ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR10]], [[ZEXT5]](s32)
+ ; SI-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]]
+ ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY4]](s32)
+ ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
+ ; SI-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C4]]
+ ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[ZEXT5]](s32)
; SI-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR11]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[TRUNC8]], [[TRUNC9]]
- ; SI-NEXT: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C1]]
+ ; SI-NEXT: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C1]]
; SI-NEXT: [[XOR3:%[0-9]+]]:_(s16) = G_XOR [[TRUNC3]], [[C2]]
- ; SI-NEXT: [[AND9:%[0-9]+]]:_(s16) = G_AND [[XOR3]], [[C1]]
- ; SI-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
+ ; SI-NEXT: [[AND13:%[0-9]+]]:_(s16) = G_AND [[XOR3]], [[C1]]
+ ; SI-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[AND12]](s16)
; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[ZEXT6]](s32)
; SI-NEXT: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; SI-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY5]](s32)
- ; SI-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
- ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[LSHR12]], [[ZEXT7]](s32)
+ ; SI-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
+ ; SI-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY5]](s32)
+ ; SI-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[AND13]](s16)
+ ; SI-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C4]]
+ ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[ZEXT7]](s32)
; SI-NEXT: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR13]](s32)
; SI-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[TRUNC10]], [[TRUNC11]]
; SI-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
index 4502629afd421fd..f3d284c7e00f500 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
@@ -215,19 +215,22 @@ body: |
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C4]](s32)
; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR2]], [[ZEXT1]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C5]]
+ ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC]], [[TRUNC1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[C]], [[C2]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[C]], [[C2]]
; SI-NEXT: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[C]], [[C3]]
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C2]]
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND3]](s16)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C2]]
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[COPY3]](s32)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR4]], [[ZEXT3]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY3]](s32)
+ ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT3]](s32)
; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC2]], [[TRUNC3]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
@@ -246,32 +249,34 @@ body: |
; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST4]](s32)
; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C1]](s32)
; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR7]](s32)
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C2]]
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C2]]
; SI-NEXT: [[XOR3:%[0-9]+]]:_(s16) = G_XOR [[TRUNC4]], [[C3]]
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[XOR3]], [[C2]]
- ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s16) = G_AND [[XOR3]], [[C2]]
+ ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT]], [[ZEXT4]](s32)
; SI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
; SI-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY8]](s32)
- ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND6]](s16)
- ; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[LSHR8]], [[ZEXT5]](s32)
+ ; SI-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY8]](s32)
+ ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
+ ; SI-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C5]]
+ ; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[ZEXT5]](s32)
; SI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR9]](s32)
; SI-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[TRUNC6]], [[TRUNC7]]
- ; SI-NEXT: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[C2]]
+ ; SI-NEXT: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[C2]]
; SI-NEXT: [[XOR4:%[0-9]+]]:_(s16) = G_XOR [[TRUNC5]], [[C3]]
- ; SI-NEXT: [[AND9:%[0-9]+]]:_(s16) = G_AND [[XOR4]], [[C2]]
- ; SI-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
+ ; SI-NEXT: [[AND13:%[0-9]+]]:_(s16) = G_AND [[XOR4]], [[C2]]
+ ; SI-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[AND12]](s16)
; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s16)
; SI-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT1]], [[ZEXT6]](s32)
; SI-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; SI-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C5]]
- ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY9]](s32)
- ; SI-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
- ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR10]], [[ZEXT7]](s32)
+ ; SI-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C5]]
+ ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY9]](s32)
+ ; SI-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[AND13]](s16)
+ ; SI-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C5]]
+ ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[ZEXT7]](s32)
; SI-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR11]](s32)
; SI-NEXT: [[OR4:%[0-9]+]]:_(s16) = G_OR [[TRUNC8]], [[TRUNC9]]
; SI-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
@@ -467,11 +472,14 @@ body: |
; SI-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32)
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND]](s32)
+ ; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C3]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND2]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C3]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
;
@@ -486,18 +494,19 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; VI-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
- ; VI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; VI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C3]], [[C2]]
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C2]](s16)
+ ; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND2]](s16)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
- ; VI-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
- ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[SHL]], [[AND2]](s16)
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
+ ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[SHL]], [[AND3]](s16)
; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; VI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C3]]
- ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND4]], [[AND3]](s16)
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C2]]
+ ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND5]], [[AND4]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL1]](s16)
; VI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
@@ -514,18 +523,19 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C3]], [[C2]]
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C2]](s16)
+ ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND2]](s16)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
- ; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[SHL]], [[AND2]](s16)
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
+ ; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[SHL]], [[AND3]](s16)
; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
+ ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C3]]
- ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND4]], [[AND3]](s16)
+ ; GFX9-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C2]]
+ ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND5]], [[AND4]](s16)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL1]](s16)
; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
@@ -557,28 +567,30 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; SI-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
+ ; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY3]](s32)
; SI-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; SI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; SI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[C1]]
+ ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY3]]
; SI-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; SI-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; SI-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; SI-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
- ; SI-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[C1]]
+ ; SI-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY3]]
; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; SI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[C1]]
- ; SI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C1]]
+ ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY3]]
+ ; SI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY3]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
- ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[C1]]
- ; SI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[C1]]
+ ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY3]]
+ ; SI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY3]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; SI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C5]](s32)
+ ; SI-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY4]](s32)
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
@@ -597,28 +609,30 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; VI-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
+ ; VI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; VI-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY3]](s32)
; VI-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; VI-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[C1]]
+ ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY3]]
; VI-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; VI-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; VI-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; VI-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
- ; VI-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[C1]]
+ ; VI-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY3]]
; VI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; VI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[C1]]
- ; VI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C1]]
+ ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY3]]
+ ; VI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY3]]
; VI-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
- ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[C1]]
- ; VI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[C1]]
+ ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY3]]
+ ; VI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY3]]
; VI-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; VI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
- ; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C5]](s32)
+ ; VI-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY4]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
@@ -637,28 +651,30 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
+ ; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY3]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; GFX9-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[C1]]
+ ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY3]]
; GFX9-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; GFX9-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; GFX9-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; GFX9-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
- ; GFX9-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[C1]]
+ ; GFX9-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY3]]
; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[C1]]
- ; GFX9-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C1]]
+ ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY3]]
+ ; GFX9-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY3]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
- ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[C1]]
- ; GFX9-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[C1]]
+ ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY3]]
+ ; GFX9-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY3]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX9-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C5]](s32)
+ ; GFX9-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY4]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
@@ -713,19 +729,22 @@ body: |
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C5]]
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C4]](s32)
; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR2]], [[ZEXT1]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C5]]
+ ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC]], [[TRUNC1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[C1]], [[C2]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[C1]], [[C2]]
; SI-NEXT: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[C1]], [[C3]]
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C2]]
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND3]](s16)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C2]]
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[COPY6]](s32)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR4]], [[ZEXT3]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY6]](s32)
+ ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT3]](s32)
; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC2]], [[TRUNC3]]
; SI-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
@@ -742,45 +761,48 @@ body: |
; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST5]](s32)
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR6]](s32)
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C2]]
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C2]]
; SI-NEXT: [[XOR3:%[0-9]+]]:_(s16) = G_XOR [[TRUNC4]], [[C3]]
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[XOR3]], [[C2]]
- ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s16) = G_AND [[XOR3]], [[C2]]
+ ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT]], [[ZEXT4]](s32)
; SI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
; SI-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY11]](s32)
- ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND6]](s16)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR7]], [[ZEXT5]](s32)
+ ; SI-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY11]](s32)
+ ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
+ ; SI-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C5]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[ZEXT5]](s32)
; SI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR8]](s32)
; SI-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[TRUNC6]], [[TRUNC7]]
- ; SI-NEXT: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[C2]]
+ ; SI-NEXT: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[C2]]
; SI-NEXT: [[XOR4:%[0-9]+]]:_(s16) = G_XOR [[TRUNC5]], [[C3]]
- ; SI-NEXT: [[AND9:%[0-9]+]]:_(s16) = G_AND [[XOR4]], [[C2]]
- ; SI-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
+ ; SI-NEXT: [[AND13:%[0-9]+]]:_(s16) = G_AND [[XOR4]], [[C2]]
+ ; SI-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[AND12]](s16)
; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s16)
; SI-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT1]], [[ZEXT6]](s32)
; SI-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; SI-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C5]]
- ; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY12]](s32)
- ; SI-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
- ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[LSHR9]], [[ZEXT7]](s32)
+ ; SI-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C5]]
+ ; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY12]](s32)
+ ; SI-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[AND13]](s16)
+ ; SI-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C5]]
+ ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[ZEXT7]](s32)
; SI-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR10]](s32)
; SI-NEXT: [[OR4:%[0-9]+]]:_(s16) = G_OR [[TRUNC8]], [[TRUNC9]]
- ; SI-NEXT: [[AND11:%[0-9]+]]:_(s16) = G_AND [[C1]], [[C2]]
+ ; SI-NEXT: [[AND16:%[0-9]+]]:_(s16) = G_AND [[C1]], [[C2]]
; SI-NEXT: [[XOR5:%[0-9]+]]:_(s16) = G_XOR [[C1]], [[C3]]
- ; SI-NEXT: [[AND12:%[0-9]+]]:_(s16) = G_AND [[XOR5]], [[C2]]
- ; SI-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[AND11]](s16)
+ ; SI-NEXT: [[AND17:%[0-9]+]]:_(s16) = G_AND [[XOR5]], [[C2]]
+ ; SI-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[AND16]](s16)
; SI-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[ZEXT8]](s32)
; SI-NEXT: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; SI-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C5]]
- ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[COPY13]](s32)
- ; SI-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[AND12]](s16)
- ; SI-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[LSHR11]], [[ZEXT9]](s32)
+ ; SI-NEXT: [[AND18:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C5]]
+ ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND18]], [[COPY13]](s32)
+ ; SI-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[AND17]](s16)
+ ; SI-NEXT: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C5]]
+ ; SI-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND19]], [[ZEXT9]](s32)
; SI-NEXT: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR12]](s32)
; SI-NEXT: [[OR5:%[0-9]+]]:_(s16) = G_OR [[TRUNC10]], [[TRUNC11]]
; SI-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
@@ -793,18 +815,19 @@ body: |
; SI-NEXT: [[XOR6:%[0-9]+]]:_(<2 x s16>) = G_XOR [[COPY5]], [[BITCAST6]]
; SI-NEXT: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[XOR6]](<2 x s16>)
; SI-NEXT: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST7]](s32)
- ; SI-NEXT: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C2]]
+ ; SI-NEXT: [[AND20:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C2]]
; SI-NEXT: [[XOR7:%[0-9]+]]:_(s16) = G_XOR [[TRUNC12]], [[C3]]
- ; SI-NEXT: [[AND15:%[0-9]+]]:_(s16) = G_AND [[XOR7]], [[C2]]
- ; SI-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[AND14]](s16)
+ ; SI-NEXT: [[AND21:%[0-9]+]]:_(s16) = G_AND [[XOR7]], [[C2]]
+ ; SI-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[AND20]](s16)
; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR5]](s16)
; SI-NEXT: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT2]], [[ZEXT10]](s32)
; SI-NEXT: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL10]](s32)
; SI-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND16:%[0-9]+]]:_(s32) = G_AND [[SHL8]], [[C5]]
- ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND16]], [[COPY17]](s32)
- ; SI-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[AND15]](s16)
- ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[LSHR13]], [[ZEXT11]](s32)
+ ; SI-NEXT: [[AND22:%[0-9]+]]:_(s32) = G_AND [[SHL8]], [[C5]]
+ ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND22]], [[COPY17]](s32)
+ ; SI-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[AND21]](s16)
+ ; SI-NEXT: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C5]]
+ ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND23]], [[ZEXT11]](s32)
; SI-NEXT: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR14]](s32)
; SI-NEXT: [[OR7:%[0-9]+]]:_(s16) = G_OR [[TRUNC13]], [[TRUNC14]]
; SI-NEXT: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -818,13 +841,14 @@ body: |
; SI-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[ZEXT12]], [[SHL11]]
; SI-NEXT: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR8]](s32)
; SI-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[OR7]](s16)
- ; SI-NEXT: [[AND17:%[0-9]+]]:_(s32) = G_AND [[BITCAST8]], [[C5]]
- ; SI-NEXT: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C]](s32)
+ ; SI-NEXT: [[AND24:%[0-9]+]]:_(s32) = G_AND [[BITCAST8]], [[C5]]
+ ; SI-NEXT: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C]](s32)
; SI-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[ZEXT14]], [[SHL12]]
; SI-NEXT: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR9]](s32)
- ; SI-NEXT: [[AND18:%[0-9]+]]:_(s32) = G_AND [[BITCAST9]], [[C5]]
- ; SI-NEXT: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C]](s32)
- ; SI-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[LSHR15]], [[SHL13]]
+ ; SI-NEXT: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C5]]
+ ; SI-NEXT: [[AND26:%[0-9]+]]:_(s32) = G_AND [[BITCAST9]], [[C5]]
+ ; SI-NEXT: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C]](s32)
+ ; SI-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[SHL13]]
; SI-NEXT: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR10]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST10]](<2 x s16>)
; SI-NEXT: $vgpr1 = COPY [[BITCAST11]](<2 x s16>)
@@ -933,9 +957,10 @@ body: |
; VI-NEXT: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C]](s32)
; VI-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL12]]
; VI-NEXT: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR9]](s32)
- ; VI-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[BITCAST9]], [[C4]]
- ; VI-NEXT: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
- ; VI-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[LSHR15]], [[SHL13]]
+ ; VI-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C4]]
+ ; VI-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[BITCAST9]], [[C4]]
+ ; VI-NEXT: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C]](s32)
+ ; VI-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[AND13]], [[SHL13]]
; VI-NEXT: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR10]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST10]](<2 x s16>)
; VI-NEXT: $vgpr1 = COPY [[BITCAST11]](<2 x s16>)
@@ -1045,19 +1070,22 @@ body: |
; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C4]](s32)
; SI-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR2]], [[ZEXT1]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C5]]
+ ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC]], [[TRUNC1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[C]], [[C2]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[C]], [[C2]]
; SI-NEXT: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[C]], [[C3]]
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C2]]
- ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND3]](s16)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C2]]
+ ; SI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
; SI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[COPY3]](s32)
- ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR4]], [[ZEXT3]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY3]](s32)
+ ; SI-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT3]](s32)
; SI-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC2]], [[TRUNC3]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
@@ -1076,32 +1104,34 @@ body: |
; SI-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST4]](s32)
; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C1]](s32)
; SI-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR7]](s32)
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C2]]
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C2]]
; SI-NEXT: [[XOR3:%[0-9]+]]:_(s16) = G_XOR [[TRUNC4]], [[C3]]
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[XOR3]], [[C2]]
- ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s16) = G_AND [[XOR3]], [[C2]]
+ ; SI-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT]], [[ZEXT4]](s32)
; SI-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
; SI-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY8]](s32)
- ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND6]](s16)
- ; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[LSHR8]], [[ZEXT5]](s32)
+ ; SI-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY8]](s32)
+ ; SI-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
+ ; SI-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C5]]
+ ; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[ZEXT5]](s32)
; SI-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR9]](s32)
; SI-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[TRUNC6]], [[TRUNC7]]
- ; SI-NEXT: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[C2]]
+ ; SI-NEXT: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[C2]]
; SI-NEXT: [[XOR4:%[0-9]+]]:_(s16) = G_XOR [[TRUNC5]], [[C3]]
- ; SI-NEXT: [[AND9:%[0-9]+]]:_(s16) = G_AND [[XOR4]], [[C2]]
- ; SI-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
+ ; SI-NEXT: [[AND13:%[0-9]+]]:_(s16) = G_AND [[XOR4]], [[C2]]
+ ; SI-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[AND12]](s16)
; SI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s16)
; SI-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT1]], [[ZEXT6]](s32)
; SI-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; SI-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C5]]
- ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY9]](s32)
- ; SI-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
- ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR10]], [[ZEXT7]](s32)
+ ; SI-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C5]]
+ ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY9]](s32)
+ ; SI-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[AND13]](s16)
+ ; SI-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C5]]
+ ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[ZEXT7]](s32)
; SI-NEXT: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR11]](s32)
; SI-NEXT: [[OR4:%[0-9]+]]:_(s16) = G_OR [[TRUNC8]], [[TRUNC9]]
; SI-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
@@ -1113,29 +1143,32 @@ body: |
; SI-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C1]](s32)
; SI-NEXT: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C1]](s32)
- ; SI-NEXT: [[AND11:%[0-9]+]]:_(s16) = G_AND [[C]], [[C2]]
+ ; SI-NEXT: [[AND16:%[0-9]+]]:_(s16) = G_AND [[C]], [[C2]]
; SI-NEXT: [[XOR5:%[0-9]+]]:_(s16) = G_XOR [[C]], [[C3]]
- ; SI-NEXT: [[AND12:%[0-9]+]]:_(s16) = G_AND [[XOR5]], [[C2]]
- ; SI-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[AND11]](s16)
+ ; SI-NEXT: [[AND17:%[0-9]+]]:_(s16) = G_AND [[XOR5]], [[C2]]
+ ; SI-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[AND16]](s16)
; SI-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[BITCAST6]], [[ZEXT10]](s32)
; SI-NEXT: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; SI-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C5]]
- ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[COPY10]](s32)
- ; SI-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[AND12]](s16)
- ; SI-NEXT: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[LSHR14]], [[ZEXT11]](s32)
+ ; SI-NEXT: [[AND18:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C5]]
+ ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND18]], [[COPY10]](s32)
+ ; SI-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[AND17]](s16)
+ ; SI-NEXT: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C5]]
+ ; SI-NEXT: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[AND19]], [[ZEXT11]](s32)
; SI-NEXT: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR15]](s32)
; SI-NEXT: [[OR6:%[0-9]+]]:_(s16) = G_OR [[TRUNC10]], [[TRUNC11]]
- ; SI-NEXT: [[AND14:%[0-9]+]]:_(s16) = G_AND [[C]], [[C2]]
+ ; SI-NEXT: [[AND20:%[0-9]+]]:_(s16) = G_AND [[C]], [[C2]]
; SI-NEXT: [[XOR6:%[0-9]+]]:_(s16) = G_XOR [[C]], [[C3]]
- ; SI-NEXT: [[AND15:%[0-9]+]]:_(s16) = G_AND [[XOR6]], [[C2]]
- ; SI-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[AND14]](s16)
+ ; SI-NEXT: [[AND21:%[0-9]+]]:_(s16) = G_AND [[XOR6]], [[C2]]
+ ; SI-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[AND20]](s16)
; SI-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[LSHR12]], [[ZEXT12]](s32)
; SI-NEXT: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; SI-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[LSHR13]], [[COPY11]](s32)
- ; SI-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[AND15]](s16)
- ; SI-NEXT: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[LSHR16]], [[ZEXT13]](s32)
+ ; SI-NEXT: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C5]]
+ ; SI-NEXT: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND22]], [[COPY11]](s32)
+ ; SI-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[AND21]](s16)
+ ; SI-NEXT: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C5]]
+ ; SI-NEXT: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[AND23]], [[ZEXT13]](s32)
; SI-NEXT: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR17]](s32)
; SI-NEXT: [[OR7:%[0-9]+]]:_(s16) = G_OR [[TRUNC12]], [[TRUNC13]]
; SI-NEXT: [[BITCAST8:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
@@ -1154,32 +1187,34 @@ body: |
; SI-NEXT: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST10]](s32)
; SI-NEXT: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST10]], [[C1]](s32)
; SI-NEXT: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR19]](s32)
- ; SI-NEXT: [[AND16:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C2]]
+ ; SI-NEXT: [[AND24:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C2]]
; SI-NEXT: [[XOR8:%[0-9]+]]:_(s16) = G_XOR [[TRUNC14]], [[C3]]
- ; SI-NEXT: [[AND17:%[0-9]+]]:_(s16) = G_AND [[XOR8]], [[C2]]
- ; SI-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[AND16]](s16)
+ ; SI-NEXT: [[AND25:%[0-9]+]]:_(s16) = G_AND [[XOR8]], [[C2]]
+ ; SI-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[AND24]](s16)
; SI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR6]](s16)
; SI-NEXT: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT2]], [[ZEXT14]](s32)
; SI-NEXT: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[SHL13]](s32)
; SI-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND18:%[0-9]+]]:_(s32) = G_AND [[SHL10]], [[C5]]
- ; SI-NEXT: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND18]], [[COPY16]](s32)
- ; SI-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[AND17]](s16)
- ; SI-NEXT: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[LSHR20]], [[ZEXT15]](s32)
+ ; SI-NEXT: [[AND26:%[0-9]+]]:_(s32) = G_AND [[SHL10]], [[C5]]
+ ; SI-NEXT: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND26]], [[COPY16]](s32)
+ ; SI-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[AND25]](s16)
+ ; SI-NEXT: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C5]]
+ ; SI-NEXT: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[AND27]], [[ZEXT15]](s32)
; SI-NEXT: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR21]](s32)
; SI-NEXT: [[OR9:%[0-9]+]]:_(s16) = G_OR [[TRUNC16]], [[TRUNC17]]
- ; SI-NEXT: [[AND19:%[0-9]+]]:_(s16) = G_AND [[TRUNC15]], [[C2]]
+ ; SI-NEXT: [[AND28:%[0-9]+]]:_(s16) = G_AND [[TRUNC15]], [[C2]]
; SI-NEXT: [[XOR9:%[0-9]+]]:_(s16) = G_XOR [[TRUNC15]], [[C3]]
- ; SI-NEXT: [[AND20:%[0-9]+]]:_(s16) = G_AND [[XOR9]], [[C2]]
- ; SI-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[AND19]](s16)
+ ; SI-NEXT: [[AND29:%[0-9]+]]:_(s16) = G_AND [[XOR9]], [[C2]]
+ ; SI-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[AND28]](s16)
; SI-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[OR7]](s16)
; SI-NEXT: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT3]], [[ZEXT16]](s32)
; SI-NEXT: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[SHL14]](s32)
; SI-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND21:%[0-9]+]]:_(s32) = G_AND [[SHL11]], [[C5]]
- ; SI-NEXT: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND21]], [[COPY17]](s32)
- ; SI-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[AND20]](s16)
- ; SI-NEXT: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[LSHR22]], [[ZEXT17]](s32)
+ ; SI-NEXT: [[AND30:%[0-9]+]]:_(s32) = G_AND [[SHL11]], [[C5]]
+ ; SI-NEXT: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND30]], [[COPY17]](s32)
+ ; SI-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[AND29]](s16)
+ ; SI-NEXT: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C5]]
+ ; SI-NEXT: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[AND31]], [[ZEXT17]](s32)
; SI-NEXT: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR23]](s32)
; SI-NEXT: [[OR10:%[0-9]+]]:_(s16) = G_OR [[TRUNC18]], [[TRUNC19]]
; SI-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[OR9]](s16)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
index 206ad3e24ee023f..8e999e400a6665f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
@@ -18,7 +18,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
; SI-NEXT: $vgpr0 = COPY [[FSUB]](s32)
- ;
; VI-LABEL: name: test_fsub_s32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -26,7 +25,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
; VI-NEXT: $vgpr0 = COPY [[FSUB]](s32)
- ;
; GFX9-LABEL: name: test_fsub_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -53,7 +51,6 @@ body: |
; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
- ;
; VI-LABEL: name: test_fsub_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -62,7 +59,6 @@ body: |
; VI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
; VI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
- ;
; GFX9-LABEL: name: test_fsub_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -91,7 +87,6 @@ body: |
; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = nnan nsz G_FADD [[COPY]], [[FNEG]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
- ;
; VI-LABEL: name: test_fsub_s64_fmf
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -100,7 +95,6 @@ body: |
; VI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
; VI-NEXT: [[FADD:%[0-9]+]]:_(s64) = nnan nsz G_FADD [[COPY]], [[FNEG]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
- ;
; GFX9-LABEL: name: test_fsub_s64_fmf
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -135,7 +129,6 @@ body: |
; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; VI-LABEL: name: test_fsub_s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -146,7 +139,6 @@ body: |
; VI-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[TRUNC]], [[TRUNC1]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSUB]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_fsub_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -184,7 +176,6 @@ body: |
; SI-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[UV1]], [[UV3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_fsub_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -196,7 +187,6 @@ body: |
; VI-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB [[UV1]], [[UV3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_fsub_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -231,7 +221,6 @@ body: |
; SI-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = nnan G_FSUB [[UV1]], [[UV3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_fsub_v2s32_flags
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -243,7 +232,6 @@ body: |
; VI-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = nnan G_FSUB [[UV1]], [[UV3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_fsub_v2s32_flags
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -279,7 +267,6 @@ body: |
; SI-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[UV2]], [[UV5]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32), [[FSUB2]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_fsub_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -292,7 +279,6 @@ body: |
; VI-NEXT: [[FSUB2:%[0-9]+]]:_(s32) = G_FSUB [[UV2]], [[UV5]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32), [[FSUB2]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_fsub_v3s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -330,7 +316,6 @@ body: |
; SI-NEXT: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[UV1]], [[FNEG1]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD]](s64), [[FADD1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_fsub_v2s64
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: {{ $}}
@@ -344,7 +329,6 @@ body: |
; VI-NEXT: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[UV1]], [[FNEG1]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD]](s64), [[FADD1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_fsub_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: {{ $}}
@@ -399,7 +383,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; VI-LABEL: name: test_fsub_v2s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -423,7 +406,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_fsub_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -494,13 +476,13 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_fsub_v3s16
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -540,13 +522,13 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_fsub_v3s16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -656,7 +638,6 @@ body: |
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_fsub_v4s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -697,7 +678,6 @@ body: |
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_fsub_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
index a655f47a8969ea3..a166c2d45abbca9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
@@ -18,7 +18,6 @@ body: |
; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; GFX7-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX7-NEXT: $vgpr0 = COPY [[SELECT]](s32)
- ;
; GFX8-LABEL: name: test_icmp_s32
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
@@ -27,7 +26,6 @@ body: |
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX8-NEXT: $vgpr0 = COPY [[SELECT]](s32)
- ;
; GFX9-LABEL: name: test_icmp_s32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -56,7 +54,6 @@ body: |
; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s64), [[COPY]]
; GFX7-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; GFX8-LABEL: name: test_icmp_s64
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
@@ -65,7 +62,6 @@ body: |
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s64), [[COPY]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; GFX9-LABEL: name: test_icmp_s64
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -99,7 +95,6 @@ body: |
; GFX7-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C]], [[TRUNC]]
; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX7-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX8-LABEL: name: test_icmp_s16
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
@@ -110,7 +105,6 @@ body: |
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C]], [[TRUNC]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_icmp_s16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -141,36 +135,37 @@ body: |
; GFX7-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[AND]]
+ ; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX7-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX7-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX7-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[TRUNC]]
; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX7-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX8-LABEL: name: test_icmp_s8
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[AND]]
+ ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[TRUNC]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_icmp_s8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[AND]]
+ ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[TRUNC]]
@@ -196,30 +191,31 @@ body: |
; GFX7-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[AND]]
+ ; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX7-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX7-NEXT: $vgpr0 = COPY [[SELECT]](s32)
- ;
; GFX8-LABEL: name: test_icmp_s24
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
+ ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[AND]]
+ ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX8-NEXT: $vgpr0 = COPY [[SELECT]](s32)
- ;
; GFX9-LABEL: name: test_icmp_s24
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[AND]]
+ ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
; GFX9-NEXT: $vgpr0 = COPY [[SELECT]](s32)
%0:_(s24) = G_CONSTANT i24 0
@@ -251,7 +247,6 @@ body: |
; GFX7-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; GFX7-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX8-LABEL: name: test_icmp_v2s32
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
@@ -267,7 +262,6 @@ body: |
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; GFX8-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_icmp_v2s32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -276,8 +270,8 @@ body: |
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[UV]]
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[UV1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
@@ -316,7 +310,6 @@ body: |
; GFX7-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; GFX7-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX8-LABEL: name: test_icmp_v3s32
; GFX8: liveins: $vgpr0_vgpr1_vgpr2
; GFX8-NEXT: {{ $}}
@@ -336,7 +329,6 @@ body: |
; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; GFX8-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_icmp_v3s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
@@ -347,8 +339,8 @@ body: |
; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]
; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
@@ -392,7 +384,6 @@ body: |
; GFX7-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C]]
; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; GFX7-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX8-LABEL: name: test_icmp_v4s32
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -416,7 +407,6 @@ body: |
; GFX8-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; GFX8-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_icmp_v4s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -429,8 +419,8 @@ body: |
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV5]]
; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV6]]
; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV3]](s32), [[UV7]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
@@ -462,7 +452,6 @@ body: |
; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p0), [[COPY1]]
; GFX7-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX7-NEXT: $vgpr0 = COPY [[SEXT]](s32)
- ;
; GFX8-LABEL: name: test_icmp_p0
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -471,7 +460,6 @@ body: |
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p0), [[COPY1]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[SEXT]](s32)
- ;
; GFX9-LABEL: name: test_icmp_p0
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -500,7 +488,6 @@ body: |
; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p1), [[COPY1]]
; GFX7-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX7-NEXT: $vgpr0 = COPY [[SEXT]](s32)
- ;
; GFX8-LABEL: name: test_icmp_p1
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -509,7 +496,6 @@ body: |
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p1), [[COPY1]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[SEXT]](s32)
- ;
; GFX9-LABEL: name: test_icmp_p1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -539,7 +525,6 @@ body: |
; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p2), [[COPY1]]
; GFX7-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX7-NEXT: $vgpr0 = COPY [[SEXT]](s32)
- ;
; GFX8-LABEL: name: test_icmp_p2
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -548,7 +533,6 @@ body: |
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p2), [[COPY1]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[SEXT]](s32)
- ;
; GFX9-LABEL: name: test_icmp_p2
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -578,7 +562,6 @@ body: |
; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p3), [[COPY1]]
; GFX7-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX7-NEXT: $vgpr0 = COPY [[SEXT]](s32)
- ;
; GFX8-LABEL: name: test_icmp_p3
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -587,7 +570,6 @@ body: |
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p3), [[COPY1]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[SEXT]](s32)
- ;
; GFX9-LABEL: name: test_icmp_p3
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -616,7 +598,6 @@ body: |
; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p4), [[COPY1]]
; GFX7-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX7-NEXT: $vgpr0 = COPY [[SEXT]](s32)
- ;
; GFX8-LABEL: name: test_icmp_p4
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -625,7 +606,6 @@ body: |
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p4), [[COPY1]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[SEXT]](s32)
- ;
; GFX9-LABEL: name: test_icmp_p4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -655,7 +635,6 @@ body: |
; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p5), [[COPY1]]
; GFX7-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX7-NEXT: $vgpr0 = COPY [[SEXT]](s32)
- ;
; GFX8-LABEL: name: test_icmp_p5
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -664,7 +643,6 @@ body: |
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p5), [[COPY1]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[SEXT]](s32)
- ;
; GFX9-LABEL: name: test_icmp_p5
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -693,7 +671,6 @@ body: |
; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p999), [[COPY1]]
; GFX7-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX7-NEXT: $vgpr0 = COPY [[SEXT]](s32)
- ;
; GFX8-LABEL: name: test_icmp_p999
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -702,7 +679,6 @@ body: |
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p999), [[COPY1]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[SEXT]](s32)
- ;
; GFX9-LABEL: name: test_icmp_p999
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -738,7 +714,6 @@ body: |
; GFX7-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX8-LABEL: name: test_icmp_v2p3
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -754,7 +729,6 @@ body: |
; GFX8-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_icmp_v2p3
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -797,7 +771,6 @@ body: |
; GFX7-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX8-LABEL: name: test_icmp_v2p999
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX8-NEXT: {{ $}}
@@ -813,7 +786,6 @@ body: |
; GFX8-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_icmp_v2p999
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: {{ $}}
@@ -857,14 +829,15 @@ body: |
; GFX7-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; GFX7-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
- ; GFX7-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LSHR]](s32), [[LSHR1]]
+ ; GFX7-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX7-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; GFX7-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND2]](s32), [[AND3]]
; GFX7-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; GFX7-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
; GFX7-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; GFX7-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[UV1]], [[UV3]]
; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX8-LABEL: name: test_icmp_v2s16
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX8-NEXT: {{ $}}
@@ -889,7 +862,6 @@ body: |
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[UV1]], [[UV3]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_icmp_v2s16
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -932,21 +904,25 @@ body: |
; GFX7: liveins: $vgpr0_vgpr1
; GFX7-NEXT: {{ $}}
; GFX7-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s64), [[C]]
+ ; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]
; GFX7-NEXT: S_ENDPGM 0, implicit [[ICMP]](s1)
- ;
; GFX8-LABEL: name: test_icmp_s33
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s64), [[C]]
+ ; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]
; GFX8-NEXT: S_ENDPGM 0, implicit [[ICMP]](s1)
- ;
; GFX9-LABEL: name: test_icmp_s33
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s64), [[C]]
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]
; GFX9-NEXT: S_ENDPGM 0, implicit [[ICMP]](s1)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
index b9edfbfa6d0a953..ff2e6296aa4b2cd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
@@ -441,12 +441,14 @@ body: |
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
@@ -488,16 +490,19 @@ body: |
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C]](s32)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL2]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[UV6]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<8 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
index d8d0f9b9cd898da..90c2b0a69b1f8f9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
@@ -890,7 +890,8 @@ body: |
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
@@ -976,12 +977,14 @@ body: |
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
@@ -1020,7 +1023,8 @@ body: |
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
@@ -1053,7 +1057,8 @@ body: |
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST1]](<2 x s16>)
@@ -1089,12 +1094,14 @@ body: |
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
@@ -1132,8 +1139,10 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
@@ -1166,12 +1175,14 @@ body: |
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
@@ -1208,8 +1219,10 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
@@ -1238,7 +1251,8 @@ body: |
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST1]](<2 x s16>), [[UV1]](<2 x s16>)
@@ -1294,7 +1308,8 @@ body: |
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST1]](<2 x s16>)
@@ -1350,7 +1365,8 @@ body: |
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST1]](<2 x s16>), [[UV1]](<2 x s16>)
@@ -1384,8 +1400,10 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
@@ -1411,7 +1429,8 @@ body: |
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST1]](<2 x s16>)
@@ -1440,7 +1459,8 @@ body: |
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST2]](<2 x s16>)
@@ -1475,9 +1495,10 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
@@ -1503,7 +1524,8 @@ body: |
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[UV1]](<2 x s16>)
@@ -1536,8 +1558,10 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
@@ -1562,7 +1586,8 @@ body: |
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST]](<2 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
index 79c726fc800493c..b97d04e809a6f7d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
@@ -811,9 +811,10 @@ body: |
; GFX6-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; GFX6-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; GFX6-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C6]]
- ; GFX6-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
- ; GFX6-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
+ ; GFX6-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C6]]
+ ; GFX6-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C6]]
+ ; GFX6-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
+ ; GFX6-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL2]]
; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
@@ -878,9 +879,10 @@ body: |
; GFX8-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; GFX8-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; GFX8-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C6]]
- ; GFX8-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
- ; GFX8-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
+ ; GFX8-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C6]]
+ ; GFX8-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C6]]
+ ; GFX8-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
+ ; GFX8-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL2]]
; GFX8-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
index 155cc06a43ea359..29bf366d13587f6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
@@ -235,13 +235,14 @@ define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
; GFX81-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
; GFX81-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX81-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; GFX81-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; GFX81-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX81-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX81-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX81-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX81-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; GFX81-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX81-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX81-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
- ; GFX81-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; GFX81-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX81-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX81-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
; GFX81-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
index 420c55f8f6da21a..a5a58bb01df9581 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
@@ -165,24 +165,30 @@ body: |
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C2]](s32)
- ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL1]]
+ ; GCN-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
+ ; GCN-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
+ ; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
+ ; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GCN-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C4]]
- ; GCN-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
- ; GCN-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
- ; GCN-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL2]]
+ ; GCN-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C4]]
+ ; GCN-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
+ ; GCN-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; GCN-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; GCN-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR5]], [[C2]](s32)
- ; GCN-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[SHL3]]
+ ; GCN-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C4]]
+ ; GCN-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C4]]
+ ; GCN-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
+ ; GCN-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GCN-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; GCN-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C4]]
- ; GCN-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C4]]
- ; GCN-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
- ; GCN-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL4]]
+ ; GCN-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C4]]
+ ; GCN-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C4]]
+ ; GCN-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
+ ; GCN-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; GCN-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; GCN-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[LSHR8]], [[C2]](s32)
- ; GCN-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR7]], [[SHL5]]
+ ; GCN-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C4]]
+ ; GCN-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C4]]
+ ; GCN-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
+ ; GCN-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; GCN-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; GCN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GCN-NEXT: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<12 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
index a63df136e003c38..2ce09043b15b643 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
@@ -19,7 +19,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; VI-LABEL: name: test_load_constant_s1_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -28,7 +27,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_s1_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -57,7 +55,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; VI-LABEL: name: test_load_constant_s2_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -66,7 +63,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_s2_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -93,14 +89,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_constant_s8_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_s8_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -125,14 +119,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_constant_s8_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_s8_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -157,14 +149,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_constant_s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_s16_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -189,14 +179,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_constant_s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_s16_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -227,7 +215,6 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_constant_s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -240,7 +227,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_s16_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -271,14 +257,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), addrspace 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_constant_s32_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), addrspace 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_s32_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -308,7 +292,6 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_constant_s32_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -321,7 +304,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_s32_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -367,7 +349,6 @@ body: |
; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; VI-LABEL: name: test_load_constant_s32_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -390,7 +371,6 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; VI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_s32_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -430,14 +410,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), align 8, addrspace 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_constant_s24_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), align 8, addrspace 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_s24_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -462,14 +440,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), addrspace 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_constant_s24_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), addrspace 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_s24_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -500,7 +476,6 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_constant_s24_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -513,7 +488,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_s24_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -556,7 +530,6 @@ body: |
; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; CI-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; VI-LABEL: name: test_load_constant_s24_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -575,7 +548,6 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; VI-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_s24_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -614,7 +586,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
; CI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; CI-NEXT: $vgpr0_vgpr1 = COPY [[AND]](s64)
- ;
; VI-LABEL: name: test_load_constant_s48_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -623,7 +594,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
; VI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[AND]](s64)
- ;
; GFX9-LABEL: name: test_load_constant_s48_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -650,14 +620,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p4) :: (load (s64), addrspace 4)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; VI-LABEL: name: test_load_constant_s64_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p4) :: (load (s64), addrspace 4)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX9-LABEL: name: test_load_constant_s64_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -681,14 +649,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p4) :: (load (s64), align 4, addrspace 4)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; VI-LABEL: name: test_load_constant_s64_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p4) :: (load (s64), align 4, addrspace 4)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX9-LABEL: name: test_load_constant_s64_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -730,7 +696,6 @@ body: |
; CI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C3]](s32)
; CI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; CI-NEXT: $vgpr0_vgpr1 = COPY [[OR2]](s64)
- ;
; VI-LABEL: name: test_load_constant_s64_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -755,7 +720,6 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C3]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR2]](s64)
- ;
; GFX9-LABEL: name: test_load_constant_s64_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -833,7 +797,6 @@ body: |
; CI-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C5]](s32)
; CI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; CI-NEXT: $vgpr0_vgpr1 = COPY [[OR6]](s64)
- ;
; VI-LABEL: name: test_load_constant_s64_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -876,7 +839,6 @@ body: |
; VI-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C5]](s32)
; VI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR6]](s64)
- ;
; GFX9-LABEL: name: test_load_constant_s64_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -937,7 +899,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>), align 16, addrspace 4)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_constant_s96_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -945,7 +906,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>), align 16, addrspace 4)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_constant_s96_align16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -971,7 +931,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>), align 8, addrspace 4)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_constant_s96_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -979,7 +938,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>), align 8, addrspace 4)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_constant_s96_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1005,7 +963,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>), align 4, addrspace 4)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_constant_s96_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1013,7 +970,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>), align 4, addrspace 4)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_constant_s96_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1060,7 +1016,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_constant_s96_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1089,7 +1044,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_constant_s96_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1183,7 +1137,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_constant_s96_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1238,7 +1191,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_constant_s96_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1316,7 +1268,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[LOAD1]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s160) = G_BITCAST [[BUILD_VECTOR]](<5 x s32>)
; CI-NEXT: S_NOP 0, implicit [[BITCAST]](s160)
- ;
; VI-LABEL: name: test_load_constant_s160_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1329,7 +1280,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[LOAD1]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s160) = G_BITCAST [[BUILD_VECTOR]](<5 x s32>)
; VI-NEXT: S_NOP 0, implicit [[BITCAST]](s160)
- ;
; GFX9-LABEL: name: test_load_constant_s160_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1368,7 +1318,6 @@ body: |
; CI-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
; CI-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
- ;
; VI-LABEL: name: test_load_constant_s224_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1384,7 +1333,6 @@ body: |
; VI-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
; VI-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
- ;
; GFX9-LABEL: name: test_load_constant_s224_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1421,7 +1369,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), addrspace 4)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_constant_s128_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1429,7 +1376,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), addrspace 4)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_constant_s128_align16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1455,7 +1401,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), align 4, addrspace 4)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_constant_s128_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1463,7 +1408,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), align 4, addrspace 4)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_constant_s128_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1551,7 +1495,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_constant_s128_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1621,7 +1564,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_constant_s128_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1709,7 +1651,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p4) :: (load (<8 x s32>), align 16, addrspace 4)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s256) = G_BITCAST [[LOAD]](<8 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](s256)
- ;
; VI-LABEL: name: test_load_constant_s256_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1717,7 +1658,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p4) :: (load (<8 x s32>), align 16, addrspace 4)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s256) = G_BITCAST [[LOAD]](<8 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](s256)
- ;
; GFX9-LABEL: name: test_load_constant_s256_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1742,14 +1682,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p4) :: (load (p1), addrspace 4)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; VI-LABEL: name: test_load_constant_p1_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p4) :: (load (p1), addrspace 4)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX9-LABEL: name: test_load_constant_p1_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1773,14 +1711,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p4) :: (load (p1), align 4, addrspace 4)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; VI-LABEL: name: test_load_constant_p1_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p4) :: (load (p1), align 4, addrspace 4)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX9-LABEL: name: test_load_constant_p1_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1841,7 +1777,6 @@ body: |
; CI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR6]](s64)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; VI-LABEL: name: test_load_constant_p1_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1885,7 +1820,6 @@ body: |
; VI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR6]](s64)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; GFX9-LABEL: name: test_load_constant_p1_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1946,14 +1880,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p4) :: (load (p3), addrspace 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; VI-LABEL: name: test_load_constant_p3_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p4) :: (load (p3), addrspace 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX9-LABEL: name: test_load_constant_p3_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1977,14 +1909,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p4) :: (load (p4), addrspace 4)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; VI-LABEL: name: test_load_constant_p4_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p4) :: (load (p4), addrspace 4)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; GFX9-LABEL: name: test_load_constant_p4_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2008,14 +1938,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p4) :: (load (p4), align 4, addrspace 4)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; VI-LABEL: name: test_load_constant_p4_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p4) :: (load (p4), align 4, addrspace 4)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; GFX9-LABEL: name: test_load_constant_p4_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2058,7 +1986,6 @@ body: |
; CI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p4) = G_INTTOPTR [[OR2]](s64)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p4)
- ;
; VI-LABEL: name: test_load_constant_p4_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2084,7 +2011,6 @@ body: |
; VI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p4) = G_INTTOPTR [[OR2]](s64)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p4)
- ;
; GFX9-LABEL: name: test_load_constant_p4_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2164,7 +2090,6 @@ body: |
; CI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p4) = G_INTTOPTR [[OR6]](s64)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p4)
- ;
; VI-LABEL: name: test_load_constant_p4_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2208,7 +2133,6 @@ body: |
; VI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p4) = G_INTTOPTR [[OR6]](s64)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p4)
- ;
; GFX9-LABEL: name: test_load_constant_p4_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2269,14 +2193,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p4) :: (load (p5), addrspace 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; VI-LABEL: name: test_load_constant_p5_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p4) :: (load (p5), addrspace 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX9-LABEL: name: test_load_constant_p5_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2307,7 +2229,6 @@ body: |
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; CI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; VI-LABEL: name: test_load_constant_p5_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2321,7 +2242,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX9-LABEL: name: test_load_constant_p5_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2369,7 +2289,6 @@ body: |
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; CI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; VI-LABEL: name: test_load_constant_p5_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2393,7 +2312,6 @@ body: |
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; VI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX9-LABEL: name: test_load_constant_p5_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2434,14 +2352,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_constant_v2s8_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_v2s8_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2467,14 +2383,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_constant_v2s8_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_v2s8_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2506,7 +2420,6 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_constant_v2s8_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2519,7 +2432,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_v2s8_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2555,8 +2467,8 @@ body: |
; CI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; CI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; CI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -2576,7 +2488,6 @@ body: |
; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; CI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; VI-LABEL: name: test_load_constant_v3s8_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2587,8 +2498,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; VI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -2606,7 +2517,6 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; VI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_v3s8_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2617,8 +2527,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -2669,8 +2579,8 @@ body: |
; CI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; CI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; CI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; CI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; CI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -2690,7 +2600,6 @@ body: |
; CI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; CI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; CI-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; VI-LABEL: name: test_load_constant_v3s8_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2711,8 +2620,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; VI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
@@ -2730,7 +2639,6 @@ body: |
; VI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; VI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; VI-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_v3s8_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2751,8 +2659,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX9-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
@@ -2789,14 +2697,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), addrspace 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_constant_v4s8_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), addrspace 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_v4s8_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2827,7 +2733,6 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_constant_v4s8_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2840,7 +2745,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_v4s8_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2887,7 +2791,6 @@ body: |
; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; VI-LABEL: name: test_load_constant_v4s8_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2910,7 +2813,6 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; VI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-LABEL: name: test_load_constant_v4s8_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2951,14 +2853,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load (<2 x s32>), addrspace 4)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_constant_v8s8_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load (<2 x s32>), addrspace 4)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_constant_v8s8_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3008,7 +2908,6 @@ body: |
; CI-NEXT: [[TRUNC3:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR3]](<4 x s32>)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s8>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s8>), [[TRUNC1]](<4 x s8>), [[TRUNC2]](<4 x s8>), [[TRUNC3]](<4 x s8>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<16 x s8>)
- ;
; VI-LABEL: name: test_load_constant_v16s8_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3040,7 +2939,6 @@ body: |
; VI-NEXT: [[TRUNC3:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR3]](<4 x s32>)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s8>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s8>), [[TRUNC1]](<4 x s8>), [[TRUNC2]](<4 x s8>), [[TRUNC3]](<4 x s8>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<16 x s8>)
- ;
; GFX9-LABEL: name: test_load_constant_v16s8_align16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3158,7 +3056,6 @@ body: |
; CI-NEXT: [[TRUNC7:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR7]](<4 x s32>)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s8>), [[TRUNC1]](<4 x s8>), [[TRUNC2]](<4 x s8>), [[TRUNC3]](<4 x s8>), [[TRUNC4]](<4 x s8>), [[TRUNC5]](<4 x s8>), [[TRUNC6]](<4 x s8>), [[TRUNC7]](<4 x s8>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<32 x s8>)
- ;
; VI-LABEL: name: test_load_constant_v32s8_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3210,7 +3107,6 @@ body: |
; VI-NEXT: [[TRUNC7:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR7]](<4 x s32>)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s8>), [[TRUNC1]](<4 x s8>), [[TRUNC2]](<4 x s8>), [[TRUNC3]](<4 x s8>), [[TRUNC4]](<4 x s8>), [[TRUNC5]](<4 x s8>), [[TRUNC6]](<4 x s8>), [[TRUNC7]](<4 x s8>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<32 x s8>)
- ;
; GFX9-LABEL: name: test_load_constant_v32s8_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3328,14 +3224,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p4) :: (load (<2 x s16>), addrspace 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_constant_v2s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p4) :: (load (<2 x s16>), addrspace 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_load_constant_v2s16_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3369,7 +3263,6 @@ body: |
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_constant_v2s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3386,7 +3279,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_load_constant_v2s16_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3436,7 +3328,6 @@ body: |
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_constant_v2s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3463,7 +3354,6 @@ body: |
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_load_constant_v2s16_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3516,13 +3406,13 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; CI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_constant_v3s16_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3542,13 +3432,13 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_load_constant_v3s16_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3611,13 +3501,13 @@ body: |
; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_constant_v3s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3646,13 +3536,13 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_load_constant_v3s16_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3722,13 +3612,13 @@ body: |
; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_constant_v3s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3757,13 +3647,13 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_load_constant_v3s16_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3847,13 +3737,13 @@ body: |
; CI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; CI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
- ; CI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
- ; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL5]]
+ ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; CI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
+ ; CI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
+ ; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL5]]
; CI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_constant_v3s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3896,13 +3786,13 @@ body: |
; VI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
- ; VI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
- ; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL5]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
+ ; VI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
+ ; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL5]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_load_constant_v3s16_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3964,14 +3854,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p4) :: (load (<4 x s16>), addrspace 4)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_constant_v4s16_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p4) :: (load (<4 x s16>), addrspace 4)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_constant_v4s16_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3995,14 +3883,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p4) :: (load (<4 x s16>), align 4, addrspace 4)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_constant_v4s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p4) :: (load (<4 x s16>), align 4, addrspace 4)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_constant_v4s16_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4048,7 +3934,6 @@ body: |
; CI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_constant_v4s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4077,7 +3962,6 @@ body: |
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_constant_v4s16_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4157,7 +4041,6 @@ body: |
; CI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_constant_v4s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4204,7 +4087,6 @@ body: |
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_constant_v4s16_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4263,7 +4145,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), align 8, addrspace 4)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<8 x s16>)
- ;
; VI-LABEL: name: test_load_constant_v8s16_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4271,7 +4152,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), align 8, addrspace 4)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[LOAD]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<8 x s16>)
- ;
; GFX9-LABEL: name: test_load_constant_v8s16_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4296,14 +4176,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load (<2 x s32>), addrspace 4)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_constant_v2s32_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load (<2 x s32>), addrspace 4)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_constant_v2s32_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4327,14 +4205,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load (<2 x s32>), align 4, addrspace 4)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_constant_v2s32_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load (<2 x s32>), align 4, addrspace 4)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_constant_v2s32_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4372,7 +4248,6 @@ body: |
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_constant_v2s32_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4393,7 +4268,6 @@ body: |
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_constant_v2s32_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4463,7 +4337,6 @@ body: |
; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_constant_v2s32_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4502,7 +4375,6 @@ body: |
; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_constant_v2s32_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4558,14 +4430,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>), align 16, addrspace 4)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; VI-LABEL: name: test_load_constant_v3s32_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>), align 16, addrspace 4)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_load_constant_v3s32_align16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4591,14 +4461,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>), align 4, addrspace 4)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; VI-LABEL: name: test_load_constant_v3s32_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>), align 4, addrspace 4)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_load_constant_v3s32_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4622,14 +4490,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), addrspace 4)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_constant_v4s32_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), addrspace 4)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_constant_v4s32_align16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4653,14 +4519,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), align 8, addrspace 4)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_constant_v4s32_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), align 8, addrspace 4)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_constant_v4s32_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4684,14 +4548,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), align 4, addrspace 4)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_constant_v4s32_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), align 4, addrspace 4)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_constant_v4s32_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4715,14 +4577,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p4) :: (load (<8 x s32>), addrspace 4)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<8 x s32>)
- ;
; VI-LABEL: name: test_load_constant_v8s32_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p4) :: (load (<8 x s32>), addrspace 4)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<8 x s32>)
- ;
; GFX9-LABEL: name: test_load_constant_v8s32_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4746,14 +4606,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[COPY]](p4) :: (load (<16 x s32>), align 32, addrspace 4)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[LOAD]](<16 x s32>)
- ;
; VI-LABEL: name: test_load_constant_v16s32_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[COPY]](p4) :: (load (<16 x s32>), align 32, addrspace 4)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[LOAD]](<16 x s32>)
- ;
; GFX9-LABEL: name: test_load_constant_v16s32_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4777,14 +4635,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[COPY]](p4) :: (load (<16 x s16>), addrspace 4)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[LOAD]](<16 x s32>)
- ;
; VI-LABEL: name: test_load_constant_v16s32_align32_extload_from_v16s16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[COPY]](p4) :: (load (<16 x s16>), addrspace 4)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[LOAD]](<16 x s32>)
- ;
; GFX9-LABEL: name: test_load_constant_v16s32_align32_extload_from_v16s16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4808,14 +4664,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p4) :: (load (<2 x s64>), addrspace 4)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_constant_v2s64_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p4) :: (load (<2 x s64>), addrspace 4)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_load_constant_v2s64_align16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4839,14 +4693,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p4) :: (load (<2 x s64>), align 8, addrspace 4)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_constant_v2s64_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p4) :: (load (<2 x s64>), align 8, addrspace 4)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_load_constant_v2s64_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4870,14 +4722,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p4) :: (load (<2 x s64>), align 4, addrspace 4)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_constant_v2s64_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p4) :: (load (<2 x s64>), align 4, addrspace 4)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_load_constant_v2s64_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4938,7 +4788,6 @@ body: |
; CI-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[SHL5]], [[ZEXT1]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR2]](s64), [[OR5]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_constant_v2s64_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4982,7 +4831,6 @@ body: |
; VI-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[SHL5]], [[ZEXT1]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR2]](s64), [[OR5]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_load_constant_v2s64_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -5114,7 +4962,6 @@ body: |
; CI-NEXT: [[OR13:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[ZEXT1]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_constant_v2s64_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -5192,7 +5039,6 @@ body: |
; VI-NEXT: [[OR13:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[ZEXT1]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_load_constant_v2s64_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -5291,7 +5137,6 @@ body: |
; CI-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64), [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[UV2]](s64), [[UV7]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_constant_v3s64_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -5302,7 +5147,6 @@ body: |
; VI-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64), [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[UV2]](s64), [[UV7]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_constant_v3s64_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -5339,7 +5183,6 @@ body: |
; CI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_constant_v3s64_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -5353,7 +5196,6 @@ body: |
; VI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_constant_v3s64_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -5493,7 +5335,6 @@ body: |
; CI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64), [[OR20]](s64), [[UV3]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_constant_v3s64_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -5607,7 +5448,6 @@ body: |
; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64), [[OR20]](s64), [[UV3]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_constant_v3s64_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -5740,14 +5580,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p4) :: (load (<4 x s64>), addrspace 4)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_constant_v4s64_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p4) :: (load (<4 x s64>), addrspace 4)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_constant_v4s64_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -5771,14 +5609,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p4) :: (load (<4 x s64>), align 8, addrspace 4)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_constant_v4s64_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p4) :: (load (<4 x s64>), align 8, addrspace 4)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_constant_v4s64_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -5941,7 +5777,6 @@ body: |
; CI-NEXT: [[OR27:%[0-9]+]]:_(s64) = G_OR [[SHL27]], [[ZEXT3]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64), [[OR20]](s64), [[OR27]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_constant_v4s64_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6087,7 +5922,6 @@ body: |
; VI-NEXT: [[OR27:%[0-9]+]]:_(s64) = G_OR [[SHL27]], [[ZEXT3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64), [[OR20]](s64), [[OR27]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_constant_v4s64_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6251,7 +6085,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p4) :: (load (<8 x s32>), addrspace 4)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s128>) = G_BITCAST [[LOAD]](<8 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<2 x s128>)
- ;
; VI-LABEL: name: test_load_constant_v2s128_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6259,7 +6092,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p4) :: (load (<8 x s32>), addrspace 4)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s128>) = G_BITCAST [[LOAD]](<8 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<2 x s128>)
- ;
; GFX9-LABEL: name: test_load_constant_v2s128_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6285,7 +6117,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), addrspace 4)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; VI-LABEL: name: test_load_constant_v2p1_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6293,7 +6124,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), addrspace 4)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-LABEL: name: test_load_constant_v2p1_align16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6319,7 +6149,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), align 8, addrspace 4)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; VI-LABEL: name: test_load_constant_v2p1_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6327,7 +6156,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), align 8, addrspace 4)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-LABEL: name: test_load_constant_v2p1_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6353,7 +6181,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), align 4, addrspace 4)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; VI-LABEL: name: test_load_constant_v2p1_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6361,7 +6188,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), align 4, addrspace 4)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-LABEL: name: test_load_constant_v2p1_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6449,7 +6275,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; VI-LABEL: name: test_load_constant_v2p1_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6519,7 +6344,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-LABEL: name: test_load_constant_v2p1_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6606,14 +6430,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p4) :: (load (<2 x p3>), addrspace 4)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; VI-LABEL: name: test_load_constant_v2p3_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p4) :: (load (<2 x p3>), addrspace 4)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; GFX9-LABEL: name: test_load_constant_v2p3_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6637,14 +6459,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p4) :: (load (<2 x p3>), align 4, addrspace 4)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; VI-LABEL: name: test_load_constant_v2p3_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p4) :: (load (<2 x p3>), align 4, addrspace 4)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; GFX9-LABEL: name: test_load_constant_v2p3_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6702,7 +6522,6 @@ body: |
; CI-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[INTTOPTR]](p3), [[INTTOPTR1]](p3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; VI-LABEL: name: test_load_constant_v2p3_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6743,7 +6562,6 @@ body: |
; VI-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[INTTOPTR]](p3), [[INTTOPTR1]](p3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; GFX9-LABEL: name: test_load_constant_v2p3_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6801,14 +6619,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_ext_load_constant_s32_from_1_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_ext_load_constant_s32_from_1_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6832,14 +6648,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_ext_load_constant_s32_from_2_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_ext_load_constant_s32_from_2_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6865,7 +6679,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_constant_s64_from_1_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6873,7 +6686,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_ext_load_constant_s64_from_1_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6899,7 +6711,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_constant_s64_from_2_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6907,7 +6718,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_ext_load_constant_s64_from_2_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6933,7 +6743,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), addrspace 4)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_constant_s64_from_4_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6941,7 +6750,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), addrspace 4)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_ext_load_constant_s64_from_4_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6970,7 +6778,6 @@ body: |
; CI-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; VI-LABEL: name: test_ext_load_constant_s128_from_4_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6981,7 +6788,6 @@ body: |
; VI-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; VI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; GFX9-LABEL: name: test_ext_load_constant_s128_from_4_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7010,7 +6816,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_constant_s64_from_2_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7018,7 +6823,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_ext_load_constant_s64_from_2_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7044,7 +6848,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_constant_s64_from_1_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7052,7 +6855,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_ext_load_constant_s64_from_1_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7109,7 +6911,6 @@ body: |
; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_extload_constant_v2s32_from_4_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7148,7 +6949,6 @@ body: |
; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_extload_constant_v2s32_from_4_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7218,7 +7018,6 @@ body: |
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_extload_constant_v2s32_from_4_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7239,7 +7038,6 @@ body: |
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_extload_constant_v2s32_from_4_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7277,14 +7075,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load (<2 x s32>), align 4, addrspace 1)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_extload_constant_v2s32_from_4_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load (<2 x s32>), align 4, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_extload_constant_v2s32_from_4_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7308,14 +7104,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>), align 4, addrspace 1)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; VI-LABEL: name: test_extload_constant_v3s32_from_6_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>), align 4, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_extload_constant_v3s32_from_6_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7339,14 +7133,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), align 4, addrspace 1)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; VI-LABEL: name: test_extload_constant_v4s32_from_8_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load (<4 x s32>), align 4, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_extload_constant_v4s32_from_8_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7466,7 +7258,6 @@ body: |
; CI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_extload_constant_v2s96_from_24_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7569,7 +7360,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-LABEL: name: test_extload_constant_v2s96_from_24_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7738,7 +7528,6 @@ body: |
; CI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_extload_constant_v2s96_from_24_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7791,7 +7580,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-LABEL: name: test_extload_constant_v2s96_from_24_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7872,7 +7660,6 @@ body: |
; CI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_extload_constant_v2s96_from_24_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7887,7 +7674,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-LABEL: name: test_extload_constant_v2s96_from_24_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7930,7 +7716,6 @@ body: |
; CI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_extload_constant_v2s96_from_24_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7945,7 +7730,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-LABEL: name: test_extload_constant_v2s96_from_24_align16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7981,7 +7765,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[COPY]](p4) :: (load (<16 x s32>), align 32, addrspace 4)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s512) = G_BITCAST [[LOAD]](<16 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BITCAST]](s512)
- ;
; VI-LABEL: name: test_load_constant_s512_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7989,7 +7772,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[COPY]](p4) :: (load (<16 x s32>), align 32, addrspace 4)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s512) = G_BITCAST [[LOAD]](<16 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BITCAST]](s512)
- ;
; GFX9-LABEL: name: test_load_constant_s512_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -8015,7 +7797,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[COPY]](p4) :: (load (<16 x s32>), align 32, addrspace 4)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s128>) = G_BITCAST [[LOAD]](<16 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BITCAST]](<4 x s128>)
- ;
; VI-LABEL: name: test_load_constant_v4s128_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -8023,7 +7804,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[COPY]](p4) :: (load (<16 x s32>), align 32, addrspace 4)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s128>) = G_BITCAST [[LOAD]](<16 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BITCAST]](<4 x s128>)
- ;
; GFX9-LABEL: name: test_load_constant_v4s128_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
index 324839482976e96..d8600768ebb6bd1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
@@ -19,7 +19,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; VI-LABEL: name: test_load_flat_s1_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -28,7 +27,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_s1_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -57,7 +55,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; VI-LABEL: name: test_load_flat_s2_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -66,7 +63,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_s2_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -93,14 +89,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8), align 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_flat_s8_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8), align 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_s8_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -125,14 +119,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_flat_s8_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_s8_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -157,14 +149,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_flat_s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_s16_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -189,14 +179,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_flat_s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_s16_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -227,7 +215,6 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_flat_s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -240,7 +227,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_s16_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -271,14 +257,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_flat_s32_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_s32_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -308,7 +292,6 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_flat_s32_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -321,7 +304,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_s32_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -367,7 +349,6 @@ body: |
; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; VI-LABEL: name: test_load_flat_s32_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -390,7 +371,6 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; VI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_s32_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -436,17 +416,17 @@ body: |
; CI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C2]]
- ; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C1]](s32)
+ ; CI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; CI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; CI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
- ; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; CI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; CI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C4]]
- ; CI-NEXT: $vgpr0_vgpr1 = COPY [[AND2]](s64)
- ;
+ ; CI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C4]]
+ ; CI-NEXT: $vgpr0_vgpr1 = COPY [[AND3]](s64)
; VI-LABEL: name: test_load_flat_s48_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -459,17 +439,17 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C2]]
- ; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C1]](s32)
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
- ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; VI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C4]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[AND2]](s64)
- ;
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C4]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[AND3]](s64)
; GFX9-LABEL: name: test_load_flat_s48_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -500,7 +480,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; CI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; VI-LABEL: name: test_load_flat_s64_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -511,7 +490,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX9-LABEL: name: test_load_flat_s64_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -539,7 +517,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; CI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; VI-LABEL: name: test_load_flat_s64_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -550,7 +527,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX9-LABEL: name: test_load_flat_s64_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -588,7 +564,6 @@ body: |
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; CI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; VI-LABEL: name: test_load_flat_s64_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -609,7 +584,6 @@ body: |
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX9-LABEL: name: test_load_flat_s64_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -683,7 +657,6 @@ body: |
; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; CI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; VI-LABEL: name: test_load_flat_s64_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -722,7 +695,6 @@ body: |
; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX9-LABEL: name: test_load_flat_s64_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -790,7 +762,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_flat_s96_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -805,7 +776,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_flat_s96_align16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -838,7 +808,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_flat_s96_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -853,7 +822,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_flat_s96_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -886,7 +854,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_flat_s96_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -901,7 +868,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_flat_s96_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -948,7 +914,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_flat_s96_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -977,7 +942,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_flat_s96_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1071,7 +1035,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_flat_s96_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1126,7 +1089,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_flat_s96_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1212,7 +1174,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s160) = G_BITCAST [[BUILD_VECTOR]](<5 x s32>)
; CI-NEXT: S_NOP 0, implicit [[BITCAST]](s160)
- ;
; VI-LABEL: name: test_load_flat_s160_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1233,7 +1194,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s160) = G_BITCAST [[BUILD_VECTOR]](<5 x s32>)
; VI-NEXT: S_NOP 0, implicit [[BITCAST]](s160)
- ;
; GFX9-LABEL: name: test_load_flat_s160_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1285,7 +1245,6 @@ body: |
; CI-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
; CI-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
- ;
; VI-LABEL: name: test_load_flat_s224_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1314,7 +1273,6 @@ body: |
; VI-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
; VI-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
- ;
; GFX9-LABEL: name: test_load_flat_s224_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1361,7 +1319,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_flat_s128_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1379,7 +1336,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_flat_s128_align16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1415,7 +1371,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_flat_s128_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1433,7 +1388,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_flat_s128_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1521,7 +1475,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_flat_s128_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1591,7 +1544,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_flat_s128_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1701,7 +1653,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s256) = G_BITCAST [[BUILD_VECTOR]](<8 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](s256)
- ;
; VI-LABEL: name: test_load_flat_s256_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1731,7 +1682,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s256) = G_BITCAST [[BUILD_VECTOR]](<8 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](s256)
- ;
; GFX9-LABEL: name: test_load_flat_s256_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1764,7 +1714,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; CI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; VI-LABEL: name: test_load_flat_p1_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1775,7 +1724,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; VI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; GFX9-LABEL: name: test_load_flat_p1_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1803,7 +1751,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; CI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; VI-LABEL: name: test_load_flat_p1_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1814,7 +1761,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; VI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; GFX9-LABEL: name: test_load_flat_p1_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1870,7 +1816,6 @@ body: |
; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; CI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; VI-LABEL: name: test_load_flat_p1_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1909,7 +1854,6 @@ body: |
; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; VI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; GFX9-LABEL: name: test_load_flat_p1_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -1970,14 +1914,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p0) :: (load (p3))
; CI-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; VI-LABEL: name: test_load_flat_p3_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p0) :: (load (p3))
; VI-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX9-LABEL: name: test_load_flat_p3_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2005,7 +1947,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p4)
- ;
; VI-LABEL: name: test_load_flat_p4_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2016,7 +1957,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; VI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p4)
- ;
; GFX9-LABEL: name: test_load_flat_p4_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2044,7 +1984,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p4)
- ;
; VI-LABEL: name: test_load_flat_p4_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2055,7 +1994,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; VI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p4)
- ;
; GFX9-LABEL: name: test_load_flat_p4_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2093,7 +2031,6 @@ body: |
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p4)
- ;
; VI-LABEL: name: test_load_flat_p4_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2114,7 +2051,6 @@ body: |
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; VI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p4)
- ;
; GFX9-LABEL: name: test_load_flat_p4_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2189,7 +2125,6 @@ body: |
; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p4)
- ;
; VI-LABEL: name: test_load_flat_p4_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2228,7 +2163,6 @@ body: |
; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; VI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p4)
- ;
; GFX9-LABEL: name: test_load_flat_p4_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2289,14 +2223,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p0) :: (load (p5))
; CI-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; VI-LABEL: name: test_load_flat_p5_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p0) :: (load (p5))
; VI-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX9-LABEL: name: test_load_flat_p5_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2327,7 +2259,6 @@ body: |
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; CI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; VI-LABEL: name: test_load_flat_p5_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2341,7 +2272,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX9-LABEL: name: test_load_flat_p5_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2389,7 +2319,6 @@ body: |
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; CI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; VI-LABEL: name: test_load_flat_p5_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2413,7 +2342,6 @@ body: |
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; VI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX9-LABEL: name: test_load_flat_p5_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2454,14 +2382,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_flat_v2s8_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_v2s8_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2487,14 +2413,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_flat_v2s8_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_v2s8_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2526,7 +2450,6 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_flat_v2s8_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2539,7 +2462,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_v2s8_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2575,8 +2497,8 @@ body: |
; CI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; CI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; CI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -2596,7 +2518,6 @@ body: |
; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; CI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; VI-LABEL: name: test_load_flat_v3s8_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2607,8 +2528,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; VI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -2626,7 +2547,6 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; VI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_v3s8_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2637,8 +2557,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -2689,8 +2609,8 @@ body: |
; CI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; CI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; CI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; CI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; CI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -2710,7 +2630,6 @@ body: |
; CI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; CI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; CI-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; VI-LABEL: name: test_load_flat_v3s8_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2731,8 +2650,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; VI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
@@ -2750,7 +2669,6 @@ body: |
; VI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; VI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; VI-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_v3s8_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2771,8 +2689,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX9-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
@@ -2809,14 +2727,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_flat_v4s8_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_v4s8_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2847,7 +2763,6 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_flat_v4s8_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2860,7 +2775,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_v4s8_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2907,7 +2821,6 @@ body: |
; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; VI-LABEL: name: test_load_flat_v4s8_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2930,7 +2843,6 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; VI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_v4s8_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -2975,7 +2887,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_flat_v8s8_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2986,7 +2897,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_flat_v8s8_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3021,7 +2931,6 @@ body: |
; CI-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from unknown-address + 12)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_flat_v16s8_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3038,7 +2947,6 @@ body: |
; VI-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from unknown-address + 12)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_flat_v16s8_align16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3085,7 +2993,6 @@ body: |
; CI-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s32) from unknown-address + 28)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<8 x s32>)
- ;
; VI-LABEL: name: test_load_flat_v32s8_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3114,7 +3021,6 @@ body: |
; VI-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s32) from unknown-address + 28)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<8 x s32>)
- ;
; GFX9-LABEL: name: test_load_flat_v32s8_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3144,14 +3050,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p0) :: (load (<2 x s16>))
; CI-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_flat_v2s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p0) :: (load (<2 x s16>))
; VI-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_load_flat_v2s16_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3185,7 +3089,6 @@ body: |
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_flat_v2s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3202,7 +3105,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_load_flat_v2s16_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3252,7 +3154,6 @@ body: |
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_flat_v2s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3279,7 +3180,6 @@ body: |
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_load_flat_v2s16_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3331,21 +3231,22 @@ body: |
; CI-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
- ; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C1]](s32)
+ ; CI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
- ; CI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
- ; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
- ; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; CI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; CI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
+ ; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
+ ; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
- ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
- ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
+ ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; CI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
+ ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
+ ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_flat_v3s16_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3364,21 +3265,22 @@ body: |
; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
- ; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C1]](s32)
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
- ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
- ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
+ ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_load_flat_v3s16_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3431,21 +3333,22 @@ body: |
; CI-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
- ; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C1]](s32)
+ ; CI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
- ; CI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
- ; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
- ; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; CI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; CI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
+ ; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
+ ; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
- ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
- ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
+ ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; CI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
+ ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
+ ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_flat_v3s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3464,21 +3367,22 @@ body: |
; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
- ; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C1]](s32)
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
- ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
- ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
+ ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_load_flat_v3s16_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3548,13 +3452,13 @@ body: |
; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_flat_v3s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3583,13 +3487,13 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_load_flat_v3s16_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3673,13 +3577,13 @@ body: |
; CI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; CI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
- ; CI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
- ; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL5]]
+ ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; CI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
+ ; CI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
+ ; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL5]]
; CI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_flat_v3s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3722,13 +3626,13 @@ body: |
; VI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
- ; VI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
- ; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL5]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
+ ; VI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
+ ; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL5]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_load_flat_v3s16_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3794,7 +3698,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s16>) from unknown-address + 4)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[LOAD]](<2 x s16>), [[LOAD1]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_flat_v4s16_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3805,7 +3708,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s16>) from unknown-address + 4)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[LOAD]](<2 x s16>), [[LOAD1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_flat_v4s16_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3833,7 +3735,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s16>) from unknown-address + 4)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[LOAD]](<2 x s16>), [[LOAD1]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_flat_v4s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3844,7 +3745,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s16>) from unknown-address + 4)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[LOAD]](<2 x s16>), [[LOAD1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_flat_v4s16_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3889,7 +3789,6 @@ body: |
; CI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_flat_v4s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3917,7 +3816,6 @@ body: |
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_flat_v4s16_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -3996,7 +3894,6 @@ body: |
; CI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_flat_v4s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4042,7 +3939,6 @@ body: |
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_flat_v4s16_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4111,7 +4007,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<8 x s16>)
- ;
; VI-LABEL: name: test_load_flat_v8s16_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4129,7 +4024,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<8 x s16>)
- ;
; GFX9-LABEL: name: test_load_flat_v8s16_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4158,7 +4052,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_flat_v2s32_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4169,7 +4062,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_flat_v2s32_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4197,7 +4089,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_flat_v2s32_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4208,7 +4099,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_flat_v2s32_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4237,7 +4127,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_flat_v2s32_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4248,7 +4137,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_flat_v2s32_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4279,7 +4167,6 @@ body: |
; CI-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s32) from unknown-address + 8, align 8)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_load_flat_v3s32_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4293,7 +4180,6 @@ body: |
; VI-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s32) from unknown-address + 8, align 8)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_load_flat_v3s32_align16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4326,7 +4212,6 @@ body: |
; CI-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s32) from unknown-address + 8)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_load_flat_v3s32_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4340,7 +4225,6 @@ body: |
; VI-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s32) from unknown-address + 8)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_load_flat_v3s32_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4374,7 +4258,6 @@ body: |
; CI-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from unknown-address + 12)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_flat_v4s32_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4391,7 +4274,6 @@ body: |
; VI-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from unknown-address + 12)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_flat_v4s32_align16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4425,7 +4307,6 @@ body: |
; CI-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from unknown-address + 12)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_flat_v4s32_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4442,7 +4323,6 @@ body: |
; VI-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from unknown-address + 12)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_flat_v4s32_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4476,7 +4356,6 @@ body: |
; CI-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from unknown-address + 12)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_flat_v4s32_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4493,7 +4372,6 @@ body: |
; VI-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from unknown-address + 12)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_flat_v4s32_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4539,7 +4417,6 @@ body: |
; CI-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s32) from unknown-address + 28)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<8 x s32>)
- ;
; VI-LABEL: name: test_load_flat_v8s32_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4568,7 +4445,6 @@ body: |
; VI-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s32) from unknown-address + 28)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<8 x s32>)
- ;
; GFX9-LABEL: name: test_load_flat_v8s32_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4642,7 +4518,6 @@ body: |
; CI-NEXT: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p0) :: (load (s32) from unknown-address + 60)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32), [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BUILD_VECTOR]](<16 x s32>)
- ;
; VI-LABEL: name: test_load_flat_v16s32_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4695,7 +4570,6 @@ body: |
; VI-NEXT: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p0) :: (load (s32) from unknown-address + 60)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32), [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BUILD_VECTOR]](<16 x s32>)
- ;
; GFX9-LABEL: name: test_load_flat_v16s32_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4740,7 +4614,6 @@ body: |
; CI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_flat_v2s64_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4758,7 +4631,6 @@ body: |
; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_load_flat_v2s64_align16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4793,7 +4665,6 @@ body: |
; CI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_flat_v2s64_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4811,7 +4682,6 @@ body: |
; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_load_flat_v2s64_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4846,7 +4716,6 @@ body: |
; CI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_flat_v2s64_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4864,7 +4733,6 @@ body: |
; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_load_flat_v2s64_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -4917,7 +4785,6 @@ body: |
; CI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_flat_v2s64_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4953,7 +4820,6 @@ body: |
; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_load_flat_v2s64_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -5077,7 +4943,6 @@ body: |
; CI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR8]](s32), [[OR11]](s32)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_flat_v2s64_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -5147,7 +5012,6 @@ body: |
; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_load_flat_v2s64_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -5261,7 +5125,6 @@ body: |
; CI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[UV3]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_flat_v3s64_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -5287,7 +5150,6 @@ body: |
; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[UV3]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_flat_v3s64_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -5339,7 +5201,6 @@ body: |
; CI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[UV3]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_flat_v3s64_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -5365,7 +5226,6 @@ body: |
; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[UV3]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_flat_v3s64_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -5493,7 +5353,6 @@ body: |
; CI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[UV3]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_flat_v3s64_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -5595,7 +5454,6 @@ body: |
; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[UV3]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_flat_v3s64_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -5751,7 +5609,6 @@ body: |
; CI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD6]](s32), [[LOAD7]](s32)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_flat_v4s64_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -5781,7 +5638,6 @@ body: |
; VI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD6]](s32), [[LOAD7]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_flat_v4s64_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -5832,7 +5688,6 @@ body: |
; CI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD6]](s32), [[LOAD7]](s32)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_flat_v4s64_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -5862,7 +5717,6 @@ body: |
; VI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD6]](s32), [[LOAD7]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_flat_v4s64_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6013,7 +5867,6 @@ body: |
; CI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR20]](s32), [[OR23]](s32)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_flat_v4s64_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6143,7 +5996,6 @@ body: |
; VI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR20]](s32), [[OR23]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_flat_v4s64_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6330,7 +6182,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s128>) = G_BITCAST [[BUILD_VECTOR]](<8 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<2 x s128>)
- ;
; VI-LABEL: name: test_load_flat_v2s128_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6360,7 +6211,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s128>) = G_BITCAST [[BUILD_VECTOR]](<8 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<2 x s128>)
- ;
; GFX9-LABEL: name: test_load_flat_v2s128_align32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6400,7 +6250,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; VI-LABEL: name: test_load_flat_v2p1_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6418,7 +6267,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-LABEL: name: test_load_flat_v2p1_align16
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6454,7 +6302,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; VI-LABEL: name: test_load_flat_v2p1_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6472,7 +6319,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-LABEL: name: test_load_flat_v2p1_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6508,7 +6354,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; VI-LABEL: name: test_load_flat_v2p1_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6526,7 +6371,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-LABEL: name: test_load_flat_v2p1_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6614,7 +6458,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; VI-LABEL: name: test_load_flat_v2p1_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6684,7 +6527,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-LABEL: name: test_load_flat_v2p1_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6775,7 +6617,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p0) :: (load (p3) from unknown-address + 4)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[LOAD]](p3), [[LOAD1]](p3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; VI-LABEL: name: test_load_flat_v2p3_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6786,7 +6627,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p0) :: (load (p3) from unknown-address + 4)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[LOAD]](p3), [[LOAD1]](p3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; GFX9-LABEL: name: test_load_flat_v2p3_align8
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6814,7 +6654,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p0) :: (load (p3) from unknown-address + 4)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[LOAD]](p3), [[LOAD1]](p3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; VI-LABEL: name: test_load_flat_v2p3_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6825,7 +6664,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p0) :: (load (p3) from unknown-address + 4)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[LOAD]](p3), [[LOAD1]](p3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; GFX9-LABEL: name: test_load_flat_v2p3_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6883,7 +6721,6 @@ body: |
; CI-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[INTTOPTR]](p3), [[INTTOPTR1]](p3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; VI-LABEL: name: test_load_flat_v2p3_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6924,7 +6761,6 @@ body: |
; VI-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[INTTOPTR]](p3), [[INTTOPTR1]](p3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; GFX9-LABEL: name: test_load_flat_v2p3_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -6982,14 +6818,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8), align 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_ext_load_flat_s32_from_1_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8), align 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_ext_load_flat_s32_from_1_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7013,14 +6847,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_ext_load_flat_s32_from_2_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_ext_load_flat_s32_from_2_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7046,7 +6878,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8), align 4)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_flat_s64_from_1_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7054,7 +6885,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8), align 4)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_ext_load_flat_s64_from_1_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7080,7 +6910,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_flat_s64_from_2_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7088,7 +6917,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_ext_load_flat_s64_from_2_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7114,7 +6942,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_flat_s64_from_4_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7122,7 +6949,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_ext_load_flat_s64_from_4_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7151,7 +6977,6 @@ body: |
; CI-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; VI-LABEL: name: test_ext_load_flat_s128_from_4_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7162,7 +6987,6 @@ body: |
; VI-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; VI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; GFX9-LABEL: name: test_ext_load_flat_s128_from_4_align4
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7191,7 +7015,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_flat_s64_from_2_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7199,7 +7022,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_ext_load_flat_s64_from_2_align2
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7225,7 +7047,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8), align 4)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_flat_s64_from_1_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7233,7 +7054,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8), align 4)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_ext_load_flat_s64_from_1_align1
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -7259,14 +7079,12 @@ body: |
; CI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 536870912)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_flat_s32_align536870912
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 536870912)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_flat_s32_align536870912
; GFX9: liveins: $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
index c0fb02fb184cf9f..fcbcfddef1580ac 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
@@ -39,7 +39,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_s1_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -48,7 +47,6 @@ body: |
; CI-HSA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CI-HSA-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-HSA-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_s1_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -57,7 +55,6 @@ body: |
; CI-MESA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CI-MESA-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-MESA-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; VI-LABEL: name: test_load_global_s1_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -66,7 +63,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s1_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -75,7 +71,6 @@ body: |
; GFX9-HSA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9-HSA-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9-HSA-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s1_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -104,7 +99,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_s2_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -113,7 +107,6 @@ body: |
; CI-HSA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CI-HSA-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-HSA-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_s2_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -122,7 +115,6 @@ body: |
; CI-MESA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CI-MESA-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-MESA-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; VI-LABEL: name: test_load_global_s2_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -131,7 +123,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s2_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -140,7 +131,6 @@ body: |
; GFX9-HSA-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; GFX9-HSA-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9-HSA-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s2_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -167,35 +157,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_s8_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_s8_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_global_s8_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s8_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s8_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -220,35 +205,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_s8_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_s8_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_global_s8_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s8_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s8_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -273,35 +253,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_s16_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_s16_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_global_s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s16_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s16_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -326,35 +301,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_s16_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_s16_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_global_s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s16_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s16_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -385,14 +355,12 @@ body: |
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_s16_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 1, addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_s16_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -405,7 +373,6 @@ body: |
; CI-MESA-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-MESA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-MESA-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_global_s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -418,14 +385,12 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s16_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 1, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s16_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -456,35 +421,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_s32_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_s32_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_global_s32_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s32_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s32_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -514,14 +474,12 @@ body: |
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_s32_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), align 2, addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_s32_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -534,7 +492,6 @@ body: |
; CI-MESA-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-MESA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-MESA-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_global_s32_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -547,14 +504,12 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s32_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), align 2, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s32_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -600,14 +555,12 @@ body: |
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; SI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_s32_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), align 1, addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_s32_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -630,7 +583,6 @@ body: |
; CI-MESA-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; CI-MESA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-MESA-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; VI-LABEL: name: test_load_global_s32_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -653,14 +605,12 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; VI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s32_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), align 1, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s32_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -700,35 +650,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), align 8, addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_s24_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), align 8, addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_s24_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), align 8, addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_global_s24_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), align 8, addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s24_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), align 8, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s24_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -753,35 +698,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_s24_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_s24_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_global_s24_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s24_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s24_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -812,7 +752,6 @@ body: |
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_s24_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -825,7 +764,6 @@ body: |
; CI-HSA-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-HSA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-HSA-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_s24_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -838,7 +776,6 @@ body: |
; CI-MESA-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-MESA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-MESA-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_global_s24_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -851,7 +788,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s24_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -864,7 +800,6 @@ body: |
; GFX9-HSA-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-HSA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-HSA-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s24_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -907,7 +842,6 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; SI-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_s24_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -920,7 +854,6 @@ body: |
; CI-HSA-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-HSA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-HSA-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_s24_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -939,7 +872,6 @@ body: |
; CI-MESA-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; CI-MESA-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; CI-MESA-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; VI-LABEL: name: test_load_global_s24_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -958,7 +890,6 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; VI-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s24_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -971,7 +902,6 @@ body: |
; GFX9-HSA-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-HSA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-HSA-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s24_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -1010,7 +940,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
; SI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[AND]](s64)
- ;
; CI-HSA-LABEL: name: test_load_global_s48_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -1019,7 +948,6 @@ body: |
; CI-HSA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
; CI-HSA-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[AND]](s64)
- ;
; CI-MESA-LABEL: name: test_load_global_s48_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -1028,7 +956,6 @@ body: |
; CI-MESA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
; CI-MESA-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[AND]](s64)
- ;
; VI-LABEL: name: test_load_global_s48_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1037,7 +964,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
; VI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[AND]](s64)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s48_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -1046,7 +972,6 @@ body: |
; GFX9-HSA-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
; GFX9-HSA-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[AND]](s64)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s48_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -1073,35 +998,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; CI-HSA-LABEL: name: test_load_global_s64_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; CI-MESA-LABEL: name: test_load_global_s64_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; VI-LABEL: name: test_load_global_s64_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s64_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s64_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -1125,35 +1045,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), align 4, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; CI-HSA-LABEL: name: test_load_global_s64_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; CI-MESA-LABEL: name: test_load_global_s64_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; VI-LABEL: name: test_load_global_s64_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), align 4, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s64_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s64_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -1195,14 +1110,12 @@ body: |
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C3]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR2]](s64)
- ;
; CI-HSA-LABEL: name: test_load_global_s64_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), align 2, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; CI-MESA-LABEL: name: test_load_global_s64_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -1227,7 +1140,6 @@ body: |
; CI-MESA-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C3]](s32)
; CI-MESA-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[OR2]](s64)
- ;
; VI-LABEL: name: test_load_global_s64_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1252,14 +1164,12 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C3]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR2]](s64)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s64_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), align 2, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s64_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -1337,14 +1247,12 @@ body: |
; SI-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C5]](s32)
; SI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR6]](s64)
- ;
; CI-HSA-LABEL: name: test_load_global_s64_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), align 1, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; CI-MESA-LABEL: name: test_load_global_s64_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -1387,7 +1295,6 @@ body: |
; CI-MESA-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C5]](s32)
; CI-MESA-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[OR6]](s64)
- ;
; VI-LABEL: name: test_load_global_s64_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1430,14 +1337,12 @@ body: |
; VI-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C5]](s32)
; VI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR6]](s64)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s64_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), align 1, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s64_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -1500,7 +1405,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-HSA-LABEL: name: test_load_global_s96_align16
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -1508,7 +1412,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 16, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-MESA-LABEL: name: test_load_global_s96_align16
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -1516,7 +1419,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 16, addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_global_s96_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1524,7 +1426,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 16, addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s96_align16
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -1532,7 +1433,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 16, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s96_align16
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -1563,7 +1463,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-HSA-LABEL: name: test_load_global_s96_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -1571,7 +1470,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 8, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-MESA-LABEL: name: test_load_global_s96_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -1579,7 +1477,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 8, addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_global_s96_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1587,7 +1484,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 8, addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s96_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -1595,7 +1491,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 8, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s96_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -1626,7 +1521,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-HSA-LABEL: name: test_load_global_s96_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -1634,7 +1528,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 4, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-MESA-LABEL: name: test_load_global_s96_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -1642,7 +1535,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 4, addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_global_s96_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1650,7 +1542,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 4, addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s96_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -1658,7 +1549,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 4, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s96_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -1705,7 +1595,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-HSA-LABEL: name: test_load_global_s96_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -1713,7 +1602,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 2, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-MESA-LABEL: name: test_load_global_s96_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -1742,7 +1630,6 @@ body: |
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_global_s96_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1771,7 +1658,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s96_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -1779,7 +1665,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 2, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s96_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -1873,7 +1758,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-HSA-LABEL: name: test_load_global_s96_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -1881,7 +1765,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 1, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-MESA-LABEL: name: test_load_global_s96_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -1936,7 +1819,6 @@ body: |
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_global_s96_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -1991,7 +1873,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s96_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -1999,7 +1880,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 1, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s96_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -2077,7 +1957,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[LOAD1]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s160) = G_BITCAST [[BUILD_VECTOR]](<5 x s32>)
; SI-NEXT: S_NOP 0, implicit [[BITCAST]](s160)
- ;
; CI-HSA-LABEL: name: test_load_global_s160_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -2090,7 +1969,6 @@ body: |
; CI-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[LOAD1]](s32)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s160) = G_BITCAST [[BUILD_VECTOR]](<5 x s32>)
; CI-HSA-NEXT: S_NOP 0, implicit [[BITCAST]](s160)
- ;
; CI-MESA-LABEL: name: test_load_global_s160_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -2103,7 +1981,6 @@ body: |
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[LOAD1]](s32)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(s160) = G_BITCAST [[BUILD_VECTOR]](<5 x s32>)
; CI-MESA-NEXT: S_NOP 0, implicit [[BITCAST]](s160)
- ;
; VI-LABEL: name: test_load_global_s160_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2116,7 +1993,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[LOAD1]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s160) = G_BITCAST [[BUILD_VECTOR]](<5 x s32>)
; VI-NEXT: S_NOP 0, implicit [[BITCAST]](s160)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s160_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -2129,7 +2005,6 @@ body: |
; GFX9-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[LOAD1]](s32)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s160) = G_BITCAST [[BUILD_VECTOR]](<5 x s32>)
; GFX9-HSA-NEXT: S_NOP 0, implicit [[BITCAST]](s160)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s160_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -2171,7 +2046,6 @@ body: |
; SI-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
; SI-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
- ;
; CI-HSA-LABEL: name: test_load_global_s224_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -2187,7 +2061,6 @@ body: |
; CI-HSA-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
; CI-HSA-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
- ;
; CI-MESA-LABEL: name: test_load_global_s224_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -2203,7 +2076,6 @@ body: |
; CI-MESA-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
; CI-MESA-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
- ;
; VI-LABEL: name: test_load_global_s224_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2219,7 +2091,6 @@ body: |
; VI-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
; VI-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s224_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -2235,7 +2106,6 @@ body: |
; GFX9-HSA-NEXT: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
; GFX9-HSA-NEXT: [[INSERT:%[0-9]+]]:_(s256) = G_INSERT [[DEF]], [[BITCAST]](s224), 0
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](s256)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s224_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -2272,7 +2142,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-HSA-LABEL: name: test_load_global_s128_align16
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -2280,7 +2149,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-MESA-LABEL: name: test_load_global_s128_align16
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -2288,7 +2156,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_global_s128_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2296,7 +2163,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s128_align16
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -2304,7 +2170,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s128_align16
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -2330,7 +2195,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 4, addrspace 1)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-HSA-LABEL: name: test_load_global_s128_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -2338,7 +2202,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 4, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-MESA-LABEL: name: test_load_global_s128_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -2346,7 +2209,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 4, addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_global_s128_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2354,7 +2216,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 4, addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s128_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -2362,7 +2223,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 4, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s128_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -2450,7 +2310,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-HSA-LABEL: name: test_load_global_s128_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -2458,7 +2317,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 1, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-MESA-LABEL: name: test_load_global_s128_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -2528,7 +2386,6 @@ body: |
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_global_s128_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2598,7 +2455,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s128_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -2606,7 +2462,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 1, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s128_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -2694,7 +2549,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), align 16, addrspace 1)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s256) = G_BITCAST [[LOAD]](<8 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](s256)
- ;
; CI-HSA-LABEL: name: test_load_global_s256_align32
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -2702,7 +2556,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), align 16, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s256) = G_BITCAST [[LOAD]](<8 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](s256)
- ;
; CI-MESA-LABEL: name: test_load_global_s256_align32
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -2710,7 +2563,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), align 16, addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(s256) = G_BITCAST [[LOAD]](<8 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](s256)
- ;
; VI-LABEL: name: test_load_global_s256_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2718,7 +2570,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), align 16, addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s256) = G_BITCAST [[LOAD]](<8 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](s256)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s256_align32
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -2726,7 +2577,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), align 16, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(s256) = G_BITCAST [[LOAD]](<8 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](s256)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s256_align32
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -2751,35 +2601,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p1) :: (load (p1), addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; CI-HSA-LABEL: name: test_load_global_p1_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p1) :: (load (p1), addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; CI-MESA-LABEL: name: test_load_global_p1_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p1) :: (load (p1), addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; VI-LABEL: name: test_load_global_p1_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p1) :: (load (p1), addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX9-HSA-LABEL: name: test_load_global_p1_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p1) :: (load (p1), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX9-MESA-LABEL: name: test_load_global_p1_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -2803,35 +2648,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p1) :: (load (p1), align 4, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; CI-HSA-LABEL: name: test_load_global_p1_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p1) :: (load (p1), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; CI-MESA-LABEL: name: test_load_global_p1_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p1) :: (load (p1), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; VI-LABEL: name: test_load_global_p1_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p1) :: (load (p1), align 4, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX9-HSA-LABEL: name: test_load_global_p1_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p1) :: (load (p1), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX9-MESA-LABEL: name: test_load_global_p1_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -2892,14 +2732,12 @@ body: |
; SI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR6]](s64)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; CI-HSA-LABEL: name: test_load_global_p1_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p1) :: (load (p1), align 1, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; CI-MESA-LABEL: name: test_load_global_p1_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -2943,7 +2781,6 @@ body: |
; CI-MESA-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; CI-MESA-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR6]](s64)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; VI-LABEL: name: test_load_global_p1_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -2987,14 +2824,12 @@ body: |
; VI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR6]](s64)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; GFX9-HSA-LABEL: name: test_load_global_p1_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p1) :: (load (p1), align 1, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX9-MESA-LABEL: name: test_load_global_p1_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -3055,35 +2890,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p1) :: (load (p3), addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; CI-HSA-LABEL: name: test_load_global_p3_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p1) :: (load (p3), addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; CI-MESA-LABEL: name: test_load_global_p3_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p1) :: (load (p3), addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; VI-LABEL: name: test_load_global_p3_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p1) :: (load (p3), addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX9-HSA-LABEL: name: test_load_global_p3_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p1) :: (load (p3), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX9-MESA-LABEL: name: test_load_global_p3_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -3107,35 +2937,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load (p4), addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; CI-HSA-LABEL: name: test_load_global_p4_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load (p4), addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; CI-MESA-LABEL: name: test_load_global_p4_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load (p4), addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; VI-LABEL: name: test_load_global_p4_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load (p4), addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; GFX9-HSA-LABEL: name: test_load_global_p4_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load (p4), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; GFX9-MESA-LABEL: name: test_load_global_p4_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -3159,35 +2984,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load (p4), align 4, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; CI-HSA-LABEL: name: test_load_global_p4_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load (p4), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; CI-MESA-LABEL: name: test_load_global_p4_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load (p4), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; VI-LABEL: name: test_load_global_p4_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load (p4), align 4, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; GFX9-HSA-LABEL: name: test_load_global_p4_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load (p4), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; GFX9-MESA-LABEL: name: test_load_global_p4_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -3230,14 +3050,12 @@ body: |
; SI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p4) = G_INTTOPTR [[OR2]](s64)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p4)
- ;
; CI-HSA-LABEL: name: test_load_global_p4_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load (p4), align 2, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; CI-MESA-LABEL: name: test_load_global_p4_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -3263,7 +3081,6 @@ body: |
; CI-MESA-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; CI-MESA-NEXT: [[INTTOPTR:%[0-9]+]]:_(p4) = G_INTTOPTR [[OR2]](s64)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p4)
- ;
; VI-LABEL: name: test_load_global_p4_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3289,14 +3106,12 @@ body: |
; VI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p4) = G_INTTOPTR [[OR2]](s64)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p4)
- ;
; GFX9-HSA-LABEL: name: test_load_global_p4_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load (p4), align 2, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; GFX9-MESA-LABEL: name: test_load_global_p4_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -3376,14 +3191,12 @@ body: |
; SI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p4) = G_INTTOPTR [[OR6]](s64)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p4)
- ;
; CI-HSA-LABEL: name: test_load_global_p4_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load (p4), align 1, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; CI-MESA-LABEL: name: test_load_global_p4_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -3427,7 +3240,6 @@ body: |
; CI-MESA-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; CI-MESA-NEXT: [[INTTOPTR:%[0-9]+]]:_(p4) = G_INTTOPTR [[OR6]](s64)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p4)
- ;
; VI-LABEL: name: test_load_global_p4_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3471,14 +3283,12 @@ body: |
; VI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p4) = G_INTTOPTR [[OR6]](s64)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p4)
- ;
; GFX9-HSA-LABEL: name: test_load_global_p4_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load (p4), align 1, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
- ;
; GFX9-MESA-LABEL: name: test_load_global_p4_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -3539,35 +3349,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p1) :: (load (p5), addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; CI-HSA-LABEL: name: test_load_global_p5_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p1) :: (load (p5), addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; CI-MESA-LABEL: name: test_load_global_p5_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p1) :: (load (p5), addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; VI-LABEL: name: test_load_global_p5_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p1) :: (load (p5), addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX9-HSA-LABEL: name: test_load_global_p5_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p1) :: (load (p5), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX9-MESA-LABEL: name: test_load_global_p5_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -3598,14 +3403,12 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; CI-HSA-LABEL: name: test_load_global_p5_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p1) :: (load (p5), align 2, addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; CI-MESA-LABEL: name: test_load_global_p5_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -3619,7 +3422,6 @@ body: |
; CI-MESA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-MESA-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; CI-MESA-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; VI-LABEL: name: test_load_global_p5_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3633,14 +3435,12 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX9-HSA-LABEL: name: test_load_global_p5_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p1) :: (load (p5), align 2, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX9-MESA-LABEL: name: test_load_global_p5_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -3688,14 +3488,12 @@ body: |
; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; SI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; CI-HSA-LABEL: name: test_load_global_p5_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p1) :: (load (p5), align 1, addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; CI-MESA-LABEL: name: test_load_global_p5_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -3719,7 +3517,6 @@ body: |
; CI-MESA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-MESA-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; CI-MESA-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; VI-LABEL: name: test_load_global_p5_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3743,14 +3540,12 @@ body: |
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; VI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX9-HSA-LABEL: name: test_load_global_p5_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p1) :: (load (p5), align 1, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX9-MESA-LABEL: name: test_load_global_p5_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -3791,35 +3586,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s8_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s8_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_global_v2s8_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s8_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s8_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -3845,35 +3635,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s8_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s8_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_global_v2s8_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s8_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s8_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -3905,14 +3690,12 @@ body: |
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s8_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 1, addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s8_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -3925,7 +3708,6 @@ body: |
; CI-MESA-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-MESA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-MESA-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_global_v2s8_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -3938,14 +3720,12 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s8_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 1, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s8_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -3981,8 +3761,8 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; SI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; SI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -4002,7 +3782,6 @@ body: |
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; SI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_v3s8_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -4013,8 +3792,8 @@ body: |
; CI-HSA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-HSA-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CI-HSA-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CI-HSA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; CI-HSA-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CI-HSA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; CI-HSA-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; CI-HSA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-HSA-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -4034,7 +3813,6 @@ body: |
; CI-HSA-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI-HSA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; CI-HSA-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_v3s8_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -4045,8 +3823,8 @@ body: |
; CI-MESA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CI-MESA-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CI-MESA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; CI-MESA-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CI-MESA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; CI-MESA-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; CI-MESA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-MESA-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -4066,7 +3844,6 @@ body: |
; CI-MESA-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI-MESA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; CI-MESA-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; VI-LABEL: name: test_load_global_v3s8_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4077,8 +3854,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; VI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -4096,7 +3873,6 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; VI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v3s8_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -4107,8 +3883,8 @@ body: |
; GFX9-HSA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-HSA-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX9-HSA-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9-HSA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX9-HSA-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-HSA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX9-HSA-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX9-HSA-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-HSA-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -4126,7 +3902,6 @@ body: |
; GFX9-HSA-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX9-HSA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; GFX9-HSA-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v3s8_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -4137,8 +3912,8 @@ body: |
; GFX9-MESA-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX9-MESA-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9-MESA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX9-MESA-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-MESA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX9-MESA-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX9-MESA-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-MESA-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -4190,8 +3965,8 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; SI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; SI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -4211,7 +3986,6 @@ body: |
; SI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; SI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; SI-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_v3s8_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -4227,8 +4001,8 @@ body: |
; CI-HSA-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C2]](s32)
; CI-HSA-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; CI-HSA-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CI-HSA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
; CI-HSA-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CI-HSA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
; CI-HSA-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI-HSA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CI-HSA-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -4248,7 +4022,6 @@ body: |
; CI-HSA-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI-HSA-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL3]]
; CI-HSA-NEXT: $vgpr0 = COPY [[OR3]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_v3s8_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -4269,8 +4042,8 @@ body: |
; CI-MESA-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; CI-MESA-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; CI-MESA-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CI-MESA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; CI-MESA-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CI-MESA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; CI-MESA-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; CI-MESA-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CI-MESA-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -4290,7 +4063,6 @@ body: |
; CI-MESA-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; CI-MESA-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; CI-MESA-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; VI-LABEL: name: test_load_global_v3s8_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4311,8 +4083,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; VI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
@@ -4330,7 +4102,6 @@ body: |
; VI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; VI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; VI-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v3s8_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -4346,8 +4117,8 @@ body: |
; GFX9-HSA-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C2]](s32)
; GFX9-HSA-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; GFX9-HSA-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9-HSA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
; GFX9-HSA-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-HSA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
; GFX9-HSA-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; GFX9-HSA-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-HSA-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
@@ -4365,7 +4136,6 @@ body: |
; GFX9-HSA-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX9-HSA-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL3]]
; GFX9-HSA-NEXT: $vgpr0 = COPY [[OR3]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v3s8_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -4386,8 +4156,8 @@ body: |
; GFX9-MESA-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; GFX9-MESA-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; GFX9-MESA-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9-MESA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX9-MESA-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-MESA-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX9-MESA-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; GFX9-MESA-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-MESA-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
@@ -4432,7 +4202,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; SI-NEXT: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
- ;
; CI-HSA-LABEL: name: test_load_global_v4s8_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -4447,7 +4216,6 @@ body: |
; CI-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; CI-HSA-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; CI-HSA-NEXT: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
- ;
; CI-MESA-LABEL: name: test_load_global_v4s8_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -4462,7 +4230,6 @@ body: |
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; CI-MESA-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; CI-MESA-NEXT: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
- ;
; VI-LABEL: name: test_load_global_v4s8_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4477,7 +4244,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v4s8_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -4498,7 +4264,6 @@ body: |
; GFX9-HSA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-HSA-NEXT: [[TRUNC4:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<4 x s16>)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[TRUNC4]](<4 x s8>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v4s8_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -4549,7 +4314,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; SI-NEXT: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
- ;
; CI-HSA-LABEL: name: test_load_global_v4s8_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -4564,7 +4328,6 @@ body: |
; CI-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; CI-HSA-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; CI-HSA-NEXT: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
- ;
; CI-MESA-LABEL: name: test_load_global_v4s8_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -4584,7 +4347,6 @@ body: |
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; CI-MESA-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; CI-MESA-NEXT: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
- ;
; VI-LABEL: name: test_load_global_v4s8_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4604,7 +4366,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v4s8_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -4625,7 +4386,6 @@ body: |
; GFX9-HSA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-HSA-NEXT: [[TRUNC4:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<4 x s16>)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[TRUNC4]](<4 x s8>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v4s8_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -4690,7 +4450,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; SI-NEXT: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
- ;
; CI-HSA-LABEL: name: test_load_global_v4s8_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -4705,7 +4464,6 @@ body: |
; CI-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; CI-HSA-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; CI-HSA-NEXT: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
- ;
; CI-MESA-LABEL: name: test_load_global_v4s8_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -4734,7 +4492,6 @@ body: |
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; CI-MESA-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; CI-MESA-NEXT: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
- ;
; VI-LABEL: name: test_load_global_v4s8_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -4763,7 +4520,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v4s8_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -4784,7 +4540,6 @@ body: |
; GFX9-HSA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-HSA-NEXT: [[TRUNC4:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<4 x s16>)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[TRUNC4]](<4 x s8>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v4s8_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -4836,35 +4591,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-HSA-LABEL: name: test_load_global_v8s8_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-MESA-LABEL: name: test_load_global_v8s8_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_global_v8s8_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v8s8_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v8s8_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -4889,35 +4639,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; CI-HSA-LABEL: name: test_load_global_v16s8_align16
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; CI-MESA-LABEL: name: test_load_global_v16s8_align16
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_global_v16s8_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v16s8_align16
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v16s8_align16
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -4942,35 +4687,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), addrspace 1)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<8 x s32>)
- ;
; CI-HSA-LABEL: name: test_load_global_v32s8_align32
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<8 x s32>)
- ;
; CI-MESA-LABEL: name: test_load_global_v32s8_align32
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<8 x s32>)
- ;
; VI-LABEL: name: test_load_global_v32s8_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<8 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v32s8_align32
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<8 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v32s8_align32
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -4996,35 +4736,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s16_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s16_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_global_v2s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s16_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s16_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -5058,14 +4793,12 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s16_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), align 2, addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s16_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -5082,7 +4815,6 @@ body: |
; CI-MESA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CI-MESA-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_global_v2s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -5099,14 +4831,12 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s16_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), align 2, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s16_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -5156,14 +4886,12 @@ body: |
; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s16_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), align 1, addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s16_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -5190,7 +4918,6 @@ body: |
; CI-MESA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-MESA-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_global_v2s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -5217,14 +4944,12 @@ body: |
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s16_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), align 1, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s16_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -5277,13 +5002,13 @@ body: |
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v3s16_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -5303,13 +5028,13 @@ body: |
; CI-HSA-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-HSA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-HSA-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-HSA-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; CI-HSA-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; CI-HSA-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; CI-HSA-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CI-HSA-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; CI-HSA-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CI-HSA-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CI-HSA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v3s16_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -5329,13 +5054,13 @@ body: |
; CI-MESA-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-MESA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-MESA-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-MESA-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; CI-MESA-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; CI-MESA-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; CI-MESA-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CI-MESA-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; CI-MESA-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CI-MESA-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CI-MESA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_global_v3s16_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -5355,13 +5080,13 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v3s16_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -5383,7 +5108,6 @@ body: |
; GFX9-HSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX9-HSA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v3s16_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -5446,13 +5170,13 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v3s16_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -5481,13 +5205,13 @@ body: |
; CI-HSA-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-HSA-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; CI-HSA-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; CI-HSA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; CI-HSA-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-HSA-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; CI-HSA-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; CI-HSA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-HSA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v3s16_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -5516,13 +5240,13 @@ body: |
; CI-MESA-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-MESA-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-MESA-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; CI-MESA-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; CI-MESA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; CI-MESA-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-MESA-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; CI-MESA-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; CI-MESA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-MESA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_global_v3s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -5551,13 +5275,13 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v3s16_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -5586,7 +5310,6 @@ body: |
; GFX9-HSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX9-HSA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v3s16_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -5656,13 +5379,13 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v3s16_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -5691,13 +5414,13 @@ body: |
; CI-HSA-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-HSA-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; CI-HSA-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; CI-HSA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; CI-HSA-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-HSA-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; CI-HSA-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; CI-HSA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-HSA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v3s16_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -5726,13 +5449,13 @@ body: |
; CI-MESA-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-MESA-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-MESA-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; CI-MESA-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; CI-MESA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; CI-MESA-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-MESA-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; CI-MESA-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; CI-MESA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-MESA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_global_v3s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -5761,13 +5484,13 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v3s16_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -5796,7 +5519,6 @@ body: |
; GFX9-HSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX9-HSA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v3s16_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -5880,13 +5602,13 @@ body: |
; SI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; SI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
- ; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
- ; SI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL5]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
+ ; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
+ ; SI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL5]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v3s16_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -5915,13 +5637,13 @@ body: |
; CI-HSA-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-HSA-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; CI-HSA-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; CI-HSA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; CI-HSA-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-HSA-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; CI-HSA-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; CI-HSA-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-HSA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v3s16_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -5964,13 +5686,13 @@ body: |
; CI-MESA-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-MESA-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; CI-MESA-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CI-MESA-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
- ; CI-MESA-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
- ; CI-MESA-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL5]]
+ ; CI-MESA-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; CI-MESA-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
+ ; CI-MESA-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
+ ; CI-MESA-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL5]]
; CI-MESA-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; CI-MESA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_global_v3s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6013,13 +5735,13 @@ body: |
; VI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
- ; VI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
- ; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL5]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
+ ; VI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
+ ; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL5]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v3s16_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -6048,7 +5770,6 @@ body: |
; GFX9-HSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX9-HSA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v3s16_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -6110,35 +5831,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v4s16_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v4s16_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_global_v4s16_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v4s16_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v4s16_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -6162,35 +5878,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), align 4, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v4s16_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v4s16_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_global_v4s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), align 4, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v4s16_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v4s16_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -6236,14 +5947,12 @@ body: |
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v4s16_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), align 2, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v4s16_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -6272,7 +5981,6 @@ body: |
; CI-MESA-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CI-MESA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_global_v4s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6301,14 +6009,12 @@ body: |
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v4s16_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), align 2, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v4s16_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -6388,14 +6094,12 @@ body: |
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v4s16_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), align 1, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v4s16_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -6442,7 +6146,6 @@ body: |
; CI-MESA-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; CI-MESA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_global_v4s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6489,14 +6192,12 @@ body: |
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v4s16_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), align 1, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v4s16_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -6569,7 +6270,6 @@ body: |
; SI-NEXT: $vgpr0 = COPY [[UV]](<2 x s16>)
; SI-NEXT: $vgpr1 = COPY [[UV1]](<2 x s16>)
; SI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v5s16_align16
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -6591,7 +6291,6 @@ body: |
; CI-HSA-NEXT: $vgpr0 = COPY [[UV]](<2 x s16>)
; CI-HSA-NEXT: $vgpr1 = COPY [[UV1]](<2 x s16>)
; CI-HSA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v5s16_align16
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -6613,7 +6312,6 @@ body: |
; CI-MESA-NEXT: $vgpr0 = COPY [[UV]](<2 x s16>)
; CI-MESA-NEXT: $vgpr1 = COPY [[UV1]](<2 x s16>)
; CI-MESA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_global_v5s16_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6635,7 +6333,6 @@ body: |
; VI-NEXT: $vgpr0 = COPY [[UV]](<2 x s16>)
; VI-NEXT: $vgpr1 = COPY [[UV1]](<2 x s16>)
; VI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v5s16_align16
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -6655,7 +6352,6 @@ body: |
; GFX9-HSA-NEXT: $vgpr0 = COPY [[UV4]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr1 = COPY [[UV9]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr2 = COPY [[BUILD_VECTOR]](<2 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v5s16_align16
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -6714,7 +6410,6 @@ body: |
; SI-NEXT: $vgpr0 = COPY [[UV]](<2 x s16>)
; SI-NEXT: $vgpr1 = COPY [[UV1]](<2 x s16>)
; SI-NEXT: $vgpr2 = COPY [[BITCAST1]](<2 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v5s16_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -6755,7 +6450,6 @@ body: |
; CI-HSA-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; CI-HSA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-HSA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v5s16_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -6796,7 +6490,6 @@ body: |
; CI-MESA-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; CI-MESA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-MESA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_global_v5s16_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -6837,7 +6530,6 @@ body: |
; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; VI-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; VI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v5s16_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -6870,7 +6562,6 @@ body: |
; GFX9-HSA-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr1 = COPY [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr2 = COPY [[BUILD_VECTOR2]](<2 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v5s16_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -6942,7 +6633,6 @@ body: |
; SI-NEXT: $vgpr0 = COPY [[UV]](<2 x s16>)
; SI-NEXT: $vgpr1 = COPY [[UV1]](<2 x s16>)
; SI-NEXT: $vgpr2 = COPY [[BITCAST1]](<2 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v5s16_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -6983,7 +6673,6 @@ body: |
; CI-HSA-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; CI-HSA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-HSA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v5s16_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -7024,7 +6713,6 @@ body: |
; CI-MESA-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; CI-MESA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-MESA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_global_v5s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7065,7 +6753,6 @@ body: |
; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; VI-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; VI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v5s16_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -7098,7 +6785,6 @@ body: |
; GFX9-HSA-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr1 = COPY [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr2 = COPY [[BUILD_VECTOR2]](<2 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v5s16_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -7188,7 +6874,6 @@ body: |
; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; SI-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; SI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v5s16_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -7229,7 +6914,6 @@ body: |
; CI-HSA-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; CI-HSA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-HSA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v5s16_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -7270,7 +6954,6 @@ body: |
; CI-MESA-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; CI-MESA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-MESA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_global_v5s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7311,7 +6994,6 @@ body: |
; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; VI-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; VI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v5s16_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -7344,7 +7026,6 @@ body: |
; GFX9-HSA-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr1 = COPY [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr2 = COPY [[BUILD_VECTOR2]](<2 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v5s16_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -7456,7 +7137,6 @@ body: |
; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; SI-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; SI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v5s16_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -7497,7 +7177,6 @@ body: |
; CI-HSA-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; CI-HSA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-HSA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v5s16_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -7560,7 +7239,6 @@ body: |
; CI-MESA-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; CI-MESA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-MESA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_global_v5s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7623,7 +7301,6 @@ body: |
; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
; VI-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; VI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v5s16_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -7656,7 +7333,6 @@ body: |
; GFX9-HSA-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr1 = COPY [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr2 = COPY [[BUILD_VECTOR2]](<2 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v5s16_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -7737,7 +7413,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v6s16_align16
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -7745,7 +7420,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 16, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v6s16_align16
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -7753,7 +7427,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 16, addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_global_v6s16_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7761,7 +7434,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 16, addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v6s16_align16
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -7769,7 +7441,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 16, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v6s16_align16
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -7800,7 +7471,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v6s16_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -7808,7 +7478,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 8, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v6s16_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -7816,7 +7485,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 8, addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_global_v6s16_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7824,7 +7492,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 8, addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v6s16_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -7832,7 +7499,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 8, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v6s16_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -7863,7 +7529,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v6s16_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -7871,7 +7536,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 4, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v6s16_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -7879,7 +7543,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 4, addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_global_v6s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -7887,7 +7550,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 4, addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v6s16_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -7895,7 +7557,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 4, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v6s16_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -7942,7 +7603,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v6s16_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -7950,7 +7610,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 2, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v6s16_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -7979,7 +7638,6 @@ body: |
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_global_v6s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -8008,7 +7666,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v6s16_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -8016,7 +7673,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 2, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v6s16_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -8110,7 +7766,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v6s16_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -8118,7 +7773,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 1, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v6s16_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -8173,7 +7827,6 @@ body: |
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_global_v6s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -8228,7 +7881,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v6s16_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -8236,7 +7888,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 1, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<6 x s16>) = G_BITCAST [[LOAD]](<3 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](<6 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v6s16_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -8324,7 +7975,6 @@ body: |
; SI-NEXT: $vgpr1 = COPY [[UV1]](<2 x s16>)
; SI-NEXT: $vgpr2 = COPY [[UV2]](<2 x s16>)
; SI-NEXT: $vgpr3 = COPY [[BITCAST3]](<2 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v7s16_align16
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -8347,7 +7997,6 @@ body: |
; CI-HSA-NEXT: $vgpr1 = COPY [[UV1]](<2 x s16>)
; CI-HSA-NEXT: $vgpr2 = COPY [[UV2]](<2 x s16>)
; CI-HSA-NEXT: $vgpr3 = COPY [[BITCAST3]](<2 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v7s16_align16
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -8370,7 +8019,6 @@ body: |
; CI-MESA-NEXT: $vgpr1 = COPY [[UV1]](<2 x s16>)
; CI-MESA-NEXT: $vgpr2 = COPY [[UV2]](<2 x s16>)
; CI-MESA-NEXT: $vgpr3 = COPY [[BITCAST3]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_global_v7s16_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -8393,7 +8041,6 @@ body: |
; VI-NEXT: $vgpr1 = COPY [[UV1]](<2 x s16>)
; VI-NEXT: $vgpr2 = COPY [[UV2]](<2 x s16>)
; VI-NEXT: $vgpr3 = COPY [[BITCAST3]](<2 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v7s16_align16
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -8415,7 +8062,6 @@ body: |
; GFX9-HSA-NEXT: $vgpr1 = COPY [[UV9]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr2 = COPY [[UV14]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr3 = COPY [[BUILD_VECTOR]](<2 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v7s16_align16
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -8507,7 +8153,6 @@ body: |
; SI-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; SI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; SI-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v7s16_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -8560,7 +8205,6 @@ body: |
; CI-HSA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-HSA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; CI-HSA-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v7s16_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -8613,7 +8257,6 @@ body: |
; CI-MESA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-MESA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; CI-MESA-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_global_v7s16_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -8666,7 +8309,6 @@ body: |
; VI-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; VI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; VI-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v7s16_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -8709,7 +8351,6 @@ body: |
; GFX9-HSA-NEXT: $vgpr1 = COPY [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr2 = COPY [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr3 = COPY [[BUILD_VECTOR3]](<2 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v7s16_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -8822,7 +8463,6 @@ body: |
; SI-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; SI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; SI-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v7s16_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -8875,7 +8515,6 @@ body: |
; CI-HSA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-HSA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; CI-HSA-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v7s16_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -8928,7 +8567,6 @@ body: |
; CI-MESA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-MESA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; CI-MESA-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_global_v7s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -8981,7 +8619,6 @@ body: |
; VI-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; VI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; VI-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v7s16_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -9024,7 +8661,6 @@ body: |
; GFX9-HSA-NEXT: $vgpr1 = COPY [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr2 = COPY [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr3 = COPY [[BUILD_VECTOR3]](<2 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v7s16_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -9137,7 +8773,6 @@ body: |
; SI-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; SI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; SI-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v7s16_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -9190,7 +8825,6 @@ body: |
; CI-HSA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-HSA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; CI-HSA-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v7s16_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -9243,7 +8877,6 @@ body: |
; CI-MESA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-MESA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; CI-MESA-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_global_v7s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -9296,7 +8929,6 @@ body: |
; VI-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; VI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; VI-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v7s16_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -9339,7 +8971,6 @@ body: |
; GFX9-HSA-NEXT: $vgpr1 = COPY [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr2 = COPY [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr3 = COPY [[BUILD_VECTOR3]](<2 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v7s16_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -9482,7 +9113,6 @@ body: |
; SI-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; SI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; SI-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v7s16_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -9535,7 +9165,6 @@ body: |
; CI-HSA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-HSA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; CI-HSA-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v7s16_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -9618,7 +9247,6 @@ body: |
; CI-MESA-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; CI-MESA-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; CI-MESA-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_global_v7s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -9701,7 +9329,6 @@ body: |
; VI-NEXT: $vgpr1 = COPY [[BITCAST2]](<2 x s16>)
; VI-NEXT: $vgpr2 = COPY [[BITCAST3]](<2 x s16>)
; VI-NEXT: $vgpr3 = COPY [[BITCAST4]](<2 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v7s16_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -9744,7 +9371,6 @@ body: |
; GFX9-HSA-NEXT: $vgpr1 = COPY [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr2 = COPY [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-HSA-NEXT: $vgpr3 = COPY [[BUILD_VECTOR3]](<2 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v7s16_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -9842,7 +9468,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[LOAD]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<8 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v8s16_align16
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -9850,7 +9475,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<8 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v8s16_align16
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -9858,7 +9482,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<8 x s16>)
- ;
; VI-LABEL: name: test_load_global_v8s16_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -9866,7 +9489,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[LOAD]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<8 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v8s16_align16
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -9874,7 +9496,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<8 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v8s16_align16
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -9900,7 +9521,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 8, addrspace 1)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[LOAD]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<8 x s16>)
- ;
; CI-HSA-LABEL: name: test_load_global_v8s16_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -9908,7 +9528,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 8, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<8 x s16>)
- ;
; CI-MESA-LABEL: name: test_load_global_v8s16_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -9916,7 +9535,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 8, addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<8 x s16>)
- ;
; VI-LABEL: name: test_load_global_v8s16_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -9924,7 +9542,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 8, addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[LOAD]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<8 x s16>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v8s16_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -9932,7 +9549,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 8, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s16>) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<8 x s16>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v8s16_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -9957,35 +9573,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s32_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s32_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_global_v2s32_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s32_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s32_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -10009,35 +9620,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), align 4, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s32_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s32_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_global_v2s32_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), align 4, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s32_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s32_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -10075,14 +9681,12 @@ body: |
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s32_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), align 2, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s32_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -10103,7 +9707,6 @@ body: |
; CI-MESA-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_global_v2s32_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -10124,14 +9727,12 @@ body: |
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s32_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), align 2, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s32_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -10201,14 +9802,12 @@ body: |
; SI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s32_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), align 1, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s32_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -10247,7 +9846,6 @@ body: |
; CI-MESA-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_global_v2s32_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -10286,14 +9884,12 @@ body: |
; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s32_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s32>), align 1, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s32_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -10351,35 +9947,30 @@ body: |
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<4 x s32>)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; CI-HSA-LABEL: name: test_load_global_v3s32_align16
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 16, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; CI-MESA-LABEL: name: test_load_global_v3s32_align16
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 16, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; VI-LABEL: name: test_load_global_v3s32_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 16, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v3s32_align16
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 16, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v3s32_align16
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -10408,35 +9999,30 @@ body: |
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; CI-HSA-LABEL: name: test_load_global_v3s32_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; CI-MESA-LABEL: name: test_load_global_v3s32_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; VI-LABEL: name: test_load_global_v3s32_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 4, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v3s32_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v3s32_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -10460,35 +10046,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; CI-HSA-LABEL: name: test_load_global_v4s32_align16
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; CI-MESA-LABEL: name: test_load_global_v4s32_align16
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_global_v4s32_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v4s32_align16
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v4s32_align16
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -10512,35 +10093,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 8, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; CI-HSA-LABEL: name: test_load_global_v4s32_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 8, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; CI-MESA-LABEL: name: test_load_global_v4s32_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 8, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_global_v4s32_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 8, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v4s32_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 8, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v4s32_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -10564,35 +10140,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 4, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; CI-HSA-LABEL: name: test_load_global_v4s32_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; CI-MESA-LABEL: name: test_load_global_v4s32_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_global_v4s32_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 4, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v4s32_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v4s32_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -10616,35 +10187,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), addrspace 1)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<8 x s32>)
- ;
; CI-HSA-LABEL: name: test_load_global_v8s32_align32
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<8 x s32>)
- ;
; CI-MESA-LABEL: name: test_load_global_v8s32_align32
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<8 x s32>)
- ;
; VI-LABEL: name: test_load_global_v8s32_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<8 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v8s32_align32
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<8 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v8s32_align32
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -10668,35 +10234,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[COPY]](p1) :: (load (<16 x s32>), align 32, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[LOAD]](<16 x s32>)
- ;
; CI-HSA-LABEL: name: test_load_global_v16s32_align32
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[COPY]](p1) :: (load (<16 x s32>), align 32, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[LOAD]](<16 x s32>)
- ;
; CI-MESA-LABEL: name: test_load_global_v16s32_align32
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[COPY]](p1) :: (load (<16 x s32>), align 32, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[LOAD]](<16 x s32>)
- ;
; VI-LABEL: name: test_load_global_v16s32_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[COPY]](p1) :: (load (<16 x s32>), align 32, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[LOAD]](<16 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v16s32_align32
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[COPY]](p1) :: (load (<16 x s32>), align 32, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[LOAD]](<16 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v16s32_align32
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -10720,35 +10281,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), addrspace 1)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s64_align16
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s64_align16
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_global_v2s64_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s64_align16
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s64_align16
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -10772,35 +10328,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), align 8, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s64_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), align 8, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s64_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), align 8, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_global_v2s64_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), align 8, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s64_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), align 8, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s64_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -10824,35 +10375,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), align 4, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s64_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s64_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_global_v2s64_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), align 4, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s64_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s64_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -10913,14 +10459,12 @@ body: |
; SI-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[SHL5]], [[ZEXT1]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR2]](s64), [[OR5]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s64_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), align 2, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s64_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -10964,7 +10508,6 @@ body: |
; CI-MESA-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[SHL5]], [[ZEXT1]]
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR2]](s64), [[OR5]](s64)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_global_v2s64_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -11008,14 +10551,12 @@ body: |
; VI-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[SHL5]], [[ZEXT1]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR2]](s64), [[OR5]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s64_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), align 2, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s64_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -11147,14 +10688,12 @@ body: |
; SI-NEXT: [[OR13:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[ZEXT1]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s64_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), align 1, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s64_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -11232,7 +10771,6 @@ body: |
; CI-MESA-NEXT: [[OR13:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[ZEXT1]]
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_global_v2s64_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -11310,14 +10848,12 @@ body: |
; VI-NEXT: [[OR13:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[ZEXT1]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s64_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load (<2 x s64>), align 1, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s64_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -11413,7 +10949,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2sp1_align16
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -11421,7 +10956,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2sp1_align16
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -11429,7 +10963,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; VI-LABEL: name: test_load_global_v2sp1_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -11437,7 +10970,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2sp1_align16
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -11445,7 +10977,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2sp1_align16
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -11474,7 +11005,6 @@ body: |
; SI-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64), [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[UV2]](s64), [[UV7]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; CI-HSA-LABEL: name: test_load_global_v3s64_align32
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -11485,7 +11015,6 @@ body: |
; CI-HSA-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64), [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; CI-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[UV2]](s64), [[UV7]](s64)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; CI-MESA-LABEL: name: test_load_global_v3s64_align32
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -11496,7 +11025,6 @@ body: |
; CI-MESA-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64), [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[UV2]](s64), [[UV7]](s64)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_global_v3s64_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -11507,7 +11035,6 @@ body: |
; VI-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64), [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[UV2]](s64), [[UV7]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v3s64_align32
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -11518,7 +11045,6 @@ body: |
; GFX9-HSA-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64), [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; GFX9-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[UV2]](s64), [[UV7]](s64)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v3s64_align32
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -11555,7 +11081,6 @@ body: |
; SI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; CI-HSA-LABEL: name: test_load_global_v3s64_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -11569,7 +11094,6 @@ body: |
; CI-HSA-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; CI-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; CI-MESA-LABEL: name: test_load_global_v3s64_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -11583,7 +11107,6 @@ body: |
; CI-MESA-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_global_v3s64_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -11597,7 +11120,6 @@ body: |
; VI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v3s64_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -11611,7 +11133,6 @@ body: |
; GFX9-HSA-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; GFX9-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v3s64_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -11751,7 +11272,6 @@ body: |
; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64), [[OR20]](s64), [[UV3]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; CI-HSA-LABEL: name: test_load_global_v3s64_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -11765,7 +11285,6 @@ body: |
; CI-HSA-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; CI-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; CI-MESA-LABEL: name: test_load_global_v3s64_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -11879,7 +11398,6 @@ body: |
; CI-MESA-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64), [[OR20]](s64), [[UV3]](s64)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_global_v3s64_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -11993,7 +11511,6 @@ body: |
; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64), [[OR20]](s64), [[UV3]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v3s64_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -12007,7 +11524,6 @@ body: |
; GFX9-HSA-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; GFX9-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v3s64_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -12140,35 +11656,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p1) :: (load (<4 x s64>), addrspace 1)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; CI-HSA-LABEL: name: test_load_global_v4s64_align32
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p1) :: (load (<4 x s64>), addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; CI-MESA-LABEL: name: test_load_global_v4s64_align32
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p1) :: (load (<4 x s64>), addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_global_v4s64_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p1) :: (load (<4 x s64>), addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v4s64_align32
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p1) :: (load (<4 x s64>), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v4s64_align32
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -12192,35 +11703,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p1) :: (load (<4 x s64>), align 8, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; CI-HSA-LABEL: name: test_load_global_v4s64_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p1) :: (load (<4 x s64>), align 8, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; CI-MESA-LABEL: name: test_load_global_v4s64_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p1) :: (load (<4 x s64>), align 8, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_global_v4s64_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p1) :: (load (<4 x s64>), align 8, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v4s64_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p1) :: (load (<4 x s64>), align 8, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v4s64_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -12383,14 +11889,12 @@ body: |
; SI-NEXT: [[OR27:%[0-9]+]]:_(s64) = G_OR [[SHL27]], [[ZEXT3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64), [[OR20]](s64), [[OR27]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; CI-HSA-LABEL: name: test_load_global_v4s64_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p1) :: (load (<4 x s64>), align 1, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; CI-MESA-LABEL: name: test_load_global_v4s64_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -12536,7 +12040,6 @@ body: |
; CI-MESA-NEXT: [[OR27:%[0-9]+]]:_(s64) = G_OR [[SHL27]], [[ZEXT3]]
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64), [[OR20]](s64), [[OR27]](s64)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_global_v4s64_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -12682,14 +12185,12 @@ body: |
; VI-NEXT: [[OR27:%[0-9]+]]:_(s64) = G_OR [[SHL27]], [[ZEXT3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64), [[OR20]](s64), [[OR27]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v4s64_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s64>) = G_LOAD [[COPY]](p1) :: (load (<4 x s64>), align 1, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[LOAD]](<4 x s64>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v4s64_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -12853,7 +12354,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), addrspace 1)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s128>) = G_BITCAST [[LOAD]](<8 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<2 x s128>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2s128_align32
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -12861,7 +12361,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s128>) = G_BITCAST [[LOAD]](<8 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<2 x s128>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2s128_align32
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -12869,7 +12368,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s128>) = G_BITCAST [[LOAD]](<8 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<2 x s128>)
- ;
; VI-LABEL: name: test_load_global_v2s128_align32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -12877,7 +12375,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s128>) = G_BITCAST [[LOAD]](<8 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<2 x s128>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2s128_align32
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -12885,7 +12382,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s128>) = G_BITCAST [[LOAD]](<8 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<2 x s128>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2s128_align32
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -12911,7 +12407,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2p1_align16
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -12919,7 +12414,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2p1_align16
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -12927,7 +12421,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; VI-LABEL: name: test_load_global_v2p1_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -12935,7 +12428,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2p1_align16
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -12943,7 +12435,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2p1_align16
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -12969,7 +12460,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 8, addrspace 1)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2p1_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -12977,7 +12467,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 8, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2p1_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -12985,7 +12474,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 8, addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; VI-LABEL: name: test_load_global_v2p1_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -12993,7 +12481,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 8, addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2p1_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -13001,7 +12488,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 8, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2p1_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -13027,7 +12513,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 4, addrspace 1)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2p1_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -13035,7 +12520,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 4, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2p1_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -13043,7 +12527,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 4, addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; VI-LABEL: name: test_load_global_v2p1_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -13051,7 +12534,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 4, addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2p1_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -13059,7 +12541,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 4, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2p1_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -13147,7 +12628,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2p1_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -13155,7 +12635,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 1, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2p1_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -13225,7 +12704,6 @@ body: |
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; VI-LABEL: name: test_load_global_v2p1_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -13295,7 +12773,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2p1_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -13303,7 +12780,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s32>), align 1, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2p1_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -13391,7 +12867,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), align 8, addrspace 1)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x p1>) = G_BITCAST [[LOAD]](<8 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<4 x p1>)
- ;
; CI-HSA-LABEL: name: test_load_global_v4p1_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -13399,7 +12874,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), align 8, addrspace 1)
; CI-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x p1>) = G_BITCAST [[LOAD]](<8 x s32>)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<4 x p1>)
- ;
; CI-MESA-LABEL: name: test_load_global_v4p1_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -13407,7 +12881,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), align 8, addrspace 1)
; CI-MESA-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x p1>) = G_BITCAST [[LOAD]](<8 x s32>)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<4 x p1>)
- ;
; VI-LABEL: name: test_load_global_v4p1_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -13415,7 +12888,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), align 8, addrspace 1)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x p1>) = G_BITCAST [[LOAD]](<8 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<4 x p1>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v4p1_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -13423,7 +12895,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[COPY]](p1) :: (load (<8 x s32>), align 8, addrspace 1)
; GFX9-HSA-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x p1>) = G_BITCAST [[LOAD]](<8 x s32>)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<4 x p1>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v4p1_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -13448,35 +12919,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p1) :: (load (<2 x p3>), addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2p3_align8
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p1) :: (load (<2 x p3>), addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2p3_align8
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p1) :: (load (<2 x p3>), addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; VI-LABEL: name: test_load_global_v2p3_align8
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p1) :: (load (<2 x p3>), addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2p3_align8
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p1) :: (load (<2 x p3>), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2p3_align8
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -13500,35 +12966,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p1) :: (load (<2 x p3>), align 4, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2p3_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p1) :: (load (<2 x p3>), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2p3_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p1) :: (load (<2 x p3>), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; VI-LABEL: name: test_load_global_v2p3_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p1) :: (load (<2 x p3>), align 4, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2p3_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p1) :: (load (<2 x p3>), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2p3_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -13586,14 +13047,12 @@ body: |
; SI-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[INTTOPTR]](p3), [[INTTOPTR1]](p3)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; CI-HSA-LABEL: name: test_load_global_v2p3_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p1) :: (load (<2 x p3>), align 1, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; CI-MESA-LABEL: name: test_load_global_v2p3_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -13634,7 +13093,6 @@ body: |
; CI-MESA-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[INTTOPTR]](p3), [[INTTOPTR1]](p3)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; VI-LABEL: name: test_load_global_v2p3_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -13675,14 +13133,12 @@ body: |
; VI-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[INTTOPTR]](p3), [[INTTOPTR1]](p3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v2p3_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p1) :: (load (<2 x p3>), align 1, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v2p3_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -13740,35 +13196,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-HSA-LABEL: name: test_ext_load_global_s32_from_1_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_ext_load_global_s32_from_1_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_ext_load_global_s32_from_1_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-HSA-LABEL: name: test_ext_load_global_s32_from_1_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_ext_load_global_s32_from_1_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -13792,35 +13243,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-HSA-LABEL: name: test_ext_load_global_s32_from_2_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_ext_load_global_s32_from_2_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_ext_load_global_s32_from_2_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-HSA-LABEL: name: test_ext_load_global_s32_from_2_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_ext_load_global_s32_from_2_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -13856,7 +13302,6 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; SI-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; CI-HSA-LABEL: name: test_ext_load_global_s32_from_s24_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -13869,7 +13314,6 @@ body: |
; CI-HSA-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-HSA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-HSA-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-MESA-LABEL: name: test_ext_load_global_s32_from_s24_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -13888,7 +13332,6 @@ body: |
; CI-MESA-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; CI-MESA-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; CI-MESA-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; VI-LABEL: name: test_ext_load_global_s32_from_s24_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -13907,7 +13350,6 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; VI-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; GFX9-HSA-LABEL: name: test_ext_load_global_s32_from_s24_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -13920,7 +13362,6 @@ body: |
; GFX9-HSA-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-HSA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-HSA-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-MESA-LABEL: name: test_ext_load_global_s32_from_s24_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -13961,7 +13402,6 @@ body: |
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-HSA-LABEL: name: test_ext_load_global_s32_from_s24_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -13974,7 +13414,6 @@ body: |
; CI-HSA-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-HSA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-HSA-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-MESA-LABEL: name: test_ext_load_global_s32_from_s24_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -13987,7 +13426,6 @@ body: |
; CI-MESA-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-MESA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-MESA-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_ext_load_global_s32_from_s24_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -14000,7 +13438,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-HSA-LABEL: name: test_ext_load_global_s32_from_s24_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -14013,7 +13450,6 @@ body: |
; GFX9-HSA-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-HSA-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-HSA-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-MESA-LABEL: name: test_ext_load_global_s32_from_s24_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -14043,35 +13479,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-HSA-LABEL: name: test_ext_load_global_s32_from_s24_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_ext_load_global_s32_from_s24_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_ext_load_global_s32_from_s24_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-HSA-LABEL: name: test_ext_load_global_s32_from_s24_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_ext_load_global_s32_from_s24_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -14097,7 +13528,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-HSA-LABEL: name: test_ext_load_global_s64_from_1_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -14105,7 +13535,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; CI-HSA-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-MESA-LABEL: name: test_ext_load_global_s64_from_1_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -14113,7 +13542,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; CI-MESA-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_global_s64_from_1_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -14121,7 +13549,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-HSA-LABEL: name: test_ext_load_global_s64_from_1_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -14129,7 +13556,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; GFX9-HSA-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-MESA-LABEL: name: test_ext_load_global_s64_from_1_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -14155,7 +13581,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-HSA-LABEL: name: test_ext_load_global_s64_from_2_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -14163,7 +13588,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; CI-HSA-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-MESA-LABEL: name: test_ext_load_global_s64_from_2_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -14171,7 +13595,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; CI-MESA-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_global_s64_from_2_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -14179,7 +13602,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-HSA-LABEL: name: test_ext_load_global_s64_from_2_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -14187,7 +13609,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; GFX9-HSA-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-MESA-LABEL: name: test_ext_load_global_s64_from_2_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -14213,7 +13634,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-HSA-LABEL: name: test_ext_load_global_s64_from_4_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -14221,7 +13641,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; CI-HSA-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-MESA-LABEL: name: test_ext_load_global_s64_from_4_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -14229,7 +13648,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; CI-MESA-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_global_s64_from_4_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -14237,7 +13655,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-HSA-LABEL: name: test_ext_load_global_s64_from_4_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -14245,7 +13662,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
; GFX9-HSA-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-MESA-LABEL: name: test_ext_load_global_s64_from_4_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -14274,7 +13690,6 @@ body: |
; SI-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; SI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; CI-HSA-LABEL: name: test_ext_load_global_s128_from_4_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -14285,7 +13700,6 @@ body: |
; CI-HSA-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CI-HSA-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; CI-MESA-LABEL: name: test_ext_load_global_s128_from_4_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -14296,7 +13710,6 @@ body: |
; CI-MESA-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CI-MESA-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; VI-LABEL: name: test_ext_load_global_s128_from_4_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -14307,7 +13720,6 @@ body: |
; VI-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; VI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; GFX9-HSA-LABEL: name: test_ext_load_global_s128_from_4_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -14318,7 +13730,6 @@ body: |
; GFX9-HSA-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; GFX9-HSA-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; GFX9-MESA-LABEL: name: test_ext_load_global_s128_from_4_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -14347,7 +13758,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-HSA-LABEL: name: test_ext_load_global_s64_from_2_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -14355,7 +13765,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; CI-HSA-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-MESA-LABEL: name: test_ext_load_global_s64_from_2_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -14363,7 +13772,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; CI-MESA-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_global_s64_from_2_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -14371,7 +13779,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-HSA-LABEL: name: test_ext_load_global_s64_from_2_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -14379,7 +13786,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
; GFX9-HSA-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-MESA-LABEL: name: test_ext_load_global_s64_from_2_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -14405,7 +13811,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-HSA-LABEL: name: test_ext_load_global_s64_from_1_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -14413,7 +13818,6 @@ body: |
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; CI-HSA-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-MESA-LABEL: name: test_ext_load_global_s64_from_1_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -14421,7 +13825,6 @@ body: |
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; CI-MESA-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_global_s64_from_1_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -14429,7 +13832,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-HSA-LABEL: name: test_ext_load_global_s64_from_1_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -14437,7 +13839,6 @@ body: |
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
; GFX9-HSA-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-MESA-LABEL: name: test_ext_load_global_s64_from_1_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -14462,35 +13863,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), align 1, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-HSA-LABEL: name: test_extload_global_v2s32_from_v2s16_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), align 1, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-MESA-LABEL: name: test_extload_global_v2s32_from_v2s16_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), align 1, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_extload_global_v2s32_from_v2s16_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), align 1, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_extload_global_v2s32_from_v2s16_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), align 1, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_extload_global_v2s32_from_v2s16_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -14514,35 +13910,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), align 2, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-HSA-LABEL: name: test_extload_global_v2s32_from_v2s16_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), align 2, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-MESA-LABEL: name: test_extload_global_v2s32_from_v2s16_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), align 2, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_extload_global_v2s32_from_v2s16_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), align 2, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_extload_global_v2s32_from_v2s16_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), align 2, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_extload_global_v2s32_from_v2s16_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -14566,35 +13957,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), addrspace 1)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-HSA-LABEL: name: test_extload_global_v2s32_from_v2s16_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-MESA-LABEL: name: test_extload_global_v2s32_from_v2s16_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_extload_global_v2s32_from_v2s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), addrspace 1)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_extload_global_v2s32_from_v2s16_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p1) :: (load (<2 x s16>), addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_extload_global_v2s32_from_v2s16_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -14618,35 +14004,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s16>), align 4, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; CI-HSA-LABEL: name: test_extload_global_v3s32_from_v3s16_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s16>), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; CI-MESA-LABEL: name: test_extload_global_v3s32_from_v3s16_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s16>), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; VI-LABEL: name: test_extload_global_v3s32_from_v3s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s16>), align 4, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_extload_global_v3s32_from_v3s16_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s16>), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_extload_global_v3s32_from_v3s16_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -14670,35 +14051,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), align 4, addrspace 1)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; CI-HSA-LABEL: name: test_extload_global_v4s32_from_v4s16_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), align 4, addrspace 1)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; CI-MESA-LABEL: name: test_extload_global_v4s32_from_v4s16_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), align 4, addrspace 1)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; VI-LABEL: name: test_extload_global_v4s32_from_v4s16_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), align 4, addrspace 1)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-HSA-LABEL: name: test_extload_global_v4s32_from_v4s16_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load (<4 x s16>), align 4, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-MESA-LABEL: name: test_extload_global_v4s32_from_v4s16_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -14818,7 +14194,6 @@ body: |
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; SI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-HSA-LABEL: name: test_global_v2s96_align1
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -14833,7 +14208,6 @@ body: |
; CI-HSA-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-HSA-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-MESA-LABEL: name: test_global_v2s96_align1
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -14936,7 +14310,6 @@ body: |
; CI-MESA-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-MESA-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_global_v2s96_align1
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -15039,7 +14412,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-HSA-LABEL: name: test_global_v2s96_align1
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -15054,7 +14426,6 @@ body: |
; GFX9-HSA-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-HSA-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-MESA-LABEL: name: test_global_v2s96_align1
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -15223,7 +14594,6 @@ body: |
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; SI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-HSA-LABEL: name: test_global_v2s96_align2
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -15238,7 +14608,6 @@ body: |
; CI-HSA-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-HSA-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-MESA-LABEL: name: test_global_v2s96_align2
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -15291,7 +14660,6 @@ body: |
; CI-MESA-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-MESA-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_global_v2s96_align2
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -15344,7 +14712,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-HSA-LABEL: name: test_global_v2s96_align2
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -15359,7 +14726,6 @@ body: |
; GFX9-HSA-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-HSA-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-MESA-LABEL: name: test_global_v2s96_align2
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -15449,7 +14815,6 @@ body: |
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; SI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-HSA-LABEL: name: test_global_v2s96_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -15464,7 +14829,6 @@ body: |
; CI-HSA-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-HSA-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-MESA-LABEL: name: test_global_v2s96_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -15479,7 +14843,6 @@ body: |
; CI-MESA-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-MESA-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_global_v2s96_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -15494,7 +14857,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-HSA-LABEL: name: test_global_v2s96_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -15509,7 +14871,6 @@ body: |
; GFX9-HSA-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-HSA-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-MESA-LABEL: name: test_global_v2s96_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -15559,7 +14920,6 @@ body: |
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; SI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-HSA-LABEL: name: test_global_v2s96_align16
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -15574,7 +14934,6 @@ body: |
; CI-HSA-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-HSA-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-MESA-LABEL: name: test_global_v2s96_align16
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -15589,7 +14948,6 @@ body: |
; CI-MESA-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-MESA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-MESA-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_global_v2s96_align16
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -15604,7 +14962,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-HSA-LABEL: name: test_global_v2s96_align16
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -15619,7 +14976,6 @@ body: |
; GFX9-HSA-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-HSA-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-HSA-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-MESA-LABEL: name: test_global_v2s96_align16
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -15718,7 +15074,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32), [[LSHR7]](s32), [[LSHR8]](s32), [[LSHR9]](s32), [[LSHR10]](s32), [[LSHR11]](s32), [[LSHR12]](s32), [[LSHR13]](s32), [[LSHR14]](s32), [[LSHR15]](s32), [[LSHR16]](s32), [[LSHR17]](s32), [[LSHR18]](s32), [[LSHR19]](s32), [[LSHR20]](s32), [[LSHR21]](s32), [[LSHR22]](s32), [[LSHR23]](s32), [[LSHR24]](s32), [[LSHR25]](s32), [[LSHR26]](s32), [[LSHR27]](s32), [[LSHR28]](s32), [[LSHR29]](s32), [[LSHR30]](s32)
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(<32 x s1>) = G_TRUNC [[BUILD_VECTOR]](<32 x s32>)
; SI-NEXT: $vgpr0 = COPY [[TRUNC]](<32 x s1>)
- ;
; CI-HSA-LABEL: name: test_load_global_v32s1_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -15789,7 +15144,6 @@ body: |
; CI-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32), [[LSHR7]](s32), [[LSHR8]](s32), [[LSHR9]](s32), [[LSHR10]](s32), [[LSHR11]](s32), [[LSHR12]](s32), [[LSHR13]](s32), [[LSHR14]](s32), [[LSHR15]](s32), [[LSHR16]](s32), [[LSHR17]](s32), [[LSHR18]](s32), [[LSHR19]](s32), [[LSHR20]](s32), [[LSHR21]](s32), [[LSHR22]](s32), [[LSHR23]](s32), [[LSHR24]](s32), [[LSHR25]](s32), [[LSHR26]](s32), [[LSHR27]](s32), [[LSHR28]](s32), [[LSHR29]](s32), [[LSHR30]](s32)
; CI-HSA-NEXT: [[TRUNC:%[0-9]+]]:_(<32 x s1>) = G_TRUNC [[BUILD_VECTOR]](<32 x s32>)
; CI-HSA-NEXT: $vgpr0 = COPY [[TRUNC]](<32 x s1>)
- ;
; CI-MESA-LABEL: name: test_load_global_v32s1_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -15860,7 +15214,6 @@ body: |
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32), [[LSHR7]](s32), [[LSHR8]](s32), [[LSHR9]](s32), [[LSHR10]](s32), [[LSHR11]](s32), [[LSHR12]](s32), [[LSHR13]](s32), [[LSHR14]](s32), [[LSHR15]](s32), [[LSHR16]](s32), [[LSHR17]](s32), [[LSHR18]](s32), [[LSHR19]](s32), [[LSHR20]](s32), [[LSHR21]](s32), [[LSHR22]](s32), [[LSHR23]](s32), [[LSHR24]](s32), [[LSHR25]](s32), [[LSHR26]](s32), [[LSHR27]](s32), [[LSHR28]](s32), [[LSHR29]](s32), [[LSHR30]](s32)
; CI-MESA-NEXT: [[TRUNC:%[0-9]+]]:_(<32 x s1>) = G_TRUNC [[BUILD_VECTOR]](<32 x s32>)
; CI-MESA-NEXT: $vgpr0 = COPY [[TRUNC]](<32 x s1>)
- ;
; VI-LABEL: name: test_load_global_v32s1_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -15931,7 +15284,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32), [[LSHR7]](s32), [[LSHR8]](s32), [[LSHR9]](s32), [[LSHR10]](s32), [[LSHR11]](s32), [[LSHR12]](s32), [[LSHR13]](s32), [[LSHR14]](s32), [[LSHR15]](s32), [[LSHR16]](s32), [[LSHR17]](s32), [[LSHR18]](s32), [[LSHR19]](s32), [[LSHR20]](s32), [[LSHR21]](s32), [[LSHR22]](s32), [[LSHR23]](s32), [[LSHR24]](s32), [[LSHR25]](s32), [[LSHR26]](s32), [[LSHR27]](s32), [[LSHR28]](s32), [[LSHR29]](s32), [[LSHR30]](s32)
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(<32 x s1>) = G_TRUNC [[BUILD_VECTOR]](<32 x s32>)
; VI-NEXT: $vgpr0 = COPY [[TRUNC]](<32 x s1>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v32s1_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -16050,7 +15402,6 @@ body: |
; GFX9-HSA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>), [[BUILD_VECTOR6]](<2 x s16>), [[BUILD_VECTOR7]](<2 x s16>), [[BUILD_VECTOR8]](<2 x s16>), [[BUILD_VECTOR9]](<2 x s16>), [[BUILD_VECTOR10]](<2 x s16>), [[BUILD_VECTOR11]](<2 x s16>), [[BUILD_VECTOR12]](<2 x s16>), [[BUILD_VECTOR13]](<2 x s16>), [[BUILD_VECTOR14]](<2 x s16>), [[BUILD_VECTOR15]](<2 x s16>)
; GFX9-HSA-NEXT: [[TRUNC32:%[0-9]+]]:_(<32 x s1>) = G_TRUNC [[CONCAT_VECTORS]](<32 x s16>)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[TRUNC32]](<32 x s1>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v32s1_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -16202,7 +15553,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32)
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s4>) = G_TRUNC [[BUILD_VECTOR]](<8 x s32>)
; SI-NEXT: $vgpr0 = COPY [[TRUNC]](<8 x s4>)
- ;
; CI-HSA-LABEL: name: test_load_global_v8s4_align4
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
@@ -16225,7 +15575,6 @@ body: |
; CI-HSA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32)
; CI-HSA-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s4>) = G_TRUNC [[BUILD_VECTOR]](<8 x s32>)
; CI-HSA-NEXT: $vgpr0 = COPY [[TRUNC]](<8 x s4>)
- ;
; CI-MESA-LABEL: name: test_load_global_v8s4_align4
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
@@ -16248,7 +15597,6 @@ body: |
; CI-MESA-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32)
; CI-MESA-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s4>) = G_TRUNC [[BUILD_VECTOR]](<8 x s32>)
; CI-MESA-NEXT: $vgpr0 = COPY [[TRUNC]](<8 x s4>)
- ;
; VI-LABEL: name: test_load_global_v8s4_align4
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -16271,7 +15619,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32)
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s4>) = G_TRUNC [[BUILD_VECTOR]](<8 x s32>)
; VI-NEXT: $vgpr0 = COPY [[TRUNC]](<8 x s4>)
- ;
; GFX9-HSA-LABEL: name: test_load_global_v8s4_align4
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
@@ -16306,7 +15653,6 @@ body: |
; GFX9-HSA-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>), [[BUILD_VECTOR3]](<2 x s16>)
; GFX9-HSA-NEXT: [[TRUNC8:%[0-9]+]]:_(<8 x s4>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[TRUNC8]](<8 x s4>)
- ;
; GFX9-MESA-LABEL: name: test_load_global_v8s4_align4
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
@@ -16359,35 +15705,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 536870912, addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-HSA-LABEL: name: test_load_global_s32_align536870912
; CI-HSA: liveins: $vgpr0_vgpr1
; CI-HSA-NEXT: {{ $}}
; CI-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 536870912, addrspace 1)
; CI-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-MESA-LABEL: name: test_load_global_s32_align536870912
; CI-MESA: liveins: $vgpr0_vgpr1
; CI-MESA-NEXT: {{ $}}
; CI-MESA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 536870912, addrspace 1)
; CI-MESA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_global_s32_align536870912
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 536870912, addrspace 1)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-HSA-LABEL: name: test_load_global_s32_align536870912
; GFX9-HSA: liveins: $vgpr0_vgpr1
; GFX9-HSA-NEXT: {{ $}}
; GFX9-HSA-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 536870912, addrspace 1)
; GFX9-HSA-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-MESA-LABEL: name: test_load_global_s32_align536870912
; GFX9-MESA: liveins: $vgpr0_vgpr1
; GFX9-MESA-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
index a94df99206304a9..46a6125225dfb1f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
@@ -24,7 +24,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; CI-LABEL: name: test_load_local_s1_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -33,7 +32,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_s1_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -42,7 +40,6 @@ body: |
; CI-DS128-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CI-DS128-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-DS128-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; VI-LABEL: name: test_load_local_s1_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -51,7 +48,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX9-LABEL: name: test_load_local_s1_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -60,7 +56,6 @@ body: |
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s1_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -69,7 +64,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9-UNALIGNED-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX10-LABEL: name: test_load_local_s1_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -78,7 +72,6 @@ body: |
; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX10-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX10-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s1_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -87,7 +80,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX10-UNALIGNED-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX11-LABEL: name: test_load_local_s1_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -96,7 +88,6 @@ body: |
; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX11-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s1_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -125,7 +116,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; CI-LABEL: name: test_load_local_s2_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -134,7 +124,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_s2_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -143,7 +132,6 @@ body: |
; CI-DS128-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CI-DS128-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-DS128-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; VI-LABEL: name: test_load_local_s2_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -152,7 +140,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX9-LABEL: name: test_load_local_s2_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -161,7 +148,6 @@ body: |
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s2_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -170,7 +156,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; GFX9-UNALIGNED-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX10-LABEL: name: test_load_local_s2_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -179,7 +164,6 @@ body: |
; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; GFX10-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX10-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s2_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -188,7 +172,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; GFX10-UNALIGNED-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX11-LABEL: name: test_load_local_s2_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -197,7 +180,6 @@ body: |
; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX11-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s2_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -224,63 +206,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_local_s8_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_s8_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; CI-DS128-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_local_s8_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_local_s8_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s8_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_local_s8_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s8_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_local_s8_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s8_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -305,63 +278,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_local_s8_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_s8_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CI-DS128-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_local_s8_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_local_s8_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s8_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_local_s8_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s8_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_local_s8_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s8_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -386,63 +350,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_local_s16_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_s16_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; CI-DS128-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_local_s16_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_local_s16_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s16_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_local_s16_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s16_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_local_s16_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s16_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -467,63 +422,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_local_s16_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_s16_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; CI-DS128-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_local_s16_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_local_s16_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s16_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_local_s16_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s16_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_local_s16_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s16_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -554,7 +500,6 @@ body: |
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-LABEL: name: test_load_local_s16_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -567,7 +512,6 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_s16_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -580,7 +524,6 @@ body: |
; CI-DS128-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-DS128-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-DS128-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_local_s16_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -593,7 +536,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_load_local_s16_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -606,14 +548,12 @@ body: |
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s16_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_local_s16_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -626,14 +566,12 @@ body: |
; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX10-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX10-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s16_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 1, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_local_s16_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -646,7 +584,6 @@ body: |
; GFX11-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX11-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s16_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -671,63 +608,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_local_s32_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_s32_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; CI-DS128-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_local_s32_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_local_s32_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s32_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_local_s32_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s32_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_local_s32_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s32_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -757,7 +685,6 @@ body: |
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-LABEL: name: test_load_local_s32_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -770,7 +697,6 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_s32_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -783,7 +709,6 @@ body: |
; CI-DS128-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-DS128-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-DS128-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_local_s32_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -796,7 +721,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_load_local_s32_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -809,14 +733,12 @@ body: |
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s32_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 2, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_local_s32_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -829,14 +751,12 @@ body: |
; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX10-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX10-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s32_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 2, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_local_s32_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -849,7 +769,6 @@ body: |
; GFX11-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX11-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s32_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -889,7 +808,6 @@ body: |
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; SI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; CI-LABEL: name: test_load_local_s32_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -912,7 +830,6 @@ body: |
; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_s32_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -935,7 +852,6 @@ body: |
; CI-DS128-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; CI-DS128-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-DS128-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; VI-LABEL: name: test_load_local_s32_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -958,7 +874,6 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; VI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-LABEL: name: test_load_local_s32_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -981,14 +896,12 @@ body: |
; GFX9-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; GFX9-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s32_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_local_s32_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -1011,14 +924,12 @@ body: |
; GFX10-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; GFX10-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; GFX10-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s32_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 1, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_local_s32_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -1041,7 +952,6 @@ body: |
; GFX11-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; GFX11-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; GFX11-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s32_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -1065,63 +975,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_local_s24_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_s24_align8
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
; CI-DS128-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_local_s24_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_local_s24_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s24_align8
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_local_s24_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s24_align8
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_local_s24_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s24_align8
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -1146,63 +1047,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_local_s24_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_s24_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; CI-DS128-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_local_s24_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_local_s24_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s24_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_local_s24_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s24_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_local_s24_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s24_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -1233,7 +1125,6 @@ body: |
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-LABEL: name: test_load_local_s24_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -1246,7 +1137,6 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_s24_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -1259,7 +1149,6 @@ body: |
; CI-DS128-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-DS128-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-DS128-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_local_s24_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -1272,7 +1161,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_load_local_s24_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -1285,7 +1173,6 @@ body: |
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s24_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -1298,7 +1185,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-UNALIGNED-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX10-LABEL: name: test_load_local_s24_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -1311,7 +1197,6 @@ body: |
; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX10-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX10-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s24_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -1324,7 +1209,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX10-UNALIGNED-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX11-LABEL: name: test_load_local_s24_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -1337,7 +1221,6 @@ body: |
; GFX11-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX11-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s24_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -1380,7 +1263,6 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; SI-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; CI-LABEL: name: test_load_local_s24_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -1399,7 +1281,6 @@ body: |
; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; CI-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_s24_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -1418,7 +1299,6 @@ body: |
; CI-DS128-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; CI-DS128-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; CI-DS128-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; VI-LABEL: name: test_load_local_s24_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -1437,7 +1317,6 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; VI-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; GFX9-LABEL: name: test_load_local_s24_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -1456,7 +1335,6 @@ body: |
; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; GFX9-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s24_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -1469,7 +1347,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-UNALIGNED-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX10-LABEL: name: test_load_local_s24_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -1488,7 +1365,6 @@ body: |
; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; GFX10-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; GFX10-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s24_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -1501,7 +1377,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX10-UNALIGNED-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX11-LABEL: name: test_load_local_s24_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -1520,7 +1395,6 @@ body: |
; GFX11-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; GFX11-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; GFX11-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s24_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -1551,63 +1425,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; CI-LABEL: name: test_load_local_s48_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; CI-DS128-LABEL: name: test_load_local_s48_align8
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; VI-LABEL: name: test_load_local_s48_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX9-LABEL: name: test_load_local_s48_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s48_align8
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX10-LABEL: name: test_load_local_s48_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s48_align8
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX11-LABEL: name: test_load_local_s48_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s48_align8
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -1632,63 +1497,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; CI-LABEL: name: test_load_local_s64_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; CI-DS128-LABEL: name: test_load_local_s64_align8
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; VI-LABEL: name: test_load_local_s64_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX9-LABEL: name: test_load_local_s64_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s64_align8
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX10-LABEL: name: test_load_local_s64_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s64_align8
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX11-LABEL: name: test_load_local_s64_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s64_align8
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -1712,63 +1568,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), align 4, addrspace 3)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; CI-LABEL: name: test_load_local_s64_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), align 4, addrspace 3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; CI-DS128-LABEL: name: test_load_local_s64_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), align 4, addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; VI-LABEL: name: test_load_local_s64_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), align 4, addrspace 3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX9-LABEL: name: test_load_local_s64_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), align 4, addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s64_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX10-LABEL: name: test_load_local_s64_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), align 4, addrspace 3)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s64_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), align 4, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX11-LABEL: name: test_load_local_s64_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), align 4, addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s64_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -1810,7 +1657,6 @@ body: |
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C3]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR2]](s64)
- ;
; CI-LABEL: name: test_load_local_s64_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -1835,7 +1681,6 @@ body: |
; CI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C3]](s32)
; CI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; CI-NEXT: $vgpr0_vgpr1 = COPY [[OR2]](s64)
- ;
; CI-DS128-LABEL: name: test_load_local_s64_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -1860,7 +1705,6 @@ body: |
; CI-DS128-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C3]](s32)
; CI-DS128-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[OR2]](s64)
- ;
; VI-LABEL: name: test_load_local_s64_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -1885,7 +1729,6 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C3]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR2]](s64)
- ;
; GFX9-LABEL: name: test_load_local_s64_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -1910,14 +1753,12 @@ body: |
; GFX9-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C3]](s32)
; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR2]](s64)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s64_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), align 2, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX10-LABEL: name: test_load_local_s64_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -1942,7 +1783,6 @@ body: |
; GFX10-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C3]](s32)
; GFX10-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[OR2]](s64)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s64_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -1957,7 +1797,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C1]](s32)
; GFX10-UNALIGNED-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXT]]
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
- ;
; GFX11-LABEL: name: test_load_local_s64_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -1982,7 +1821,6 @@ body: |
; GFX11-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C3]](s32)
; GFX11-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[OR2]](s64)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s64_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -2042,7 +1880,6 @@ body: |
; SI-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C5]](s32)
; SI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[OR6]](s64)
- ;
; CI-LABEL: name: test_load_local_s64_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -2085,7 +1922,6 @@ body: |
; CI-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C5]](s32)
; CI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; CI-NEXT: $vgpr0_vgpr1 = COPY [[OR6]](s64)
- ;
; CI-DS128-LABEL: name: test_load_local_s64_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -2128,7 +1964,6 @@ body: |
; CI-DS128-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C5]](s32)
; CI-DS128-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[OR6]](s64)
- ;
; VI-LABEL: name: test_load_local_s64_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -2171,7 +2006,6 @@ body: |
; VI-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C5]](s32)
; VI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[OR6]](s64)
- ;
; GFX9-LABEL: name: test_load_local_s64_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -2214,14 +2048,12 @@ body: |
; GFX9-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C5]](s32)
; GFX9-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[OR6]](s64)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s64_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
- ;
; GFX10-LABEL: name: test_load_local_s64_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -2264,7 +2096,6 @@ body: |
; GFX10-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C5]](s32)
; GFX10-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[OR6]](s64)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s64_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -2279,7 +2110,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C1]](s32)
; GFX10-UNALIGNED-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXT]]
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[OR]](s64)
- ;
; GFX11-LABEL: name: test_load_local_s64_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -2322,7 +2152,6 @@ body: |
; GFX11-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C5]](s32)
; GFX11-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[OR6]](s64)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s64_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -2393,7 +2222,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-LABEL: name: test_load_local_s96_align16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -2447,7 +2275,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-DS128-LABEL: name: test_load_local_s96_align16
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -2501,7 +2328,6 @@ body: |
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; CI-DS128-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_local_s96_align16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -2555,7 +2381,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_local_s96_align16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -2609,7 +2434,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s96_align16
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -2617,7 +2441,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s32>), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX10-LABEL: name: test_load_local_s96_align16
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -2671,7 +2494,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s96_align16
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -2686,7 +2508,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX10-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX11-LABEL: name: test_load_local_s96_align16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -2740,7 +2561,6 @@ body: |
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s96_align16
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -2771,7 +2591,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-LABEL: name: test_load_local_s96_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -2784,7 +2603,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-DS128-LABEL: name: test_load_local_s96_align8
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -2799,7 +2617,6 @@ body: |
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; CI-DS128-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_local_s96_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -2814,7 +2631,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_local_s96_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -2829,7 +2645,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s96_align8
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -2837,7 +2652,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s32>), align 8, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX10-LABEL: name: test_load_local_s96_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -2852,7 +2666,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s96_align8
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -2867,7 +2680,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX10-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX11-LABEL: name: test_load_local_s96_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -2882,7 +2694,6 @@ body: |
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s96_align8
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -2913,7 +2724,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-LABEL: name: test_load_local_s96_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -2926,7 +2736,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-DS128-LABEL: name: test_load_local_s96_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -2941,7 +2750,6 @@ body: |
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; CI-DS128-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_local_s96_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -2956,7 +2764,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_local_s96_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -2971,7 +2778,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s96_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -2979,7 +2785,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s32>), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX10-LABEL: name: test_load_local_s96_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -2994,7 +2799,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s96_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -3009,7 +2813,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX10-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX11-LABEL: name: test_load_local_s96_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -3024,7 +2827,6 @@ body: |
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s96_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -3071,7 +2873,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-LABEL: name: test_load_local_s96_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -3100,7 +2901,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-DS128-LABEL: name: test_load_local_s96_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -3129,7 +2929,6 @@ body: |
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; CI-DS128-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_local_s96_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -3158,7 +2957,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_local_s96_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -3187,7 +2985,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s96_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -3195,7 +2992,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s32>), align 2, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX10-LABEL: name: test_load_local_s96_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -3224,7 +3020,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s96_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -3239,7 +3034,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX10-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX11-LABEL: name: test_load_local_s96_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -3268,7 +3062,6 @@ body: |
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s96_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -3340,7 +3133,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-LABEL: name: test_load_local_s96_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -3394,7 +3186,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-DS128-LABEL: name: test_load_local_s96_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -3448,7 +3239,6 @@ body: |
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; CI-DS128-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_local_s96_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -3502,7 +3292,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_local_s96_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -3556,7 +3345,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s96_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -3564,7 +3352,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s32>), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX10-LABEL: name: test_load_local_s96_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -3618,7 +3405,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s96_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -3633,7 +3419,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX10-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX11-LABEL: name: test_load_local_s96_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -3687,7 +3472,6 @@ body: |
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s96_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -3775,7 +3559,6 @@ body: |
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s32>), [[BUILD_VECTOR1]](<2 x s32>)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[CONCAT_VECTORS]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-LABEL: name: test_load_local_s128_align16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -3845,7 +3628,6 @@ body: |
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s32>), [[BUILD_VECTOR1]](<2 x s32>)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[CONCAT_VECTORS]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-DS128-LABEL: name: test_load_local_s128_align16
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -3914,7 +3696,6 @@ body: |
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-DS128-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_local_s128_align16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -3983,7 +3764,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_local_s128_align16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -4052,7 +3832,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s128_align16
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -4060,7 +3839,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX10-LABEL: name: test_load_local_s128_align16
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -4129,7 +3907,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s128_align16
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -4147,7 +3924,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX11-LABEL: name: test_load_local_s128_align16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -4216,7 +3992,6 @@ body: |
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s128_align16
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -4246,7 +4021,6 @@ body: |
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[CONCAT_VECTORS]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-LABEL: name: test_load_local_s128_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -4258,7 +4032,6 @@ body: |
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[CONCAT_VECTORS]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-DS128-LABEL: name: test_load_local_s128_align8
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -4266,7 +4039,6 @@ body: |
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 8, addrspace 3)
; CI-DS128-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_local_s128_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -4274,7 +4046,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 8, addrspace 3)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_local_s128_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -4282,7 +4053,6 @@ body: |
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 8, addrspace 3)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s128_align8
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -4290,7 +4060,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 8, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX10-LABEL: name: test_load_local_s128_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -4308,7 +4077,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s128_align8
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -4326,7 +4094,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX11-LABEL: name: test_load_local_s128_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -4334,7 +4101,6 @@ body: |
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 8, addrspace 3)
; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s128_align8
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -4364,7 +4130,6 @@ body: |
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[CONCAT_VECTORS]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-LABEL: name: test_load_local_s128_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -4376,7 +4141,6 @@ body: |
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[CONCAT_VECTORS]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-DS128-LABEL: name: test_load_local_s128_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -4394,7 +4158,6 @@ body: |
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-DS128-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_local_s128_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -4412,7 +4175,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_local_s128_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -4430,7 +4192,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s128_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -4438,7 +4199,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX10-LABEL: name: test_load_local_s128_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -4456,7 +4216,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s128_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -4474,7 +4233,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX11-LABEL: name: test_load_local_s128_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -4492,7 +4250,6 @@ body: |
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s128_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -4547,7 +4304,6 @@ body: |
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s32>), [[BUILD_VECTOR1]](<2 x s32>)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[CONCAT_VECTORS]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-LABEL: name: test_load_local_s128_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -4584,7 +4340,6 @@ body: |
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s32>), [[BUILD_VECTOR1]](<2 x s32>)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[CONCAT_VECTORS]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-DS128-LABEL: name: test_load_local_s128_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -4620,7 +4375,6 @@ body: |
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; CI-DS128-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_local_s128_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -4656,7 +4410,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_local_s128_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -4692,7 +4445,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s128_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -4700,7 +4452,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 2, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX10-LABEL: name: test_load_local_s128_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -4736,7 +4487,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s128_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -4754,7 +4504,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX11-LABEL: name: test_load_local_s128_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -4790,7 +4539,6 @@ body: |
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s128_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -4878,7 +4626,6 @@ body: |
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s32>), [[BUILD_VECTOR1]](<2 x s32>)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[CONCAT_VECTORS]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-LABEL: name: test_load_local_s128_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -4948,7 +4695,6 @@ body: |
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s32>), [[BUILD_VECTOR1]](<2 x s32>)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[CONCAT_VECTORS]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-DS128-LABEL: name: test_load_local_s128_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -5017,7 +4763,6 @@ body: |
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-DS128-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_local_s128_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -5086,7 +4831,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_local_s128_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -5155,7 +4899,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_s128_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -5163,7 +4906,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX10-LABEL: name: test_load_local_s128_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -5232,7 +4974,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_s128_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -5250,7 +4991,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX11-LABEL: name: test_load_local_s128_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -5319,7 +5059,6 @@ body: |
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_s128_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -5344,63 +5083,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), addrspace 3)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; CI-LABEL: name: test_load_local_p1_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), addrspace 3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; CI-DS128-LABEL: name: test_load_local_p1_align8
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; VI-LABEL: name: test_load_local_p1_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), addrspace 3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX9-LABEL: name: test_load_local_p1_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_p1_align8
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX10-LABEL: name: test_load_local_p1_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), addrspace 3)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_p1_align8
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX11-LABEL: name: test_load_local_p1_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_p1_align8
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -5433,42 +5163,36 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXT]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR]](s64)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; CI-LABEL: name: test_load_local_p1_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), align 4, addrspace 3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; CI-DS128-LABEL: name: test_load_local_p1_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), align 4, addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; VI-LABEL: name: test_load_local_p1_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), align 4, addrspace 3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX9-LABEL: name: test_load_local_p1_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), align 4, addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_p1_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX10-LABEL: name: test_load_local_p1_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -5484,7 +5208,6 @@ body: |
; GFX10-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXT]]
; GFX10-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR]](s64)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_p1_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -5500,14 +5223,12 @@ body: |
; GFX10-UNALIGNED-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXT]]
; GFX10-UNALIGNED-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR]](s64)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; GFX11-LABEL: name: test_load_local_p1_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), align 4, addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_p1_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -5550,7 +5271,6 @@ body: |
; SI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR2]](s64)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; CI-LABEL: name: test_load_local_p1_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -5576,7 +5296,6 @@ body: |
; CI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR2]](s64)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; CI-DS128-LABEL: name: test_load_local_p1_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -5602,7 +5321,6 @@ body: |
; CI-DS128-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; CI-DS128-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR2]](s64)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; VI-LABEL: name: test_load_local_p1_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -5628,7 +5346,6 @@ body: |
; VI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR2]](s64)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; GFX9-LABEL: name: test_load_local_p1_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -5654,14 +5371,12 @@ body: |
; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; GFX9-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR2]](s64)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_p1_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), align 2, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX10-LABEL: name: test_load_local_p1_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -5687,7 +5402,6 @@ body: |
; GFX10-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; GFX10-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR2]](s64)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_p1_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -5703,7 +5417,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXT]]
; GFX10-UNALIGNED-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR]](s64)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; GFX11-LABEL: name: test_load_local_p1_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -5729,7 +5442,6 @@ body: |
; GFX11-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]]
; GFX11-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR2]](s64)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_p1_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -5790,7 +5502,6 @@ body: |
; SI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR6]](s64)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; CI-LABEL: name: test_load_local_p1_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -5834,7 +5545,6 @@ body: |
; CI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR6]](s64)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; CI-DS128-LABEL: name: test_load_local_p1_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -5878,7 +5588,6 @@ body: |
; CI-DS128-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; CI-DS128-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR6]](s64)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; VI-LABEL: name: test_load_local_p1_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -5922,7 +5631,6 @@ body: |
; VI-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR6]](s64)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; GFX9-LABEL: name: test_load_local_p1_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -5966,14 +5674,12 @@ body: |
; GFX9-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; GFX9-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR6]](s64)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_p1_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load (p1), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
- ;
; GFX10-LABEL: name: test_load_local_p1_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -6017,7 +5723,6 @@ body: |
; GFX10-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; GFX10-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR6]](s64)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_p1_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -6033,7 +5738,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXT]]
; GFX10-UNALIGNED-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR]](s64)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; GFX11-LABEL: name: test_load_local_p1_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -6077,7 +5781,6 @@ body: |
; GFX11-NEXT: [[OR6:%[0-9]+]]:_(s64) = G_OR [[SHL6]], [[ZEXT]]
; GFX11-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[OR6]](s64)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[INTTOPTR]](p1)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_p1_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -6101,63 +5804,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; CI-LABEL: name: test_load_local_p3_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; CI-DS128-LABEL: name: test_load_local_p3_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
; CI-DS128-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; VI-LABEL: name: test_load_local_p3_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX9-LABEL: name: test_load_local_p3_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_p3_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX10-LABEL: name: test_load_local_p3_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_p3_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX11-LABEL: name: test_load_local_p3_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), addrspace 3)
; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_p3_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -6188,7 +5882,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; CI-LABEL: name: test_load_local_p3_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -6202,7 +5895,6 @@ body: |
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR]](s32)
; CI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; CI-DS128-LABEL: name: test_load_local_p3_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -6216,7 +5908,6 @@ body: |
; CI-DS128-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-DS128-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR]](s32)
; CI-DS128-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; VI-LABEL: name: test_load_local_p3_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -6230,7 +5921,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; GFX9-LABEL: name: test_load_local_p3_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -6244,14 +5934,12 @@ body: |
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_p3_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), align 2, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX10-LABEL: name: test_load_local_p3_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -6265,14 +5953,12 @@ body: |
; GFX10-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX10-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR]](s32)
; GFX10-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_p3_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), align 2, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX11-LABEL: name: test_load_local_p3_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -6286,7 +5972,6 @@ body: |
; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX11-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR]](s32)
; GFX11-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_p3_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -6327,7 +6012,6 @@ body: |
; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR2]](s32)
; SI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; CI-LABEL: name: test_load_local_p3_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -6351,7 +6035,6 @@ body: |
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR2]](s32)
; CI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; CI-DS128-LABEL: name: test_load_local_p3_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -6375,7 +6058,6 @@ body: |
; CI-DS128-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-DS128-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR2]](s32)
; CI-DS128-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; VI-LABEL: name: test_load_local_p3_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -6399,7 +6081,6 @@ body: |
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR2]](s32)
; VI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; GFX9-LABEL: name: test_load_local_p3_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -6423,14 +6104,12 @@ body: |
; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; GFX9-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR2]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_p3_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX10-LABEL: name: test_load_local_p3_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -6454,14 +6133,12 @@ body: |
; GFX10-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; GFX10-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR2]](s32)
; GFX10-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_p3_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p3) :: (load (p3), align 1, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX11-LABEL: name: test_load_local_p3_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -6485,7 +6162,6 @@ body: |
; GFX11-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; GFX11-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR2]](s32)
; GFX11-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_p3_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -6509,63 +6185,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p3) :: (load (p5), addrspace 3)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; CI-LABEL: name: test_load_local_p5_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p3) :: (load (p5), addrspace 3)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; CI-DS128-LABEL: name: test_load_local_p5_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p3) :: (load (p5), addrspace 3)
; CI-DS128-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; VI-LABEL: name: test_load_local_p5_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p3) :: (load (p5), addrspace 3)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX9-LABEL: name: test_load_local_p5_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p3) :: (load (p5), addrspace 3)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_p5_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p3) :: (load (p5), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX10-LABEL: name: test_load_local_p5_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p3) :: (load (p5), addrspace 3)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_p5_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p3) :: (load (p5), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX11-LABEL: name: test_load_local_p5_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p3) :: (load (p5), addrspace 3)
; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_p5_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -6596,7 +6263,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; CI-LABEL: name: test_load_local_p5_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -6610,7 +6276,6 @@ body: |
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; CI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; CI-DS128-LABEL: name: test_load_local_p5_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -6624,7 +6289,6 @@ body: |
; CI-DS128-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-DS128-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; CI-DS128-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; VI-LABEL: name: test_load_local_p5_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -6638,7 +6302,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX9-LABEL: name: test_load_local_p5_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -6652,14 +6315,12 @@ body: |
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_p5_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p3) :: (load (p5), align 2, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX10-LABEL: name: test_load_local_p5_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -6673,14 +6334,12 @@ body: |
; GFX10-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX10-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; GFX10-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_p5_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p3) :: (load (p5), align 2, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX11-LABEL: name: test_load_local_p5_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -6694,7 +6353,6 @@ body: |
; GFX11-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX11-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; GFX11-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_p5_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -6735,7 +6393,6 @@ body: |
; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; SI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; CI-LABEL: name: test_load_local_p5_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -6759,7 +6416,6 @@ body: |
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; CI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; CI-DS128-LABEL: name: test_load_local_p5_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -6783,7 +6439,6 @@ body: |
; CI-DS128-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-DS128-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; CI-DS128-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; VI-LABEL: name: test_load_local_p5_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -6807,7 +6462,6 @@ body: |
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; VI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX9-LABEL: name: test_load_local_p5_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -6831,14 +6485,12 @@ body: |
; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; GFX9-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_p5_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p3) :: (load (p5), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX10-LABEL: name: test_load_local_p5_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -6862,14 +6514,12 @@ body: |
; GFX10-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; GFX10-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; GFX10-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_p5_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p3) :: (load (p5), align 1, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX11-LABEL: name: test_load_local_p5_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -6893,7 +6543,6 @@ body: |
; GFX11-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; GFX11-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; GFX11-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_p5_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -6917,63 +6566,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_local_v2s8_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_v2s8_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; CI-DS128-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_local_v2s8_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_local_v2s8_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s8_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_local_v2s8_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s8_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_local_v2s8_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2s8_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -7007,7 +6647,6 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[LSHR]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; CI-LABEL: name: test_load_local_v2s8_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -7022,7 +6661,6 @@ body: |
; CI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[LSHR]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v2s8_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -7037,7 +6675,6 @@ body: |
; CI-DS128-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[LSHR]](s32)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_local_v2s8_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -7052,7 +6689,6 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[LSHR]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v2s8_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -7067,7 +6703,6 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[LSHR]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s8_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -7077,7 +6712,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
; GFX9-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v2s8_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -7092,7 +6726,6 @@ body: |
; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[LSHR]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s8_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -7102,7 +6735,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v2s8_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -7117,7 +6749,6 @@ body: |
; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[LSHR]](s32)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2s8_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -7149,8 +6780,8 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; SI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; SI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -7170,7 +6801,6 @@ body: |
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; SI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; CI-LABEL: name: test_load_local_v3s8_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -7181,8 +6811,8 @@ body: |
; CI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; CI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; CI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -7202,7 +6832,6 @@ body: |
; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; CI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_v3s8_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -7213,8 +6842,8 @@ body: |
; CI-DS128-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CI-DS128-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CI-DS128-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; CI-DS128-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CI-DS128-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; CI-DS128-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; CI-DS128-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-DS128-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -7234,7 +6863,6 @@ body: |
; CI-DS128-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI-DS128-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; CI-DS128-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; VI-LABEL: name: test_load_local_v3s8_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -7245,8 +6873,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; VI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -7264,7 +6892,6 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; VI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-LABEL: name: test_load_local_v3s8_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -7275,8 +6902,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -7294,7 +6921,6 @@ body: |
; GFX9-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; GFX9-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v3s8_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -7305,8 +6931,8 @@ body: |
; GFX9-UNALIGNED-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-UNALIGNED-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX9-UNALIGNED-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9-UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX9-UNALIGNED-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX9-UNALIGNED-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX9-UNALIGNED-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-UNALIGNED-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -7324,7 +6950,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX9-UNALIGNED-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX10-LABEL: name: test_load_local_v3s8_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -7335,8 +6960,8 @@ body: |
; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX10-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -7354,7 +6979,6 @@ body: |
; GFX10-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX10-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; GFX10-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v3s8_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -7365,8 +6989,8 @@ body: |
; GFX10-UNALIGNED-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX10-UNALIGNED-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10-UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX10-UNALIGNED-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX10-UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX10-UNALIGNED-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX10-UNALIGNED-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX10-UNALIGNED-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -7384,7 +7008,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX10-UNALIGNED-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX11-LABEL: name: test_load_local_v3s8_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -7395,8 +7018,8 @@ body: |
; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX11-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX11-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX11-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -7414,7 +7037,6 @@ body: |
; GFX11-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX11-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; GFX11-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v3s8_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -7425,8 +7047,8 @@ body: |
; GFX11-UNALIGNED-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX11-UNALIGNED-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX11-UNALIGNED-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX11-UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX11-UNALIGNED-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX11-UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX11-UNALIGNED-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX11-UNALIGNED-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX11-UNALIGNED-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -7477,8 +7099,8 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; SI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; SI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -7498,7 +7120,6 @@ body: |
; SI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; SI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; SI-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; CI-LABEL: name: test_load_local_v3s8_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -7519,8 +7140,8 @@ body: |
; CI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; CI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; CI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; CI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; CI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -7540,7 +7161,6 @@ body: |
; CI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; CI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; CI-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_v3s8_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -7561,8 +7181,8 @@ body: |
; CI-DS128-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; CI-DS128-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; CI-DS128-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CI-DS128-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; CI-DS128-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CI-DS128-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; CI-DS128-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; CI-DS128-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CI-DS128-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -7582,7 +7202,6 @@ body: |
; CI-DS128-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; CI-DS128-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; CI-DS128-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; VI-LABEL: name: test_load_local_v3s8_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -7603,8 +7222,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; VI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
@@ -7622,7 +7241,6 @@ body: |
; VI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; VI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; VI-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; GFX9-LABEL: name: test_load_local_v3s8_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -7643,8 +7261,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX9-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
@@ -7662,7 +7280,6 @@ body: |
; GFX9-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; GFX9-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; GFX9-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v3s8_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -7678,8 +7295,8 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C2]](s32)
; GFX9-UNALIGNED-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; GFX9-UNALIGNED-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9-UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
; GFX9-UNALIGNED-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
; GFX9-UNALIGNED-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; GFX9-UNALIGNED-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-UNALIGNED-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
@@ -7697,7 +7314,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX9-UNALIGNED-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL3]]
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[OR3]](s32)
- ;
; GFX10-LABEL: name: test_load_local_v3s8_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -7718,8 +7334,8 @@ body: |
; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; GFX10-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX10-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX10-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
@@ -7737,7 +7353,6 @@ body: |
; GFX10-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; GFX10-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; GFX10-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v3s8_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -7753,8 +7368,8 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C2]](s32)
; GFX10-UNALIGNED-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; GFX10-UNALIGNED-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10-UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
; GFX10-UNALIGNED-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX10-UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
; GFX10-UNALIGNED-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; GFX10-UNALIGNED-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX10-UNALIGNED-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
@@ -7772,7 +7387,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX10-UNALIGNED-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL3]]
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[OR3]](s32)
- ;
; GFX11-LABEL: name: test_load_local_v3s8_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -7793,8 +7407,8 @@ body: |
; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX11-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX11-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX11-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
@@ -7812,7 +7426,6 @@ body: |
; GFX11-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; GFX11-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; GFX11-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v3s8_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -7828,8 +7441,8 @@ body: |
; GFX11-UNALIGNED-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C2]](s32)
; GFX11-UNALIGNED-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; GFX11-UNALIGNED-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX11-UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
; GFX11-UNALIGNED-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX11-UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
; GFX11-UNALIGNED-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; GFX11-UNALIGNED-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX11-UNALIGNED-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
@@ -7866,63 +7479,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_local_v4s8_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-DS128-LABEL: name: test_load_local_v4s8_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; CI-DS128-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_local_v4s8_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_local_v4s8_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v4s8_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_local_v4s8_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v4s8_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_local_v4s8_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v4s8_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -7947,63 +7551,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-LABEL: name: test_load_local_v8s8_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v8s8_align8
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_local_v8s8_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v8s8_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v8s8_align8
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v8s8_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v8s8_align8
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v8s8_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v8s8_align8
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -8088,7 +7683,6 @@ body: |
; SI-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; CI-LABEL: name: test_load_local_v16s8_align16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -8155,7 +7749,6 @@ body: |
; CI-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v16s8_align16
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -8223,7 +7816,6 @@ body: |
; CI-DS128-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_local_v16s8_align16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -8291,7 +7883,6 @@ body: |
; VI-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v16s8_align16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -8359,14 +7950,12 @@ body: |
; GFX9-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v16s8_align16
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v16s8_align16
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -8434,7 +8023,6 @@ body: |
; GFX10-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v16s8_align16
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -8451,7 +8039,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s32) from unknown-address + 12, align 1, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v16s8_align16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -8519,7 +8106,6 @@ body: |
; GFX11-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v16s8_align16
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -8544,63 +8130,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; CI-LABEL: name: test_load_local_v2s16_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; CI-DS128-LABEL: name: test_load_local_v2s16_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; CI-DS128-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_local_v2s16_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_load_local_v2s16_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s16_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX10-LABEL: name: test_load_local_v2s16_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s16_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX11-LABEL: name: test_load_local_v2s16_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2s16_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -8634,7 +8211,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; CI-LABEL: name: test_load_local_v2s16_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -8651,7 +8227,6 @@ body: |
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; CI-DS128-LABEL: name: test_load_local_v2s16_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -8668,7 +8243,6 @@ body: |
; CI-DS128-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-DS128-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CI-DS128-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_local_v2s16_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -8685,7 +8259,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_load_local_v2s16_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -8698,14 +8271,12 @@ body: |
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD1]](s32)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s16_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 2, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX10-LABEL: name: test_load_local_v2s16_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -8718,14 +8289,12 @@ body: |
; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD1]](s32)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX10-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s16_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 2, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX11-LABEL: name: test_load_local_v2s16_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -8738,7 +8307,6 @@ body: |
; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD1]](s32)
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX11-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2s16_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -8782,7 +8350,6 @@ body: |
; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; CI-LABEL: name: test_load_local_v2s16_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -8809,7 +8376,6 @@ body: |
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; CI-DS128-LABEL: name: test_load_local_v2s16_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -8836,7 +8402,6 @@ body: |
; CI-DS128-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; CI-DS128-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-DS128-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_local_v2s16_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -8863,7 +8428,6 @@ body: |
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_load_local_v2s16_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -8886,14 +8450,12 @@ body: |
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s16_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX10-LABEL: name: test_load_local_v2s16_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -8916,14 +8478,12 @@ body: |
; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX10-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s16_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 1, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX11-LABEL: name: test_load_local_v2s16_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -8946,7 +8506,6 @@ body: |
; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX11-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2s16_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -8983,13 +8542,13 @@ body: |
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-LABEL: name: test_load_local_v3s16_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -9009,13 +8568,13 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; CI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-DS128-LABEL: name: test_load_local_v3s16_align8
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -9035,13 +8594,13 @@ body: |
; CI-DS128-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-DS128-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-DS128-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-DS128-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; CI-DS128-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; CI-DS128-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; CI-DS128-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CI-DS128-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; CI-DS128-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CI-DS128-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-DS128-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CI-DS128-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_local_v3s16_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -9061,13 +8620,13 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_load_local_v3s16_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -9089,7 +8648,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v3s16_align8
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -9111,7 +8669,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX9-UNALIGNED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX10-LABEL: name: test_load_local_v3s16_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -9133,7 +8690,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v3s16_align8
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -9155,7 +8711,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX10-UNALIGNED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX11-LABEL: name: test_load_local_v3s16_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -9177,7 +8732,6 @@ body: |
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV]](<2 x s16>), [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v3s16_align8
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -9240,13 +8794,13 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-LABEL: name: test_load_local_v3s16_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -9275,13 +8829,13 @@ body: |
; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-DS128-LABEL: name: test_load_local_v3s16_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -9310,13 +8864,13 @@ body: |
; CI-DS128-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-DS128-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-DS128-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-DS128-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; CI-DS128-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; CI-DS128-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; CI-DS128-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-DS128-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; CI-DS128-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; CI-DS128-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-DS128-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-DS128-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_local_v3s16_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -9345,13 +8899,13 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_load_local_v3s16_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -9380,7 +8934,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v3s16_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -9409,7 +8962,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX9-UNALIGNED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX10-LABEL: name: test_load_local_v3s16_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -9438,7 +8990,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v3s16_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -9467,7 +9018,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX10-UNALIGNED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX11-LABEL: name: test_load_local_v3s16_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -9496,7 +9046,6 @@ body: |
; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v3s16_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -9580,13 +9129,13 @@ body: |
; SI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; SI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
- ; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
- ; SI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL5]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
+ ; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
+ ; SI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL5]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-LABEL: name: test_load_local_v3s16_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -9629,13 +9178,13 @@ body: |
; CI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; CI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
- ; CI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
- ; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL5]]
+ ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; CI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
+ ; CI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
+ ; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL5]]
; CI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-DS128-LABEL: name: test_load_local_v3s16_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -9678,13 +9227,13 @@ body: |
; CI-DS128-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-DS128-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; CI-DS128-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CI-DS128-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
- ; CI-DS128-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
- ; CI-DS128-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL5]]
+ ; CI-DS128-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; CI-DS128-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
+ ; CI-DS128-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
+ ; CI-DS128-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL5]]
; CI-DS128-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; CI-DS128-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_local_v3s16_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -9727,13 +9276,13 @@ body: |
; VI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
- ; VI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
- ; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL5]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
+ ; VI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
+ ; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL5]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_load_local_v3s16_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -9776,7 +9325,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v3s16_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -9805,7 +9353,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX9-UNALIGNED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX10-LABEL: name: test_load_local_v3s16_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -9848,7 +9395,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v3s16_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -9877,7 +9423,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX10-UNALIGNED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX11-LABEL: name: test_load_local_v3s16_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -9920,7 +9465,6 @@ body: |
; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v3s16_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -9967,63 +9511,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), addrspace 3)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; CI-LABEL: name: test_load_local_v4s16_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), addrspace 3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; CI-DS128-LABEL: name: test_load_local_v4s16_align8
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_local_v4s16_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), addrspace 3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_local_v4s16_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v4s16_align8
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX10-LABEL: name: test_load_local_v4s16_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), addrspace 3)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v4s16_align8
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX11-LABEL: name: test_load_local_v4s16_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v4s16_align8
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -10069,42 +9604,36 @@ body: |
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; CI-LABEL: name: test_load_local_v4s16_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 4, addrspace 3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; CI-DS128-LABEL: name: test_load_local_v4s16_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 4, addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_local_v4s16_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 4, addrspace 3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_local_v4s16_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 4, addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v4s16_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX10-LABEL: name: test_load_local_v4s16_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -10127,7 +9656,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v4s16_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -10150,14 +9678,12 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX10-UNALIGNED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX11-LABEL: name: test_load_local_v4s16_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 4, addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v4s16_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -10202,7 +9728,6 @@ body: |
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; CI-LABEL: name: test_load_local_v4s16_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -10231,7 +9756,6 @@ body: |
; CI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; CI-DS128-LABEL: name: test_load_local_v4s16_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -10260,7 +9784,6 @@ body: |
; CI-DS128-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CI-DS128-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_local_v4s16_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -10289,7 +9812,6 @@ body: |
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_local_v4s16_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -10312,14 +9834,12 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v4s16_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 2, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX10-LABEL: name: test_load_local_v4s16_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -10342,7 +9862,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v4s16_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -10365,7 +9884,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX10-UNALIGNED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX11-LABEL: name: test_load_local_v4s16_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -10388,7 +9906,6 @@ body: |
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v4s16_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -10452,7 +9969,6 @@ body: |
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; CI-LABEL: name: test_load_local_v4s16_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -10499,7 +10015,6 @@ body: |
; CI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; CI-DS128-LABEL: name: test_load_local_v4s16_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -10546,7 +10061,6 @@ body: |
; CI-DS128-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; CI-DS128-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_local_v4s16_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -10593,7 +10107,6 @@ body: |
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_local_v4s16_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -10634,14 +10147,12 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v4s16_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<4 x s16>)
- ;
; GFX10-LABEL: name: test_load_local_v4s16_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -10682,7 +10193,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v4s16_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -10705,7 +10215,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX10-UNALIGNED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX11-LABEL: name: test_load_local_v4s16_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -10746,7 +10255,6 @@ body: |
; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v4s16_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -10770,63 +10278,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-LABEL: name: test_load_local_v2s32_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v2s32_align8
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_local_v2s32_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v2s32_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s32_align8
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v2s32_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s32_align8
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v2s32_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2s32_align8
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -10850,63 +10349,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), align 4, addrspace 3)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-LABEL: name: test_load_local_v2s32_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), align 4, addrspace 3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v2s32_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), align 4, addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_local_v2s32_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), align 4, addrspace 3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v2s32_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), align 4, addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s32_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v2s32_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), align 4, addrspace 3)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s32_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), align 4, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v2s32_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), align 4, addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2s32_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -10944,7 +10434,6 @@ body: |
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; CI-LABEL: name: test_load_local_v2s32_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -10965,7 +10454,6 @@ body: |
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v2s32_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -10986,7 +10474,6 @@ body: |
; CI-DS128-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_local_v2s32_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -11007,7 +10494,6 @@ body: |
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v2s32_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -11028,14 +10514,12 @@ body: |
; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s32_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), align 2, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v2s32_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -11056,7 +10540,6 @@ body: |
; GFX10-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s32_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -11067,7 +10550,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s32) from unknown-address + 4, align 2, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v2s32_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -11088,7 +10570,6 @@ body: |
; GFX11-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2s32_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -11144,7 +10625,6 @@ body: |
; SI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; CI-LABEL: name: test_load_local_v2s32_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -11183,7 +10663,6 @@ body: |
; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v2s32_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -11222,7 +10701,6 @@ body: |
; CI-DS128-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_local_v2s32_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -11261,7 +10739,6 @@ body: |
; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v2s32_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -11300,14 +10777,12 @@ body: |
; GFX9-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s32_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s32>), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v2s32_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -11346,7 +10821,6 @@ body: |
; GFX10-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s32_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -11357,7 +10831,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s32) from unknown-address + 4, align 1, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v2s32_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -11396,7 +10869,6 @@ body: |
; GFX11-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2s32_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -11466,7 +10938,6 @@ body: |
; SI-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[SHL8]], [[OR6]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; CI-LABEL: name: test_load_local_v3s32_align16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -11519,7 +10990,6 @@ body: |
; CI-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[SHL8]], [[OR6]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v3s32_align16
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -11572,7 +11042,6 @@ body: |
; CI-DS128-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[SHL8]], [[OR6]]
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_load_local_v3s32_align16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -11625,7 +11094,6 @@ body: |
; VI-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[SHL8]], [[OR6]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v3s32_align16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -11678,14 +11146,12 @@ body: |
; GFX9-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[SHL8]], [[OR6]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v3s32_align16
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s32>), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v3s32_align16
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -11738,7 +11204,6 @@ body: |
; GFX10-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[SHL8]], [[OR6]]
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v3s32_align16
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -11752,7 +11217,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s32) from unknown-address + 8, align 1, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v3s32_align16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -11805,7 +11269,6 @@ body: |
; GFX11-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[SHL8]], [[OR6]]
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v3s32_align16
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -11834,7 +11297,6 @@ body: |
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; CI-LABEL: name: test_load_local_v3s32_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -11846,7 +11308,6 @@ body: |
; CI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v3s32_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -11860,7 +11321,6 @@ body: |
; CI-DS128-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s32) from unknown-address + 8, addrspace 3)
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_load_local_v3s32_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -11874,7 +11334,6 @@ body: |
; VI-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s32) from unknown-address + 8, addrspace 3)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v3s32_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -11888,14 +11347,12 @@ body: |
; GFX9-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s32) from unknown-address + 8, addrspace 3)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v3s32_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s32>), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v3s32_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -11909,7 +11366,6 @@ body: |
; GFX10-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s32) from unknown-address + 8, addrspace 3)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v3s32_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -11923,7 +11379,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s32) from unknown-address + 8, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v3s32_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -11937,7 +11392,6 @@ body: |
; GFX11-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s32) from unknown-address + 8, addrspace 3)
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v3s32_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -11965,7 +11419,6 @@ body: |
; SI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load (<2 x s32>) from unknown-address + 8, addrspace 3)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x s32>)
- ;
; CI-LABEL: name: test_load_local_v4s32_align16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -11976,56 +11429,48 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load (<2 x s32>) from unknown-address + 8, addrspace 3)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v4s32_align16
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_local_v4s32_align16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), addrspace 3)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v4s32_align16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v4s32_align16
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v4s32_align16
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), addrspace 3)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v4s32_align16
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v4s32_align16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v4s32_align16
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -12053,7 +11498,6 @@ body: |
; SI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load (<2 x s32>) from unknown-address + 8, addrspace 3)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x s32>)
- ;
; CI-LABEL: name: test_load_local_v4s32_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -12064,35 +11508,30 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load (<2 x s32>) from unknown-address + 8, addrspace 3)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v4s32_align8
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 8, addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_local_v4s32_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 8, addrspace 3)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v4s32_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 8, addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v4s32_align8
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 8, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v4s32_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -12109,7 +11548,6 @@ body: |
; GFX10-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s32) from unknown-address + 12, addrspace 3)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v4s32_align8
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -12126,14 +11564,12 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s32) from unknown-address + 12, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v4s32_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 8, addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v4s32_align8
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -12161,7 +11597,6 @@ body: |
; SI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load (<2 x s32>) from unknown-address + 8, align 4, addrspace 3)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x s32>)
- ;
; CI-LABEL: name: test_load_local_v4s32_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -12172,7 +11607,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load (<2 x s32>) from unknown-address + 8, align 4, addrspace 3)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v4s32_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -12189,7 +11623,6 @@ body: |
; CI-DS128-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s32) from unknown-address + 12, addrspace 3)
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_local_v4s32_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -12206,7 +11639,6 @@ body: |
; VI-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s32) from unknown-address + 12, addrspace 3)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v4s32_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -12223,14 +11655,12 @@ body: |
; GFX9-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s32) from unknown-address + 12, addrspace 3)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v4s32_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v4s32_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -12247,7 +11677,6 @@ body: |
; GFX10-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s32) from unknown-address + 12, addrspace 3)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v4s32_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -12264,7 +11693,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s32) from unknown-address + 12, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v4s32_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -12281,7 +11709,6 @@ body: |
; GFX11-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s32) from unknown-address + 12, addrspace 3)
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v4s32_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -12334,7 +11761,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s32>), [[BUILD_VECTOR1]](<2 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x s32>)
- ;
; CI-LABEL: name: test_load_local_v4s32_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -12370,7 +11796,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s32>), [[BUILD_VECTOR1]](<2 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v4s32_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -12405,7 +11830,6 @@ body: |
; CI-DS128-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SHL3]], [[ZEXTLOAD3]]
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_local_v4s32_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -12440,7 +11864,6 @@ body: |
; VI-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SHL3]], [[ZEXTLOAD3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v4s32_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -12475,14 +11898,12 @@ body: |
; GFX9-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SHL3]], [[ZEXTLOAD3]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v4s32_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 2, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v4s32_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -12517,7 +11938,6 @@ body: |
; GFX10-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SHL3]], [[ZEXTLOAD3]]
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v4s32_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -12534,7 +11954,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s32) from unknown-address + 12, align 2, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v4s32_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -12569,7 +11988,6 @@ body: |
; GFX11-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SHL3]], [[ZEXTLOAD3]]
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v4s32_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -12655,7 +12073,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR8]](s32), [[OR11]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s32>), [[BUILD_VECTOR1]](<2 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x s32>)
- ;
; CI-LABEL: name: test_load_local_v4s32_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -12724,7 +12141,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR8]](s32), [[OR11]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s32>), [[BUILD_VECTOR1]](<2 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v4s32_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -12792,7 +12208,6 @@ body: |
; CI-DS128-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_local_v4s32_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -12860,7 +12275,6 @@ body: |
; VI-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v4s32_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -12928,14 +12342,12 @@ body: |
; GFX9-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v4s32_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v4s32_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -13003,7 +12415,6 @@ body: |
; GFX10-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v4s32_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -13020,7 +12431,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s32) from unknown-address + 12, align 1, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v4s32_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -13088,7 +12498,6 @@ body: |
; GFX11-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v4s32_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -13122,7 +12531,6 @@ body: |
; SI-NEXT: [[LOAD3:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD2]](p3) :: (load (<2 x s32>) from unknown-address + 24, addrspace 3)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>), [[LOAD2]](<2 x s32>), [[LOAD3]](<2 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<8 x s32>)
- ;
; CI-LABEL: name: test_load_local_v8s32_align32
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -13139,7 +12547,6 @@ body: |
; CI-NEXT: [[LOAD3:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD2]](p3) :: (load (<2 x s32>) from unknown-address + 24, addrspace 3)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>), [[LOAD2]](<2 x s32>), [[LOAD3]](<2 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<8 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v8s32_align32
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -13150,7 +12557,6 @@ body: |
; CI-DS128-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load (<4 x s32>) from unknown-address + 16, addrspace 3)
; CI-DS128-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<8 x s32>)
- ;
; VI-LABEL: name: test_load_local_v8s32_align32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -13161,7 +12567,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load (<4 x s32>) from unknown-address + 16, addrspace 3)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<8 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v8s32_align32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -13172,7 +12577,6 @@ body: |
; GFX9-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load (<4 x s32>) from unknown-address + 16, addrspace 3)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<8 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v8s32_align32
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -13183,7 +12587,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load (<4 x s32>) from unknown-address + 16, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<8 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v8s32_align32
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -13194,7 +12597,6 @@ body: |
; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load (<4 x s32>) from unknown-address + 16, addrspace 3)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<8 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v8s32_align32
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -13205,7 +12607,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load (<4 x s32>) from unknown-address + 16, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<8 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v8s32_align32
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -13216,7 +12617,6 @@ body: |
; GFX11-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load (<4 x s32>) from unknown-address + 16, addrspace 3)
; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<8 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v8s32_align32
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -13266,7 +12666,6 @@ body: |
; SI-NEXT: [[LOAD7:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD6]](p3) :: (load (<2 x s32>) from unknown-address + 56, addrspace 3)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>), [[LOAD2]](<2 x s32>), [[LOAD3]](<2 x s32>), [[LOAD4]](<2 x s32>), [[LOAD5]](<2 x s32>), [[LOAD6]](<2 x s32>), [[LOAD7]](<2 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[CONCAT_VECTORS]](<16 x s32>)
- ;
; CI-LABEL: name: test_load_local_v16s32_align32
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -13295,7 +12694,6 @@ body: |
; CI-NEXT: [[LOAD7:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD6]](p3) :: (load (<2 x s32>) from unknown-address + 56, addrspace 3)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>), [[LOAD2]](<2 x s32>), [[LOAD3]](<2 x s32>), [[LOAD4]](<2 x s32>), [[LOAD5]](<2 x s32>), [[LOAD6]](<2 x s32>), [[LOAD7]](<2 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[CONCAT_VECTORS]](<16 x s32>)
- ;
; CI-DS128-LABEL: name: test_load_local_v16s32_align32
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -13312,7 +12710,6 @@ body: |
; CI-DS128-NEXT: [[LOAD3:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD2]](p3) :: (load (<4 x s32>) from unknown-address + 48, addrspace 3)
; CI-DS128-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>), [[LOAD2]](<4 x s32>), [[LOAD3]](<4 x s32>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[CONCAT_VECTORS]](<16 x s32>)
- ;
; VI-LABEL: name: test_load_local_v16s32_align32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -13329,7 +12726,6 @@ body: |
; VI-NEXT: [[LOAD3:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD2]](p3) :: (load (<4 x s32>) from unknown-address + 48, addrspace 3)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>), [[LOAD2]](<4 x s32>), [[LOAD3]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[CONCAT_VECTORS]](<16 x s32>)
- ;
; GFX9-LABEL: name: test_load_local_v16s32_align32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -13346,7 +12742,6 @@ body: |
; GFX9-NEXT: [[LOAD3:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD2]](p3) :: (load (<4 x s32>) from unknown-address + 48, addrspace 3)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>), [[LOAD2]](<4 x s32>), [[LOAD3]](<4 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[CONCAT_VECTORS]](<16 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v16s32_align32
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -13363,7 +12758,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD3:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD2]](p3) :: (load (<4 x s32>) from unknown-address + 48, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>), [[LOAD2]](<4 x s32>), [[LOAD3]](<4 x s32>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[CONCAT_VECTORS]](<16 x s32>)
- ;
; GFX10-LABEL: name: test_load_local_v16s32_align32
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -13380,7 +12774,6 @@ body: |
; GFX10-NEXT: [[LOAD3:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD2]](p3) :: (load (<4 x s32>) from unknown-address + 48, addrspace 3)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>), [[LOAD2]](<4 x s32>), [[LOAD3]](<4 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[CONCAT_VECTORS]](<16 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v16s32_align32
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -13397,7 +12790,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD3:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD2]](p3) :: (load (<4 x s32>) from unknown-address + 48, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>), [[LOAD2]](<4 x s32>), [[LOAD3]](<4 x s32>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[CONCAT_VECTORS]](<16 x s32>)
- ;
; GFX11-LABEL: name: test_load_local_v16s32_align32
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -13414,7 +12806,6 @@ body: |
; GFX11-NEXT: [[LOAD3:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD2]](p3) :: (load (<4 x s32>) from unknown-address + 48, addrspace 3)
; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>), [[LOAD2]](<4 x s32>), [[LOAD3]](<4 x s32>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[CONCAT_VECTORS]](<16 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v16s32_align32
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -13452,7 +12843,6 @@ body: |
; SI-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p3) :: (load (s64) from unknown-address + 8, align 4, addrspace 3)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; CI-LABEL: name: test_load_local_v2s64_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -13463,7 +12853,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p3) :: (load (s64) from unknown-address + 8, align 4, addrspace 3)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; CI-DS128-LABEL: name: test_load_local_v2s64_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -13474,7 +12863,6 @@ body: |
; CI-DS128-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p3) :: (load (s64) from unknown-address + 8, align 4, addrspace 3)
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_local_v2s64_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -13485,7 +12873,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p3) :: (load (s64) from unknown-address + 8, align 4, addrspace 3)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_load_local_v2s64_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -13496,14 +12883,12 @@ body: |
; GFX9-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p3) :: (load (s64) from unknown-address + 8, align 4, addrspace 3)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s64_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p3) :: (load (<2 x s64>), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; GFX10-LABEL: name: test_load_local_v2s64_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -13514,7 +12899,6 @@ body: |
; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p3) :: (load (s64) from unknown-address + 8, align 4, addrspace 3)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s64_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -13525,7 +12909,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p3) :: (load (s64) from unknown-address + 8, align 4, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX11-LABEL: name: test_load_local_v2s64_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -13536,7 +12919,6 @@ body: |
; GFX11-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p3) :: (load (s64) from unknown-address + 8, align 4, addrspace 3)
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2s64_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -13630,7 +13012,6 @@ body: |
; SI-NEXT: [[OR13:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[ZEXT1]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; CI-LABEL: name: test_load_local_v2s64_align16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -13707,7 +13088,6 @@ body: |
; CI-NEXT: [[OR13:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[ZEXT1]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; CI-DS128-LABEL: name: test_load_local_v2s64_align16
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -13784,7 +13164,6 @@ body: |
; CI-DS128-NEXT: [[OR13:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[ZEXT1]]
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_local_v2s64_align16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -13861,7 +13240,6 @@ body: |
; VI-NEXT: [[OR13:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[ZEXT1]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_load_local_v2s64_align16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -13938,14 +13316,12 @@ body: |
; GFX9-NEXT: [[OR13:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[ZEXT1]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s64_align16
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p3) :: (load (<2 x s64>), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
- ;
; GFX10-LABEL: name: test_load_local_v2s64_align16
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -14022,7 +13398,6 @@ body: |
; GFX10-NEXT: [[OR13:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[ZEXT1]]
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s64_align16
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -14048,7 +13423,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[ZEXT1]]
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR]](s64), [[OR1]](s64)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX11-LABEL: name: test_load_local_v2s64_align16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -14125,7 +13499,6 @@ body: |
; GFX11-NEXT: [[OR13:%[0-9]+]]:_(s64) = G_OR [[SHL13]], [[ZEXT1]]
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[OR6]](s64), [[OR13]](s64)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2s64_align16
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -14158,7 +13531,6 @@ body: |
; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64), [[LOAD2]](s64), [[UV3]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; CI-LABEL: name: test_load_local_v3s64_align32
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -14174,7 +13546,6 @@ body: |
; CI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64), [[LOAD2]](s64), [[UV3]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; CI-DS128-LABEL: name: test_load_local_v3s64_align32
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -14188,7 +13559,6 @@ body: |
; CI-DS128-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_local_v3s64_align32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -14202,7 +13572,6 @@ body: |
; VI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_local_v3s64_align32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -14216,7 +13585,6 @@ body: |
; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v3s64_align32
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -14230,7 +13598,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; GFX9-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX10-LABEL: name: test_load_local_v3s64_align32
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -14244,7 +13611,6 @@ body: |
; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v3s64_align32
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -14258,7 +13624,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX11-LABEL: name: test_load_local_v3s64_align32
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -14272,7 +13637,6 @@ body: |
; GFX11-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[UV]](s64), [[UV1]](s64), [[LOAD1]](s64), [[UV5]](s64)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v3s64_align32
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -14315,7 +13679,6 @@ body: |
; SI-NEXT: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD2]](p3) :: (load (s64) from unknown-address + 24, addrspace 3)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64), [[LOAD2]](s64), [[LOAD3]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; CI-LABEL: name: test_load_local_v4s64_align32
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -14332,7 +13695,6 @@ body: |
; CI-NEXT: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD2]](p3) :: (load (s64) from unknown-address + 24, addrspace 3)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64), [[LOAD2]](s64), [[LOAD3]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; CI-DS128-LABEL: name: test_load_local_v4s64_align32
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -14343,7 +13705,6 @@ body: |
; CI-DS128-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p3) :: (load (<2 x s64>) from unknown-address + 16, addrspace 3)
; CI-DS128-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_local_v4s64_align32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -14354,7 +13715,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p3) :: (load (<2 x s64>) from unknown-address + 16, addrspace 3)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_local_v4s64_align32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -14365,7 +13725,6 @@ body: |
; GFX9-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p3) :: (load (<2 x s64>) from unknown-address + 16, addrspace 3)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<4 x s64>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v4s64_align32
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -14376,7 +13735,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p3) :: (load (<2 x s64>) from unknown-address + 16, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<4 x s64>)
- ;
; GFX10-LABEL: name: test_load_local_v4s64_align32
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -14387,7 +13745,6 @@ body: |
; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p3) :: (load (<2 x s64>) from unknown-address + 16, addrspace 3)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<4 x s64>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v4s64_align32
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -14398,7 +13755,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p3) :: (load (<2 x s64>) from unknown-address + 16, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<4 x s64>)
- ;
; GFX11-LABEL: name: test_load_local_v4s64_align32
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -14409,7 +13765,6 @@ body: |
; GFX11-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p3) :: (load (<2 x s64>) from unknown-address + 16, addrspace 3)
; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<4 x s64>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v4s64_align32
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -14442,7 +13797,6 @@ body: |
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[CONCAT_VECTORS]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; CI-LABEL: name: test_load_local_v2p1_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -14454,7 +13808,6 @@ body: |
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[LOAD]](<2 x s32>), [[LOAD1]](<2 x s32>)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[CONCAT_VECTORS]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; CI-DS128-LABEL: name: test_load_local_v2p1_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -14472,7 +13825,6 @@ body: |
; CI-DS128-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-DS128-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; VI-LABEL: name: test_load_local_v2p1_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -14490,7 +13842,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-LABEL: name: test_load_local_v2p1_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -14508,7 +13859,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2p1_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -14516,7 +13866,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s32>), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[LOAD]](<4 x s32>)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX10-LABEL: name: test_load_local_v2p1_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -14534,7 +13883,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2p1_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -14552,7 +13900,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-UNALIGNED-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX11-LABEL: name: test_load_local_v2p1_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -14570,7 +13917,6 @@ body: |
; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2p1_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -14595,63 +13941,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p3) :: (load (<2 x p3>), addrspace 3)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; CI-LABEL: name: test_load_local_v2p3_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p3) :: (load (<2 x p3>), addrspace 3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; CI-DS128-LABEL: name: test_load_local_v2p3_align8
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p3) :: (load (<2 x p3>), addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; VI-LABEL: name: test_load_local_v2p3_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p3) :: (load (<2 x p3>), addrspace 3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; GFX9-LABEL: name: test_load_local_v2p3_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p3) :: (load (<2 x p3>), addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2p3_align8
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p3) :: (load (<2 x p3>), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; GFX10-LABEL: name: test_load_local_v2p3_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p3) :: (load (<2 x p3>), addrspace 3)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2p3_align8
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p3) :: (load (<2 x p3>), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; GFX11-LABEL: name: test_load_local_v2p3_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[COPY]](p3) :: (load (<2 x p3>), addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x p3>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2p3_align8
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -14675,63 +14012,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_extload_local_s32_from_1_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-DS128-LABEL: name: test_extload_local_s32_from_1_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; CI-DS128-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_extload_local_s32_from_1_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_extload_local_s32_from_1_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_extload_local_s32_from_1_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_extload_local_s32_from_1_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_extload_local_s32_from_1_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_extload_local_s32_from_1_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_extload_local_s32_from_1_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -14755,63 +14083,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_extload_local_s32_from_2_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-DS128-LABEL: name: test_extload_local_s32_from_2_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; CI-DS128-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_extload_local_s32_from_2_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_extload_local_s32_from_2_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-UNALIGNED-LABEL: name: test_extload_local_s32_from_2_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_extload_local_s32_from_2_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-UNALIGNED-LABEL: name: test_extload_local_s32_from_2_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_extload_local_s32_from_2_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-UNALIGNED-LABEL: name: test_extload_local_s32_from_2_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -14837,7 +14156,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-LABEL: name: test_extload_local_s64_from_1_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -14845,7 +14163,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-DS128-LABEL: name: test_extload_local_s64_from_1_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -14853,7 +14170,6 @@ body: |
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; CI-DS128-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_extload_local_s64_from_1_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -14861,7 +14177,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_extload_local_s64_from_1_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -14869,7 +14184,6 @@ body: |
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-UNALIGNED-LABEL: name: test_extload_local_s64_from_1_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -14877,7 +14191,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX10-LABEL: name: test_extload_local_s64_from_1_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -14885,7 +14198,6 @@ body: |
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX10-UNALIGNED-LABEL: name: test_extload_local_s64_from_1_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -14893,7 +14205,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX11-LABEL: name: test_extload_local_s64_from_1_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -14901,7 +14212,6 @@ body: |
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX11-UNALIGNED-LABEL: name: test_extload_local_s64_from_1_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -14927,7 +14237,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-LABEL: name: test_extload_local_s64_from_2_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -14935,7 +14244,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-DS128-LABEL: name: test_extload_local_s64_from_2_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -14943,7 +14251,6 @@ body: |
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; CI-DS128-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_extload_local_s64_from_2_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -14951,7 +14258,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_extload_local_s64_from_2_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -14959,7 +14265,6 @@ body: |
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-UNALIGNED-LABEL: name: test_extload_local_s64_from_2_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -14967,7 +14272,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX10-LABEL: name: test_extload_local_s64_from_2_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -14975,7 +14279,6 @@ body: |
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX10-UNALIGNED-LABEL: name: test_extload_local_s64_from_2_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -14983,7 +14286,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX11-LABEL: name: test_extload_local_s64_from_2_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -14991,7 +14293,6 @@ body: |
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX11-UNALIGNED-LABEL: name: test_extload_local_s64_from_2_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -15017,7 +14318,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-LABEL: name: test_extload_local_s64_from_4_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -15025,7 +14325,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-DS128-LABEL: name: test_extload_local_s64_from_4_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -15033,7 +14332,6 @@ body: |
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; CI-DS128-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_extload_local_s64_from_4_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -15041,7 +14339,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_extload_local_s64_from_4_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -15049,7 +14346,6 @@ body: |
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-UNALIGNED-LABEL: name: test_extload_local_s64_from_4_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -15057,7 +14353,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX9-UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX10-LABEL: name: test_extload_local_s64_from_4_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -15065,7 +14360,6 @@ body: |
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX10-UNALIGNED-LABEL: name: test_extload_local_s64_from_4_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -15073,7 +14367,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX10-UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX11-LABEL: name: test_extload_local_s64_from_4_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -15081,7 +14374,6 @@ body: |
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX11-UNALIGNED-LABEL: name: test_extload_local_s64_from_4_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -15110,7 +14402,6 @@ body: |
; SI-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; SI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; CI-LABEL: name: test_extload_local_s128_from_4_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -15121,7 +14412,6 @@ body: |
; CI-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; CI-DS128-LABEL: name: test_extload_local_s128_from_4_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -15132,7 +14422,6 @@ body: |
; CI-DS128-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CI-DS128-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; VI-LABEL: name: test_extload_local_s128_from_4_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -15143,7 +14432,6 @@ body: |
; VI-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; VI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; GFX9-LABEL: name: test_extload_local_s128_from_4_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -15154,7 +14442,6 @@ body: |
; GFX9-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; GFX9-UNALIGNED-LABEL: name: test_extload_local_s128_from_4_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -15165,7 +14452,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; GFX9-UNALIGNED-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; GFX10-LABEL: name: test_extload_local_s128_from_4_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -15176,7 +14462,6 @@ body: |
; GFX10-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; GFX10-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; GFX10-UNALIGNED-LABEL: name: test_extload_local_s128_from_4_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -15187,7 +14472,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; GFX10-UNALIGNED-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; GFX11-LABEL: name: test_extload_local_s128_from_4_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -15198,7 +14482,6 @@ body: |
; GFX11-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; GFX11-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; GFX11-UNALIGNED-LABEL: name: test_extload_local_s128_from_4_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -15227,7 +14510,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-LABEL: name: test_extload_local_s64_from_2_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -15235,7 +14517,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-DS128-LABEL: name: test_extload_local_s64_from_2_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -15243,7 +14524,6 @@ body: |
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; CI-DS128-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_extload_local_s64_from_2_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -15251,7 +14531,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_extload_local_s64_from_2_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -15259,7 +14538,6 @@ body: |
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-UNALIGNED-LABEL: name: test_extload_local_s64_from_2_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -15267,7 +14545,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX10-LABEL: name: test_extload_local_s64_from_2_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -15275,7 +14552,6 @@ body: |
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX10-UNALIGNED-LABEL: name: test_extload_local_s64_from_2_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -15283,7 +14559,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX11-LABEL: name: test_extload_local_s64_from_2_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -15291,7 +14566,6 @@ body: |
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX11-UNALIGNED-LABEL: name: test_extload_local_s64_from_2_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -15317,7 +14591,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-LABEL: name: test_extload_local_s64_from_1_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -15325,7 +14598,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-DS128-LABEL: name: test_extload_local_s64_from_1_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -15333,7 +14605,6 @@ body: |
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; CI-DS128-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_extload_local_s64_from_1_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -15341,7 +14612,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_extload_local_s64_from_1_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -15349,7 +14619,6 @@ body: |
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-UNALIGNED-LABEL: name: test_extload_local_s64_from_1_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -15357,7 +14626,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX10-LABEL: name: test_extload_local_s64_from_1_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -15365,7 +14633,6 @@ body: |
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX10-UNALIGNED-LABEL: name: test_extload_local_s64_from_1_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -15373,7 +14640,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX10-UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX11-LABEL: name: test_extload_local_s64_from_1_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -15381,7 +14647,6 @@ body: |
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
; GFX11-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX11-UNALIGNED-LABEL: name: test_extload_local_s64_from_1_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -15406,63 +14671,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 1, addrspace 3)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-LABEL: name: test_extload_local_v2s32_from_4_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 1, addrspace 3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-DS128-LABEL: name: test_extload_local_v2s32_from_4_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 1, addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_extload_local_v2s32_from_4_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 1, addrspace 3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_extload_local_v2s32_from_4_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 1, addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_extload_local_v2s32_from_4_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 1, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_extload_local_v2s32_from_4_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 1, addrspace 3)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_extload_local_v2s32_from_4_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 1, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_extload_local_v2s32_from_4_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 1, addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_extload_local_v2s32_from_4_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -15486,63 +14742,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 2, addrspace 3)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-LABEL: name: test_extload_local_v2s32_from_4_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 2, addrspace 3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-DS128-LABEL: name: test_extload_local_v2s32_from_4_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 2, addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_extload_local_v2s32_from_4_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 2, addrspace 3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_extload_local_v2s32_from_4_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 2, addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_extload_local_v2s32_from_4_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 2, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_extload_local_v2s32_from_4_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 2, addrspace 3)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_extload_local_v2s32_from_4_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 2, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_extload_local_v2s32_from_4_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), align 2, addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_extload_local_v2s32_from_4_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -15566,63 +14813,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-LABEL: name: test_extload_local_v2s32_from_4_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-DS128-LABEL: name: test_extload_local_v2s32_from_4_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_extload_local_v2s32_from_4_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_extload_local_v2s32_from_4_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_extload_local_v2s32_from_4_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_extload_local_v2s32_from_4_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_extload_local_v2s32_from_4_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_extload_local_v2s32_from_4_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>), addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_extload_local_v2s32_from_4_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -15646,63 +14884,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s16>), align 4, addrspace 3)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; CI-LABEL: name: test_extload_local_v3s32_from_6_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s16>), align 4, addrspace 3)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; CI-DS128-LABEL: name: test_extload_local_v3s32_from_6_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s16>), align 4, addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; VI-LABEL: name: test_extload_local_v3s32_from_6_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s16>), align 4, addrspace 3)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_extload_local_v3s32_from_6_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s16>), align 4, addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_extload_local_v3s32_from_6_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s16>), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX10-LABEL: name: test_extload_local_v3s32_from_6_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s16>), align 4, addrspace 3)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_extload_local_v3s32_from_6_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s16>), align 4, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX11-LABEL: name: test_extload_local_v3s32_from_6_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s16>), align 4, addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_extload_local_v3s32_from_6_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -15726,63 +14955,54 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 4, addrspace 3)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; CI-LABEL: name: test_extload_local_v4s32_from_8_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 4, addrspace 3)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; CI-DS128-LABEL: name: test_extload_local_v4s32_from_8_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
; CI-DS128-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 4, addrspace 3)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; VI-LABEL: name: test_extload_local_v4s32_from_8_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 4, addrspace 3)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_extload_local_v4s32_from_8_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 4, addrspace 3)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-UNALIGNED-LABEL: name: test_extload_local_v4s32_from_8_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
; GFX9-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 4, addrspace 3)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX10-LABEL: name: test_extload_local_v4s32_from_8_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 4, addrspace 3)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX10-UNALIGNED-LABEL: name: test_extload_local_v4s32_from_8_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
; GFX10-UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 4, addrspace 3)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX11-LABEL: name: test_extload_local_v4s32_from_8_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load (<4 x s16>), align 4, addrspace 3)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX11-UNALIGNED-LABEL: name: test_extload_local_v4s32_from_8_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -15901,7 +15121,6 @@ body: |
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; SI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-LABEL: name: test_load_local_v2s96_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -16003,7 +15222,6 @@ body: |
; CI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-DS128-LABEL: name: test_load_local_v2s96_align1
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -16105,7 +15323,6 @@ body: |
; CI-DS128-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-DS128-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_load_local_v2s96_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -16207,7 +15424,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-LABEL: name: test_load_local_v2s96_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -16309,7 +15525,6 @@ body: |
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s96_align1
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -16324,7 +15539,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-UNALIGNED-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX10-LABEL: name: test_load_local_v2s96_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -16426,7 +15640,6 @@ body: |
; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX10-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s96_align1
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -16453,7 +15666,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX10-UNALIGNED-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX11-LABEL: name: test_load_local_v2s96_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -16555,7 +15767,6 @@ body: |
; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX11-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2s96_align1
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -16636,7 +15847,6 @@ body: |
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; SI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-LABEL: name: test_load_local_v2s96_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -16689,7 +15899,6 @@ body: |
; CI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-DS128-LABEL: name: test_load_local_v2s96_align2
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -16742,7 +15951,6 @@ body: |
; CI-DS128-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-DS128-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_load_local_v2s96_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -16795,7 +16003,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-LABEL: name: test_load_local_v2s96_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -16848,7 +16055,6 @@ body: |
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s96_align2
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -16863,7 +16069,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-UNALIGNED-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX10-LABEL: name: test_load_local_v2s96_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -16916,7 +16121,6 @@ body: |
; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX10-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s96_align2
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -16943,7 +16147,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX10-UNALIGNED-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX11-LABEL: name: test_load_local_v2s96_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -16996,7 +16199,6 @@ body: |
; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX11-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2s96_align2
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -17048,7 +16250,6 @@ body: |
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; SI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-LABEL: name: test_load_local_v2s96_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -17072,7 +16273,6 @@ body: |
; CI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-DS128-LABEL: name: test_load_local_v2s96_align4
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -17099,7 +16299,6 @@ body: |
; CI-DS128-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-DS128-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_load_local_v2s96_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -17126,7 +16325,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-LABEL: name: test_load_local_v2s96_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -17153,7 +16351,6 @@ body: |
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s96_align4
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -17168,7 +16365,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-UNALIGNED-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX10-LABEL: name: test_load_local_v2s96_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -17195,7 +16391,6 @@ body: |
; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX10-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s96_align4
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -17222,7 +16417,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX10-UNALIGNED-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX11-LABEL: name: test_load_local_v2s96_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -17249,7 +16443,6 @@ body: |
; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX11-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2s96_align4
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
@@ -17301,7 +16494,6 @@ body: |
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; SI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-LABEL: name: test_load_local_v2s96_align16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -17325,7 +16517,6 @@ body: |
; CI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-DS128-LABEL: name: test_load_local_v2s96_align16
; CI-DS128: liveins: $vgpr0
; CI-DS128-NEXT: {{ $}}
@@ -17347,7 +16538,6 @@ body: |
; CI-DS128-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-DS128-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-DS128-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_load_local_v2s96_align16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -17369,7 +16559,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-LABEL: name: test_load_local_v2s96_align16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -17391,7 +16580,6 @@ body: |
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s96_align16
; GFX9-UNALIGNED: liveins: $vgpr0
; GFX9-UNALIGNED-NEXT: {{ $}}
@@ -17406,7 +16594,6 @@ body: |
; GFX9-UNALIGNED-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-UNALIGNED-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX10-LABEL: name: test_load_local_v2s96_align16
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -17428,7 +16615,6 @@ body: |
; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX10-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s96_align16
; GFX10-UNALIGNED: liveins: $vgpr0
; GFX10-UNALIGNED-NEXT: {{ $}}
@@ -17450,7 +16636,6 @@ body: |
; GFX10-UNALIGNED-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX10-UNALIGNED-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX10-UNALIGNED-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX11-LABEL: name: test_load_local_v2s96_align16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -17472,7 +16657,6 @@ body: |
; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX11-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX11-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX11-UNALIGNED-LABEL: name: test_load_local_v2s96_align16
; GFX11-UNALIGNED: liveins: $vgpr0
; GFX11-UNALIGNED-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
index 40884567f9962ae..620f01280529435 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
@@ -20,7 +20,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; CI-LABEL: name: test_load_private_s1_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -29,7 +28,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; VI-LABEL: name: test_load_private_s1_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -38,7 +36,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX9-LABEL: name: test_load_private_s1_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -47,7 +44,6 @@ body: |
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX10-LABEL: name: test_load_private_s1_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -56,7 +52,6 @@ body: |
; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX10-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX10-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX11-LABEL: name: test_load_private_s1_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -85,7 +80,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; CI-LABEL: name: test_load_private_s2_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -94,7 +88,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; VI-LABEL: name: test_load_private_s2_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -103,7 +96,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX9-LABEL: name: test_load_private_s2_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -112,7 +104,6 @@ body: |
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX10-LABEL: name: test_load_private_s2_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -121,7 +112,6 @@ body: |
; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; GFX10-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX10-NEXT: $vgpr0 = COPY [[AND]](s32)
- ;
; GFX11-LABEL: name: test_load_private_s2_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -148,35 +138,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_private_s8_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_private_s8_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_private_s8_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_private_s8_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_private_s8_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -201,35 +186,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_private_s8_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_private_s8_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_private_s8_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_private_s8_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_private_s8_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -254,35 +234,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_private_s16_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_private_s16_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_private_s16_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_private_s16_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_private_s16_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -307,35 +282,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_private_s16_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_private_s16_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_private_s16_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_private_s16_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_private_s16_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -366,7 +336,6 @@ body: |
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-LABEL: name: test_load_private_s16_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -379,7 +348,6 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_private_s16_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -392,7 +360,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_load_private_s16_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -405,7 +372,6 @@ body: |
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX10-LABEL: name: test_load_private_s16_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -418,7 +384,6 @@ body: |
; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX10-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX10-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX11-LABEL: name: test_load_private_s16_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -443,35 +408,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_private_s32_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_private_s32_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_private_s32_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_private_s32_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_private_s32_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -501,7 +461,6 @@ body: |
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-LABEL: name: test_load_private_s32_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -514,7 +473,6 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_private_s32_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -527,7 +485,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_load_private_s32_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -540,7 +497,6 @@ body: |
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX10-LABEL: name: test_load_private_s32_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -553,7 +509,6 @@ body: |
; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX10-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX10-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX11-LABEL: name: test_load_private_s32_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -593,7 +548,6 @@ body: |
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; SI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; CI-LABEL: name: test_load_private_s32_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -616,7 +570,6 @@ body: |
; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; VI-LABEL: name: test_load_private_s32_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -639,7 +592,6 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; VI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-LABEL: name: test_load_private_s32_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -662,7 +614,6 @@ body: |
; GFX9-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; GFX9-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX10-LABEL: name: test_load_private_s32_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -685,7 +636,6 @@ body: |
; GFX10-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C3]](s32)
; GFX10-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; GFX10-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX11-LABEL: name: test_load_private_s32_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -709,35 +659,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), align 8, addrspace 5)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_private_s24_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), align 8, addrspace 5)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_private_s24_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), align 8, addrspace 5)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_private_s24_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), align 8, addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_private_s24_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), align 8, addrspace 5)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_private_s24_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -762,35 +707,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_private_s24_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_private_s24_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_private_s24_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_private_s24_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_private_s24_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -821,7 +761,6 @@ body: |
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; CI-LABEL: name: test_load_private_s24_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -834,7 +773,6 @@ body: |
; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; VI-LABEL: name: test_load_private_s24_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -847,7 +785,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX9-LABEL: name: test_load_private_s24_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -860,7 +797,6 @@ body: |
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX10-LABEL: name: test_load_private_s24_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -873,7 +809,6 @@ body: |
; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX10-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX10-NEXT: $vgpr0 = COPY [[OR]](s32)
- ;
; GFX11-LABEL: name: test_load_private_s24_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -916,7 +851,6 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; SI-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; CI-LABEL: name: test_load_private_s24_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -935,7 +869,6 @@ body: |
; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; CI-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; VI-LABEL: name: test_load_private_s24_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -954,7 +887,6 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; VI-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; GFX9-LABEL: name: test_load_private_s24_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -973,7 +905,6 @@ body: |
; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; GFX9-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; GFX10-LABEL: name: test_load_private_s24_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -992,7 +923,6 @@ body: |
; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C3]](s32)
; GFX10-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[OR]]
; GFX10-NEXT: $vgpr0 = COPY [[OR1]](s32)
- ;
; GFX11-LABEL: name: test_load_private_s24_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -1029,15 +959,15 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C2]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C1]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; CI-LABEL: name: test_load_private_s48_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -1050,15 +980,15 @@ body: |
; CI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C2]]
- ; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C1]](s32)
+ ; CI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; CI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; CI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
- ; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; VI-LABEL: name: test_load_private_s48_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -1071,15 +1001,15 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C2]]
- ; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C1]](s32)
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
- ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX9-LABEL: name: test_load_private_s48_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -1092,15 +1022,15 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C2]]
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C1]](s32)
+ ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
- ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX10-LABEL: name: test_load_private_s48_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -1113,15 +1043,15 @@ body: |
; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX10-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C2]]
- ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C1]](s32)
+ ; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX10-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; GFX10-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
- ; GFX10-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; GFX10-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX11-LABEL: name: test_load_private_s48_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -1150,7 +1080,6 @@ body: |
; SI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; SI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; CI-LABEL: name: test_load_private_s64_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -1161,7 +1090,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; CI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; VI-LABEL: name: test_load_private_s64_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -1172,7 +1100,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX9-LABEL: name: test_load_private_s64_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -1183,7 +1110,6 @@ body: |
; GFX9-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX10-LABEL: name: test_load_private_s64_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -1194,7 +1120,6 @@ body: |
; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX11-LABEL: name: test_load_private_s64_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -1222,7 +1147,6 @@ body: |
; SI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; SI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; CI-LABEL: name: test_load_private_s64_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -1233,7 +1157,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; CI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; VI-LABEL: name: test_load_private_s64_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -1244,7 +1167,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX9-LABEL: name: test_load_private_s64_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -1255,7 +1177,6 @@ body: |
; GFX9-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX10-LABEL: name: test_load_private_s64_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -1266,7 +1187,6 @@ body: |
; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX11-LABEL: name: test_load_private_s64_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -1304,7 +1224,6 @@ body: |
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; SI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; CI-LABEL: name: test_load_private_s64_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -1325,7 +1244,6 @@ body: |
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; CI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; VI-LABEL: name: test_load_private_s64_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -1346,7 +1264,6 @@ body: |
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX9-LABEL: name: test_load_private_s64_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -1367,7 +1284,6 @@ body: |
; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX10-LABEL: name: test_load_private_s64_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -1388,7 +1304,6 @@ body: |
; GFX10-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX11-LABEL: name: test_load_private_s64_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -1444,7 +1359,6 @@ body: |
; SI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; SI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; CI-LABEL: name: test_load_private_s64_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -1483,7 +1397,6 @@ body: |
; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; CI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; VI-LABEL: name: test_load_private_s64_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -1522,7 +1435,6 @@ body: |
; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX9-LABEL: name: test_load_private_s64_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -1561,7 +1473,6 @@ body: |
; GFX9-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX10-LABEL: name: test_load_private_s64_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -1600,7 +1511,6 @@ body: |
; GFX10-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX11-LABEL: name: test_load_private_s64_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -1671,7 +1581,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-LABEL: name: test_load_private_s96_align16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -1725,7 +1634,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_private_s96_align16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -1779,7 +1687,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_private_s96_align16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -1833,7 +1740,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX10-LABEL: name: test_load_private_s96_align16
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -1887,7 +1793,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX11-LABEL: name: test_load_private_s96_align16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -1920,7 +1825,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-LABEL: name: test_load_private_s96_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -1935,7 +1839,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_private_s96_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -1950,7 +1853,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_private_s96_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -1965,7 +1867,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX10-LABEL: name: test_load_private_s96_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -1980,7 +1881,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX11-LABEL: name: test_load_private_s96_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -2013,7 +1913,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-LABEL: name: test_load_private_s96_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -2028,7 +1927,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_private_s96_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -2043,7 +1941,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_private_s96_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -2058,7 +1955,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX10-LABEL: name: test_load_private_s96_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -2073,7 +1969,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX11-LABEL: name: test_load_private_s96_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -2120,7 +2015,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-LABEL: name: test_load_private_s96_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -2149,7 +2043,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_private_s96_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -2178,7 +2071,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_private_s96_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -2207,7 +2099,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX10-LABEL: name: test_load_private_s96_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -2236,7 +2127,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX11-LABEL: name: test_load_private_s96_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -2308,7 +2198,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; CI-LABEL: name: test_load_private_s96_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -2362,7 +2251,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; VI-LABEL: name: test_load_private_s96_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -2416,7 +2304,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX9-LABEL: name: test_load_private_s96_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -2470,7 +2357,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX10-LABEL: name: test_load_private_s96_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -2524,7 +2410,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR]](<3 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
- ;
; GFX11-LABEL: name: test_load_private_s96_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -2611,7 +2496,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-LABEL: name: test_load_private_s128_align16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -2680,7 +2564,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_private_s128_align16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -2749,7 +2632,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_private_s128_align16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -2818,7 +2700,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX10-LABEL: name: test_load_private_s128_align16
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -2887,7 +2768,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX11-LABEL: name: test_load_private_s128_align16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -2923,7 +2803,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-LABEL: name: test_load_private_s128_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -2941,7 +2820,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_private_s128_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -2959,7 +2837,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_private_s128_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -2977,7 +2854,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX10-LABEL: name: test_load_private_s128_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -2995,7 +2871,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX11-LABEL: name: test_load_private_s128_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -3031,7 +2906,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-LABEL: name: test_load_private_s128_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -3049,7 +2923,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_private_s128_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -3067,7 +2940,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_private_s128_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -3085,7 +2957,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX10-LABEL: name: test_load_private_s128_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -3103,7 +2974,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX11-LABEL: name: test_load_private_s128_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -3157,7 +3027,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-LABEL: name: test_load_private_s128_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -3193,7 +3062,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_private_s128_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -3229,7 +3097,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_private_s128_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -3265,7 +3132,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX10-LABEL: name: test_load_private_s128_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -3301,7 +3167,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX11-LABEL: name: test_load_private_s128_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -3388,7 +3253,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; CI-LABEL: name: test_load_private_s128_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -3457,7 +3321,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; VI-LABEL: name: test_load_private_s128_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -3526,7 +3389,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX9-LABEL: name: test_load_private_s128_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -3595,7 +3457,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX10-LABEL: name: test_load_private_s128_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -3664,7 +3525,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
- ;
; GFX11-LABEL: name: test_load_private_s128_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -3693,7 +3553,6 @@ body: |
; SI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; SI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; CI-LABEL: name: test_load_private_p1_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -3704,7 +3563,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; CI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; VI-LABEL: name: test_load_private_p1_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -3715,7 +3573,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; VI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; GFX9-LABEL: name: test_load_private_p1_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -3726,7 +3583,6 @@ body: |
; GFX9-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; GFX9-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; GFX10-LABEL: name: test_load_private_p1_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -3737,7 +3593,6 @@ body: |
; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; GFX11-LABEL: name: test_load_private_p1_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -3765,7 +3620,6 @@ body: |
; SI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; SI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; CI-LABEL: name: test_load_private_p1_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -3776,7 +3630,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; CI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; VI-LABEL: name: test_load_private_p1_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -3787,7 +3640,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; VI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; GFX9-LABEL: name: test_load_private_p1_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -3798,7 +3650,6 @@ body: |
; GFX9-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; GFX9-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; GFX10-LABEL: name: test_load_private_p1_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -3809,7 +3660,6 @@ body: |
; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; GFX11-LABEL: name: test_load_private_p1_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -3847,7 +3697,6 @@ body: |
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; SI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; CI-LABEL: name: test_load_private_p1_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -3868,7 +3717,6 @@ body: |
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; CI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; VI-LABEL: name: test_load_private_p1_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -3889,7 +3737,6 @@ body: |
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; VI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; GFX9-LABEL: name: test_load_private_p1_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -3910,7 +3757,6 @@ body: |
; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; GFX10-LABEL: name: test_load_private_p1_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -3931,7 +3777,6 @@ body: |
; GFX10-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; GFX11-LABEL: name: test_load_private_p1_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -3987,7 +3832,6 @@ body: |
; SI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; SI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; CI-LABEL: name: test_load_private_p1_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -4026,7 +3870,6 @@ body: |
; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; CI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; VI-LABEL: name: test_load_private_p1_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -4065,7 +3908,6 @@ body: |
; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; VI-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; GFX9-LABEL: name: test_load_private_p1_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -4104,7 +3946,6 @@ body: |
; GFX9-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; GFX10-LABEL: name: test_load_private_p1_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -4143,7 +3984,6 @@ body: |
; GFX10-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p1)
- ;
; GFX11-LABEL: name: test_load_private_p1_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -4167,35 +4007,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p5) :: (load (p3), addrspace 5)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; CI-LABEL: name: test_load_private_p3_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p5) :: (load (p3), addrspace 5)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; VI-LABEL: name: test_load_private_p3_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p5) :: (load (p3), addrspace 5)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX9-LABEL: name: test_load_private_p3_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p5) :: (load (p3), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX10-LABEL: name: test_load_private_p3_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p5) :: (load (p3), addrspace 5)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](p3)
- ;
; GFX11-LABEL: name: test_load_private_p3_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -4226,7 +4061,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; CI-LABEL: name: test_load_private_p3_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -4240,7 +4074,6 @@ body: |
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR]](s32)
; CI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; VI-LABEL: name: test_load_private_p3_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -4254,7 +4087,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; GFX9-LABEL: name: test_load_private_p3_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -4268,7 +4100,6 @@ body: |
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; GFX10-LABEL: name: test_load_private_p3_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -4282,7 +4113,6 @@ body: |
; GFX10-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX10-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR]](s32)
; GFX10-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; GFX11-LABEL: name: test_load_private_p3_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -4323,7 +4153,6 @@ body: |
; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR2]](s32)
; SI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; CI-LABEL: name: test_load_private_p3_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -4347,7 +4176,6 @@ body: |
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR2]](s32)
; CI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; VI-LABEL: name: test_load_private_p3_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -4371,7 +4199,6 @@ body: |
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR2]](s32)
; VI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; GFX9-LABEL: name: test_load_private_p3_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -4395,7 +4222,6 @@ body: |
; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; GFX9-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR2]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; GFX10-LABEL: name: test_load_private_p3_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -4419,7 +4245,6 @@ body: |
; GFX10-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; GFX10-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR2]](s32)
; GFX10-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
- ;
; GFX11-LABEL: name: test_load_private_p3_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -4443,35 +4268,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p5) :: (load (p5), addrspace 5)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; CI-LABEL: name: test_load_private_p5_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p5) :: (load (p5), addrspace 5)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; VI-LABEL: name: test_load_private_p5_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p5) :: (load (p5), addrspace 5)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX9-LABEL: name: test_load_private_p5_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p5) :: (load (p5), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX10-LABEL: name: test_load_private_p5_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[COPY]](p5) :: (load (p5), addrspace 5)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](p5)
- ;
; GFX11-LABEL: name: test_load_private_p5_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -4502,7 +4322,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; CI-LABEL: name: test_load_private_p5_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -4516,7 +4335,6 @@ body: |
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; CI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; VI-LABEL: name: test_load_private_p5_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -4530,7 +4348,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX9-LABEL: name: test_load_private_p5_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -4544,7 +4361,6 @@ body: |
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX9-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX10-LABEL: name: test_load_private_p5_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -4558,7 +4374,6 @@ body: |
; GFX10-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; GFX10-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR]](s32)
; GFX10-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX11-LABEL: name: test_load_private_p5_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -4599,7 +4414,6 @@ body: |
; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; SI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; SI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; CI-LABEL: name: test_load_private_p5_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -4623,7 +4437,6 @@ body: |
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; CI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; CI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; VI-LABEL: name: test_load_private_p5_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -4647,7 +4460,6 @@ body: |
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; VI-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; VI-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX9-LABEL: name: test_load_private_p5_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -4671,7 +4483,6 @@ body: |
; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; GFX9-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; GFX9-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX10-LABEL: name: test_load_private_p5_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -4695,7 +4506,6 @@ body: |
; GFX10-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL2]], [[OR]]
; GFX10-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[OR2]](s32)
; GFX10-NEXT: $vgpr0 = COPY [[INTTOPTR]](p5)
- ;
; GFX11-LABEL: name: test_load_private_p5_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -4719,35 +4529,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_private_v2s8_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_private_v2s8_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_private_v2s8_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_private_v2s8_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_private_v2s8_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -4781,7 +4586,6 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[LSHR]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; CI-LABEL: name: test_load_private_v2s8_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -4796,7 +4600,6 @@ body: |
; CI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[LSHR]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_private_v2s8_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -4811,7 +4614,6 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[LSHR]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v2s8_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -4826,7 +4628,6 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[LSHR]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v2s8_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -4841,7 +4642,6 @@ body: |
; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[LSHR]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v2s8_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -4873,8 +4673,8 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; SI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; SI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -4894,7 +4694,6 @@ body: |
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; SI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; CI-LABEL: name: test_load_private_v3s8_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -4905,8 +4704,8 @@ body: |
; CI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; CI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; CI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -4926,7 +4725,6 @@ body: |
; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; CI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; VI-LABEL: name: test_load_private_v3s8_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -4937,8 +4735,8 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; VI-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -4956,7 +4754,6 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; VI-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-LABEL: name: test_load_private_v3s8_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -4967,8 +4764,8 @@ body: |
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -4986,7 +4783,6 @@ body: |
; GFX9-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; GFX9-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX10-LABEL: name: test_load_private_v3s8_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -4997,8 +4793,8 @@ body: |
; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX10-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -5016,7 +4812,6 @@ body: |
; GFX10-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX10-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; GFX10-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX11-LABEL: name: test_load_private_v3s8_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -5027,8 +4822,8 @@ body: |
; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX11-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
; GFX11-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX11-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C2]]
@@ -5079,8 +4874,8 @@ body: |
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; SI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; SI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -5100,7 +4895,6 @@ body: |
; SI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; SI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; SI-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; CI-LABEL: name: test_load_private_v3s8_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -5121,8 +4915,8 @@ body: |
; CI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; CI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; CI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; CI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; CI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -5142,7 +4936,6 @@ body: |
; CI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; CI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; CI-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; VI-LABEL: name: test_load_private_v3s8_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -5163,8 +4956,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; VI-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
@@ -5182,7 +4975,6 @@ body: |
; VI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; VI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; VI-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; GFX9-LABEL: name: test_load_private_v3s8_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -5203,8 +4995,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX9-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
@@ -5222,7 +5014,6 @@ body: |
; GFX9-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; GFX9-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; GFX9-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; GFX10-LABEL: name: test_load_private_v3s8_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -5243,8 +5034,8 @@ body: |
; GFX10-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C1]](s32)
; GFX10-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR1]], [[C3]](s32)
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX10-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX10-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
@@ -5262,7 +5053,6 @@ body: |
; GFX10-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; GFX10-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; GFX10-NEXT: $vgpr0 = COPY [[OR4]](s32)
- ;
; GFX11-LABEL: name: test_load_private_v3s8_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -5278,8 +5068,8 @@ body: |
; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C2]](s32)
; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C1]](s32)
; GFX11-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
; GFX11-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
; GFX11-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX11-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
@@ -5316,35 +5106,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_load_private_v4s8_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_load_private_v4s8_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_load_private_v4s8_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_load_private_v4s8_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_load_private_v4s8_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -5373,7 +5158,6 @@ body: |
; SI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; CI-LABEL: name: test_load_private_v8s8_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -5384,7 +5168,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_private_v8s8_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -5395,7 +5178,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v8s8_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -5406,7 +5188,6 @@ body: |
; GFX9-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v8s8_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -5417,7 +5198,6 @@ body: |
; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v8s8_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -5503,7 +5283,6 @@ body: |
; SI-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; CI-LABEL: name: test_load_private_v16s8_align16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -5571,7 +5350,6 @@ body: |
; CI-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_private_v16s8_align16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -5639,7 +5417,6 @@ body: |
; VI-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v16s8_align16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -5707,7 +5484,6 @@ body: |
; GFX9-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v16s8_align16
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -5775,7 +5551,6 @@ body: |
; GFX10-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v16s8_align16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -5800,35 +5575,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), addrspace 5)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; CI-LABEL: name: test_load_private_v2s16_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), addrspace 5)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_private_v2s16_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), addrspace 5)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_load_private_v2s16_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX10-LABEL: name: test_load_private_v2s16_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), addrspace 5)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
- ;
; GFX11-LABEL: name: test_load_private_v2s16_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -5862,7 +5632,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; CI-LABEL: name: test_load_private_v2s16_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -5879,7 +5648,6 @@ body: |
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_private_v2s16_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -5896,7 +5664,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_load_private_v2s16_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -5909,7 +5676,6 @@ body: |
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD1]](s32)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- ;
; GFX10-LABEL: name: test_load_private_v2s16_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -5922,7 +5688,6 @@ body: |
; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD1]](s32)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX10-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- ;
; GFX11-LABEL: name: test_load_private_v2s16_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -5966,7 +5731,6 @@ body: |
; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; CI-LABEL: name: test_load_private_v2s16_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -5993,7 +5757,6 @@ body: |
; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; VI-LABEL: name: test_load_private_v2s16_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -6020,7 +5783,6 @@ body: |
; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_load_private_v2s16_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -6043,7 +5805,6 @@ body: |
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- ;
; GFX10-LABEL: name: test_load_private_v2s16_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -6066,7 +5827,6 @@ body: |
; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX10-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- ;
; GFX11-LABEL: name: test_load_private_v2s16_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -6102,21 +5862,22 @@ body: |
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C1]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-LABEL: name: test_load_private_v3s16_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -6135,21 +5896,22 @@ body: |
; CI-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
- ; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C1]](s32)
+ ; CI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
- ; CI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
- ; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
- ; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; CI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; CI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
+ ; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
+ ; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
- ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
- ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
+ ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; CI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
+ ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
+ ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_private_v3s16_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -6168,21 +5930,22 @@ body: |
; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
- ; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C1]](s32)
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
- ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
- ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
- ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; VI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
+ ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
+ ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_load_private_v3s16_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -6210,7 +5973,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX10-LABEL: name: test_load_private_v3s16_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -6238,7 +6000,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX11-LABEL: name: test_load_private_v3s16_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -6301,13 +6062,13 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-LABEL: name: test_load_private_v3s16_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -6336,13 +6097,13 @@ body: |
; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; CI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_private_v3s16_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -6371,13 +6132,13 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL2]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_load_private_v3s16_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -6406,7 +6167,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX10-LABEL: name: test_load_private_v3s16_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -6435,7 +6195,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX11-LABEL: name: test_load_private_v3s16_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -6519,13 +6278,13 @@ body: |
; SI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; SI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; SI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
- ; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
- ; SI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL5]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
+ ; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
+ ; SI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL5]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; CI-LABEL: name: test_load_private_v3s16_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -6568,13 +6327,13 @@ body: |
; CI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; CI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
- ; CI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
- ; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL5]]
+ ; CI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; CI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
+ ; CI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
+ ; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL5]]
; CI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_load_private_v3s16_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -6617,13 +6376,13 @@ body: |
; VI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; VI-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
- ; VI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
- ; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL5]]
+ ; VI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; VI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
+ ; VI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
+ ; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL5]]
; VI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_load_private_v3s16_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -6666,7 +6425,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX10-LABEL: name: test_load_private_v3s16_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -6709,7 +6467,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX11-LABEL: name: test_load_private_v3s16_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -6760,7 +6517,6 @@ body: |
; SI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD]](p5) :: (load (<2 x s16>) from unknown-address + 4, addrspace 5)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[LOAD]](<2 x s16>), [[LOAD1]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; CI-LABEL: name: test_load_private_v4s16_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -6771,7 +6527,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD]](p5) :: (load (<2 x s16>) from unknown-address + 4, addrspace 5)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[LOAD]](<2 x s16>), [[LOAD1]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_private_v4s16_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -6782,7 +6537,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD]](p5) :: (load (<2 x s16>) from unknown-address + 4, addrspace 5)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[LOAD]](<2 x s16>), [[LOAD1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_private_v4s16_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -6793,7 +6547,6 @@ body: |
; GFX9-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD]](p5) :: (load (<2 x s16>) from unknown-address + 4, addrspace 5)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[LOAD]](<2 x s16>), [[LOAD1]](<2 x s16>)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX10-LABEL: name: test_load_private_v4s16_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -6804,7 +6557,6 @@ body: |
; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD]](p5) :: (load (<2 x s16>) from unknown-address + 4, addrspace 5)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[LOAD]](<2 x s16>), [[LOAD1]](<2 x s16>)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX11-LABEL: name: test_load_private_v4s16_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -6832,7 +6584,6 @@ body: |
; SI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD]](p5) :: (load (<2 x s16>) from unknown-address + 4, addrspace 5)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[LOAD]](<2 x s16>), [[LOAD1]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; CI-LABEL: name: test_load_private_v4s16_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -6843,7 +6594,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD]](p5) :: (load (<2 x s16>) from unknown-address + 4, addrspace 5)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[LOAD]](<2 x s16>), [[LOAD1]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_private_v4s16_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -6854,7 +6604,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD]](p5) :: (load (<2 x s16>) from unknown-address + 4, addrspace 5)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[LOAD]](<2 x s16>), [[LOAD1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_private_v4s16_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -6865,7 +6614,6 @@ body: |
; GFX9-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD]](p5) :: (load (<2 x s16>) from unknown-address + 4, addrspace 5)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[LOAD]](<2 x s16>), [[LOAD1]](<2 x s16>)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX10-LABEL: name: test_load_private_v4s16_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -6876,7 +6624,6 @@ body: |
; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD]](p5) :: (load (<2 x s16>) from unknown-address + 4, addrspace 5)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[LOAD]](<2 x s16>), [[LOAD1]](<2 x s16>)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX11-LABEL: name: test_load_private_v4s16_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -6920,7 +6667,6 @@ body: |
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; CI-LABEL: name: test_load_private_v4s16_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -6948,7 +6694,6 @@ body: |
; CI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_private_v4s16_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -6976,7 +6721,6 @@ body: |
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_private_v4s16_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -6998,7 +6742,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX10-LABEL: name: test_load_private_v4s16_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -7020,7 +6763,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX11-LABEL: name: test_load_private_v4s16_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -7083,7 +6825,6 @@ body: |
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; CI-LABEL: name: test_load_private_v4s16_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -7129,7 +6870,6 @@ body: |
; CI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; CI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_load_private_v4s16_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -7175,7 +6915,6 @@ body: |
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_load_private_v4s16_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -7215,7 +6954,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX10-LABEL: name: test_load_private_v4s16_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -7255,7 +6993,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX10-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX11-LABEL: name: test_load_private_v4s16_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -7283,7 +7020,6 @@ body: |
; SI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; CI-LABEL: name: test_load_private_v2s32_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -7294,7 +7030,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_private_v2s32_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -7305,7 +7040,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v2s32_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -7316,7 +7050,6 @@ body: |
; GFX9-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v2s32_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -7327,7 +7060,6 @@ body: |
; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v2s32_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -7355,7 +7087,6 @@ body: |
; SI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; CI-LABEL: name: test_load_private_v2s32_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -7366,7 +7097,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_private_v2s32_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -7377,7 +7107,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v2s32_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -7388,7 +7117,6 @@ body: |
; GFX9-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v2s32_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -7399,7 +7127,6 @@ body: |
; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s32) from unknown-address + 4, addrspace 5)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v2s32_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -7437,7 +7164,6 @@ body: |
; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; CI-LABEL: name: test_load_private_v2s32_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -7458,7 +7184,6 @@ body: |
; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_private_v2s32_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -7479,7 +7204,6 @@ body: |
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v2s32_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -7500,7 +7224,6 @@ body: |
; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v2s32_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -7521,7 +7244,6 @@ body: |
; GFX10-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]]
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v2s32_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -7577,7 +7299,6 @@ body: |
; SI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; CI-LABEL: name: test_load_private_v2s32_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -7616,7 +7337,6 @@ body: |
; CI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_load_private_v2s32_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -7655,7 +7375,6 @@ body: |
; VI-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v2s32_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -7694,7 +7413,6 @@ body: |
; GFX9-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v2s32_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -7733,7 +7451,6 @@ body: |
; GFX10-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[SHL5]], [[OR3]]
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v2s32_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -7803,7 +7520,6 @@ body: |
; SI-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[SHL8]], [[OR6]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; CI-LABEL: name: test_load_private_v3s32_align16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -7856,7 +7572,6 @@ body: |
; CI-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[SHL8]], [[OR6]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_load_private_v3s32_align16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -7909,7 +7624,6 @@ body: |
; VI-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[SHL8]], [[OR6]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v3s32_align16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -7962,7 +7676,6 @@ body: |
; GFX9-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[SHL8]], [[OR6]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v3s32_align16
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -8015,7 +7728,6 @@ body: |
; GFX10-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[SHL8]], [[OR6]]
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v3s32_align16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -8046,7 +7758,6 @@ body: |
; SI-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s32) from unknown-address + 8, addrspace 5)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; CI-LABEL: name: test_load_private_v3s32_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -8060,7 +7771,6 @@ body: |
; CI-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s32) from unknown-address + 8, addrspace 5)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_load_private_v3s32_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -8074,7 +7784,6 @@ body: |
; VI-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s32) from unknown-address + 8, addrspace 5)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v3s32_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -8088,7 +7797,6 @@ body: |
; GFX9-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s32) from unknown-address + 8, addrspace 5)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v3s32_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -8102,7 +7810,6 @@ body: |
; GFX10-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s32) from unknown-address + 8, addrspace 5)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v3s32_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -8187,7 +7894,6 @@ body: |
; SI-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; CI-LABEL: name: test_load_private_v4s32_align16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -8255,7 +7961,6 @@ body: |
; CI-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_private_v4s32_align16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -8323,7 +8028,6 @@ body: |
; VI-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v4s32_align16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -8391,7 +8095,6 @@ body: |
; GFX9-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v4s32_align16
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -8459,7 +8162,6 @@ body: |
; GFX10-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v4s32_align16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -8493,7 +8195,6 @@ body: |
; SI-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s32) from unknown-address + 12, addrspace 5)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; CI-LABEL: name: test_load_private_v4s32_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -8510,7 +8211,6 @@ body: |
; CI-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s32) from unknown-address + 12, addrspace 5)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_private_v4s32_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -8527,7 +8227,6 @@ body: |
; VI-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s32) from unknown-address + 12, addrspace 5)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v4s32_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -8544,7 +8243,6 @@ body: |
; GFX9-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s32) from unknown-address + 12, addrspace 5)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v4s32_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -8561,7 +8259,6 @@ body: |
; GFX10-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s32) from unknown-address + 12, addrspace 5)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v4s32_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -8595,7 +8292,6 @@ body: |
; SI-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s32) from unknown-address + 12, addrspace 5)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; CI-LABEL: name: test_load_private_v4s32_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -8612,7 +8308,6 @@ body: |
; CI-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s32) from unknown-address + 12, addrspace 5)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_private_v4s32_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -8629,7 +8324,6 @@ body: |
; VI-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s32) from unknown-address + 12, addrspace 5)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v4s32_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -8646,7 +8340,6 @@ body: |
; GFX9-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s32) from unknown-address + 12, addrspace 5)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v4s32_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -8663,7 +8356,6 @@ body: |
; GFX10-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s32) from unknown-address + 12, addrspace 5)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v4s32_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -8715,7 +8407,6 @@ body: |
; SI-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SHL3]], [[ZEXTLOAD3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; CI-LABEL: name: test_load_private_v4s32_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -8750,7 +8441,6 @@ body: |
; CI-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SHL3]], [[ZEXTLOAD3]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_private_v4s32_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -8785,7 +8475,6 @@ body: |
; VI-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SHL3]], [[ZEXTLOAD3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v4s32_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -8820,7 +8509,6 @@ body: |
; GFX9-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SHL3]], [[ZEXTLOAD3]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v4s32_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -8855,7 +8543,6 @@ body: |
; GFX10-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SHL3]], [[ZEXTLOAD3]]
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v4s32_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -8940,7 +8627,6 @@ body: |
; SI-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; CI-LABEL: name: test_load_private_v4s32_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -9008,7 +8694,6 @@ body: |
; CI-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; VI-LABEL: name: test_load_private_v4s32_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -9076,7 +8761,6 @@ body: |
; VI-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v4s32_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -9144,7 +8828,6 @@ body: |
; GFX9-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v4s32_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -9212,7 +8895,6 @@ body: |
; GFX10-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[SHL11]], [[OR9]]
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v4s32_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -9258,7 +8940,6 @@ body: |
; SI-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s32) from unknown-address + 28, addrspace 5)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<8 x s32>)
- ;
; CI-LABEL: name: test_load_private_v8s32_align32
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -9287,7 +8968,6 @@ body: |
; CI-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s32) from unknown-address + 28, addrspace 5)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<8 x s32>)
- ;
; VI-LABEL: name: test_load_private_v8s32_align32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -9316,7 +8996,6 @@ body: |
; VI-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s32) from unknown-address + 28, addrspace 5)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<8 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v8s32_align32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -9345,7 +9024,6 @@ body: |
; GFX9-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s32) from unknown-address + 28, addrspace 5)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<8 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v8s32_align32
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -9374,7 +9052,6 @@ body: |
; GFX10-NEXT: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s32) from unknown-address + 28, addrspace 5)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<8 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v8s32_align32
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -9448,7 +9125,6 @@ body: |
; SI-NEXT: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s32) from unknown-address + 60, addrspace 5)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32), [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BUILD_VECTOR]](<16 x s32>)
- ;
; CI-LABEL: name: test_load_private_v16s32_align32
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -9501,7 +9177,6 @@ body: |
; CI-NEXT: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s32) from unknown-address + 60, addrspace 5)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32), [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BUILD_VECTOR]](<16 x s32>)
- ;
; VI-LABEL: name: test_load_private_v16s32_align32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -9554,7 +9229,6 @@ body: |
; VI-NEXT: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s32) from unknown-address + 60, addrspace 5)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32), [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BUILD_VECTOR]](<16 x s32>)
- ;
; GFX9-LABEL: name: test_load_private_v16s32_align32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -9607,7 +9281,6 @@ body: |
; GFX9-NEXT: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s32) from unknown-address + 60, addrspace 5)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32), [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BUILD_VECTOR]](<16 x s32>)
- ;
; GFX10-LABEL: name: test_load_private_v16s32_align32
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -9660,7 +9333,6 @@ body: |
; GFX10-NEXT: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s32) from unknown-address + 60, addrspace 5)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32), [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BUILD_VECTOR]](<16 x s32>)
- ;
; GFX11-LABEL: name: test_load_private_v16s32_align32
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -9705,7 +9377,6 @@ body: |
; SI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; CI-LABEL: name: test_load_private_v2s64_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -9723,7 +9394,6 @@ body: |
; CI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_private_v2s64_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -9741,7 +9411,6 @@ body: |
; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_load_private_v2s64_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -9759,7 +9428,6 @@ body: |
; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX10-LABEL: name: test_load_private_v2s64_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -9777,7 +9445,6 @@ body: |
; GFX10-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX11-LABEL: name: test_load_private_v2s64_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -9863,7 +9530,6 @@ body: |
; SI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR8]](s32), [[OR11]](s32)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; CI-LABEL: name: test_load_private_v2s64_align16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -9932,7 +9598,6 @@ body: |
; CI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR8]](s32), [[OR11]](s32)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_load_private_v2s64_align16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -10001,7 +9666,6 @@ body: |
; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR8]](s32), [[OR11]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_load_private_v2s64_align16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -10070,7 +9734,6 @@ body: |
; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR8]](s32), [[OR11]](s32)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX10-LABEL: name: test_load_private_v2s64_align16
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -10139,7 +9802,6 @@ body: |
; GFX10-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR8]](s32), [[OR11]](s32)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX11-LABEL: name: test_load_private_v2s64_align16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -10182,7 +9844,6 @@ body: |
; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[UV3]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; CI-LABEL: name: test_load_private_v3s64_align32
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -10208,7 +9869,6 @@ body: |
; CI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[UV3]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_private_v3s64_align32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -10234,7 +9894,6 @@ body: |
; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[UV3]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_private_v3s64_align32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -10260,7 +9919,6 @@ body: |
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[UV3]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX10-LABEL: name: test_load_private_v3s64_align32
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -10286,7 +9944,6 @@ body: |
; GFX10-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[UV3]](s64)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX11-LABEL: name: test_load_private_v3s64_align32
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -10342,7 +9999,6 @@ body: |
; SI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD6]](s32), [[LOAD7]](s32)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; CI-LABEL: name: test_load_private_v4s64_align32
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -10372,7 +10028,6 @@ body: |
; CI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD6]](s32), [[LOAD7]](s32)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_load_private_v4s64_align32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -10402,7 +10057,6 @@ body: |
; VI-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD6]](s32), [[LOAD7]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_load_private_v4s64_align32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -10432,7 +10086,6 @@ body: |
; GFX9-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD6]](s32), [[LOAD7]](s32)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX10-LABEL: name: test_load_private_v4s64_align32
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -10462,7 +10115,6 @@ body: |
; GFX10-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD6]](s32), [[LOAD7]](s32)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX11-LABEL: name: test_load_private_v4s64_align32
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -10501,7 +10153,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; CI-LABEL: name: test_load_private_v2p1_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -10519,7 +10170,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; VI-LABEL: name: test_load_private_v2p1_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -10537,7 +10187,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX9-LABEL: name: test_load_private_v2p1_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -10555,7 +10204,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX10-LABEL: name: test_load_private_v2p1_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -10573,7 +10221,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p1>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](<2 x p1>)
- ;
; GFX11-LABEL: name: test_load_private_v2p1_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -10621,7 +10268,6 @@ body: |
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x p1>) = G_BITCAST [[BUILD_VECTOR]](<8 x s32>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<4 x p1>)
- ;
; CI-LABEL: name: test_load_private_v4p1_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -10651,7 +10297,6 @@ body: |
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x p1>) = G_BITCAST [[BUILD_VECTOR]](<8 x s32>)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<4 x p1>)
- ;
; VI-LABEL: name: test_load_private_v4p1_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -10681,7 +10326,6 @@ body: |
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x p1>) = G_BITCAST [[BUILD_VECTOR]](<8 x s32>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<4 x p1>)
- ;
; GFX9-LABEL: name: test_load_private_v4p1_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -10711,7 +10355,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x p1>) = G_BITCAST [[BUILD_VECTOR]](<8 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<4 x p1>)
- ;
; GFX10-LABEL: name: test_load_private_v4p1_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -10741,7 +10384,6 @@ body: |
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x p1>) = G_BITCAST [[BUILD_VECTOR]](<8 x s32>)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BITCAST]](<4 x p1>)
- ;
; GFX11-LABEL: name: test_load_private_v4p1_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -10774,7 +10416,6 @@ body: |
; SI-NEXT: [[LOAD1:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p5) :: (load (p3) from unknown-address + 4, addrspace 5)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[LOAD]](p3), [[LOAD1]](p3)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; CI-LABEL: name: test_load_private_v2p3_align8
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -10785,7 +10426,6 @@ body: |
; CI-NEXT: [[LOAD1:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p5) :: (load (p3) from unknown-address + 4, addrspace 5)
; CI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[LOAD]](p3), [[LOAD1]](p3)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; VI-LABEL: name: test_load_private_v2p3_align8
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -10796,7 +10436,6 @@ body: |
; VI-NEXT: [[LOAD1:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p5) :: (load (p3) from unknown-address + 4, addrspace 5)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[LOAD]](p3), [[LOAD1]](p3)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; GFX9-LABEL: name: test_load_private_v2p3_align8
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -10807,7 +10446,6 @@ body: |
; GFX9-NEXT: [[LOAD1:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p5) :: (load (p3) from unknown-address + 4, addrspace 5)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[LOAD]](p3), [[LOAD1]](p3)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; GFX10-LABEL: name: test_load_private_v2p3_align8
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -10818,7 +10456,6 @@ body: |
; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p5) :: (load (p3) from unknown-address + 4, addrspace 5)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[LOAD]](p3), [[LOAD1]](p3)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
- ;
; GFX11-LABEL: name: test_load_private_v2p3_align8
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -10842,35 +10479,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_ext_load_private_s32_from_1_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_ext_load_private_s32_from_1_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_ext_load_private_s32_from_1_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_ext_load_private_s32_from_1_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_ext_load_private_s32_from_1_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -10894,35 +10526,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; CI-LABEL: name: test_ext_load_private_s32_from_2_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; VI-LABEL: name: test_ext_load_private_s32_from_2_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX9-LABEL: name: test_ext_load_private_s32_from_2_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX10-LABEL: name: test_ext_load_private_s32_from_2_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; GFX10-NEXT: $vgpr0 = COPY [[LOAD]](s32)
- ;
; GFX11-LABEL: name: test_ext_load_private_s32_from_2_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -10948,7 +10575,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-LABEL: name: test_ext_load_private_s64_from_1_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -10956,7 +10582,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_private_s64_from_1_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -10964,7 +10589,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_ext_load_private_s64_from_1_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -10972,7 +10596,6 @@ body: |
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX10-LABEL: name: test_ext_load_private_s64_from_1_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -10980,7 +10603,6 @@ body: |
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX11-LABEL: name: test_ext_load_private_s64_from_1_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -11006,7 +10628,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-LABEL: name: test_ext_load_private_s64_from_2_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -11014,7 +10635,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_private_s64_from_2_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -11022,7 +10642,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_ext_load_private_s64_from_2_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -11030,7 +10649,6 @@ body: |
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX10-LABEL: name: test_ext_load_private_s64_from_2_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -11038,7 +10656,6 @@ body: |
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX11-LABEL: name: test_ext_load_private_s64_from_2_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -11064,7 +10681,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-LABEL: name: test_ext_load_private_s64_from_4_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -11072,7 +10688,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_private_s64_from_4_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -11080,7 +10695,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_ext_load_private_s64_from_4_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -11088,7 +10702,6 @@ body: |
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX10-LABEL: name: test_ext_load_private_s64_from_4_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -11096,7 +10709,6 @@ body: |
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX11-LABEL: name: test_ext_load_private_s64_from_4_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -11125,7 +10737,6 @@ body: |
; SI-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; SI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; CI-LABEL: name: test_ext_load_private_s128_from_4_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -11136,7 +10747,6 @@ body: |
; CI-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; VI-LABEL: name: test_ext_load_private_s128_from_4_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -11147,7 +10757,6 @@ body: |
; VI-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; VI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; GFX9-LABEL: name: test_ext_load_private_s128_from_4_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -11158,7 +10767,6 @@ body: |
; GFX9-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; GFX10-LABEL: name: test_ext_load_private_s128_from_4_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -11169,7 +10777,6 @@ body: |
; GFX10-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; GFX10-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV1]](s128)
- ;
; GFX11-LABEL: name: test_ext_load_private_s128_from_4_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -11198,7 +10805,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-LABEL: name: test_ext_load_private_s64_from_2_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -11206,7 +10812,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_private_s64_from_2_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -11214,7 +10819,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_ext_load_private_s64_from_2_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -11222,7 +10826,6 @@ body: |
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX10-LABEL: name: test_ext_load_private_s64_from_2_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -11230,7 +10833,6 @@ body: |
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX11-LABEL: name: test_ext_load_private_s64_from_2_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -11256,7 +10858,6 @@ body: |
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; CI-LABEL: name: test_ext_load_private_s64_from_1_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -11264,7 +10865,6 @@ body: |
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; VI-LABEL: name: test_ext_load_private_s64_from_1_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -11272,7 +10872,6 @@ body: |
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX9-LABEL: name: test_ext_load_private_s64_from_1_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -11280,7 +10879,6 @@ body: |
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX10-LABEL: name: test_ext_load_private_s64_from_1_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -11288,7 +10886,6 @@ body: |
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
- ;
; GFX11-LABEL: name: test_ext_load_private_s64_from_1_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -11313,35 +10910,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), align 1, addrspace 5)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-LABEL: name: test_extload_private_v2s32_from_4_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), align 1, addrspace 5)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_extload_private_v2s32_from_4_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), align 1, addrspace 5)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_extload_private_v2s32_from_4_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), align 1, addrspace 5)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_extload_private_v2s32_from_4_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), align 1, addrspace 5)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_extload_private_v2s32_from_4_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -11365,35 +10957,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), align 2, addrspace 5)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-LABEL: name: test_extload_private_v2s32_from_4_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), align 2, addrspace 5)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_extload_private_v2s32_from_4_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), align 2, addrspace 5)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_extload_private_v2s32_from_4_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), align 2, addrspace 5)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_extload_private_v2s32_from_4_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), align 2, addrspace 5)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_extload_private_v2s32_from_4_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -11417,35 +11004,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), addrspace 5)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; CI-LABEL: name: test_extload_private_v2s32_from_4_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), addrspace 5)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; VI-LABEL: name: test_extload_private_v2s32_from_4_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), addrspace 5)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_extload_private_v2s32_from_4_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), addrspace 5)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_extload_private_v2s32_from_4_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p5) :: (load (<2 x s16>), addrspace 5)
; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
- ;
; GFX11-LABEL: name: test_extload_private_v2s32_from_4_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -11469,35 +11051,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p5) :: (load (<3 x s16>), align 4, addrspace 5)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; CI-LABEL: name: test_extload_private_v3s32_from_6_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p5) :: (load (<3 x s16>), align 4, addrspace 5)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; VI-LABEL: name: test_extload_private_v3s32_from_6_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p5) :: (load (<3 x s16>), align 4, addrspace 5)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_extload_private_v3s32_from_6_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p5) :: (load (<3 x s16>), align 4, addrspace 5)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX10-LABEL: name: test_extload_private_v3s32_from_6_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p5) :: (load (<3 x s16>), align 4, addrspace 5)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
- ;
; GFX11-LABEL: name: test_extload_private_v3s32_from_6_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -11521,35 +11098,30 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p5) :: (load (<4 x s16>), align 4, addrspace 5)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; CI-LABEL: name: test_extload_private_v4s32_from_8_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p5) :: (load (<4 x s16>), align 4, addrspace 5)
; CI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; VI-LABEL: name: test_extload_private_v4s32_from_8_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p5) :: (load (<4 x s16>), align 4, addrspace 5)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX9-LABEL: name: test_extload_private_v4s32_from_8_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p5) :: (load (<4 x s16>), align 4, addrspace 5)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX10-LABEL: name: test_extload_private_v4s32_from_8_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p5) :: (load (<4 x s16>), align 4, addrspace 5)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
- ;
; GFX11-LABEL: name: test_extload_private_v4s32_from_8_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -11668,7 +11240,6 @@ body: |
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; SI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-LABEL: name: test_load_private_v2s96_align1
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -11770,7 +11341,6 @@ body: |
; CI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_load_private_v2s96_align1
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -11872,7 +11442,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-LABEL: name: test_load_private_v2s96_align1
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -11974,7 +11543,6 @@ body: |
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX10-LABEL: name: test_load_private_v2s96_align1
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -12076,7 +11644,6 @@ body: |
; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX10-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX11-LABEL: name: test_load_private_v2s96_align1
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -12157,7 +11724,6 @@ body: |
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; SI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-LABEL: name: test_load_private_v2s96_align2
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -12210,7 +11776,6 @@ body: |
; CI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_load_private_v2s96_align2
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -12263,7 +11828,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-LABEL: name: test_load_private_v2s96_align2
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -12316,7 +11880,6 @@ body: |
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX10-LABEL: name: test_load_private_v2s96_align2
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -12369,7 +11932,6 @@ body: |
; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX10-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX11-LABEL: name: test_load_private_v2s96_align2
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -12424,7 +11986,6 @@ body: |
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; SI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-LABEL: name: test_load_private_v2s96_align4
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -12451,7 +12012,6 @@ body: |
; CI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_load_private_v2s96_align4
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -12478,7 +12038,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-LABEL: name: test_load_private_v2s96_align4
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -12505,7 +12064,6 @@ body: |
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX10-LABEL: name: test_load_private_v2s96_align4
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -12532,7 +12090,6 @@ body: |
; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX10-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX11-LABEL: name: test_load_private_v2s96_align4
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
@@ -12587,7 +12144,6 @@ body: |
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; SI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; CI-LABEL: name: test_load_private_v2s96_align16
; CI: liveins: $vgpr0
; CI-NEXT: {{ $}}
@@ -12614,7 +12170,6 @@ body: |
; CI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; CI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; CI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; VI-LABEL: name: test_load_private_v2s96_align16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
@@ -12641,7 +12196,6 @@ body: |
; VI-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; VI-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX9-LABEL: name: test_load_private_v2s96_align16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
@@ -12668,7 +12222,6 @@ body: |
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX9-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX10-LABEL: name: test_load_private_v2s96_align16
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
@@ -12695,7 +12248,6 @@ body: |
; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
; GFX10-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
; GFX10-NEXT: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
- ;
; GFX11-LABEL: name: test_load_private_v2s96_align16
; GFX11: liveins: $vgpr0
; GFX11-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
index 3ec9a48b02e69ca..8b2d986682c7104 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
@@ -18,7 +18,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[LSHR]](s32)
- ;
; VI-LABEL: name: test_lshr_s32_s32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -26,7 +25,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
; VI-NEXT: $vgpr0 = COPY [[LSHR]](s32)
- ;
; GFX9-LABEL: name: test_lshr_s32_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -53,7 +51,6 @@ body: |
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
- ;
; VI-LABEL: name: test_lshr_s64_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -62,7 +59,6 @@ body: |
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
- ;
; GFX9-LABEL: name: test_lshr_s64_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -89,7 +85,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
- ;
; VI-LABEL: name: test_lshr_s64_s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -97,7 +92,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
- ;
; GFX9-LABEL: name: test_lshr_s64_s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -125,7 +119,6 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
- ;
; VI-LABEL: name: test_lshr_s64_s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -135,7 +128,6 @@ body: |
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
- ;
; GFX9-LABEL: name: test_lshr_s64_s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -167,7 +159,6 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[LSHR]](s32)
- ;
; VI-LABEL: name: test_lshr_s16_s32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -178,7 +169,6 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_lshr_s16_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -213,7 +203,6 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
; SI-NEXT: $vgpr0 = COPY [[LSHR]](s32)
- ;
; VI-LABEL: name: test_lshr_s16_s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -224,7 +213,6 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_lshr_s16_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -261,28 +249,26 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
; SI-NEXT: $vgpr0 = COPY [[LSHR]](s32)
- ;
; VI-LABEL: name: test_lshr_s16_i8
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_lshr_s16_i8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s16)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
@@ -312,28 +298,26 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
; SI-NEXT: $vgpr0 = COPY [[LSHR]](s32)
- ;
; VI-LABEL: name: test_lshr_i8_i8
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND1]], [[AND]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_lshr_i8_i8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -366,7 +350,6 @@ body: |
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[UV3]](s32)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LSHR]](s32), [[LSHR1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_lshr_v2s32_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -378,7 +361,6 @@ body: |
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[UV3]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LSHR]](s32), [[LSHR1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_lshr_v2s32_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -414,7 +396,6 @@ body: |
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[UV5]](s32)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_lshr_v3s32_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -427,7 +408,6 @@ body: |
; VI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[UV5]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_lshr_v3s32_v3s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -463,7 +443,6 @@ body: |
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[UV3]](s32)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LSHR]](s64), [[LSHR1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_lshr_v2s64_v2s32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -475,7 +454,6 @@ body: |
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[UV3]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LSHR]](s64), [[LSHR1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_lshr_v2s64_v2s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -513,7 +491,6 @@ body: |
; SI-NEXT: [[UV7:%[0-9]+]]:_(s64), [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64), [[UV10:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[LSHR]](s64), [[LSHR1]](s64), [[LSHR2]](s64), [[UV10]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_lshr_v3s64_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; VI-NEXT: {{ $}}
@@ -528,7 +505,6 @@ body: |
; VI-NEXT: [[UV7:%[0-9]+]]:_(s64), [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64), [[UV10:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[LSHR]](s64), [[LSHR1]](s64), [[LSHR2]](s64), [[UV10]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_lshr_v3s64_v3s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; GFX9-NEXT: {{ $}}
@@ -572,14 +548,15 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[LSHR1]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; VI-LABEL: name: test_lshr_v2s16_v2s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -602,7 +579,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_lshr_v2s16_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -634,14 +610,14 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[UV]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[UV1]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[UV1]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; VI-LABEL: name: test_lshr_v2s16_v2s32
; VI: liveins: $vgpr0, $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -663,7 +639,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_lshr_v2s16_v2s32
; GFX9: liveins: $vgpr0, $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -711,26 +686,28 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[LSHR1]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[AND4]](s32)
; SI-NEXT: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; SI-NEXT: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL]]
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR5]], [[C]](s32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL1]]
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL1]]
; SI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_lshr_v3s16_v3s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -764,12 +741,13 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[LSHR4]](s16)
- ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR5]], [[C]](s32)
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
+ ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_lshr_v3s16_v3s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -832,32 +810,34 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[LSHR1]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[AND4]](s32)
; SI-NEXT: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; SI-NEXT: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>)
; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL]]
; SI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
- ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL1]]
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL1]]
; SI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[SHL2]]
+ ; SI-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
+ ; SI-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C]](s32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL2]]
; SI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_ashr_v3s16_v3s16
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -897,13 +877,13 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[SHL2]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_ashr_v3s16_v3s16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -973,24 +953,27 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[LSHR2]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[LSHR3]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[AND4]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[AND6]](s32)
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
- ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C1]]
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL1]]
+ ; SI-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
+ ; SI-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C1]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C]](s32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL1]]
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_lshr_v4s16_v4s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -1031,7 +1014,6 @@ body: |
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_lshr_v4s16_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1060,70 +1042,68 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
+ ; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
+ ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[COPY1]](s32)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[COPY1]](s32)
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[SUB1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
- ; SI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[SUB]](s32)
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[LSHR2]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV]], [[SELECT]]
- ; SI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[LSHR]], [[C2]]
+ ; SI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[LSHR]], [[C1]]
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_lshr_s128_s128
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; VI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
+ ; VI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
+ ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[COPY1]](s32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[COPY1]](s32)
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[SUB1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
- ; VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[SUB]](s32)
; VI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[LSHR2]]
; VI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV]], [[SELECT]]
- ; VI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[LSHR]], [[C2]]
+ ; VI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[LSHR]], [[C1]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9-LABEL: name: test_lshr_s128_s128
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
+ ; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
+ ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[COPY1]](s32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[COPY1]](s32)
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[SUB1]](s32)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[SUB]](s32)
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[LSHR2]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV]], [[SELECT]]
- ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[LSHR]], [[C2]]
+ ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[LSHR]], [[C1]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
@@ -1162,7 +1142,6 @@ body: |
; SI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[LSHR]], [[C2]]
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_lshr_s128_s132
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1186,7 +1165,6 @@ body: |
; VI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[LSHR]], [[C2]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9-LABEL: name: test_lshr_s128_s132
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
@@ -1227,13 +1205,11 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY]](s128)
- ;
; VI-LABEL: name: test_lshr_s128_s32_0
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY]](s128)
- ;
; GFX9-LABEL: name: test_lshr_s128_s32_0
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
@@ -1265,7 +1241,6 @@ body: |
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_lshr_s128_s32_23
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1279,7 +1254,6 @@ body: |
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9-LABEL: name: test_lshr_s128_s32_23
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
@@ -1318,7 +1292,6 @@ body: |
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_lshr_s128_s32_31
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1332,7 +1305,6 @@ body: |
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9-LABEL: name: test_lshr_s128_s32_31
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
@@ -1370,7 +1342,6 @@ body: |
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_lshr_s128_s32_32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1383,7 +1354,6 @@ body: |
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9-LABEL: name: test_lshr_s128_s32_32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
@@ -1421,7 +1391,6 @@ body: |
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_lshr_s128_s32_33
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1435,7 +1404,6 @@ body: |
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[C]](s32)
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[LSHR1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9-LABEL: name: test_lshr_s128_s32_33
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
@@ -1471,7 +1439,6 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LSHR]](s64), [[C1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_lshr_s128_s32_127
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1482,7 +1449,6 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LSHR]](s64), [[C1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9-LABEL: name: test_lshr_s128_s32_127
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
@@ -1510,33 +1476,33 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
+ ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; SI-NEXT: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](s256)
- ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
- ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
+ ; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
+ ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; SI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; SI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; SI-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; SI-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; SI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; SI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; SI-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; SI-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[COPY1]](s32)
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[COPY1]](s32)
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[SUB3]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
- ; SI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[SUB2]](s32)
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[LSHR2]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]]
- ; SI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR]], [[C3]]
+ ; SI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR]], [[C1]]
; SI-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
- ; SI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; SI-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; SI-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; SI-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; SI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; SI-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; SI-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; SI-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[COPY1]](s32)
; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[COPY1]](s32)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32)
@@ -1544,27 +1510,27 @@ body: |
; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
; SI-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR5]]
; SI-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]]
- ; SI-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR3]], [[C3]]
+ ; SI-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR3]], [[C1]]
; SI-NEXT: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; SI-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
- ; SI-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
- ; SI-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
- ; SI-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
+ ; SI-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C3]]
+ ; SI-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB1]]
+ ; SI-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C3]]
+ ; SI-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C]]
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB1]](s32)
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB7]](s32)
; SI-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR6]], [[SHL3]]
; SI-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB6]](s32)
- ; SI-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C3]]
+ ; SI-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C1]]
; SI-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[SHL4]]
; SI-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV7]], [[SELECT7]]
; SI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT6]]
; SI-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; SI-NEXT: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; SI-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
- ; SI-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
- ; SI-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
- ; SI-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
+ ; SI-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C3]]
+ ; SI-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB]]
+ ; SI-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C3]]
+ ; SI-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C]]
; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB]](s32)
; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB]](s32)
; SI-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB9]](s32)
@@ -1572,51 +1538,50 @@ body: |
; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB8]](s32)
; SI-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[LSHR9]]
; SI-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV8]], [[SELECT9]]
- ; SI-NEXT: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[LSHR7]], [[C3]]
+ ; SI-NEXT: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[LSHR7]], [[C1]]
; SI-NEXT: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT10]]
; SI-NEXT: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]]
; SI-NEXT: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; SI-NEXT: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV10]], [[SELECT12]]
; SI-NEXT: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV11]], [[SELECT13]]
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT14]](s64), [[SELECT15]](s64)
- ; SI-NEXT: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT1]], [[C3]]
- ; SI-NEXT: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C3]]
+ ; SI-NEXT: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT1]], [[C1]]
+ ; SI-NEXT: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C1]]
; SI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64)
; SI-NEXT: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV2]](s256)
- ;
; VI-LABEL: name: test_lshr_s256_s256
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
+ ; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; VI-NEXT: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](s256)
- ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; VI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
- ; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
+ ; VI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
+ ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; VI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; VI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; VI-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; VI-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; VI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; VI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; VI-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; VI-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[COPY1]](s32)
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[COPY1]](s32)
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[SUB3]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
- ; VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[SUB2]](s32)
; VI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[LSHR2]]
; VI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]]
- ; VI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR]], [[C3]]
+ ; VI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR]], [[C1]]
; VI-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
- ; VI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; VI-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; VI-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; VI-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; VI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; VI-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; VI-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; VI-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; VI-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[COPY1]](s32)
; VI-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[COPY1]](s32)
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32)
@@ -1624,27 +1589,27 @@ body: |
; VI-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
; VI-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR5]]
; VI-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]]
- ; VI-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR3]], [[C3]]
+ ; VI-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR3]], [[C1]]
; VI-NEXT: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; VI-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
- ; VI-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
- ; VI-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
- ; VI-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
+ ; VI-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C3]]
+ ; VI-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB1]]
+ ; VI-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C3]]
+ ; VI-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C]]
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB1]](s32)
; VI-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB7]](s32)
; VI-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR6]], [[SHL3]]
; VI-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB6]](s32)
- ; VI-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C3]]
+ ; VI-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C1]]
; VI-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[SHL4]]
; VI-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV7]], [[SELECT7]]
; VI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT6]]
; VI-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; VI-NEXT: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; VI-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
- ; VI-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
- ; VI-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
- ; VI-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
+ ; VI-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C3]]
+ ; VI-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB]]
+ ; VI-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C3]]
+ ; VI-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C]]
; VI-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB]](s32)
; VI-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB]](s32)
; VI-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB9]](s32)
@@ -1652,51 +1617,50 @@ body: |
; VI-NEXT: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB8]](s32)
; VI-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[LSHR9]]
; VI-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV8]], [[SELECT9]]
- ; VI-NEXT: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[LSHR7]], [[C3]]
+ ; VI-NEXT: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[LSHR7]], [[C1]]
; VI-NEXT: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT10]]
; VI-NEXT: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]]
; VI-NEXT: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; VI-NEXT: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV10]], [[SELECT12]]
; VI-NEXT: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV11]], [[SELECT13]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT14]](s64), [[SELECT15]](s64)
- ; VI-NEXT: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT1]], [[C3]]
- ; VI-NEXT: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C3]]
+ ; VI-NEXT: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT1]], [[C1]]
+ ; VI-NEXT: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C1]]
; VI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64)
; VI-NEXT: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV2]](s256)
- ;
; GFX9-LABEL: name: test_lshr_s256_s256
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](s256)
- ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
+ ; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
+ ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; GFX9-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; GFX9-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; GFX9-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; GFX9-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[COPY1]](s32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[COPY1]](s32)
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[SUB3]](s32)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV3]], [[SUB2]](s32)
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[LSHR2]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV2]], [[SELECT]]
- ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR]], [[C3]]
+ ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[LSHR]], [[C1]]
; GFX9-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
- ; GFX9-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; GFX9-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; GFX9-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; GFX9-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[COPY1]](s32)
; GFX9-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[COPY1]](s32)
; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32)
@@ -1704,27 +1668,27 @@ body: |
; GFX9-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR5]]
; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]]
- ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR3]], [[C3]]
+ ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR3]], [[C1]]
; GFX9-NEXT: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; GFX9-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
- ; GFX9-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
- ; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
- ; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
+ ; GFX9-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C3]]
+ ; GFX9-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB1]]
+ ; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C3]]
+ ; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C]]
; GFX9-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB1]](s32)
; GFX9-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB7]](s32)
; GFX9-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[SUB1]](s32)
; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR6]], [[SHL3]]
; GFX9-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB6]](s32)
- ; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C3]]
+ ; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL2]], [[C1]]
; GFX9-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[SHL4]]
; GFX9-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV7]], [[SELECT7]]
; GFX9-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT6]]
; GFX9-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; GFX9-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
- ; GFX9-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
- ; GFX9-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
- ; GFX9-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
+ ; GFX9-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C3]]
+ ; GFX9-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB]]
+ ; GFX9-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C3]]
+ ; GFX9-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C]]
; GFX9-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB]](s32)
; GFX9-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB]](s32)
; GFX9-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB9]](s32)
@@ -1732,15 +1696,15 @@ body: |
; GFX9-NEXT: [[LSHR9:%[0-9]+]]:_(s64) = G_LSHR [[UV9]], [[SUB8]](s32)
; GFX9-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[LSHR9]]
; GFX9-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV8]], [[SELECT9]]
- ; GFX9-NEXT: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[LSHR7]], [[C3]]
+ ; GFX9-NEXT: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[LSHR7]], [[C1]]
; GFX9-NEXT: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT10]]
; GFX9-NEXT: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]]
; GFX9-NEXT: [[UV10:%[0-9]+]]:_(s64), [[UV11:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
; GFX9-NEXT: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV10]], [[SELECT12]]
; GFX9-NEXT: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV11]], [[SELECT13]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT14]](s64), [[SELECT15]](s64)
- ; GFX9-NEXT: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT1]], [[C3]]
- ; GFX9-NEXT: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C3]]
+ ; GFX9-NEXT: [[SELECT16:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT1]], [[C1]]
+ ; GFX9-NEXT: [[SELECT17:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C1]]
; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64)
; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV2]](s256)
@@ -1797,7 +1761,6 @@ body: |
; SI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
- ;
; VI-LABEL: name: test_lshr_v2s128_v2s32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -1838,7 +1801,6 @@ body: |
; VI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT4]](s64), [[SELECT5]](s64)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
- ;
; GFX9-LABEL: name: test_lshr_v2s128_v2s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -1897,12 +1859,12 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %23(s64)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
; SI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; SI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; SI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C1]]
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
@@ -1923,19 +1885,18 @@ body: |
; SI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
- ;
; VI-LABEL: name: test_lshr_s65_s32
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %23(s64)
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C1]]
; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
@@ -1956,19 +1917,18 @@ body: |
; VI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
- ;
; GFX9-LABEL: name: test_lshr_s65_s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %23(s64)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C1]]
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
@@ -2008,12 +1968,12 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %23(s64)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
; SI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; SI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; SI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C1]]
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
@@ -2034,18 +1994,17 @@ body: |
; SI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
- ;
; VI-LABEL: name: test_lshr_s65_s32_constant8
; VI: liveins: $vgpr0_vgpr1_vgpr2
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %23(s64)
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C1]]
; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
@@ -2066,18 +2025,17 @@ body: |
; VI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
- ;
; GFX9-LABEL: name: test_lshr_s65_s32_constant8
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %23(s64)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C1]]
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
@@ -2119,12 +2077,12 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[COPY1]](s32)
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; SI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
; SI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; SI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; SI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; SI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C2]]
; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
@@ -2145,7 +2103,6 @@ body: |
; SI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
- ;
; VI-LABEL: name: test_lshr_s65_s32_known_pow2
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; VI-NEXT: {{ $}}
@@ -2153,12 +2110,12 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[COPY1]](s32)
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; VI-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; VI-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C1]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C2]]
; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
@@ -2179,7 +2136,6 @@ body: |
; VI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT1]](s64), [[SELECT2]](s64)
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
- ;
; GFX9-LABEL: name: test_lshr_s65_s32_known_pow2
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; GFX9-NEXT: {{ $}}
@@ -2187,12 +2143,12 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[COPY1]](s32)
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[MV]], [[C1]]
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[MV1]], [[C2]]
; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
index 70f7e7ae623c396..c1b3b758c22cf90 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
@@ -23,8 +23,8 @@ body: |
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
@@ -91,11 +91,14 @@ body: |
bb.0:
; CHECK-LABEL: name: test_merge_s16_s8_s8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C2]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[C2]], [[C1]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C3]](s32)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[C1]], [[TRUNC]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s8) = G_CONSTANT i8 0
@@ -112,22 +115,26 @@ body: |
; CHECK-LABEL: name: test_merge_s24_s8_s8_s8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[COPY]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[C1]], [[TRUNC]]
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[C2]], [[C1]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[C5]], [[C1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C3]](s32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[C3]], [[TRUNC1]]
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND1]], [[TRUNC1]]
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C6]](s32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; CHECK-NEXT: $vgpr0 = COPY [[OR2]](s32)
%0:_(s8) = G_CONSTANT i8 0
@@ -147,14 +154,18 @@ body: |
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C4]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C]], [[SHL]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C4]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[SHL]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C5]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C5]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C6]](s32)
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C6]](s32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK-NEXT: $vgpr0 = COPY [[OR2]](s32)
%0:_(s8) = G_CONSTANT i8 0
@@ -231,40 +242,47 @@ body: |
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[C6]], [[C5]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[COPY]](s32)
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY]](s32)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[C5]], [[TRUNC]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[COPY1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[COPY2]](s32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC1]]
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[COPY2]](s32)
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[COPY4]](s32)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC2]]
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s16) = COPY [[C6]](s16)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[COPY4]](s32)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s16) = COPY [[C7]](s16)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C5]]
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[COPY7]](s32)
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[COPY3]], [[TRUNC3]]
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C9]]
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C7]](s32)
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND1]], [[TRUNC3]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C8]]
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C9]](s32)
; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[TRUNC4]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C9]]
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C8]](s32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C8]]
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C10]](s32)
; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[TRUNC5]]
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR5]](s16)
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C10]](s32)
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C11]](s32)
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL6]]
; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s24) = G_TRUNC [[OR6]](s32)
; CHECK-NEXT: S_NOP 0, implicit [[TRUNC6]](s24)
@@ -290,39 +308,47 @@ body: |
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[C7]], [[C6]]
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[COPY]](s32)
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY]](s32)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[C6]], [[TRUNC]]
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[COPY1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[COPY2]](s32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC1]]
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[COPY2]](s32)
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[COPY4]](s32)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC2]]
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s16) = COPY [[C7]](s16)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[COPY4]](s32)
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s16) = COPY [[C8]](s16)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C6]]
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[COPY7]](s32)
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[COPY3]], [[TRUNC3]]
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[C5]], [[C8]](s32)
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND1]], [[TRUNC3]]
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C10]](s32)
; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[TRUNC4]]
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C10]]
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C9]](s32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C9]]
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C11]](s32)
; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[TRUNC5]]
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR5]](s16)
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C11]](s32)
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C12]](s32)
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL6]]
; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s28) = G_TRUNC [[OR6]](s32)
; CHECK-NEXT: S_NOP 0, implicit [[TRUNC6]](s28)
@@ -350,25 +376,33 @@ body: |
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C4]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C]], [[SHL]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C4]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[SHL]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C8]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C8]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C9]](s32)
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C9]](s32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[C10]](s32)
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C10]](s32)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[C5]], [[C11]](s32)
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C11]](s32)
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[C6]], [[C12]](s32)
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C12]](s32)
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[C7]], [[C13]](s32)
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C13]](s32)
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
; CHECK-NEXT: S_NOP 0, implicit [[OR6]](s32)
%0:_(s4) = G_CONSTANT i4 0
@@ -392,34 +426,43 @@ body: |
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[COPY]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[C5]], [[C4]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY]](s32)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[C4]], [[TRUNC]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[COPY1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[C7]], [[C4]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[COPY2]](s32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[C6]], [[TRUNC1]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[COPY2]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND1]], [[TRUNC1]]
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C8]], [[C4]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[COPY4]](s32)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[C7]], [[TRUNC2]]
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C5]](s32)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC2]]
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[C9]], [[C4]]
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C6]](s32)
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[C8]], [[TRUNC3]]
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[TRUNC3]]
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C9]](s32)
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C10]](s32)
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C9]](s32)
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C10]](s32)
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL5]]
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR4]](s32), [[OR5]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
@@ -447,49 +490,62 @@ body: |
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[C8]], [[C7]]
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY]](s32)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[C7]], [[TRUNC]]
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[COPY1]](s32)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[C9]], [[TRUNC1]]
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[C10]], [[C7]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[COPY2]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[COPY2]](s32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND1]], [[TRUNC1]]
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C11]], [[C7]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[COPY4]](s32)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[C10]], [[TRUNC2]]
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[COPY3]](s32)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC2]]
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[C12]], [[C7]]
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[COPY6]](s32)
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[C11]], [[TRUNC3]]
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s16) = COPY [[C8]](s16)
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[C5]], [[COPY5]](s32)
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[TRUNC3]]
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s16) = COPY [[C9]](s16)
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C7]]
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[COPY9]](s32)
; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
- ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s16) = G_OR [[COPY4]], [[TRUNC4]]
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 10
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[C6]], [[COPY6]](s32)
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC4]]
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s16) = G_CONSTANT i16 10
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[C13]], [[C7]]
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY12]], [[COPY11]](s32)
; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
- ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s16) = G_OR [[C12]], [[TRUNC5]]
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s16) = G_OR [[AND5]], [[TRUNC5]]
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C13]](s32)
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C14]](s32)
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL6]]
; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
- ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C13]](s32)
+ ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C14]](s32)
; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL7]]
; CHECK-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR4]](s16)
; CHECK-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[OR5]](s16)
- ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[ZEXT5]], [[C13]](s32)
+ ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[ZEXT5]], [[C14]](s32)
; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[ZEXT4]], [[SHL8]]
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[OR6]](s32), [[OR7]](s32), [[OR8]](s32)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
@@ -549,36 +605,44 @@ body: |
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[COPY]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[C4]], [[C3]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY]](s32)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[C3]], [[TRUNC]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[COPY1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[C7]], [[C3]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[COPY2]](s32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[C5]], [[TRUNC1]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[COPY2]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND1]], [[TRUNC1]]
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C8]], [[C3]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[COPY4]](s32)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[C6]], [[TRUNC2]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C8]]
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C4]](s32)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC2]]
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[C9]], [[C3]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C6]]
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C5]](s32)
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[C7]], [[TRUNC3]]
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[TRUNC3]]
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C9]](s32)
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C10]](s32)
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C9]](s32)
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C10]](s32)
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL5]]
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR4]](s32), [[OR5]](s32)
; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s56) = G_TRUNC [[MV]](s64)
@@ -603,249 +667,315 @@ body: |
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C]], [[SHL]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C2]](s32)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[SHL]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C3]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C3]](s32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C4]](s32)
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C4]](s32)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C5]](s32)
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C5]](s32)
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C6]](s32)
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C6]](s32)
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C7]](s32)
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C7]](s32)
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C8]](s32)
+ ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C8]](s32)
; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
- ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C9]](s32)
+ ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C9]](s32)
; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C10]](s32)
+ ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[C10]](s32)
; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]]
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C11]](s32)
+ ; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[COPY11]], [[C11]](s32)
; CHECK-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C12]](s32)
+ ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[COPY12]], [[C12]](s32)
; CHECK-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
+ ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
- ; CHECK-NEXT: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C13]](s32)
+ ; CHECK-NEXT: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[C13]](s32)
; CHECK-NEXT: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]]
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
- ; CHECK-NEXT: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C14]](s32)
+ ; CHECK-NEXT: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[COPY14]], [[C14]](s32)
; CHECK-NEXT: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C15]](s32)
+ ; CHECK-NEXT: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[COPY15]], [[C15]](s32)
; CHECK-NEXT: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
+ ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C16]](s32)
+ ; CHECK-NEXT: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C16]](s32)
; CHECK-NEXT: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
- ; CHECK-NEXT: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C17]](s32)
+ ; CHECK-NEXT: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C17]](s32)
; CHECK-NEXT: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 18
- ; CHECK-NEXT: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C18]](s32)
+ ; CHECK-NEXT: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C18]](s32)
; CHECK-NEXT: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
- ; CHECK-NEXT: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C19]](s32)
+ ; CHECK-NEXT: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C19]](s32)
; CHECK-NEXT: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR17]], [[SHL18]]
+ ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK-NEXT: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C20]](s32)
+ ; CHECK-NEXT: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C20]](s32)
; CHECK-NEXT: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
+ ; CHECK-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C21]](s32)
+ ; CHECK-NEXT: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[COPY21]], [[C21]](s32)
; CHECK-NEXT: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
+ ; CHECK-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 22
- ; CHECK-NEXT: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C22]](s32)
+ ; CHECK-NEXT: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[COPY22]], [[C22]](s32)
; CHECK-NEXT: [[OR21:%[0-9]+]]:_(s32) = G_OR [[OR20]], [[SHL21]]
+ ; CHECK-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
- ; CHECK-NEXT: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C23]](s32)
+ ; CHECK-NEXT: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[COPY23]], [[C23]](s32)
; CHECK-NEXT: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
+ ; CHECK-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C24]](s32)
+ ; CHECK-NEXT: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[COPY24]], [[C24]](s32)
; CHECK-NEXT: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
+ ; CHECK-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C25:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
- ; CHECK-NEXT: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C25]](s32)
+ ; CHECK-NEXT: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[COPY25]], [[C25]](s32)
; CHECK-NEXT: [[OR24:%[0-9]+]]:_(s32) = G_OR [[OR23]], [[SHL24]]
+ ; CHECK-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C26:%[0-9]+]]:_(s32) = G_CONSTANT i32 26
- ; CHECK-NEXT: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C26]](s32)
+ ; CHECK-NEXT: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[COPY26]], [[C26]](s32)
; CHECK-NEXT: [[OR25:%[0-9]+]]:_(s32) = G_OR [[OR24]], [[SHL25]]
+ ; CHECK-NEXT: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C27:%[0-9]+]]:_(s32) = G_CONSTANT i32 27
- ; CHECK-NEXT: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C27]](s32)
+ ; CHECK-NEXT: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[COPY27]], [[C27]](s32)
; CHECK-NEXT: [[OR26:%[0-9]+]]:_(s32) = G_OR [[OR25]], [[SHL26]]
+ ; CHECK-NEXT: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C28:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
- ; CHECK-NEXT: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C28]](s32)
+ ; CHECK-NEXT: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[COPY28]], [[C28]](s32)
; CHECK-NEXT: [[OR27:%[0-9]+]]:_(s32) = G_OR [[OR26]], [[SHL27]]
+ ; CHECK-NEXT: [[COPY29:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C29:%[0-9]+]]:_(s32) = G_CONSTANT i32 29
- ; CHECK-NEXT: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C29]](s32)
+ ; CHECK-NEXT: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[COPY29]], [[C29]](s32)
; CHECK-NEXT: [[OR28:%[0-9]+]]:_(s32) = G_OR [[OR27]], [[SHL28]]
+ ; CHECK-NEXT: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
- ; CHECK-NEXT: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C30]](s32)
+ ; CHECK-NEXT: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[COPY30]], [[C30]](s32)
; CHECK-NEXT: [[OR29:%[0-9]+]]:_(s32) = G_OR [[OR28]], [[SHL29]]
+ ; CHECK-NEXT: [[COPY31:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK-NEXT: [[C31:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; CHECK-NEXT: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C31]](s32)
+ ; CHECK-NEXT: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[COPY31]], [[C31]](s32)
; CHECK-NEXT: [[OR30:%[0-9]+]]:_(s32) = G_OR [[OR29]], [[SHL30]]
- ; CHECK-NEXT: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C1]](s32)
- ; CHECK-NEXT: [[OR31:%[0-9]+]]:_(s32) = G_OR [[C]], [[SHL31]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL32:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32)
+ ; CHECK-NEXT: [[COPY32:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[COPY33:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[COPY33]], [[C1]](s32)
+ ; CHECK-NEXT: [[OR31:%[0-9]+]]:_(s32) = G_OR [[COPY32]], [[SHL31]]
+ ; CHECK-NEXT: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL32:%[0-9]+]]:_(s32) = G_SHL [[COPY34]], [[C2]](s32)
; CHECK-NEXT: [[OR32:%[0-9]+]]:_(s32) = G_OR [[OR31]], [[SHL32]]
- ; CHECK-NEXT: [[SHL33:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C3]](s32)
+ ; CHECK-NEXT: [[COPY35:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[SHL33:%[0-9]+]]:_(s32) = G_SHL [[COPY35]], [[C3]](s32)
; CHECK-NEXT: [[OR33:%[0-9]+]]:_(s32) = G_OR [[OR32]], [[SHL33]]
- ; CHECK-NEXT: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C4]](s32)
+ ; CHECK-NEXT: [[COPY36:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[COPY36]], [[C4]](s32)
; CHECK-NEXT: [[OR34:%[0-9]+]]:_(s32) = G_OR [[OR33]], [[SHL34]]
- ; CHECK-NEXT: [[SHL35:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C5]](s32)
+ ; CHECK-NEXT: [[COPY37:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL35:%[0-9]+]]:_(s32) = G_SHL [[COPY37]], [[C5]](s32)
; CHECK-NEXT: [[OR35:%[0-9]+]]:_(s32) = G_OR [[OR34]], [[SHL35]]
- ; CHECK-NEXT: [[SHL36:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C6]](s32)
+ ; CHECK-NEXT: [[COPY38:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL36:%[0-9]+]]:_(s32) = G_SHL [[COPY38]], [[C6]](s32)
; CHECK-NEXT: [[OR36:%[0-9]+]]:_(s32) = G_OR [[OR35]], [[SHL36]]
- ; CHECK-NEXT: [[SHL37:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C7]](s32)
+ ; CHECK-NEXT: [[COPY39:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL37:%[0-9]+]]:_(s32) = G_SHL [[COPY39]], [[C7]](s32)
; CHECK-NEXT: [[OR37:%[0-9]+]]:_(s32) = G_OR [[OR36]], [[SHL37]]
- ; CHECK-NEXT: [[SHL38:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C8]](s32)
+ ; CHECK-NEXT: [[COPY40:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL38:%[0-9]+]]:_(s32) = G_SHL [[COPY40]], [[C8]](s32)
; CHECK-NEXT: [[OR38:%[0-9]+]]:_(s32) = G_OR [[OR37]], [[SHL38]]
- ; CHECK-NEXT: [[SHL39:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C9]](s32)
+ ; CHECK-NEXT: [[COPY41:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL39:%[0-9]+]]:_(s32) = G_SHL [[COPY41]], [[C9]](s32)
; CHECK-NEXT: [[OR39:%[0-9]+]]:_(s32) = G_OR [[OR38]], [[SHL39]]
- ; CHECK-NEXT: [[SHL40:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C10]](s32)
+ ; CHECK-NEXT: [[COPY42:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL40:%[0-9]+]]:_(s32) = G_SHL [[COPY42]], [[C10]](s32)
; CHECK-NEXT: [[OR40:%[0-9]+]]:_(s32) = G_OR [[OR39]], [[SHL40]]
- ; CHECK-NEXT: [[SHL41:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C11]](s32)
+ ; CHECK-NEXT: [[COPY43:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL41:%[0-9]+]]:_(s32) = G_SHL [[COPY43]], [[C11]](s32)
; CHECK-NEXT: [[OR41:%[0-9]+]]:_(s32) = G_OR [[OR40]], [[SHL41]]
- ; CHECK-NEXT: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C12]](s32)
+ ; CHECK-NEXT: [[COPY44:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[COPY44]], [[C12]](s32)
; CHECK-NEXT: [[OR42:%[0-9]+]]:_(s32) = G_OR [[OR41]], [[SHL42]]
- ; CHECK-NEXT: [[SHL43:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C13]](s32)
+ ; CHECK-NEXT: [[COPY45:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL43:%[0-9]+]]:_(s32) = G_SHL [[COPY45]], [[C13]](s32)
; CHECK-NEXT: [[OR43:%[0-9]+]]:_(s32) = G_OR [[OR42]], [[SHL43]]
- ; CHECK-NEXT: [[SHL44:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C14]](s32)
+ ; CHECK-NEXT: [[COPY46:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL44:%[0-9]+]]:_(s32) = G_SHL [[COPY46]], [[C14]](s32)
; CHECK-NEXT: [[OR44:%[0-9]+]]:_(s32) = G_OR [[OR43]], [[SHL44]]
- ; CHECK-NEXT: [[SHL45:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C15]](s32)
+ ; CHECK-NEXT: [[COPY47:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL45:%[0-9]+]]:_(s32) = G_SHL [[COPY47]], [[C15]](s32)
; CHECK-NEXT: [[OR45:%[0-9]+]]:_(s32) = G_OR [[OR44]], [[SHL45]]
- ; CHECK-NEXT: [[SHL46:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C16]](s32)
+ ; CHECK-NEXT: [[COPY48:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL46:%[0-9]+]]:_(s32) = G_SHL [[COPY48]], [[C16]](s32)
; CHECK-NEXT: [[OR46:%[0-9]+]]:_(s32) = G_OR [[OR45]], [[SHL46]]
- ; CHECK-NEXT: [[SHL47:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C17]](s32)
+ ; CHECK-NEXT: [[COPY49:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL47:%[0-9]+]]:_(s32) = G_SHL [[COPY49]], [[C17]](s32)
; CHECK-NEXT: [[OR47:%[0-9]+]]:_(s32) = G_OR [[OR46]], [[SHL47]]
- ; CHECK-NEXT: [[SHL48:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C18]](s32)
+ ; CHECK-NEXT: [[COPY50:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL48:%[0-9]+]]:_(s32) = G_SHL [[COPY50]], [[C18]](s32)
; CHECK-NEXT: [[OR48:%[0-9]+]]:_(s32) = G_OR [[OR47]], [[SHL48]]
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK-NEXT: [[SHL49:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C19]](s32)
+ ; CHECK-NEXT: [[COPY51:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[SHL49:%[0-9]+]]:_(s32) = G_SHL [[COPY51]], [[C19]](s32)
; CHECK-NEXT: [[OR49:%[0-9]+]]:_(s32) = G_OR [[OR48]], [[SHL49]]
- ; CHECK-NEXT: [[SHL50:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C20]](s32)
+ ; CHECK-NEXT: [[COPY52:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[SHL50:%[0-9]+]]:_(s32) = G_SHL [[COPY52]], [[C20]](s32)
; CHECK-NEXT: [[OR50:%[0-9]+]]:_(s32) = G_OR [[OR49]], [[SHL50]]
- ; CHECK-NEXT: [[SHL51:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C21]](s32)
+ ; CHECK-NEXT: [[COPY53:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL51:%[0-9]+]]:_(s32) = G_SHL [[COPY53]], [[C21]](s32)
; CHECK-NEXT: [[OR51:%[0-9]+]]:_(s32) = G_OR [[OR50]], [[SHL51]]
- ; CHECK-NEXT: [[SHL52:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C22]](s32)
+ ; CHECK-NEXT: [[COPY54:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL52:%[0-9]+]]:_(s32) = G_SHL [[COPY54]], [[C22]](s32)
; CHECK-NEXT: [[OR52:%[0-9]+]]:_(s32) = G_OR [[OR51]], [[SHL52]]
- ; CHECK-NEXT: [[SHL53:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C23]](s32)
+ ; CHECK-NEXT: [[COPY55:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL53:%[0-9]+]]:_(s32) = G_SHL [[COPY55]], [[C23]](s32)
; CHECK-NEXT: [[OR53:%[0-9]+]]:_(s32) = G_OR [[OR52]], [[SHL53]]
- ; CHECK-NEXT: [[SHL54:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C24]](s32)
+ ; CHECK-NEXT: [[COPY56:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL54:%[0-9]+]]:_(s32) = G_SHL [[COPY56]], [[C24]](s32)
; CHECK-NEXT: [[OR54:%[0-9]+]]:_(s32) = G_OR [[OR53]], [[SHL54]]
- ; CHECK-NEXT: [[SHL55:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C25]](s32)
+ ; CHECK-NEXT: [[COPY57:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL55:%[0-9]+]]:_(s32) = G_SHL [[COPY57]], [[C25]](s32)
; CHECK-NEXT: [[OR55:%[0-9]+]]:_(s32) = G_OR [[OR54]], [[SHL55]]
- ; CHECK-NEXT: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C26]](s32)
+ ; CHECK-NEXT: [[COPY58:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[COPY58]], [[C26]](s32)
; CHECK-NEXT: [[OR56:%[0-9]+]]:_(s32) = G_OR [[OR55]], [[SHL56]]
- ; CHECK-NEXT: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C27]](s32)
+ ; CHECK-NEXT: [[COPY59:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[COPY59]], [[C27]](s32)
; CHECK-NEXT: [[OR57:%[0-9]+]]:_(s32) = G_OR [[OR56]], [[SHL57]]
- ; CHECK-NEXT: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C28]](s32)
+ ; CHECK-NEXT: [[COPY60:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[COPY60]], [[C28]](s32)
; CHECK-NEXT: [[OR58:%[0-9]+]]:_(s32) = G_OR [[OR57]], [[SHL58]]
- ; CHECK-NEXT: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C29]](s32)
+ ; CHECK-NEXT: [[COPY61:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[COPY61]], [[C29]](s32)
; CHECK-NEXT: [[OR59:%[0-9]+]]:_(s32) = G_OR [[OR58]], [[SHL59]]
- ; CHECK-NEXT: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C30]](s32)
+ ; CHECK-NEXT: [[COPY62:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[COPY62]], [[C30]](s32)
; CHECK-NEXT: [[OR60:%[0-9]+]]:_(s32) = G_OR [[OR59]], [[SHL60]]
- ; CHECK-NEXT: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C31]](s32)
+ ; CHECK-NEXT: [[COPY63:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[COPY63]], [[C31]](s32)
; CHECK-NEXT: [[OR61:%[0-9]+]]:_(s32) = G_OR [[OR60]], [[SHL61]]
- ; CHECK-NEXT: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C1]](s32)
- ; CHECK-NEXT: [[OR62:%[0-9]+]]:_(s32) = G_OR [[C]], [[SHL62]]
- ; CHECK-NEXT: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C2]](s32)
+ ; CHECK-NEXT: [[COPY64:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[COPY65:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[COPY65]], [[C1]](s32)
+ ; CHECK-NEXT: [[OR62:%[0-9]+]]:_(s32) = G_OR [[COPY64]], [[SHL62]]
+ ; CHECK-NEXT: [[COPY66:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[COPY66]], [[C2]](s32)
; CHECK-NEXT: [[OR63:%[0-9]+]]:_(s32) = G_OR [[OR62]], [[SHL63]]
- ; CHECK-NEXT: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C3]](s32)
+ ; CHECK-NEXT: [[COPY67:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[COPY67]], [[C3]](s32)
; CHECK-NEXT: [[OR64:%[0-9]+]]:_(s32) = G_OR [[OR63]], [[SHL64]]
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL65:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C4]](s32)
+ ; CHECK-NEXT: [[COPY68:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL65:%[0-9]+]]:_(s32) = G_SHL [[COPY68]], [[C4]](s32)
; CHECK-NEXT: [[OR65:%[0-9]+]]:_(s32) = G_OR [[OR64]], [[SHL65]]
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL66:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C5]](s32)
+ ; CHECK-NEXT: [[COPY69:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL66:%[0-9]+]]:_(s32) = G_SHL [[COPY69]], [[C5]](s32)
; CHECK-NEXT: [[OR66:%[0-9]+]]:_(s32) = G_OR [[OR65]], [[SHL66]]
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL67:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C6]](s32)
+ ; CHECK-NEXT: [[COPY70:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL67:%[0-9]+]]:_(s32) = G_SHL [[COPY70]], [[C6]](s32)
; CHECK-NEXT: [[OR67:%[0-9]+]]:_(s32) = G_OR [[OR66]], [[SHL67]]
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL68:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C7]](s32)
+ ; CHECK-NEXT: [[COPY71:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL68:%[0-9]+]]:_(s32) = G_SHL [[COPY71]], [[C7]](s32)
; CHECK-NEXT: [[OR68:%[0-9]+]]:_(s32) = G_OR [[OR67]], [[SHL68]]
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL69:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C8]](s32)
+ ; CHECK-NEXT: [[COPY72:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL69:%[0-9]+]]:_(s32) = G_SHL [[COPY72]], [[C8]](s32)
; CHECK-NEXT: [[OR69:%[0-9]+]]:_(s32) = G_OR [[OR68]], [[SHL69]]
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL70:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C9]](s32)
+ ; CHECK-NEXT: [[COPY73:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL70:%[0-9]+]]:_(s32) = G_SHL [[COPY73]], [[C9]](s32)
; CHECK-NEXT: [[OR70:%[0-9]+]]:_(s32) = G_OR [[OR69]], [[SHL70]]
- ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL71:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C10]](s32)
+ ; CHECK-NEXT: [[COPY74:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL71:%[0-9]+]]:_(s32) = G_SHL [[COPY74]], [[C10]](s32)
; CHECK-NEXT: [[OR71:%[0-9]+]]:_(s32) = G_OR [[OR70]], [[SHL71]]
- ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL72:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C11]](s32)
+ ; CHECK-NEXT: [[COPY75:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL72:%[0-9]+]]:_(s32) = G_SHL [[COPY75]], [[C11]](s32)
; CHECK-NEXT: [[OR72:%[0-9]+]]:_(s32) = G_OR [[OR71]], [[SHL72]]
- ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[C12]](s32)
+ ; CHECK-NEXT: [[COPY76:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[COPY76]], [[C12]](s32)
; CHECK-NEXT: [[OR73:%[0-9]+]]:_(s32) = G_OR [[OR72]], [[SHL73]]
- ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL74:%[0-9]+]]:_(s32) = G_SHL [[COPY11]], [[C13]](s32)
+ ; CHECK-NEXT: [[COPY77:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL74:%[0-9]+]]:_(s32) = G_SHL [[COPY77]], [[C13]](s32)
; CHECK-NEXT: [[OR74:%[0-9]+]]:_(s32) = G_OR [[OR73]], [[SHL74]]
- ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL75:%[0-9]+]]:_(s32) = G_SHL [[COPY12]], [[C14]](s32)
+ ; CHECK-NEXT: [[COPY78:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL75:%[0-9]+]]:_(s32) = G_SHL [[COPY78]], [[C14]](s32)
; CHECK-NEXT: [[OR75:%[0-9]+]]:_(s32) = G_OR [[OR74]], [[SHL75]]
- ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL76:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[C15]](s32)
+ ; CHECK-NEXT: [[COPY79:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL76:%[0-9]+]]:_(s32) = G_SHL [[COPY79]], [[C15]](s32)
; CHECK-NEXT: [[OR76:%[0-9]+]]:_(s32) = G_OR [[OR75]], [[SHL76]]
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL77:%[0-9]+]]:_(s32) = G_SHL [[COPY14]], [[C16]](s32)
+ ; CHECK-NEXT: [[COPY80:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL77:%[0-9]+]]:_(s32) = G_SHL [[COPY80]], [[C16]](s32)
; CHECK-NEXT: [[OR77:%[0-9]+]]:_(s32) = G_OR [[OR76]], [[SHL77]]
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL78:%[0-9]+]]:_(s32) = G_SHL [[COPY15]], [[C17]](s32)
+ ; CHECK-NEXT: [[COPY81:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL78:%[0-9]+]]:_(s32) = G_SHL [[COPY81]], [[C17]](s32)
; CHECK-NEXT: [[OR78:%[0-9]+]]:_(s32) = G_OR [[OR77]], [[SHL78]]
- ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL79:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C18]](s32)
+ ; CHECK-NEXT: [[COPY82:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL79:%[0-9]+]]:_(s32) = G_SHL [[COPY82]], [[C18]](s32)
; CHECK-NEXT: [[OR79:%[0-9]+]]:_(s32) = G_OR [[OR78]], [[SHL79]]
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL80:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C19]](s32)
+ ; CHECK-NEXT: [[COPY83:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL80:%[0-9]+]]:_(s32) = G_SHL [[COPY83]], [[C19]](s32)
; CHECK-NEXT: [[OR80:%[0-9]+]]:_(s32) = G_OR [[OR79]], [[SHL80]]
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL81:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C20]](s32)
+ ; CHECK-NEXT: [[COPY84:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL81:%[0-9]+]]:_(s32) = G_SHL [[COPY84]], [[C20]](s32)
; CHECK-NEXT: [[OR81:%[0-9]+]]:_(s32) = G_OR [[OR80]], [[SHL81]]
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL82:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C21]](s32)
+ ; CHECK-NEXT: [[COPY85:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL82:%[0-9]+]]:_(s32) = G_SHL [[COPY85]], [[C21]](s32)
; CHECK-NEXT: [[OR82:%[0-9]+]]:_(s32) = G_OR [[OR81]], [[SHL82]]
- ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL83:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C22]](s32)
+ ; CHECK-NEXT: [[COPY86:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL83:%[0-9]+]]:_(s32) = G_SHL [[COPY86]], [[C22]](s32)
; CHECK-NEXT: [[OR83:%[0-9]+]]:_(s32) = G_OR [[OR82]], [[SHL83]]
- ; CHECK-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL84:%[0-9]+]]:_(s32) = G_SHL [[COPY21]], [[C23]](s32)
+ ; CHECK-NEXT: [[COPY87:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL84:%[0-9]+]]:_(s32) = G_SHL [[COPY87]], [[C23]](s32)
; CHECK-NEXT: [[OR84:%[0-9]+]]:_(s32) = G_OR [[OR83]], [[SHL84]]
- ; CHECK-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL85:%[0-9]+]]:_(s32) = G_SHL [[COPY22]], [[C24]](s32)
+ ; CHECK-NEXT: [[COPY88:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL85:%[0-9]+]]:_(s32) = G_SHL [[COPY88]], [[C24]](s32)
; CHECK-NEXT: [[OR85:%[0-9]+]]:_(s32) = G_OR [[OR84]], [[SHL85]]
- ; CHECK-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL86:%[0-9]+]]:_(s32) = G_SHL [[COPY23]], [[C25]](s32)
+ ; CHECK-NEXT: [[COPY89:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL86:%[0-9]+]]:_(s32) = G_SHL [[COPY89]], [[C25]](s32)
; CHECK-NEXT: [[OR86:%[0-9]+]]:_(s32) = G_OR [[OR85]], [[SHL86]]
- ; CHECK-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL87:%[0-9]+]]:_(s32) = G_SHL [[COPY24]], [[C26]](s32)
+ ; CHECK-NEXT: [[COPY90:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL87:%[0-9]+]]:_(s32) = G_SHL [[COPY90]], [[C26]](s32)
; CHECK-NEXT: [[OR87:%[0-9]+]]:_(s32) = G_OR [[OR86]], [[SHL87]]
- ; CHECK-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL88:%[0-9]+]]:_(s32) = G_SHL [[COPY25]], [[C27]](s32)
+ ; CHECK-NEXT: [[COPY91:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL88:%[0-9]+]]:_(s32) = G_SHL [[COPY91]], [[C27]](s32)
; CHECK-NEXT: [[OR88:%[0-9]+]]:_(s32) = G_OR [[OR87]], [[SHL88]]
- ; CHECK-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL89:%[0-9]+]]:_(s32) = G_SHL [[COPY26]], [[C28]](s32)
+ ; CHECK-NEXT: [[COPY92:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL89:%[0-9]+]]:_(s32) = G_SHL [[COPY92]], [[C28]](s32)
; CHECK-NEXT: [[OR89:%[0-9]+]]:_(s32) = G_OR [[OR88]], [[SHL89]]
- ; CHECK-NEXT: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL90:%[0-9]+]]:_(s32) = G_SHL [[COPY27]], [[C29]](s32)
+ ; CHECK-NEXT: [[COPY93:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL90:%[0-9]+]]:_(s32) = G_SHL [[COPY93]], [[C29]](s32)
; CHECK-NEXT: [[OR90:%[0-9]+]]:_(s32) = G_OR [[OR89]], [[SHL90]]
- ; CHECK-NEXT: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL91:%[0-9]+]]:_(s32) = G_SHL [[COPY28]], [[C30]](s32)
+ ; CHECK-NEXT: [[COPY94:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL91:%[0-9]+]]:_(s32) = G_SHL [[COPY94]], [[C30]](s32)
; CHECK-NEXT: [[OR91:%[0-9]+]]:_(s32) = G_OR [[OR90]], [[SHL91]]
- ; CHECK-NEXT: [[COPY29:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK-NEXT: [[SHL92:%[0-9]+]]:_(s32) = G_SHL [[COPY29]], [[C31]](s32)
+ ; CHECK-NEXT: [[COPY95:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK-NEXT: [[SHL92:%[0-9]+]]:_(s32) = G_SHL [[COPY95]], [[C31]](s32)
; CHECK-NEXT: [[OR92:%[0-9]+]]:_(s32) = G_OR [[OR91]], [[SHL92]]
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[OR30]](s32), [[OR61]](s32), [[OR92]](s32)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s68) = G_TRUNC [[MV]](s96)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
index 483698e01417b4d..3174495e6bf0af2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
@@ -472,9 +472,10 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV6]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS2]](<6 x s16>)
@@ -533,9 +534,10 @@ body: |
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
@@ -544,9 +546,10 @@ body: |
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[SHL1]]
; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL2]]
; CHECK-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
@@ -561,17 +564,20 @@ body: |
; CHECK-NEXT: [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>), [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF2]](<8 x s16>)
; CHECK-NEXT: [[BITCAST11:%[0-9]+]]:_(s32) = G_BITCAST [[UV12]](<2 x s16>)
; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST11]], [[C]](s32)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C]](s32)
- ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL4]]
; CHECK-NEXT: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST10]], [[C1]]
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
- ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL5]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST10]], [[C1]]
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
+ ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL5]]
; CHECK-NEXT: [[BITCAST13:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR7]](s32)
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[LSHR4]], [[C]](s32)
- ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL6]]
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
+ ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
; CHECK-NEXT: [[BITCAST14:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR8]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS4:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST12]](<2 x s16>), [[BITCAST13]](<2 x s16>), [[BITCAST14]](<2 x s16>), [[UV13]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS4]](<8 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
index 00612d552a1048a..7b439e501854cf3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
@@ -179,9 +179,10 @@ body: |
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C6]](s32)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
; CHECK-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C7]]
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32)
- ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL4]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C7]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C7]]
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL4]]
; CHECK-NEXT: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV2]](<2 x s16>), [[BITCAST8]](<2 x s16>), [[BITCAST9]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS2]](<6 x s16>)
@@ -1372,8 +1373,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.0, [[TRUNC1]](s16), %bb.1
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
@@ -1429,8 +1430,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.0, [[TRUNC1]](s16), %bb.1
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
@@ -1653,7 +1654,9 @@ body: |
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND]](s32), [[AND1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LSHR]](s32), [[LSHR1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND2]](s32), [[AND3]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
; CHECK-NEXT: G_BRCOND [[ICMP2]](s1), %bb.1
; CHECK-NEXT: G_BR %bb.2
@@ -1667,10 +1670,12 @@ body: |
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY2]](<2 x s16>)
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C3]](s32)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C4]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND2]](s32), [[AND3]]
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LSHR2]](s32), [[LSHR3]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C4]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND4]](s32), [[AND5]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND6]](s32), [[AND7]]
; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
@@ -1679,9 +1684,9 @@ body: |
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s1)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s1)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C5]]
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C5]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND4]](s32), [[AND5]](s32)
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C5]]
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C5]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND8]](s32), [[AND9]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir
index 80d1aa4d8889d81..227d4645ea6478b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir
@@ -12,8 +12,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p1) = G_PTRMASK [[COPY]], [[AND]](s64)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[PTRMASK]](p1)
@@ -94,8 +94,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[COPY]], [[AND]](s64)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[PTRMASK]](p0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
index 07aca9f80be58de..e5017d0b615d78b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
@@ -21,33 +21,36 @@ body: |
; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
+ ; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX6-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY2]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; GFX6-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; GFX6-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[C1]]
+ ; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY2]]
; GFX6-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; GFX6-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; GFX6-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; GFX6-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
- ; GFX6-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[C1]]
+ ; GFX6-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY2]]
; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[C1]]
- ; GFX6-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C1]]
+ ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY2]]
+ ; GFX6-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY2]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
- ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[C1]]
- ; GFX6-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[C1]]
+ ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY2]]
+ ; GFX6-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY2]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
; GFX6-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
+ ; GFX6-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
- ; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C5]](s32)
+ ; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY3]](s32)
; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
- ; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[AND3]](s32)
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
; GFX6-NEXT: $sgpr0 = COPY [[OR]](s32)
;
@@ -59,38 +62,41 @@ body: |
; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C]](s32)
+ ; GFX8-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX8-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY2]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; GFX8-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C2]]
; GFX8-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX8-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[C]]
+ ; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY2]]
; GFX8-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; GFX8-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; GFX8-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; GFX8-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
- ; GFX8-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[C]]
+ ; GFX8-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY2]]
; GFX8-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
- ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[C]]
- ; GFX8-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C]]
+ ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY2]]
+ ; GFX8-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY2]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
- ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[C]]
- ; GFX8-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[C]]
+ ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY2]]
+ ; GFX8-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY2]]
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SELECT1]](s32)
; GFX8-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SELECT1]](s32)
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND1]](s16)
; GFX8-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 14
- ; GFX8-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; GFX8-NEXT: [[SUB4:%[0-9]+]]:_(s16) = G_SUB [[C5]], [[COPY2]]
+ ; GFX8-NEXT: [[COPY3:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
+ ; GFX8-NEXT: [[SUB4:%[0-9]+]]:_(s16) = G_SUB [[C5]], [[COPY3]]
; GFX8-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
- ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND2]], [[C6]](s16)
- ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[SUB4]], [[C4]]
- ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[LSHR]], [[AND3]](s16)
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C6]], [[C4]]
+ ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
+ ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND3]], [[AND2]](s16)
+ ; GFX8-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[SUB4]], [[C4]]
+ ; GFX8-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C4]]
+ ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND5]], [[AND4]](s16)
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX8-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
@@ -208,33 +214,36 @@ body: |
; GFX-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; GFX-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[C1]](s32)
+ ; GFX-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY2]](s32)
; GFX-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; GFX-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; GFX-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[C1]]
+ ; GFX-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY2]]
; GFX-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; GFX-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; GFX-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; GFX-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
- ; GFX-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[C1]]
+ ; GFX-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY2]]
; GFX-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; GFX-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[C1]]
- ; GFX-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C1]]
+ ; GFX-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY2]]
+ ; GFX-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY2]]
; GFX-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
- ; GFX-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[C1]]
- ; GFX-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[C1]]
+ ; GFX-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY2]]
+ ; GFX-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY2]]
; GFX-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
; GFX-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
; GFX-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
+ ; GFX-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; GFX-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
- ; GFX-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C5]](s32)
+ ; GFX-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY3]](s32)
; GFX-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
- ; GFX-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[AND3]](s32)
+ ; GFX-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
; GFX-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
; GFX-NEXT: $sgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $sgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
index dba20e128237cdc..09aaf8d548758a3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
@@ -256,16 +256,17 @@ body: |
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST9]], [[C2]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[SHL2]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C2]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST9]], [[C2]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK-NEXT: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST10]](<2 x s16>), [[BITCAST11]](<2 x s16>), [[BITCAST12]](<2 x s16>)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]]
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C3]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND5]](s32), [[AND6]](s32), [[AND7]](s32)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]]
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C3]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND6]](s32), [[AND7]](s32), [[AND8]](s32)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
index 11018723d979a6c..a175a87f239e352 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
@@ -31,7 +31,6 @@ body: |
; GFX6-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; GFX8-LABEL: name: saddsat_s7
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -55,7 +54,6 @@ body: |
; GFX8-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[ADD]], [[C]](s16)
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: saddsat_s7
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -105,7 +103,6 @@ body: |
; GFX6-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; GFX8-LABEL: name: saddsat_s8
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -129,7 +126,6 @@ body: |
; GFX8-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[ADD]], [[C]](s16)
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: saddsat_s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -191,8 +187,8 @@ body: |
; GFX6-NEXT: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB2]]
; GFX6-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[SMIN3]]
; GFX6-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ADD1]], [[C1]](s32)
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; GFX6-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C5]]
; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -202,7 +198,6 @@ body: |
; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX8-LABEL: name: saddsat_v2s8
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -246,7 +241,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: saddsat_v2s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -317,7 +311,6 @@ body: |
; GFX6-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; GFX8-LABEL: name: saddsat_s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -337,7 +330,6 @@ body: |
; GFX8-NEXT: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[SMIN1]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: saddsat_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -403,7 +395,6 @@ body: |
; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL4]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX8-LABEL: name: saddsat_v2s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -441,7 +432,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: saddsat_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -522,13 +512,13 @@ body: |
; GFX6-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL7]]
; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
- ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
- ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL8]]
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
+ ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL8]]
; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX8-LABEL: name: saddsat_v3s16
; GFX8: liveins: $vgpr0_vgpr1_vgpr2
; GFX8-NEXT: {{ $}}
@@ -587,13 +577,13 @@ body: |
; GFX8-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; GFX8-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
- ; GFX8-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL2]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
+ ; GFX8-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; GFX8-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: saddsat_v3s16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
@@ -719,7 +709,6 @@ body: |
; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX8-LABEL: name: saddsat_v4s16
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -787,7 +776,6 @@ body: |
; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: saddsat_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -827,7 +815,6 @@ body: |
; GFX6-NEXT: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX6-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[SMIN1]]
; GFX6-NEXT: $vgpr0 = COPY [[ADD]](s32)
- ;
; GFX8-LABEL: name: saddsat_s32
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -844,7 +831,6 @@ body: |
; GFX8-NEXT: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX8-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[SMIN1]]
; GFX8-NEXT: $vgpr0 = COPY [[ADD]](s32)
- ;
; GFX9-LABEL: name: saddsat_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -890,7 +876,6 @@ body: |
; GFX6-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[SMIN3]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX8-LABEL: name: saddsat_v2s32
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -917,7 +902,6 @@ body: |
; GFX8-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[SMIN3]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: saddsat_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -965,7 +949,6 @@ body: |
; GFX6-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO2]](s32), [[UADDE2]](s32)
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[XOR]](s1), [[MV1]], [[MV]]
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; GFX8-LABEL: name: saddsat_s64
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -990,7 +973,6 @@ body: |
; GFX8-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO2]](s32), [[UADDE2]](s32)
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[XOR]](s1), [[MV1]], [[MV]]
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; GFX9-LABEL: name: saddsat_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1069,7 +1051,6 @@ body: |
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[XOR1]](s1), [[MV3]], [[MV2]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT]](s64), [[SELECT1]](s64)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX8-LABEL: name: saddsat_v2s64
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX8-NEXT: {{ $}}
@@ -1112,7 +1093,6 @@ body: |
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[XOR1]](s1), [[MV3]], [[MV2]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT]](s64), [[SELECT1]](s64)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: saddsat_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
index 93a7e837cdd9b8a..674f23e2f411ce7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
@@ -417,9 +417,10 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV6]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS2]](<6 x s16>)
@@ -1361,9 +1362,10 @@ body: |
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; CHECK-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
@@ -1399,8 +1401,8 @@ body: |
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[ICMP1]](s1)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[ICMP2]](s1)
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[ANYEXT]], [[ANYEXT1]]
- ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C1]]
; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
index 40c48e10f933ffa..d5f992a42b07ad1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
@@ -17,14 +17,12 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; GFX9-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
- ;
; GFX8-LABEL: name: test_sext_inreg_s32_1
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; GFX8-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
- ;
; GFX6-LABEL: name: test_sext_inreg_s32_1
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
@@ -48,14 +46,12 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 2
; GFX9-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
- ;
; GFX8-LABEL: name: test_sext_inreg_s32_2
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 2
; GFX8-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
- ;
; GFX6-LABEL: name: test_sext_inreg_s32_2
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
@@ -79,14 +75,12 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX9-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
- ;
; GFX8-LABEL: name: test_sext_inreg_s32_8
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX8-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
- ;
; GFX6-LABEL: name: test_sext_inreg_s32_8
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
@@ -110,14 +104,12 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX9-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
- ;
; GFX8-LABEL: name: test_sext_inreg_s32_16
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX8-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
- ;
; GFX6-LABEL: name: test_sext_inreg_s32_16
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
@@ -141,14 +133,12 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 31
; GFX9-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
- ;
; GFX8-LABEL: name: test_sext_inreg_s32_31
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 31
; GFX8-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
- ;
; GFX6-LABEL: name: test_sext_inreg_s32_31
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
@@ -172,14 +162,12 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 1
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX8-LABEL: name: test_sext_inreg_s64_1
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 1
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX6-LABEL: name: test_sext_inreg_s64_1
; GFX6: liveins: $vgpr0_vgpr1
; GFX6-NEXT: {{ $}}
@@ -203,14 +191,12 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 2
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX8-LABEL: name: test_sext_inreg_s64_2
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 2
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX6-LABEL: name: test_sext_inreg_s64_2
; GFX6: liveins: $vgpr0_vgpr1
; GFX6-NEXT: {{ $}}
@@ -234,14 +220,12 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX8-LABEL: name: test_sext_inreg_s64_8
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX6-LABEL: name: test_sext_inreg_s64_8
; GFX6: liveins: $vgpr0_vgpr1
; GFX6-NEXT: {{ $}}
@@ -265,14 +249,12 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX8-LABEL: name: test_sext_inreg_s64_16
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX6-LABEL: name: test_sext_inreg_s64_16
; GFX6: liveins: $vgpr0_vgpr1
; GFX6-NEXT: {{ $}}
@@ -296,14 +278,12 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 31
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX8-LABEL: name: test_sext_inreg_s64_31
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 31
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX6-LABEL: name: test_sext_inreg_s64_31
; GFX6: liveins: $vgpr0_vgpr1
; GFX6-NEXT: {{ $}}
@@ -327,14 +307,12 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX8-LABEL: name: test_sext_inreg_s64_32
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX6-LABEL: name: test_sext_inreg_s64_32
; GFX6: liveins: $vgpr0_vgpr1
; GFX6-NEXT: {{ $}}
@@ -358,14 +336,12 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 33
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX8-LABEL: name: test_sext_inreg_s64_33
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 33
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX6-LABEL: name: test_sext_inreg_s64_33
; GFX6: liveins: $vgpr0_vgpr1
; GFX6-NEXT: {{ $}}
@@ -389,14 +365,12 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 63
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX8-LABEL: name: test_sext_inreg_s64_63
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 63
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
- ;
; GFX6-LABEL: name: test_sext_inreg_s64_63
; GFX6: liveins: $vgpr0_vgpr1
; GFX6-NEXT: {{ $}}
@@ -421,7 +395,6 @@ body: |
; GFX9-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX9-NEXT: S_ENDPGM 0, implicit [[TRUNC]](s16)
- ;
; GFX8-LABEL: name: test_sext_inreg_s16_1
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
@@ -431,7 +404,6 @@ body: |
; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX8-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16)
; GFX8-NEXT: S_ENDPGM 0, implicit [[ASHR]](s16)
- ;
; GFX6-LABEL: name: test_sext_inreg_s16_1
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
@@ -459,7 +431,6 @@ body: |
; GFX9-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 15
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX9-NEXT: S_ENDPGM 0, implicit [[TRUNC]](s16)
- ;
; GFX8-LABEL: name: test_sext_inreg_s16_15
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
@@ -469,7 +440,6 @@ body: |
; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX8-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16)
; GFX8-NEXT: S_ENDPGM 0, implicit [[ASHR]](s16)
- ;
; GFX6-LABEL: name: test_sext_inreg_s16_15
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
@@ -503,7 +473,6 @@ body: |
; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[MV]](s64), [[MV]](s64)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV1]](s192)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
- ;
; GFX8-LABEL: name: test_sext_inreg_s96_8
; GFX8: liveins: $vgpr0_vgpr1_vgpr2
; GFX8-NEXT: {{ $}}
@@ -517,7 +486,6 @@ body: |
; GFX8-NEXT: [[MV1:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[MV]](s64), [[MV]](s64)
; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV1]](s192)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
- ;
; GFX6-LABEL: name: test_sext_inreg_s96_8
; GFX6: liveins: $vgpr0_vgpr1_vgpr2
; GFX6-NEXT: {{ $}}
@@ -552,7 +520,6 @@ body: |
; GFX9-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX8-LABEL: name: test_sext_inreg_s128_8
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -563,7 +530,6 @@ body: |
; GFX8-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX6-LABEL: name: test_sext_inreg_s128_8
; GFX6: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX6-NEXT: {{ $}}
@@ -598,7 +564,6 @@ body: |
; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s320) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[MV]](s64), [[MV]](s64), [[MV]](s64), [[MV]](s64)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s160) = G_TRUNC [[MV1]](s320)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY [[TRUNC1]](s160)
- ;
; GFX8-LABEL: name: test_sext_inreg_s160_8
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
; GFX8-NEXT: {{ $}}
@@ -612,7 +577,6 @@ body: |
; GFX8-NEXT: [[MV1:%[0-9]+]]:_(s320) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[MV]](s64), [[MV]](s64), [[MV]](s64), [[MV]](s64)
; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s160) = G_TRUNC [[MV1]](s320)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY [[TRUNC1]](s160)
- ;
; GFX6-LABEL: name: test_sext_inreg_s160_8
; GFX6: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
; GFX6-NEXT: {{ $}}
@@ -647,7 +611,6 @@ body: |
; GFX9-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
- ;
; GFX8-LABEL: name: test_sext_inreg_256_8
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX8-NEXT: {{ $}}
@@ -658,7 +621,6 @@ body: |
; GFX8-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
- ;
; GFX6-LABEL: name: test_sext_inreg_256_8
; GFX6: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX6-NEXT: {{ $}}
@@ -690,7 +652,6 @@ body: |
; GFX9-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[MV]](s512)
- ;
; GFX8-LABEL: name: test_sext_inreg_512_8
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX8-NEXT: {{ $}}
@@ -701,7 +662,6 @@ body: |
; GFX8-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[MV]](s512)
- ;
; GFX6-LABEL: name: test_sext_inreg_512_8
; GFX6: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX6-NEXT: {{ $}}
@@ -733,7 +693,6 @@ body: |
; GFX9-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[MV]](s1024)
- ;
; GFX8-LABEL: name: test_sext_inreg_1024_8
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX8-NEXT: {{ $}}
@@ -744,7 +703,6 @@ body: |
; GFX8-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[MV]](s1024)
- ;
; GFX6-LABEL: name: test_sext_inreg_1024_8
; GFX6: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX6-NEXT: {{ $}}
@@ -775,7 +733,6 @@ body: |
; GFX9-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX8-LABEL: name: test_sext_inreg_v2s32_1
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
@@ -785,7 +742,6 @@ body: |
; GFX8-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX6-LABEL: name: test_sext_inreg_v2s32_1
; GFX6: liveins: $vgpr0_vgpr1
; GFX6-NEXT: {{ $}}
@@ -815,7 +771,6 @@ body: |
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s16>)
; GFX9-NEXT: [[ASHR:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s16>)
; GFX9-NEXT: $vgpr0 = COPY [[ASHR]](<2 x s16>)
- ;
; GFX8-LABEL: name: test_sext_inreg_v2s16_1
; GFX8: liveins: $vgpr0
; GFX8-NEXT: {{ $}}
@@ -836,7 +791,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; GFX6-LABEL: name: test_sext_inreg_v2s16_1
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
@@ -900,7 +854,6 @@ body: |
; GFX9-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](s16), [[TRUNC6]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR3]](<2 x s16>), [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX8-LABEL: name: test_sext_inreg_v3s16_1
; GFX8: liveins: $vgpr0_vgpr1_vgpr2
; GFX8-NEXT: {{ $}}
@@ -936,13 +889,13 @@ body: |
; GFX8-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C2]]
- ; GFX8-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL5]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C2]]
+ ; GFX8-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL5]]
; GFX8-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX6-LABEL: name: test_sext_inreg_v3s16_1
; GFX6: liveins: $vgpr0_vgpr1_vgpr2
; GFX6-NEXT: {{ $}}
@@ -971,9 +924,10 @@ body: |
; GFX6-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; GFX6-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
- ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; GFX6-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
@@ -1001,7 +955,6 @@ body: |
; GFX9-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 1
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX8-LABEL: name: test_sext_inreg_v3s32_1
; GFX8: liveins: $vgpr0_vgpr1_vgpr2
; GFX8-NEXT: {{ $}}
@@ -1012,7 +965,6 @@ body: |
; GFX8-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 1
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX6-LABEL: name: test_sext_inreg_v3s32_1
; GFX6: liveins: $vgpr0_vgpr1_vgpr2
; GFX6-NEXT: {{ $}}
@@ -1045,7 +997,6 @@ body: |
; GFX9-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV3]], 1
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32), [[SEXT_INREG3]](s32)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX8-LABEL: name: test_sext_inreg_v4s32_1
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -1057,7 +1008,6 @@ body: |
; GFX8-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV3]], 1
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32), [[SEXT_INREG3]](s32)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
- ;
; GFX6-LABEL: name: test_sext_inreg_v4s32_1
; GFX6: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX6-NEXT: {{ $}}
@@ -1094,7 +1044,6 @@ body: |
; GFX9-NEXT: [[ASHR1:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SHL1]], [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[ASHR]](<2 x s16>), [[ASHR1]](<2 x s16>)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX8-LABEL: name: test_sext_inreg_v4s16_1
; GFX8: liveins: $vgpr0_vgpr1
; GFX8-NEXT: {{ $}}
@@ -1130,7 +1079,6 @@ body: |
; GFX8-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX6-LABEL: name: test_sext_inreg_v4s16_1
; GFX6: liveins: $vgpr0_vgpr1
; GFX6-NEXT: {{ $}}
@@ -1183,7 +1131,6 @@ body: |
; GFX9-NEXT: [[ASHR2:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SHL2]], [[BUILD_VECTOR2]](<2 x s16>)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[ASHR]](<2 x s16>), [[ASHR1]](<2 x s16>), [[ASHR2]](<2 x s16>)
; GFX9-NEXT: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX8-LABEL: name: test_sext_inreg_v6s16_1
; GFX8: [[DEF:%[0-9]+]]:_(<6 x s16>) = G_IMPLICIT_DEF
; GFX8-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<6 x s16>)
@@ -1230,7 +1177,6 @@ body: |
; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX8-NEXT: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX6-LABEL: name: test_sext_inreg_v6s16_1
; GFX6: [[DEF:%[0-9]+]]:_(<6 x s16>) = G_IMPLICIT_DEF
; GFX6-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<6 x s16>)
@@ -1295,7 +1241,6 @@ body: |
; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SEXT_INREG1]](s64), [[ASHR1]](s64)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
- ;
; GFX8-LABEL: name: test_sext_inreg_v2s128_1
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX8-NEXT: {{ $}}
@@ -1313,7 +1258,6 @@ body: |
; GFX8-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SEXT_INREG1]](s64), [[ASHR1]](s64)
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
- ;
; GFX6-LABEL: name: test_sext_inreg_v2s128_1
; GFX6: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX6-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
index 847ffc8aadc073b..12d1ce39c0a9824 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
@@ -659,8 +659,8 @@ body: |
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C3]](s16)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 7
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[C4]](s16)
- ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C5]]
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C5]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
index b1de5dbdff9f1ae..1b620f65d164a1b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
@@ -18,7 +18,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[SHL]](s32)
- ;
; VI-LABEL: name: test_shl_s32_s32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -26,7 +25,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; VI-NEXT: $vgpr0 = COPY [[SHL]](s32)
- ;
; GFX9-LABEL: name: test_shl_s32_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -53,7 +51,6 @@ body: |
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[TRUNC]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](s64)
- ;
; VI-LABEL: name: test_shl_s64_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -62,7 +59,6 @@ body: |
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[TRUNC]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](s64)
- ;
; GFX9-LABEL: name: test_shl_s64_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -89,7 +85,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](s64)
- ;
; VI-LABEL: name: test_shl_s64_s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -97,7 +92,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](s64)
- ;
; GFX9-LABEL: name: test_shl_s64_s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -125,7 +119,6 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](s64)
- ;
; VI-LABEL: name: test_shl_s64_s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -135,7 +128,6 @@ body: |
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](s64)
- ;
; GFX9-LABEL: name: test_shl_s64_s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -165,7 +157,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[SHL]](s32)
- ;
; VI-LABEL: name: test_shl_s16_s32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -176,7 +167,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_shl_s16_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -210,7 +200,6 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
; SI-NEXT: $vgpr0 = COPY [[SHL]](s32)
- ;
; VI-LABEL: name: test_shl_s16_s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -221,7 +210,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_shl_s16_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -256,28 +244,26 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
; SI-NEXT: $vgpr0 = COPY [[SHL]](s32)
- ;
; VI-LABEL: name: test_shl_s16_i8
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_shl_s16_i8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s16)
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
@@ -306,27 +292,25 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
; SI-NEXT: $vgpr0 = COPY [[SHL]](s32)
- ;
; VI-LABEL: name: test_shl_i8_i8
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_shl_i8_i8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND]](s16)
@@ -359,7 +343,6 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[UV3]](s32)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SHL]](s32), [[SHL1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_shl_v2s32_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -371,7 +354,6 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[UV3]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SHL]](s32), [[SHL1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_shl_v2s32_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -407,7 +389,6 @@ body: |
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[UV5]](s32)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SHL]](s32), [[SHL1]](s32), [[SHL2]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_shl_v3s32_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -420,7 +401,6 @@ body: |
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[UV5]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SHL]](s32), [[SHL1]](s32), [[SHL2]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_shl_v3s32_v3s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -456,7 +436,6 @@ body: |
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[UV3]](s32)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SHL]](s64), [[SHL1]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; VI-LABEL: name: test_shl_v2s64_v2s32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -468,7 +447,6 @@ body: |
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[UV3]](s32)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SHL]](s64), [[SHL1]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_shl_v2s64_v2s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -506,7 +484,6 @@ body: |
; SI-NEXT: [[UV7:%[0-9]+]]:_(s64), [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64), [[UV10:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[SHL]](s64), [[SHL1]](s64), [[SHL2]](s64), [[UV10]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; VI-LABEL: name: test_shl_v3s64_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; VI-NEXT: {{ $}}
@@ -521,7 +498,6 @@ body: |
; VI-NEXT: [[UV7:%[0-9]+]]:_(s64), [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64), [[UV10:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[SHL]](s64), [[SHL1]](s64), [[SHL2]](s64), [[UV10]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
- ;
; GFX9-LABEL: name: test_shl_v3s64_v3s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; GFX9-NEXT: {{ $}}
@@ -564,14 +540,14 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[AND]](s32)
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[LSHR1]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C1]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[AND1]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C1]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL2]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; VI-LABEL: name: test_shl_v2s16_v2s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -594,7 +570,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_shl_v2s16_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -632,7 +607,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; SI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; VI-LABEL: name: test_shl_v2s16_v2s32
; VI: liveins: $vgpr0, $vgpr0_vgpr1
; VI-NEXT: {{ $}}
@@ -654,7 +628,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_shl_v2s16_v2s32
; GFX9: liveins: $vgpr0, $vgpr0_vgpr1
; GFX9-NEXT: {{ $}}
@@ -700,31 +673,32 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[AND]](s32)
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[LSHR1]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[AND1]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[AND1]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[AND2]](s32)
; SI-NEXT: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; SI-NEXT: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>)
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C1]]
- ; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL3]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C1]]
+ ; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL3]]
; SI-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C1]]
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
- ; SI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL4]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C1]]
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; SI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL4]]
; SI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
- ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL5]]
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
+ ; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; SI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; VI-LABEL: name: test_shl_v3s16_v3s16
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -764,13 +738,13 @@ body: |
; VI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; VI-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; VI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL5]]
+ ; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; VI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; VI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; VI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL5]]
; VI-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: test_shl_v3s16_v3s16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -840,23 +814,24 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[AND]](s32)
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[LSHR2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[AND1]](s32)
- ; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[LSHR3]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C1]]
- ; SI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[AND1]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[AND2]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; SI-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[AND3]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C1]]
+ ; SI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL4]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C1]]
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C1]]
- ; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL5]]
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C1]]
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C1]]
+ ; SI-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL5]]
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_shl_v4s16_v4s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -897,7 +872,6 @@ body: |
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_shl_v4s16_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -930,27 +904,25 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
; SI-NEXT: $vgpr0 = COPY [[SHL]](s32)
- ;
; VI-LABEL: name: test_shl_s7_s7
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 127
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND]](s16)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_shl_s7_s7
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 127
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND]](s16)
@@ -978,7 +950,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; SI-NEXT: $vgpr0 = COPY [[SHL]](s32)
- ;
; VI-LABEL: name: test_shl_i24_i32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -986,7 +957,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; VI-NEXT: $vgpr0 = COPY [[SHL]](s32)
- ;
; GFX9-LABEL: name: test_shl_i24_i32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -1013,68 +983,66 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
+ ; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
+ ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[COPY1]](s32)
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[SUB1]](s32)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[COPY1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]]
- ; SI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[SUB]](s32)
- ; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[C2]]
+ ; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[C1]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[SHL2]]
; SI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV1]], [[SELECT1]]
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_shl_s128_s128
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; VI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
+ ; VI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
+ ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[COPY1]](s32)
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[SUB1]](s32)
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[COPY1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]]
- ; VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[SUB]](s32)
- ; VI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[C2]]
+ ; VI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[C1]]
; VI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[SHL2]]
; VI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV1]], [[SELECT1]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9-LABEL: name: test_shl_s128_s128
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
+ ; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
+ ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[COPY1]](s32)
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[SUB1]](s32)
; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[COPY1]](s32)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[SUB]](s32)
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[C2]]
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[C1]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR]], [[SHL2]]
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV1]], [[SELECT1]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
@@ -1115,7 +1083,6 @@ body: |
; SI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV1]], [[SELECT1]]
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_shl_s128_s132
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1139,7 +1106,6 @@ body: |
; VI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV1]], [[SELECT1]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9-LABEL: name: test_shl_s128_s132
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
@@ -1180,13 +1146,11 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY]](s128)
- ;
; VI-LABEL: name: test_shl_s128_s32_0
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[COPY]](s128)
- ;
; GFX9-LABEL: name: test_shl_s128_s32_0
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
@@ -1218,7 +1182,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_shl_s128_s32_23
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1232,7 +1195,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9-LABEL: name: test_shl_s128_s32_23
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
@@ -1271,7 +1233,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_shl_s128_s32_31
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1285,7 +1246,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9-LABEL: name: test_shl_s128_s32_31
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
@@ -1323,7 +1283,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_shl_s128_s32_32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1336,7 +1295,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9-LABEL: name: test_shl_s128_s32_32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
@@ -1374,7 +1332,6 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_shl_s128_s32_33
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1388,7 +1345,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SHL]](s64), [[OR]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9-LABEL: name: test_shl_s128_s32_33
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
@@ -1424,7 +1380,6 @@ body: |
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C1]](s32)
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C]](s64), [[SHL]](s64)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; VI-LABEL: name: test_shl_s128_s32_127
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; VI-NEXT: {{ $}}
@@ -1435,7 +1390,6 @@ body: |
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[C1]](s32)
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C]](s64), [[SHL]](s64)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
- ;
; GFX9-LABEL: name: test_shl_s128_s32_127
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; GFX9-NEXT: {{ $}}
@@ -1463,33 +1417,33 @@ body: |
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
+ ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; SI-NEXT: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](s256)
- ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
- ; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; SI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
+ ; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
+ ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
+ ; SI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; SI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; SI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
- ; SI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; SI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; SI-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; SI-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; SI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; SI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; SI-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; SI-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; SI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[COPY1]](s32)
; SI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[SUB3]](s32)
; SI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[COPY1]](s32)
; SI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]]
- ; SI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[SUB2]](s32)
- ; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL]], [[C3]]
+ ; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL]], [[C1]]
; SI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[SHL2]]
; SI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV3]], [[SELECT1]]
; SI-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
- ; SI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
- ; SI-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
- ; SI-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
- ; SI-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
+ ; SI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C3]]
+ ; SI-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB1]]
+ ; SI-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C3]]
+ ; SI-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C]]
; SI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB1]](s32)
; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[SUB1]](s32)
; SI-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32)
@@ -1497,37 +1451,37 @@ body: |
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
; SI-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR3]]
; SI-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]]
- ; SI-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR1]], [[C3]]
+ ; SI-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR1]], [[C1]]
; SI-NEXT: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; SI-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; SI-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; SI-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; SI-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; SI-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; SI-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; SI-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; SI-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; SI-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[COPY1]](s32)
; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB7]](s32)
; SI-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[COPY1]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL5]]
; SI-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB6]](s32)
- ; SI-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL4]], [[C3]]
+ ; SI-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL4]], [[C1]]
; SI-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[SHL6]]
; SI-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV7]], [[SELECT7]]
; SI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT6]]
; SI-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; SI-NEXT: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
- ; SI-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
- ; SI-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
- ; SI-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
- ; SI-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
+ ; SI-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C3]]
+ ; SI-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB]]
+ ; SI-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C3]]
+ ; SI-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C]]
; SI-NEXT: [[SHL7:%[0-9]+]]:_(s64) = G_SHL [[UV8]], [[SUB]](s32)
; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB9]](s32)
; SI-NEXT: [[SHL8:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB]](s32)
; SI-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR5]], [[SHL8]]
; SI-NEXT: [[SHL9:%[0-9]+]]:_(s64) = G_SHL [[UV8]], [[SUB8]](s32)
- ; SI-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[SHL7]], [[C3]]
+ ; SI-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[SHL7]], [[C1]]
; SI-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[SHL9]]
; SI-NEXT: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV9]], [[SELECT10]]
- ; SI-NEXT: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT]], [[C3]]
- ; SI-NEXT: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C3]]
+ ; SI-NEXT: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT]], [[C1]]
+ ; SI-NEXT: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C1]]
; SI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT12]](s64), [[SELECT13]](s64)
; SI-NEXT: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT9]]
; SI-NEXT: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]]
@@ -1537,39 +1491,38 @@ body: |
; SI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64)
; SI-NEXT: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV2]](s256)
- ;
; VI-LABEL: name: test_shl_s256_s256
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
+ ; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; VI-NEXT: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](s256)
- ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; VI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
- ; VI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; VI-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
+ ; VI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
+ ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
+ ; VI-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; VI-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
- ; VI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; VI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; VI-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; VI-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; VI-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; VI-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; VI-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; VI-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; VI-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[COPY1]](s32)
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[SUB3]](s32)
; VI-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[COPY1]](s32)
; VI-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]]
- ; VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; VI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[SUB2]](s32)
- ; VI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL]], [[C3]]
+ ; VI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL]], [[C1]]
; VI-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[SHL2]]
; VI-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV3]], [[SELECT1]]
; VI-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
- ; VI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
- ; VI-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
- ; VI-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
- ; VI-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
+ ; VI-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C3]]
+ ; VI-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB1]]
+ ; VI-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C3]]
+ ; VI-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C]]
; VI-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB1]](s32)
; VI-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[SUB1]](s32)
; VI-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32)
@@ -1577,37 +1530,37 @@ body: |
; VI-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
; VI-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR3]]
; VI-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]]
- ; VI-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR1]], [[C3]]
+ ; VI-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR1]], [[C1]]
; VI-NEXT: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; VI-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; VI-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; VI-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; VI-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; VI-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; VI-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; VI-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; VI-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; VI-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[COPY1]](s32)
; VI-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB7]](s32)
; VI-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[COPY1]](s32)
; VI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL5]]
; VI-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB6]](s32)
- ; VI-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL4]], [[C3]]
+ ; VI-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL4]], [[C1]]
; VI-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[SHL6]]
; VI-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV7]], [[SELECT7]]
; VI-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT6]]
; VI-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; VI-NEXT: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
- ; VI-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
- ; VI-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
- ; VI-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
- ; VI-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
+ ; VI-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C3]]
+ ; VI-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB]]
+ ; VI-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C3]]
+ ; VI-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C]]
; VI-NEXT: [[SHL7:%[0-9]+]]:_(s64) = G_SHL [[UV8]], [[SUB]](s32)
; VI-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB9]](s32)
; VI-NEXT: [[SHL8:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB]](s32)
; VI-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR5]], [[SHL8]]
; VI-NEXT: [[SHL9:%[0-9]+]]:_(s64) = G_SHL [[UV8]], [[SUB8]](s32)
- ; VI-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[SHL7]], [[C3]]
+ ; VI-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[SHL7]], [[C1]]
; VI-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[SHL9]]
; VI-NEXT: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV9]], [[SELECT10]]
- ; VI-NEXT: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT]], [[C3]]
- ; VI-NEXT: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C3]]
+ ; VI-NEXT: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT]], [[C1]]
+ ; VI-NEXT: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C1]]
; VI-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT12]](s64), [[SELECT13]](s64)
; VI-NEXT: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT9]]
; VI-NEXT: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]]
@@ -1617,39 +1570,38 @@ body: |
; VI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT16]](s64), [[SELECT17]](s64)
; VI-NEXT: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s128), [[MV1]](s128)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV2]](s256)
- ;
; GFX9-LABEL: name: test_shl_s256_s256
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
+ ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](s256)
- ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C]]
- ; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
- ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C]]
- ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
- ; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
+ ; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
+ ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
- ; GFX9-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; GFX9-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; GFX9-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; GFX9-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[COPY1]](s32)
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[SUB3]](s32)
; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV3]], [[COPY1]](s32)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]]
- ; GFX9-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX9-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[SUB2]](s32)
- ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL]], [[C3]]
+ ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL]], [[C1]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[OR]], [[SHL2]]
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV3]], [[SELECT1]]
; GFX9-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
- ; GFX9-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C2]]
- ; GFX9-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB1]]
- ; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C2]]
- ; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
+ ; GFX9-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C3]]
+ ; GFX9-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB1]]
+ ; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB1]](s32), [[C3]]
+ ; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB1]](s32), [[C]]
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB1]](s32)
; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV4]], [[SUB1]](s32)
; GFX9-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[UV5]], [[SUB5]](s32)
@@ -1657,37 +1609,37 @@ body: |
; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[OR1]], [[LSHR3]]
; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s1), [[UV4]], [[SELECT3]]
- ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR1]], [[C3]]
+ ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s1), [[LSHR1]], [[C1]]
; GFX9-NEXT: [[UV6:%[0-9]+]]:_(s64), [[UV7:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV1]](s128)
- ; GFX9-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C2]]
- ; GFX9-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[COPY1]]
- ; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C2]]
- ; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C1]]
+ ; GFX9-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
+ ; GFX9-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[COPY1]]
+ ; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY1]](s32), [[C3]]
+ ; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GFX9-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[COPY1]](s32)
; GFX9-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[UV6]], [[SUB7]](s32)
; GFX9-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[UV7]], [[COPY1]](s32)
; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL5]]
; GFX9-NEXT: [[SHL6:%[0-9]+]]:_(s64) = G_SHL [[UV6]], [[SUB6]](s32)
- ; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL4]], [[C3]]
+ ; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[SHL4]], [[C1]]
; GFX9-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[OR2]], [[SHL6]]
; GFX9-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[UV7]], [[SELECT7]]
; GFX9-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT6]]
; GFX9-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT5]], [[SELECT8]]
; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s64), [[UV9:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](s128)
- ; GFX9-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C2]]
- ; GFX9-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SUB]]
- ; GFX9-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C2]]
- ; GFX9-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C1]]
+ ; GFX9-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C3]]
+ ; GFX9-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SUB]]
+ ; GFX9-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[SUB]](s32), [[C3]]
+ ; GFX9-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[SUB]](s32), [[C]]
; GFX9-NEXT: [[SHL7:%[0-9]+]]:_(s64) = G_SHL [[UV8]], [[SUB]](s32)
; GFX9-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV8]], [[SUB9]](s32)
; GFX9-NEXT: [[SHL8:%[0-9]+]]:_(s64) = G_SHL [[UV9]], [[SUB]](s32)
; GFX9-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR5]], [[SHL8]]
; GFX9-NEXT: [[SHL9:%[0-9]+]]:_(s64) = G_SHL [[UV8]], [[SUB8]](s32)
- ; GFX9-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[SHL7]], [[C3]]
+ ; GFX9-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[SHL7]], [[C1]]
; GFX9-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s1), [[OR5]], [[SHL9]]
; GFX9-NEXT: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s1), [[UV9]], [[SELECT10]]
- ; GFX9-NEXT: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT]], [[C3]]
- ; GFX9-NEXT: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C3]]
+ ; GFX9-NEXT: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT]], [[C1]]
+ ; GFX9-NEXT: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SELECT2]], [[C1]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT12]](s64), [[SELECT13]](s64)
; GFX9-NEXT: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR3]], [[SELECT9]]
; GFX9-NEXT: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[OR4]], [[SELECT11]]
@@ -1750,7 +1702,6 @@ body: |
; SI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT3]](s64), [[SELECT5]](s64)
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; SI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
- ;
; VI-LABEL: name: test_shl_v2s128_v2s32
; VI: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -1791,7 +1742,6 @@ body: |
; VI-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT3]](s64), [[SELECT5]](s64)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; VI-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
- ;
; GFX9-LABEL: name: test_shl_v2s128_v2s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -1872,7 +1822,6 @@ body: |
; SI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
- ;
; VI-LABEL: name: test_shl_s65_s32
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; VI-NEXT: {{ $}}
@@ -1901,7 +1850,6 @@ body: |
; VI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
- ;
; GFX9-LABEL: name: test_shl_s65_s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; GFX9-NEXT: {{ $}}
@@ -1971,7 +1919,6 @@ body: |
; SI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
- ;
; VI-LABEL: name: test_shl_s65_s32_constant8
; VI: liveins: $vgpr0_vgpr1_vgpr2
; VI-NEXT: {{ $}}
@@ -1999,7 +1946,6 @@ body: |
; VI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
- ;
; GFX9-LABEL: name: test_shl_s65_s32_constant8
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
@@ -2070,7 +2016,6 @@ body: |
; SI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
- ;
; VI-LABEL: name: test_shl_s65_s32_known_pow2
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; VI-NEXT: {{ $}}
@@ -2100,7 +2045,6 @@ body: |
; VI-NEXT: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SELECT]](s64), [[SELECT2]](s64)
; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s128)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
- ;
; GFX9-LABEL: name: test_shl_s65_s32_known_pow2
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
index c8bd8ab33f18cbf..402454d989d6055 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
@@ -291,7 +291,8 @@ body: |
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C1]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
@@ -322,9 +323,10 @@ body: |
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
@@ -356,13 +358,14 @@ body: |
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
index a99a34f090466c8..9388d31b7d3c206 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
@@ -23,7 +23,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C]], [[SHL]]
; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_undef_undef
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -63,7 +62,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_0_undef
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -107,7 +105,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL]]
; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_undef_0
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -148,11 +145,11 @@ body: |
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C1]](s32)
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_0_1
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -195,12 +192,12 @@ body: |
; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_1_0
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -249,7 +246,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_0_0
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -289,11 +285,13 @@ body: |
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_1_1
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -341,7 +339,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_2_2
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -387,7 +384,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_2_undef
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -431,7 +427,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL]]
; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_undef_2
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -472,11 +467,11 @@ body: |
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C1]](s32)
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_2_3
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -519,12 +514,12 @@ body: |
; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_3_2
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -564,11 +559,12 @@ body: |
; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL]]
; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_undef_3
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -604,12 +600,13 @@ body: |
; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_3_undef
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -647,11 +644,13 @@ body: |
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_3_3
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -699,7 +698,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_0_2
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -747,7 +745,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_2_0
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -789,12 +786,12 @@ body: |
; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_3_0
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -838,11 +835,11 @@ body: |
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C1]](s32)
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_0_3
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -885,12 +882,12 @@ body: |
; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_1_2
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -934,11 +931,11 @@ body: |
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C1]](s32)
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v2s16_2_1
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -983,17 +980,17 @@ body: |
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; GFX8-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL1]]
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX8-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX8-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v4s16_v3s16_2_0
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1001,7 +998,7 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; GFX9-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
+ ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
@@ -1009,9 +1006,9 @@ body: |
; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
- ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](s16), [[TRUNC1]](s16)
- ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC]](s16)
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](s32)
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
+ ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX9-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
@@ -1047,12 +1044,12 @@ body: |
; GFX8-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v4s16_1_0
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1101,11 +1098,13 @@ body: |
; GFX8-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST1]](<2 x s32>)
; GFX8-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: shufflevector_v2s16_v4s16_1_3
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
index 51fffb7551a1259..4b1ac64b32b5a0f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
@@ -15,7 +15,6 @@ body: |
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8-NEXT: [[SMULH:%[0-9]+]]:_(s32) = G_SMULH [[COPY]], [[COPY1]]
; GFX8-NEXT: $vgpr0 = COPY [[SMULH]](s32)
- ;
; GFX9-LABEL: name: test_smulh_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -46,7 +45,6 @@ body: |
; GFX8-NEXT: [[SMULH1:%[0-9]+]]:_(s32) = G_SMULH [[UV1]], [[UV3]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SMULH]](s32), [[SMULH1]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_smulh_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -82,7 +80,6 @@ body: |
; GFX8-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[MUL]], [[C]](s32)
; GFX8-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ASHR]], 16
; GFX8-NEXT: $vgpr0 = COPY [[SEXT_INREG2]](s32)
- ;
; GFX9-LABEL: name: test_smulh_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -127,7 +124,6 @@ body: |
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR2]](s16)
; GFX8-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 8
; GFX8-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
- ;
; GFX9-LABEL: name: test_smulh_s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -185,7 +181,6 @@ body: |
; GFX8-NEXT: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG4]](s32), [[SEXT_INREG5]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_smulh_v2s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -251,7 +246,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_smulh_v2s8
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX9-NEXT: {{ $}}
@@ -355,8 +349,8 @@ body: |
; GFX8-NEXT: [[ASHR10:%[0-9]+]]:_(s16) = G_ASHR [[SHL7]], [[C3]](s16)
; GFX8-NEXT: [[MUL3:%[0-9]+]]:_(s16) = G_MUL [[ASHR9]], [[ASHR10]]
; GFX8-NEXT: [[ASHR11:%[0-9]+]]:_(s16) = G_ASHR [[MUL3]], [[C3]](s16)
- ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR2]](s16)
; GFX8-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR2]](s16)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
; GFX8-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR5]](s16)
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C4]]
@@ -371,7 +365,6 @@ body: |
; GFX8-NEXT: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL10]]
; GFX8-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-LABEL: name: test_smulh_v4s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
index cd75462271a36b5..9ba2ebe8c4b4d9a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
@@ -21,7 +21,6 @@ body: |
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[MUL]](s32)
; GFX8-NEXT: $vgpr1 = COPY [[SEXT]](s32)
- ;
; GFX9-LABEL: name: test_smulo_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -73,7 +72,6 @@ body: |
; GFX8-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8-NEXT: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR1]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_smulo_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -126,7 +124,6 @@ body: |
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[SEXT_INREG3]](s32)
; GFX8-NEXT: $vgpr1 = COPY [[SEXT]](s32)
- ;
; GFX9-LABEL: name: test_smulo_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -172,7 +169,6 @@ body: |
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[SEXT_INREG3]](s32)
; GFX8-NEXT: $vgpr1 = COPY [[SEXT]](s32)
- ;
; GFX9-LABEL: name: test_smulo_s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -239,7 +235,6 @@ body: |
; GFX8-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG8]](s32), [[SEXT_INREG9]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR1]](<2 x s32>)
; GFX8-NEXT: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_smulo_v2s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -301,8 +296,8 @@ body: |
; GFX8-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG3]], [[SEXT_INREG4]]
; GFX8-NEXT: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL1]], 8
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[SEXT_INREG5]]
- ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[MUL]](s32)
; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[MUL]](s32)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[MUL1]](s32)
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -315,7 +310,6 @@ body: |
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX8-NEXT: $vgpr1 = COPY [[ANYEXT1]](s32)
; GFX8-NEXT: $vgpr2 = COPY [[ANYEXT2]](s32)
- ;
; GFX9-LABEL: name: test_smulo_v2s8
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX9-NEXT: {{ $}}
@@ -333,8 +327,8 @@ body: |
; GFX9-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG3]], [[SEXT_INREG4]]
; GFX9-NEXT: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL1]], 8
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[SEXT_INREG5]]
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[MUL]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[MUL]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[MUL1]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -417,7 +411,6 @@ body: |
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[OR2]](s32)
; GFX8-NEXT: $vgpr1 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_smulo_v4s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -499,7 +492,6 @@ body: |
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[OR]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[SEXT_INREG3]](s32)
; GFX8-NEXT: $vgpr1 = COPY [[SEXT]](s32)
- ;
; GFX9-LABEL: name: test_smulo_s24
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
index 5bc314d29c97fee..43496a8aec8c4a4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
@@ -31,15 +31,14 @@ body: |
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL1]]
; GFX6-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SELECT1]], [[C1]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[ASHR1]](s32)
- ;
; GFX8-LABEL: name: sshlsat_s7
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 127
+ ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C1]](s16)
@@ -55,15 +54,14 @@ body: |
; GFX8-NEXT: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SELECT1]], [[C1]](s16)
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR1]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: sshlsat_s7
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 127
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C1]](s16)
@@ -114,15 +112,14 @@ body: |
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL1]]
; GFX6-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SELECT1]], [[C1]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[ASHR1]](s32)
- ;
; GFX8-LABEL: name: sshlsat_s8
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C1]](s16)
@@ -138,15 +135,14 @@ body: |
; GFX8-NEXT: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SELECT1]], [[C1]](s16)
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR1]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: sshlsat_s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C1]](s16)
@@ -208,8 +204,8 @@ body: |
; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s32), [[ASHR2]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SELECT2]], [[SHL3]]
; GFX6-NEXT: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SELECT3]], [[C1]](s32)
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; GFX6-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C6]]
; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C2]]
@@ -218,7 +214,6 @@ body: |
; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC1]]
; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX8-LABEL: name: sshlsat_v2s8
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -228,8 +223,8 @@ body: |
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C2]](s16)
@@ -260,7 +255,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL4]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: sshlsat_v2s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -270,8 +264,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C2]](s16)
@@ -340,7 +334,6 @@ body: |
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL1]]
; GFX6-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SELECT1]], [[C1]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[ASHR1]](s32)
- ;
; GFX8-LABEL: name: sshlsat_s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -359,7 +352,6 @@ body: |
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: sshlsat_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -416,21 +408,21 @@ body: |
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[ASHR]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL1]]
; GFX6-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SELECT1]], [[C]](s32)
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX6-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
- ; GFX6-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[LSHR1]](s32)
- ; GFX6-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[LSHR1]](s32)
+ ; GFX6-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND1]](s32)
+ ; GFX6-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[AND1]](s32)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL2]](s32), [[C4]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[C2]], [[C3]]
; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s32), [[ASHR2]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SELECT2]], [[SHL3]]
; GFX6-NEXT: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SELECT3]], [[C]](s32)
- ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
- ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C1]]
- ; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL4]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C1]]
+ ; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX8-LABEL: name: sshlsat_v2s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -466,7 +458,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: sshlsat_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -522,32 +513,34 @@ body: |
; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; GFX6-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
- ; GFX6-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[LSHR1]](s32)
- ; GFX6-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[LSHR1]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
- ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL]](s32), [[C3]]
- ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
+ ; GFX6-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[AND]](s32)
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL]](s32), [[C4]]
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[C3]]
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[ASHR]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL1]]
; GFX6-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SELECT1]], [[C]](s32)
- ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C4]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; GFX6-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
- ; GFX6-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND]](s32)
- ; GFX6-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[AND]](s32)
- ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL2]](s32), [[C3]]
- ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND1]](s32)
+ ; GFX6-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[AND1]](s32)
+ ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL2]](s32), [[C4]]
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[C2]], [[C3]]
; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s32), [[ASHR2]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SELECT2]], [[SHL3]]
; GFX6-NEXT: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SELECT3]], [[C]](s32)
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
- ; GFX6-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[SHL4]], [[LSHR2]](s32)
- ; GFX6-NEXT: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[SHL5]], [[LSHR2]](s32)
- ; GFX6-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL4]](s32), [[C3]]
- ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s1), [[C1]], [[C2]]
+ ; GFX6-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[SHL4]], [[AND2]](s32)
+ ; GFX6-NEXT: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[SHL5]], [[AND2]](s32)
+ ; GFX6-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL4]](s32), [[C4]]
+ ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s1), [[C2]], [[C3]]
; GFX6-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL4]](s32), [[ASHR4]]
; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SELECT4]], [[SHL5]]
; GFX6-NEXT: [[ASHR5:%[0-9]+]]:_(s32) = G_ASHR [[SELECT5]], [[C]](s32)
@@ -556,23 +549,23 @@ body: |
; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
- ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C4]]
- ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C4]]
- ; GFX6-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL6]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C1]]
+ ; GFX6-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL6]]
; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR5]], [[C4]]
- ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]]
- ; GFX6-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
- ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL7]]
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ASHR5]], [[C1]]
+ ; GFX6-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; GFX6-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL7]]
; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
- ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
- ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL8]]
+ ; GFX6-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; GFX6-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
+ ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL8]]
; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX8-LABEL: name: sshlsat_v3s16
; GFX8: liveins: $vgpr0_vgpr1_vgpr2
; GFX8-NEXT: {{ $}}
@@ -628,13 +621,13 @@ body: |
; GFX8-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; GFX8-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
- ; GFX8-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL5]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
+ ; GFX8-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL5]]
; GFX8-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: sshlsat_v3s16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
@@ -730,44 +723,45 @@ body: |
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[ASHR]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL1]]
; GFX6-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SELECT1]], [[C]](s32)
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; GFX6-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
- ; GFX6-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[LSHR2]](s32)
- ; GFX6-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[LSHR2]](s32)
+ ; GFX6-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND1]](s32)
+ ; GFX6-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[AND1]](s32)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL2]](s32), [[C4]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[C2]], [[C3]]
; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s32), [[ASHR2]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SELECT2]], [[SHL3]]
; GFX6-NEXT: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SELECT3]], [[C]](s32)
- ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
- ; GFX6-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[SHL4]], [[AND1]](s32)
- ; GFX6-NEXT: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[SHL5]], [[AND1]](s32)
+ ; GFX6-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[SHL4]], [[AND2]](s32)
+ ; GFX6-NEXT: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[SHL5]], [[AND2]](s32)
; GFX6-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL4]](s32), [[C4]]
; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s1), [[C2]], [[C3]]
; GFX6-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL4]](s32), [[ASHR4]]
; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SELECT4]], [[SHL5]]
; GFX6-NEXT: [[ASHR5:%[0-9]+]]:_(s32) = G_ASHR [[SELECT5]], [[C]](s32)
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
; GFX6-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
- ; GFX6-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[SHL6]], [[LSHR3]](s32)
- ; GFX6-NEXT: [[ASHR6:%[0-9]+]]:_(s32) = G_ASHR [[SHL7]], [[LSHR3]](s32)
+ ; GFX6-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[SHL6]], [[AND3]](s32)
+ ; GFX6-NEXT: [[ASHR6:%[0-9]+]]:_(s32) = G_ASHR [[SHL7]], [[AND3]](s32)
; GFX6-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL6]](s32), [[C4]]
; GFX6-NEXT: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s1), [[C2]], [[C3]]
; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL6]](s32), [[ASHR6]]
; GFX6-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s1), [[SELECT6]], [[SHL7]]
; GFX6-NEXT: [[ASHR7:%[0-9]+]]:_(s32) = G_ASHR [[SELECT7]], [[C]](s32)
- ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
- ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C1]]
- ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL8]]
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C1]]
+ ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL8]]
; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ASHR5]], [[C1]]
- ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ASHR7]], [[C1]]
- ; GFX6-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
- ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL9]]
+ ; GFX6-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ASHR5]], [[C1]]
+ ; GFX6-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ASHR7]], [[C1]]
+ ; GFX6-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL9]]
; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX8-LABEL: name: sshlsat_v4s16
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -831,7 +825,6 @@ body: |
; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: sshlsat_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -914,7 +907,6 @@ body: |
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[ASHR]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL]]
; GFX6-NEXT: $vgpr0 = COPY [[SELECT1]](s32)
- ;
; GFX8-LABEL: name: sshlsat_s32
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -930,7 +922,6 @@ body: |
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[ASHR]]
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL]]
; GFX8-NEXT: $vgpr0 = COPY [[SELECT1]](s32)
- ;
; GFX9-LABEL: name: sshlsat_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -982,7 +973,6 @@ body: |
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SELECT2]], [[SHL1]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT1]](s32), [[SELECT3]](s32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX8-LABEL: name: sshlsat_v2s32
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -1007,7 +997,6 @@ body: |
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SELECT2]], [[SHL1]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT1]](s32), [[SELECT3]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: sshlsat_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1060,7 +1049,6 @@ body: |
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[ASHR]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL]]
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT1]](s64)
- ;
; GFX8-LABEL: name: sshlsat_s64
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -1077,7 +1065,6 @@ body: |
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[ASHR]]
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL]]
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT1]](s64)
- ;
; GFX9-LABEL: name: sshlsat_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1132,7 +1119,6 @@ body: |
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[SELECT2]], [[SHL1]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT1]](s64), [[SELECT3]](s64)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX8-LABEL: name: sshlsat_v2s64
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX8-NEXT: {{ $}}
@@ -1159,7 +1145,6 @@ body: |
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[SELECT2]], [[SHL1]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT1]](s64), [[SELECT3]](s64)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: sshlsat_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
index 57b1ab9b194ec50..896d057fd74f67f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
@@ -256,16 +256,17 @@ body: |
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST9]], [[C2]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[SHL2]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C2]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST9]], [[C2]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK-NEXT: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST10]](<2 x s16>), [[BITCAST11]](<2 x s16>), [[BITCAST12]](<2 x s16>)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]]
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C3]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND5]](s32), [[AND6]](s32), [[AND7]](s32)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]]
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C3]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND6]](s32), [[AND7]](s32), [[AND8]](s32)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
index ba5d29080948757..7d6b8c5f6219022 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
@@ -31,7 +31,6 @@ body: |
; GFX6-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; GFX8-LABEL: name: ssubsat_s7
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -55,7 +54,6 @@ body: |
; GFX8-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SUB2]], [[C]](s16)
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: ssubsat_s7
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -105,7 +103,6 @@ body: |
; GFX6-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; GFX8-LABEL: name: ssubsat_s8
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -129,7 +126,6 @@ body: |
; GFX8-NEXT: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SUB2]], [[C]](s16)
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: ssubsat_s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -191,8 +187,8 @@ body: |
; GFX6-NEXT: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB4]]
; GFX6-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[SMIN3]]
; GFX6-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SUB5]], [[C1]](s32)
- ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; GFX6-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; GFX6-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C5]]
; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -202,7 +198,6 @@ body: |
; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX8-LABEL: name: ssubsat_v2s8
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -246,7 +241,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: ssubsat_v2s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -317,7 +311,6 @@ body: |
; GFX6-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[ASHR]](s32)
- ;
; GFX8-LABEL: name: ssubsat_s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -337,7 +330,6 @@ body: |
; GFX8-NEXT: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[SMIN1]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB2]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: ssubsat_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -403,7 +395,6 @@ body: |
; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL4]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX8-LABEL: name: ssubsat_v2s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -441,7 +432,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: ssubsat_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -522,13 +512,13 @@ body: |
; GFX6-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL7]]
; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
- ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
- ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL8]]
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
+ ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL8]]
; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX8-LABEL: name: ssubsat_v3s16
; GFX8: liveins: $vgpr0_vgpr1_vgpr2
; GFX8-NEXT: {{ $}}
@@ -587,13 +577,13 @@ body: |
; GFX8-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; GFX8-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
- ; GFX8-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL2]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
+ ; GFX8-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; GFX8-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: ssubsat_v3s16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
@@ -719,7 +709,6 @@ body: |
; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX8-LABEL: name: ssubsat_v4s16
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -787,7 +776,6 @@ body: |
; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: ssubsat_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -827,7 +815,6 @@ body: |
; GFX6-NEXT: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX6-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[SMIN1]]
; GFX6-NEXT: $vgpr0 = COPY [[SUB2]](s32)
- ;
; GFX8-LABEL: name: ssubsat_s32
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -844,7 +831,6 @@ body: |
; GFX8-NEXT: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX8-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[SMIN1]]
; GFX8-NEXT: $vgpr0 = COPY [[SUB2]](s32)
- ;
; GFX9-LABEL: name: ssubsat_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -890,7 +876,6 @@ body: |
; GFX6-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[UV1]], [[SMIN3]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SUB2]](s32), [[SUB5]](s32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX8-LABEL: name: ssubsat_v2s32
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -917,7 +902,6 @@ body: |
; GFX8-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[UV1]], [[SMIN3]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SUB2]](s32), [[SUB5]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: ssubsat_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -965,7 +949,6 @@ body: |
; GFX6-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[XOR]](s1), [[MV1]], [[MV]]
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; GFX8-LABEL: name: ssubsat_s64
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -990,7 +973,6 @@ body: |
; GFX8-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[XOR]](s1), [[MV1]], [[MV]]
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; GFX9-LABEL: name: ssubsat_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1069,7 +1051,6 @@ body: |
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[XOR1]](s1), [[MV3]], [[MV2]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT]](s64), [[SELECT1]](s64)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX8-LABEL: name: ssubsat_v2s64
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX8-NEXT: {{ $}}
@@ -1112,7 +1093,6 @@ body: |
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[XOR1]](s1), [[MV3]], [[MV2]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT]](s64), [[SELECT1]](s64)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: ssubsat_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
index c2fdbff77868f01..fb1e0537556fa35 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
@@ -21,7 +21,6 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; SI-NEXT: G_STORE [[AND1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s1_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
@@ -31,7 +30,6 @@ body: |
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; CI-NEXT: G_STORE [[AND1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s1_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -41,7 +39,6 @@ body: |
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; VI-NEXT: G_STORE [[AND1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s1_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -71,7 +68,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: G_STORE [[AND]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s7_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
@@ -80,7 +76,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CI-NEXT: G_STORE [[AND]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s7_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -89,7 +84,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI-NEXT: G_STORE [[AND]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s7_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -116,21 +110,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s8_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s8_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s8_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -162,14 +153,12 @@ body: |
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s16_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s16_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -183,7 +172,6 @@ body: |
; VI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI-NEXT: G_STORE [[ANYEXT]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s16_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -208,21 +196,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s16_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s16_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s16_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -247,21 +232,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s16_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s16_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s16_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -292,7 +274,6 @@ body: |
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s24_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
@@ -305,7 +286,6 @@ body: |
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; CI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
; CI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s24_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -318,7 +298,6 @@ body: |
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
; VI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s24_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -355,7 +334,6 @@ body: |
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s24_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
@@ -368,7 +346,6 @@ body: |
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; CI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; CI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s24_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -381,7 +358,6 @@ body: |
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s24_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -425,7 +401,6 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s24_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
@@ -438,7 +413,6 @@ body: |
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; CI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 1, addrspace 1)
; CI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s24_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -458,7 +432,6 @@ body: |
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; VI-NEXT: G_STORE [[ANYEXT]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s24_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -491,7 +464,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33554431
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: G_STORE [[AND]](s32), [[COPY]](p1) :: (store (s32), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s25_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
@@ -500,7 +472,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33554431
; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CI-NEXT: G_STORE [[AND]](s32), [[COPY]](p1) :: (store (s32), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s25_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -509,7 +480,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33554431
; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI-NEXT: G_STORE [[AND]](s32), [[COPY]](p1) :: (store (s32), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s25_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -573,18 +543,17 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s32_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s32), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s32_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -609,7 +578,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
; VI-NEXT: G_STORE [[ANYEXT1]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s32_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -639,14 +607,12 @@ body: |
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s32_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s32), align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s32_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -659,7 +625,6 @@ body: |
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s32_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -683,21 +648,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s32), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s32_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s32), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s32_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s32), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s32_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -735,18 +697,17 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_p3_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr2
; CI-NEXT: G_STORE [[COPY1]](p3), [[COPY]](p1) :: (store (p3), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p3_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -772,7 +733,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
; VI-NEXT: G_STORE [[ANYEXT1]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_p3_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -803,14 +763,12 @@ body: |
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_p3_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr2
; CI-NEXT: G_STORE [[COPY1]](p3), [[COPY]](p1) :: (store (p3), align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p3_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -824,7 +782,6 @@ body: |
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_p3_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -848,21 +805,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr2
; SI-NEXT: G_STORE [[COPY1]](p3), [[COPY]](p1) :: (store (p3), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_p3_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr2
; CI-NEXT: G_STORE [[COPY1]](p3), [[COPY]](p1) :: (store (p3), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p3_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr2
; VI-NEXT: G_STORE [[COPY1]](p3), [[COPY]](p1) :: (store (p3), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_p3_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -904,18 +858,18 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]
+ ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C6]](s64)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; SI-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C5]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY4]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C5]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C6]](s64)
; SI-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s48_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
@@ -929,7 +883,6 @@ body: |
; CI-NEXT: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store (s32), align 1, addrspace 1)
; CI-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; CI-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s48_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -966,7 +919,6 @@ body: |
; VI-NEXT: G_STORE [[TRUNC3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR4]](s16)
; VI-NEXT: G_STORE [[ANYEXT2]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s48_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1011,7 +963,6 @@ body: |
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; SI-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s48_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
@@ -1025,7 +976,6 @@ body: |
; CI-NEXT: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store (s32), align 2, addrspace 1)
; CI-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; CI-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s48_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -1045,7 +995,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; VI-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s48_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1121,7 +1070,8 @@ body: |
; SI-NEXT: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[COPY4]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]
+ ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY4]](s32)
; SI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C6]](s64)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -1130,24 +1080,23 @@ body: |
; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY5]], [[C2]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C6]](s64)
; SI-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LSHR4]], [[COPY7]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]]
+ ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY7]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C6]](s64)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s64_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store (s64), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s64_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -1194,7 +1143,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR6]](s16)
; VI-NEXT: G_STORE [[ANYEXT3]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s64_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1236,14 +1184,12 @@ body: |
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s64_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store (s64), align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s64_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -1268,7 +1214,6 @@ body: |
; VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
; VI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s64_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1292,21 +1237,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store (s64), align 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s64_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store (s64), align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s64_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store (s64), align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s64_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1330,21 +1272,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store (s64), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s64_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store (s64), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s64_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store (s64), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s64_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1368,21 +1307,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store (s64), align 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s64_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store (s64), align 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s64_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store (s64), align 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s64_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1426,7 +1362,8 @@ body: |
; SI-NEXT: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[COPY4]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]
+ ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY4]](s32)
; SI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C6]](s64)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -1435,24 +1372,23 @@ body: |
; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY5]], [[C2]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C6]](s64)
; SI-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LSHR4]], [[COPY7]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]]
+ ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY7]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C6]](s64)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_p0_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](p0), [[COPY]](p1) :: (store (p0), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p0_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -1500,7 +1436,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR6]](s16)
; VI-NEXT: G_STORE [[ANYEXT3]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_p0_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1543,14 +1478,12 @@ body: |
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_p0_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](p0), [[COPY]](p1) :: (store (p0), align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p0_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -1576,7 +1509,6 @@ body: |
; VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
; VI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_p0_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1600,21 +1532,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](p0), [[COPY]](p1) :: (store (p0), align 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_p0_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](p0), [[COPY]](p1) :: (store (p0), align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p0_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](p0), [[COPY]](p1) :: (store (p0), align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_p0_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1638,21 +1567,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](p0), [[COPY]](p1) :: (store (p0), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_p0_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](p0), [[COPY]](p1) :: (store (p0), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p0_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](p0), [[COPY]](p1) :: (store (p0), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_p0_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1676,21 +1602,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](p0), [[COPY]](p1) :: (store (p0), align 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_p0_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](p0), [[COPY]](p1) :: (store (p0), align 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p0_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](p0), [[COPY]](p1) :: (store (p0), align 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_p0_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1734,7 +1657,8 @@ body: |
; SI-NEXT: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[COPY4]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]
+ ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY4]](s32)
; SI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C6]](s64)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -1743,24 +1667,23 @@ body: |
; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY5]], [[C2]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C6]](s64)
; SI-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LSHR4]], [[COPY7]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]]
+ ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY7]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C6]](s64)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_p999_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](p999), [[COPY]](p1) :: (store (p999), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p999_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -1808,7 +1731,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR6]](s16)
; VI-NEXT: G_STORE [[ANYEXT3]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_p999_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1851,14 +1773,12 @@ body: |
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_p999_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](p999), [[COPY]](p1) :: (store (p999), align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p999_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -1884,7 +1804,6 @@ body: |
; VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
; VI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_p999_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1908,21 +1827,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](p999), [[COPY]](p1) :: (store (p999), align 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_p999_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](p999), [[COPY]](p1) :: (store (p999), align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p999_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](p999), [[COPY]](p1) :: (store (p999), align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_p999_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1946,21 +1862,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](p999), [[COPY]](p1) :: (store (p999), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_p999_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](p999), [[COPY]](p1) :: (store (p999), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p999_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](p999), [[COPY]](p1) :: (store (p999), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_p999_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -1984,21 +1897,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](p999), [[COPY]](p1) :: (store (p999), align 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_p999_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](p999), [[COPY]](p1) :: (store (p999), align 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p999_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](p999), [[COPY]](p1) :: (store (p999), align 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_p999_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2036,7 +1946,8 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -2046,24 +1957,23 @@ body: |
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY4]], [[C]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2s32_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](<2 x s32>), [[COPY]](p1) :: (store (<2 x s32>), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s32_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -2106,7 +2016,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR5]](s16)
; VI-NEXT: G_STORE [[ANYEXT3]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2s32_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2144,14 +2053,12 @@ body: |
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2s32_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](<2 x s32>), [[COPY]](p1) :: (store (<2 x s32>), align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s32_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -2172,7 +2079,6 @@ body: |
; VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2s32_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2196,21 +2102,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](<2 x s32>), [[COPY]](p1) :: (store (<2 x s32>), align 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2s32_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](<2 x s32>), [[COPY]](p1) :: (store (<2 x s32>), align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s32_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](<2 x s32>), [[COPY]](p1) :: (store (<2 x s32>), align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2s32_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2234,21 +2137,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](<2 x s32>), [[COPY]](p1) :: (store (<2 x s32>), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2s32_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](<2 x s32>), [[COPY]](p1) :: (store (<2 x s32>), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s32_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](<2 x s32>), [[COPY]](p1) :: (store (<2 x s32>), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2s32_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2272,21 +2172,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](<2 x s32>), [[COPY]](p1) :: (store (<2 x s32>), align 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2s32_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](<2 x s32>), [[COPY]](p1) :: (store (<2 x s32>), align 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s32_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](<2 x s32>), [[COPY]](p1) :: (store (<2 x s32>), align 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2s32_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2325,7 +2222,8 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -2336,24 +2234,23 @@ body: |
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY4]], [[C]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2p3_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](<2 x p3>), [[COPY]](p1) :: (store (<2 x p3>), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2p3_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -2398,7 +2295,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR5]](s16)
; VI-NEXT: G_STORE [[ANYEXT3]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2p3_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2438,14 +2334,12 @@ body: |
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2p3_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](<2 x p3>), [[COPY]](p1) :: (store (<2 x p3>), align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2p3_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -2468,7 +2362,6 @@ body: |
; VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2p3_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2492,21 +2385,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](<2 x p3>), [[COPY]](p1) :: (store (<2 x p3>), align 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2p3_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](<2 x p3>), [[COPY]](p1) :: (store (<2 x p3>), align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2p3_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](<2 x p3>), [[COPY]](p1) :: (store (<2 x p3>), align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2p3_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2530,21 +2420,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](<2 x p3>), [[COPY]](p1) :: (store (<2 x p3>), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2p3_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](<2 x p3>), [[COPY]](p1) :: (store (<2 x p3>), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2p3_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](<2 x p3>), [[COPY]](p1) :: (store (<2 x p3>), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2p3_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2568,21 +2455,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](<2 x p3>), [[COPY]](p1) :: (store (<2 x p3>), align 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2p3_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](<2 x p3>), [[COPY]](p1) :: (store (<2 x p3>), align 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2p3_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](<2 x p3>), [[COPY]](p1) :: (store (<2 x p3>), align 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2p3_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2643,14 +2527,12 @@ body: |
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s64)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v4s16_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](<4 x s16>), [[COPY]](p1) :: (store (<4 x s16>), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v4s16_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -2694,7 +2576,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR5]](s16)
; VI-NEXT: G_STORE [[ANYEXT3]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v4s16_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2733,14 +2614,12 @@ body: |
; SI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v4s16_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](<4 x s16>), [[COPY]](p1) :: (store (<4 x s16>), align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v4s16_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -2762,7 +2641,6 @@ body: |
; VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; VI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v4s16_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2786,21 +2664,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](<4 x s16>), [[COPY]](p1) :: (store (<4 x s16>), align 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v4s16_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](<4 x s16>), [[COPY]](p1) :: (store (<4 x s16>), align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v4s16_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](<4 x s16>), [[COPY]](p1) :: (store (<4 x s16>), align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v4s16_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2824,21 +2699,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](<4 x s16>), [[COPY]](p1) :: (store (<4 x s16>), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v4s16_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](<4 x s16>), [[COPY]](p1) :: (store (<4 x s16>), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v4s16_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](<4 x s16>), [[COPY]](p1) :: (store (<4 x s16>), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v4s16_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2862,21 +2734,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](<4 x s16>), [[COPY]](p1) :: (store (<4 x s16>), align 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v4s16_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; CI-NEXT: G_STORE [[COPY1]](<4 x s16>), [[COPY]](p1) :: (store (<4 x s16>), align 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v4s16_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; VI-NEXT: G_STORE [[COPY1]](<4 x s16>), [[COPY]](p1) :: (store (<4 x s16>), align 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v4s16_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -2914,7 +2783,8 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -2924,13 +2794,14 @@ body: |
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY4]], [[C]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
@@ -2940,24 +2811,23 @@ body: |
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY7]], [[C]](s32)
; SI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; SI-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY8]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY8]](s32)
; SI-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[COPY9]](s32)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY9]](s32)
; SI-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD8]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI-NEXT: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v3s32_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; CI-NEXT: G_STORE [[COPY1]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v3s32_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
@@ -3017,7 +2887,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; VI-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR8]](s16)
; VI-NEXT: G_STORE [[ANYEXT5]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v3s32_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; GFX9-NEXT: {{ $}}
@@ -3062,14 +2931,12 @@ body: |
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v3s32_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; CI-NEXT: G_STORE [[COPY1]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v3s32_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
@@ -3097,7 +2964,6 @@ body: |
; VI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; VI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v3s32_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; GFX9-NEXT: {{ $}}
@@ -3126,21 +2992,18 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV2]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v3s32_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; CI-NEXT: G_STORE [[COPY1]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v3s32_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; VI-NEXT: G_STORE [[COPY1]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v3s32_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; GFX9-NEXT: {{ $}}
@@ -3169,21 +3032,18 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV2]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 8, align 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v3s32_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; CI-NEXT: G_STORE [[COPY1]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 8, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v3s32_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; VI-NEXT: G_STORE [[COPY1]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 8, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v3s32_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; GFX9-NEXT: {{ $}}
@@ -3212,21 +3072,18 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV2]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 8, align 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v3s32_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; CI-NEXT: G_STORE [[COPY1]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v3s32_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; VI-NEXT: G_STORE [[COPY1]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v3s32_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; GFX9-NEXT: {{ $}}
@@ -3264,7 +3121,8 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -3274,13 +3132,14 @@ body: |
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY4]], [[C]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
@@ -3290,13 +3149,14 @@ body: |
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY7]], [[C]](s32)
; SI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; SI-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY8]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY8]](s32)
; SI-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[COPY9]](s32)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY9]](s32)
; SI-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD8]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI-NEXT: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
@@ -3306,24 +3166,23 @@ body: |
; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY10]], [[C]](s32)
; SI-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
; SI-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY11]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY11]](s32)
; SI-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY10]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR9]], [[COPY12]](s32)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
+ ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY12]](s32)
; SI-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD12]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI-NEXT: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v4s32_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: G_STORE [[COPY1]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v4s32_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -3400,7 +3259,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR11]](s16)
; VI-NEXT: G_STORE [[ANYEXT7]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v4s32_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -3452,14 +3310,12 @@ body: |
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v4s32_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: G_STORE [[COPY1]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v4s32_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -3494,7 +3350,6 @@ body: |
; VI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v4s32_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -3518,21 +3373,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: G_STORE [[COPY1]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v4s32_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: G_STORE [[COPY1]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v4s32_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: G_STORE [[COPY1]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v4s32_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -3556,21 +3408,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: G_STORE [[COPY1]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v4s32_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: G_STORE [[COPY1]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 8, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v4s32_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: G_STORE [[COPY1]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 8, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v4s32_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -3594,21 +3443,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: G_STORE [[COPY1]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v4s32_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: G_STORE [[COPY1]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v4s32_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: G_STORE [[COPY1]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v4s32_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -3652,7 +3498,8 @@ body: |
; SI-NEXT: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[COPY4]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]
+ ; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY4]](s32)
; SI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C6]](s64)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -3661,13 +3508,14 @@ body: |
; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY5]], [[C2]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C6]](s64)
; SI-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LSHR4]], [[COPY7]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]]
+ ; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY7]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C6]](s64)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
@@ -3682,13 +3530,14 @@ body: |
; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[COPY10]], [[C2]](s32)
; SI-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
; SI-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C5]]
- ; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY11]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C5]]
+ ; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY11]](s32)
; SI-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C6]](s64)
; SI-NEXT: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI-NEXT: G_STORE [[LSHR9]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[LSHR8]], [[COPY12]](s32)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C5]]
+ ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY12]](s32)
; SI-NEXT: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD9]], [[C6]](s64)
; SI-NEXT: G_STORE [[LSHR8]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI-NEXT: G_STORE [[LSHR10]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
@@ -3697,24 +3546,23 @@ body: |
; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[COPY13]], [[C2]](s32)
; SI-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD8]], [[C3]](s64)
; SI-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C5]]
- ; SI-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY14]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C5]]
+ ; SI-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY14]](s32)
; SI-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD8]], [[C6]](s64)
; SI-NEXT: G_STORE [[COPY13]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR12]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[LSHR11]], [[COPY15]](s32)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C5]]
+ ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY15]](s32)
; SI-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD12]], [[C6]](s64)
; SI-NEXT: G_STORE [[LSHR11]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI-NEXT: G_STORE [[LSHR13]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2s64_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: G_STORE [[COPY1]](<2 x s64>), [[COPY]](p1) :: (store (<2 x s64>), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s64_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -3800,7 +3648,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR11]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR13]](s16)
; VI-NEXT: G_STORE [[ANYEXT7]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2s64_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -3861,14 +3708,12 @@ body: |
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C3]](s64)
; SI-NEXT: G_STORE [[COPY8]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2s64_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: G_STORE [[COPY1]](<2 x s64>), [[COPY]](p1) :: (store (<2 x s64>), align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s64_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -3912,7 +3757,6 @@ body: |
; VI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C3]](s64)
; VI-NEXT: G_STORE [[COPY8]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2s64_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -3936,21 +3780,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: G_STORE [[COPY1]](<2 x s64>), [[COPY]](p1) :: (store (<2 x s64>), align 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2s64_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: G_STORE [[COPY1]](<2 x s64>), [[COPY]](p1) :: (store (<2 x s64>), align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s64_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: G_STORE [[COPY1]](<2 x s64>), [[COPY]](p1) :: (store (<2 x s64>), align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2s64_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -3974,21 +3815,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: G_STORE [[COPY1]](<2 x s64>), [[COPY]](p1) :: (store (<2 x s64>), align 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2s64_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: G_STORE [[COPY1]](<2 x s64>), [[COPY]](p1) :: (store (<2 x s64>), align 8, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s64_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: G_STORE [[COPY1]](<2 x s64>), [[COPY]](p1) :: (store (<2 x s64>), align 8, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2s64_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -4012,21 +3850,18 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: G_STORE [[COPY1]](<2 x s64>), [[COPY]](p1) :: (store (<2 x s64>), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2s64_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: G_STORE [[COPY1]](<2 x s64>), [[COPY]](p1) :: (store (<2 x s64>), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s64_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: G_STORE [[COPY1]](<2 x s64>), [[COPY]](p1) :: (store (<2 x s64>), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2s64_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -4065,7 +3900,8 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -4075,13 +3911,14 @@ body: |
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY4]], [[C]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
@@ -4091,13 +3928,14 @@ body: |
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY7]], [[C]](s32)
; SI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; SI-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY8]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY8]](s32)
; SI-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[COPY9]](s32)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY9]](s32)
; SI-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD8]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI-NEXT: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
@@ -4107,17 +3945,17 @@ body: |
; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY10]], [[C]](s32)
; SI-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
; SI-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY11]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY11]](s32)
; SI-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY10]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR9]], [[COPY12]](s32)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
+ ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY12]](s32)
; SI-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD12]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI-NEXT: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v8s16_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
@@ -4125,7 +3963,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<8 x s16>)
; CI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v8s16_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -4203,7 +4040,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR11]](s16)
; VI-NEXT: G_STORE [[ANYEXT7]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v8s16_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -4257,7 +4093,6 @@ body: |
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v8s16_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
@@ -4265,7 +4100,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<8 x s16>)
; CI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v8s16_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -4301,7 +4135,6 @@ body: |
; VI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v8s16_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -4327,7 +4160,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<8 x s16>)
; SI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v8s16_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
@@ -4335,7 +4167,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<8 x s16>)
; CI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v8s16_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -4343,7 +4174,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<8 x s16>)
; VI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v8s16_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -4369,7 +4199,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<8 x s16>)
; SI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v8s16_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
@@ -4377,7 +4206,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<8 x s16>)
; CI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 8, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v8s16_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -4385,7 +4213,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<8 x s16>)
; VI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 8, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v8s16_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -4411,7 +4238,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<8 x s16>)
; SI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v8s16_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
@@ -4419,7 +4245,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<8 x s16>)
; CI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v8s16_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -4427,7 +4252,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<8 x s16>)
; VI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v8s16_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -4467,7 +4291,8 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -4477,13 +4302,14 @@ body: |
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY4]], [[C]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
@@ -4493,13 +4319,14 @@ body: |
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY7]], [[C]](s32)
; SI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; SI-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY8]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY8]](s32)
; SI-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[COPY9]](s32)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY9]](s32)
; SI-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD8]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI-NEXT: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
@@ -4509,17 +4336,17 @@ body: |
; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY10]], [[C]](s32)
; SI-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
; SI-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY11]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY11]](s32)
; SI-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY10]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR9]], [[COPY12]](s32)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
+ ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY12]](s32)
; SI-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD12]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI-NEXT: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2p0_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
@@ -4527,7 +4354,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x p0>)
; CI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2p0_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -4605,7 +4431,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR11]](s16)
; VI-NEXT: G_STORE [[ANYEXT7]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2p0_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -4659,7 +4484,6 @@ body: |
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2p0_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
@@ -4667,7 +4491,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x p0>)
; CI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2p0_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -4703,7 +4526,6 @@ body: |
; VI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2p0_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -4729,7 +4551,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x p0>)
; SI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2p0_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
@@ -4737,7 +4558,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x p0>)
; CI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2p0_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -4745,7 +4565,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x p0>)
; VI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2p0_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -4771,7 +4590,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x p0>)
; SI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2p0_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
@@ -4779,7 +4597,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x p0>)
; CI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 8, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2p0_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -4787,7 +4604,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x p0>)
; VI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 8, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2p0_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -4813,7 +4629,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x p0>)
; SI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2p0_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
@@ -4821,7 +4636,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x p0>)
; CI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2p0_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -4829,7 +4643,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x p0>)
; VI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2p0_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -4869,7 +4682,8 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -4879,13 +4693,14 @@ body: |
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY4]], [[C]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
@@ -4895,17 +4710,17 @@ body: |
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY7]], [[C]](s32)
; SI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; SI-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY8]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY8]](s32)
; SI-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[COPY9]](s32)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY9]](s32)
; SI-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD8]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI-NEXT: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s96_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; CI-NEXT: {{ $}}
@@ -4913,7 +4728,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr2_vgpr3_vgpr4
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<3 x s32>) = G_BITCAST [[COPY1]](s96)
; CI-NEXT: G_STORE [[BITCAST]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s96_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
@@ -4974,7 +4788,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; VI-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR8]](s16)
; VI-NEXT: G_STORE [[ANYEXT5]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s96_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; GFX9-NEXT: {{ $}}
@@ -5021,7 +4834,6 @@ body: |
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s96_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; CI-NEXT: {{ $}}
@@ -5029,7 +4841,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr2_vgpr3_vgpr4
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<3 x s32>) = G_BITCAST [[COPY1]](s96)
; CI-NEXT: G_STORE [[BITCAST]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s96_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
@@ -5058,7 +4869,6 @@ body: |
; VI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; VI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s96_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; GFX9-NEXT: {{ $}}
@@ -5089,7 +4899,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV2]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s96_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; CI-NEXT: {{ $}}
@@ -5097,7 +4906,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr2_vgpr3_vgpr4
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<3 x s32>) = G_BITCAST [[COPY1]](s96)
; CI-NEXT: G_STORE [[BITCAST]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s96_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
@@ -5105,7 +4913,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr2_vgpr3_vgpr4
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<3 x s32>) = G_BITCAST [[COPY1]](s96)
; VI-NEXT: G_STORE [[BITCAST]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s96_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; GFX9-NEXT: {{ $}}
@@ -5136,7 +4943,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV2]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 8, align 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s96_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; CI-NEXT: {{ $}}
@@ -5144,7 +4950,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr2_vgpr3_vgpr4
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<3 x s32>) = G_BITCAST [[COPY1]](s96)
; CI-NEXT: G_STORE [[BITCAST]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 8, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s96_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
@@ -5152,7 +4957,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr2_vgpr3_vgpr4
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<3 x s32>) = G_BITCAST [[COPY1]](s96)
; VI-NEXT: G_STORE [[BITCAST]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 8, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s96_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; GFX9-NEXT: {{ $}}
@@ -5183,7 +4987,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV2]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 8, align 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s96_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; CI-NEXT: {{ $}}
@@ -5191,7 +4994,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr2_vgpr3_vgpr4
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<3 x s32>) = G_BITCAST [[COPY1]](s96)
; CI-NEXT: G_STORE [[BITCAST]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s96_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
@@ -5199,7 +5001,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr2_vgpr3_vgpr4
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<3 x s32>) = G_BITCAST [[COPY1]](s96)
; VI-NEXT: G_STORE [[BITCAST]](<3 x s32>), [[COPY]](p1) :: (store (<3 x s32>), align 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s96_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; GFX9-NEXT: {{ $}}
@@ -5239,7 +5040,8 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -5249,13 +5051,14 @@ body: |
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY4]], [[C]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
@@ -5265,13 +5068,14 @@ body: |
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY7]], [[C]](s32)
; SI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; SI-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY8]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY8]](s32)
; SI-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[COPY9]](s32)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY9]](s32)
; SI-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD8]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI-NEXT: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
@@ -5281,17 +5085,17 @@ body: |
; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY10]], [[C]](s32)
; SI-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
; SI-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY11]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY11]](s32)
; SI-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY10]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR9]], [[COPY12]](s32)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
+ ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY12]](s32)
; SI-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD12]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI-NEXT: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s128_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
@@ -5299,7 +5103,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](s128)
; CI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s128_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -5377,7 +5180,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR11]](s16)
; VI-NEXT: G_STORE [[ANYEXT7]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s128_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -5431,7 +5233,6 @@ body: |
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s128_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
@@ -5439,7 +5240,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](s128)
; CI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s128_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -5475,7 +5275,6 @@ body: |
; VI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s128_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -5501,7 +5300,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](s128)
; SI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s128_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
@@ -5509,7 +5307,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](s128)
; CI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s128_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -5517,7 +5314,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](s128)
; VI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s128_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -5543,7 +5339,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](s128)
; SI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s128_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
@@ -5551,7 +5346,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](s128)
; CI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 8, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s128_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -5559,7 +5353,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](s128)
; VI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), align 8, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s128_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -5585,7 +5378,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](s128)
; SI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s128_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: {{ $}}
@@ -5593,7 +5385,6 @@ body: |
; CI-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; CI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](s128)
; CI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s128_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -5601,7 +5392,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](s128)
; VI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s128_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -5640,7 +5430,8 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -5650,13 +5441,14 @@ body: |
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY4]], [[C]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
@@ -5666,13 +5458,14 @@ body: |
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY7]], [[C]](s32)
; SI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; SI-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY8]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY8]](s32)
; SI-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[COPY9]](s32)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY9]](s32)
; SI-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD8]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI-NEXT: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
@@ -5682,13 +5475,14 @@ body: |
; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY10]], [[C]](s32)
; SI-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
; SI-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY11]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY11]](s32)
; SI-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY10]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR9]], [[COPY12]](s32)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
+ ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY12]](s32)
; SI-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD12]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI-NEXT: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
@@ -5698,17 +5492,17 @@ body: |
; SI-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[COPY13]], [[C]](s32)
; SI-NEXT: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C1]](s64)
; SI-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY14]](s32)
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
+ ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY14]](s32)
; SI-NEXT: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY13]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; SI-NEXT: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; SI-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[LSHR12]], [[COPY15]](s32)
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C3]]
+ ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[COPY15]](s32)
; SI-NEXT: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD16]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; SI-NEXT: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v5s32_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -5720,7 +5514,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v5s32_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -5814,7 +5607,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; VI-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR14]](s16)
; VI-NEXT: G_STORE [[ANYEXT9]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v5s32_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -5878,7 +5670,6 @@ body: |
; SI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v5s32_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -5890,7 +5681,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v5s32_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -5932,7 +5722,6 @@ body: |
; VI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; VI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v5s32_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -5966,7 +5755,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v5s32_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -5978,7 +5766,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v5s32_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -5990,7 +5777,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v5s32_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -6024,7 +5810,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v5s32_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -6036,7 +5821,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 8, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v5s32_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -6048,7 +5832,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 8, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v5s32_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -6082,7 +5865,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v5s32_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -6094,7 +5876,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v5s32_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -6106,7 +5887,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v5s32_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -6149,7 +5929,8 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -6159,13 +5940,14 @@ body: |
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY4]], [[C]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
@@ -6175,13 +5957,14 @@ body: |
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY7]], [[C]](s32)
; SI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; SI-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY8]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY8]](s32)
; SI-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[COPY9]](s32)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY9]](s32)
; SI-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD8]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI-NEXT: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
@@ -6191,13 +5974,14 @@ body: |
; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY10]], [[C]](s32)
; SI-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
; SI-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY11]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY11]](s32)
; SI-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY10]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR9]], [[COPY12]](s32)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
+ ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY12]](s32)
; SI-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD12]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI-NEXT: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
@@ -6207,17 +5991,17 @@ body: |
; SI-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[COPY13]], [[C]](s32)
; SI-NEXT: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C1]](s64)
; SI-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY14]](s32)
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
+ ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY14]](s32)
; SI-NEXT: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY13]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; SI-NEXT: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; SI-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[LSHR12]], [[COPY15]](s32)
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C3]]
+ ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[COPY15]](s32)
; SI-NEXT: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD16]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; SI-NEXT: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v5p3_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -6230,7 +6014,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v5p3_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -6325,7 +6108,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; VI-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR14]](s16)
; VI-NEXT: G_STORE [[ANYEXT9]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v5p3_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -6391,7 +6173,6 @@ body: |
; SI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v5p3_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -6404,7 +6185,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v5p3_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -6447,7 +6227,6 @@ body: |
; VI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; VI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v5p3_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -6483,7 +6262,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v5p3_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -6496,7 +6274,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v5p3_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -6509,7 +6286,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v5p3_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -6545,7 +6321,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v5p3_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -6558,7 +6333,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 8, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v5p3_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -6571,7 +6345,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 8, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v5p3_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -6607,7 +6380,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v5p3_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -6620,7 +6392,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v5p3_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -6633,7 +6404,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v5p3_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -6669,7 +6439,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v10s16_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -6682,7 +6451,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v10s16_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -6695,7 +6463,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v10s16_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -6741,7 +6508,6 @@ body: |
; SI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
; SI-NEXT: G_STORE [[BITCAST1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v11s16_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -6764,7 +6530,6 @@ body: |
; CI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
; CI-NEXT: G_STORE [[BITCAST1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v11s16_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -6787,7 +6552,6 @@ body: |
; VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
; VI-NEXT: G_STORE [[BITCAST1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v11s16_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -6834,7 +6598,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV8]](<2 x s32>), [[PTR_ADD]](p1) :: (store (<2 x s32>) into unknown-address + 16, align 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v12s16_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -6848,7 +6611,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV8]](<2 x s32>), [[PTR_ADD]](p1) :: (store (<2 x s32>) into unknown-address + 16, align 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v12s16_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -6862,7 +6624,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV8]](<2 x s32>), [[PTR_ADD]](p1) :: (store (<2 x s32>) into unknown-address + 16, align 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v12s16_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -6908,7 +6669,8 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -6918,13 +6680,14 @@ body: |
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY4]], [[C]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
@@ -6934,13 +6697,14 @@ body: |
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY7]], [[C]](s32)
; SI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; SI-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY8]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY8]](s32)
; SI-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[COPY9]](s32)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY9]](s32)
; SI-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD8]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI-NEXT: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
@@ -6950,13 +6714,14 @@ body: |
; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY10]], [[C]](s32)
; SI-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
; SI-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY11]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY11]](s32)
; SI-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY10]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR9]], [[COPY12]](s32)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
+ ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY12]](s32)
; SI-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD12]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI-NEXT: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
@@ -6966,17 +6731,17 @@ body: |
; SI-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[COPY13]], [[C]](s32)
; SI-NEXT: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C1]](s64)
; SI-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY14]](s32)
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
+ ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY14]](s32)
; SI-NEXT: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY13]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; SI-NEXT: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; SI-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[LSHR12]], [[COPY15]](s32)
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C3]]
+ ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[COPY15]](s32)
; SI-NEXT: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD16]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; SI-NEXT: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s160_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -6989,7 +6754,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s160_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -7084,7 +6848,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; VI-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR14]](s16)
; VI-NEXT: G_STORE [[ANYEXT9]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s160_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -7150,7 +6913,6 @@ body: |
; SI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s160_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -7163,7 +6925,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s160_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -7206,7 +6967,6 @@ body: |
; VI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; VI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s160_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -7242,7 +7002,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s160_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -7255,7 +7014,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s160_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -7268,7 +7026,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s160_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -7304,7 +7061,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s160_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -7317,7 +7073,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 8, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s160_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -7330,7 +7085,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 8, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s160_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -7366,7 +7120,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s160_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; CI-NEXT: {{ $}}
@@ -7379,7 +7132,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s160_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; VI-NEXT: {{ $}}
@@ -7392,7 +7144,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV4]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 16, align 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s160_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
; GFX9-NEXT: {{ $}}
@@ -7437,7 +7188,8 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -7447,13 +7199,14 @@ body: |
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY4]], [[C]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
@@ -7463,13 +7216,14 @@ body: |
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY7]], [[C]](s32)
; SI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; SI-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY8]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY8]](s32)
; SI-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[COPY9]](s32)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY9]](s32)
; SI-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD8]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI-NEXT: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
@@ -7479,13 +7233,14 @@ body: |
; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY10]], [[C]](s32)
; SI-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
; SI-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY11]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY11]](s32)
; SI-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY10]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR9]], [[COPY12]](s32)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
+ ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY12]](s32)
; SI-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD12]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI-NEXT: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
@@ -7496,13 +7251,14 @@ body: |
; SI-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[COPY13]], [[C]](s32)
; SI-NEXT: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C1]](s64)
; SI-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY14]](s32)
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
+ ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY14]](s32)
; SI-NEXT: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY13]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; SI-NEXT: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; SI-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[LSHR12]], [[COPY15]](s32)
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C3]]
+ ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[COPY15]](s32)
; SI-NEXT: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD16]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; SI-NEXT: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
@@ -7511,13 +7267,14 @@ body: |
; SI-NEXT: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[COPY16]], [[C]](s32)
; SI-NEXT: [[PTR_ADD20:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C1]](s64)
; SI-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
- ; SI-NEXT: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY17]](s32)
+ ; SI-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI-NEXT: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY17]](s32)
; SI-NEXT: [[PTR_ADD21:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY16]](s32), [[PTR_ADD19]](p1) :: (store (s8) into unknown-address + 20, addrspace 1)
; SI-NEXT: G_STORE [[LSHR16]](s32), [[PTR_ADD21]](p1) :: (store (s8) into unknown-address + 21, addrspace 1)
; SI-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[LSHR15]], [[COPY18]](s32)
+ ; SI-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C3]]
+ ; SI-NEXT: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[COPY18]](s32)
; SI-NEXT: [[PTR_ADD22:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD20]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR15]](s32), [[PTR_ADD20]](p1) :: (store (s8) into unknown-address + 22, addrspace 1)
; SI-NEXT: G_STORE [[LSHR17]](s32), [[PTR_ADD22]](p1) :: (store (s8) into unknown-address + 23, addrspace 1)
@@ -7526,13 +7283,14 @@ body: |
; SI-NEXT: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[COPY19]], [[C]](s32)
; SI-NEXT: [[PTR_ADD24:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C1]](s64)
; SI-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
- ; SI-NEXT: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY20]](s32)
+ ; SI-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; SI-NEXT: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[AND12]], [[COPY20]](s32)
; SI-NEXT: [[PTR_ADD25:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY19]](s32), [[PTR_ADD23]](p1) :: (store (s8) into unknown-address + 24, addrspace 1)
; SI-NEXT: G_STORE [[LSHR19]](s32), [[PTR_ADD25]](p1) :: (store (s8) into unknown-address + 25, addrspace 1)
; SI-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[LSHR18]], [[COPY21]](s32)
+ ; SI-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C3]]
+ ; SI-NEXT: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[COPY21]](s32)
; SI-NEXT: [[PTR_ADD26:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD24]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR18]](s32), [[PTR_ADD24]](p1) :: (store (s8) into unknown-address + 26, addrspace 1)
; SI-NEXT: G_STORE [[LSHR20]](s32), [[PTR_ADD26]](p1) :: (store (s8) into unknown-address + 27, addrspace 1)
@@ -7541,17 +7299,17 @@ body: |
; SI-NEXT: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[COPY22]], [[C]](s32)
; SI-NEXT: [[PTR_ADD28:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C1]](s64)
; SI-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
- ; SI-NEXT: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY23]](s32)
+ ; SI-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; SI-NEXT: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY23]](s32)
; SI-NEXT: [[PTR_ADD29:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY22]](s32), [[PTR_ADD27]](p1) :: (store (s8) into unknown-address + 28, addrspace 1)
; SI-NEXT: G_STORE [[LSHR22]](s32), [[PTR_ADD29]](p1) :: (store (s8) into unknown-address + 29, addrspace 1)
; SI-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[LSHR21]], [[COPY24]](s32)
+ ; SI-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C3]]
+ ; SI-NEXT: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[COPY24]](s32)
; SI-NEXT: [[PTR_ADD30:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD28]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR21]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
; SI-NEXT: G_STORE [[LSHR23]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v8s32_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; CI-NEXT: {{ $}}
@@ -7562,7 +7320,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v8s32_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; VI-NEXT: {{ $}}
@@ -7706,7 +7463,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR21]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
; VI-NEXT: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR23]](s16)
; VI-NEXT: G_STORE [[ANYEXT15]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v8s32_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT: {{ $}}
@@ -7789,7 +7545,6 @@ body: |
; SI-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD13]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY9]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
; SI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v8s32_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; CI-NEXT: {{ $}}
@@ -7800,7 +7555,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v8s32_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; VI-NEXT: {{ $}}
@@ -7862,7 +7616,6 @@ body: |
; VI-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD13]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY9]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
; VI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v8s32_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT: {{ $}}
@@ -7894,7 +7647,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v8s32_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; CI-NEXT: {{ $}}
@@ -7905,7 +7657,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v8s32_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; VI-NEXT: {{ $}}
@@ -7916,7 +7667,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v8s32_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT: {{ $}}
@@ -7948,7 +7698,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v8s32_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; CI-NEXT: {{ $}}
@@ -7959,7 +7708,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 8, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v8s32_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; VI-NEXT: {{ $}}
@@ -7970,7 +7718,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 8, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v8s32_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT: {{ $}}
@@ -8002,7 +7749,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v8s32_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; CI-NEXT: {{ $}}
@@ -8013,7 +7759,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v8s32_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; VI-NEXT: {{ $}}
@@ -8024,7 +7769,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v8s32_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT: {{ $}}
@@ -8057,7 +7801,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v2s128_align32
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; CI-NEXT: {{ $}}
@@ -8069,7 +7812,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s128_align32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; VI-NEXT: {{ $}}
@@ -8081,7 +7823,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v2s128_align32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT: {{ $}}
@@ -8126,7 +7867,8 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -8136,13 +7878,14 @@ body: |
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY4]], [[C]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY6]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
@@ -8152,13 +7895,14 @@ body: |
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY7]], [[C]](s32)
; SI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; SI-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY8]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY8]](s32)
; SI-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[COPY9]](s32)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY9]](s32)
; SI-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD8]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI-NEXT: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
@@ -8168,13 +7912,14 @@ body: |
; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY10]], [[C]](s32)
; SI-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
; SI-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY11]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY11]](s32)
; SI-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY10]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR9]], [[COPY12]](s32)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
+ ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY12]](s32)
; SI-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD12]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI-NEXT: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
@@ -8185,13 +7930,14 @@ body: |
; SI-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[COPY13]], [[C]](s32)
; SI-NEXT: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C1]](s64)
; SI-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY14]](s32)
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
+ ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY14]](s32)
; SI-NEXT: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY13]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; SI-NEXT: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; SI-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[LSHR12]], [[COPY15]](s32)
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C3]]
+ ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[COPY15]](s32)
; SI-NEXT: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD16]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; SI-NEXT: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
@@ -8200,13 +7946,14 @@ body: |
; SI-NEXT: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[COPY16]], [[C]](s32)
; SI-NEXT: [[PTR_ADD20:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C1]](s64)
; SI-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
- ; SI-NEXT: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY17]](s32)
+ ; SI-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI-NEXT: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY17]](s32)
; SI-NEXT: [[PTR_ADD21:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY16]](s32), [[PTR_ADD19]](p1) :: (store (s8) into unknown-address + 20, addrspace 1)
; SI-NEXT: G_STORE [[LSHR16]](s32), [[PTR_ADD21]](p1) :: (store (s8) into unknown-address + 21, addrspace 1)
; SI-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[LSHR15]], [[COPY18]](s32)
+ ; SI-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C3]]
+ ; SI-NEXT: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[COPY18]](s32)
; SI-NEXT: [[PTR_ADD22:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD20]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR15]](s32), [[PTR_ADD20]](p1) :: (store (s8) into unknown-address + 22, addrspace 1)
; SI-NEXT: G_STORE [[LSHR17]](s32), [[PTR_ADD22]](p1) :: (store (s8) into unknown-address + 23, addrspace 1)
@@ -8215,13 +7962,14 @@ body: |
; SI-NEXT: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[COPY19]], [[C]](s32)
; SI-NEXT: [[PTR_ADD24:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C1]](s64)
; SI-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
- ; SI-NEXT: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY20]](s32)
+ ; SI-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; SI-NEXT: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[AND12]], [[COPY20]](s32)
; SI-NEXT: [[PTR_ADD25:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY19]](s32), [[PTR_ADD23]](p1) :: (store (s8) into unknown-address + 24, addrspace 1)
; SI-NEXT: G_STORE [[LSHR19]](s32), [[PTR_ADD25]](p1) :: (store (s8) into unknown-address + 25, addrspace 1)
; SI-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[LSHR18]], [[COPY21]](s32)
+ ; SI-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C3]]
+ ; SI-NEXT: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[COPY21]](s32)
; SI-NEXT: [[PTR_ADD26:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD24]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR18]](s32), [[PTR_ADD24]](p1) :: (store (s8) into unknown-address + 26, addrspace 1)
; SI-NEXT: G_STORE [[LSHR20]](s32), [[PTR_ADD26]](p1) :: (store (s8) into unknown-address + 27, addrspace 1)
@@ -8230,17 +7978,17 @@ body: |
; SI-NEXT: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[COPY22]], [[C]](s32)
; SI-NEXT: [[PTR_ADD28:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C1]](s64)
; SI-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
- ; SI-NEXT: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY23]](s32)
+ ; SI-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; SI-NEXT: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY23]](s32)
; SI-NEXT: [[PTR_ADD29:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY22]](s32), [[PTR_ADD27]](p1) :: (store (s8) into unknown-address + 28, addrspace 1)
; SI-NEXT: G_STORE [[LSHR22]](s32), [[PTR_ADD29]](p1) :: (store (s8) into unknown-address + 29, addrspace 1)
; SI-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[LSHR21]], [[COPY24]](s32)
+ ; SI-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C3]]
+ ; SI-NEXT: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[COPY24]](s32)
; SI-NEXT: [[PTR_ADD30:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD28]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR21]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
; SI-NEXT: G_STORE [[LSHR23]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s256_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; CI-NEXT: {{ $}}
@@ -8252,7 +8000,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s256_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; VI-NEXT: {{ $}}
@@ -8397,7 +8144,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR21]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
; VI-NEXT: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR23]](s16)
; VI-NEXT: G_STORE [[ANYEXT15]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s256_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT: {{ $}}
@@ -8482,7 +8228,6 @@ body: |
; SI-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD13]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY9]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
; SI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s256_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; CI-NEXT: {{ $}}
@@ -8494,7 +8239,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s256_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; VI-NEXT: {{ $}}
@@ -8557,7 +8301,6 @@ body: |
; VI-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD13]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY9]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
; VI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s256_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT: {{ $}}
@@ -8591,7 +8334,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 4, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s256_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; CI-NEXT: {{ $}}
@@ -8603,7 +8345,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s256_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; VI-NEXT: {{ $}}
@@ -8615,7 +8356,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 4, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s256_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT: {{ $}}
@@ -8649,7 +8389,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s256_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; CI-NEXT: {{ $}}
@@ -8661,7 +8400,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 8, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s256_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; VI-NEXT: {{ $}}
@@ -8673,7 +8411,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, align 8, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s256_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT: {{ $}}
@@ -8707,7 +8444,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s256_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; CI-NEXT: {{ $}}
@@ -8719,7 +8455,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s256_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; VI-NEXT: {{ $}}
@@ -8731,7 +8466,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s256_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT: {{ $}}
@@ -8765,7 +8499,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_s256_align32
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; CI-NEXT: {{ $}}
@@ -8777,7 +8510,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_s256_align32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; VI-NEXT: {{ $}}
@@ -8789,7 +8521,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_s256_align32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT: {{ $}}
@@ -8822,7 +8553,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v8s32_align32
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; CI-NEXT: {{ $}}
@@ -8833,7 +8563,6 @@ body: |
; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v8s32_align32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; VI-NEXT: {{ $}}
@@ -8844,7 +8573,6 @@ body: |
; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI-NEXT: G_STORE [[UV1]](<4 x s32>), [[PTR_ADD]](p1) :: (store (<4 x s32>) into unknown-address + 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v8s32_align32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT: {{ $}}
@@ -8890,7 +8618,8 @@ body: |
; SI-NEXT: G_STORE [[COPY4]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY5]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
@@ -8900,13 +8629,14 @@ body: |
; SI-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY6]], [[C]](s32)
; SI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
; SI-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
- ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY7]](s32)
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY7]](s32)
; SI-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR3]], [[COPY8]](s32)
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; SI-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY8]](s32)
; SI-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD4]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI-NEXT: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
@@ -8916,13 +8646,14 @@ body: |
; SI-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY9]], [[C]](s32)
; SI-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
; SI-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY10]](s32)
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
+ ; SI-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY10]](s32)
; SI-NEXT: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY9]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI-NEXT: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[LSHR6]], [[COPY11]](s32)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
+ ; SI-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY11]](s32)
; SI-NEXT: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD8]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI-NEXT: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
@@ -8932,13 +8663,14 @@ body: |
; SI-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY12]], [[C]](s32)
; SI-NEXT: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
; SI-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
- ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY13]](s32)
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY13]](s32)
; SI-NEXT: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY12]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI-NEXT: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR9]], [[COPY14]](s32)
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
+ ; SI-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY14]](s32)
; SI-NEXT: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD12]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI-NEXT: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
@@ -8948,13 +8680,14 @@ body: |
; SI-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[COPY15]], [[C]](s32)
; SI-NEXT: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C1]](s64)
; SI-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
- ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY16]](s32)
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY16]](s32)
; SI-NEXT: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY15]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; SI-NEXT: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; SI-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[LSHR12]], [[COPY17]](s32)
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C3]]
+ ; SI-NEXT: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[COPY17]](s32)
; SI-NEXT: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD16]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; SI-NEXT: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
@@ -8963,13 +8696,14 @@ body: |
; SI-NEXT: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[COPY18]], [[C]](s32)
; SI-NEXT: [[PTR_ADD20:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C1]](s64)
; SI-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
- ; SI-NEXT: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY19]](s32)
+ ; SI-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; SI-NEXT: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY19]](s32)
; SI-NEXT: [[PTR_ADD21:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY18]](s32), [[PTR_ADD19]](p1) :: (store (s8) into unknown-address + 20, addrspace 1)
; SI-NEXT: G_STORE [[LSHR16]](s32), [[PTR_ADD21]](p1) :: (store (s8) into unknown-address + 21, addrspace 1)
; SI-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[LSHR15]], [[COPY20]](s32)
+ ; SI-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C3]]
+ ; SI-NEXT: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[COPY20]](s32)
; SI-NEXT: [[PTR_ADD22:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD20]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR15]](s32), [[PTR_ADD20]](p1) :: (store (s8) into unknown-address + 22, addrspace 1)
; SI-NEXT: G_STORE [[LSHR17]](s32), [[PTR_ADD22]](p1) :: (store (s8) into unknown-address + 23, addrspace 1)
@@ -8978,13 +8712,14 @@ body: |
; SI-NEXT: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[COPY21]], [[C]](s32)
; SI-NEXT: [[PTR_ADD24:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C1]](s64)
; SI-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; SI-NEXT: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY22]](s32)
+ ; SI-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
+ ; SI-NEXT: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[AND12]], [[COPY22]](s32)
; SI-NEXT: [[PTR_ADD25:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY21]](s32), [[PTR_ADD23]](p1) :: (store (s8) into unknown-address + 24, addrspace 1)
; SI-NEXT: G_STORE [[LSHR19]](s32), [[PTR_ADD25]](p1) :: (store (s8) into unknown-address + 25, addrspace 1)
; SI-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[LSHR18]], [[COPY23]](s32)
+ ; SI-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C3]]
+ ; SI-NEXT: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[COPY23]](s32)
; SI-NEXT: [[PTR_ADD26:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD24]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR18]](s32), [[PTR_ADD24]](p1) :: (store (s8) into unknown-address + 26, addrspace 1)
; SI-NEXT: G_STORE [[LSHR20]](s32), [[PTR_ADD26]](p1) :: (store (s8) into unknown-address + 27, addrspace 1)
@@ -8993,13 +8728,14 @@ body: |
; SI-NEXT: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[COPY24]], [[C]](s32)
; SI-NEXT: [[PTR_ADD28:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C1]](s64)
; SI-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
- ; SI-NEXT: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY25]](s32)
+ ; SI-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; SI-NEXT: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY25]](s32)
; SI-NEXT: [[PTR_ADD29:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY24]](s32), [[PTR_ADD27]](p1) :: (store (s8) into unknown-address + 28, addrspace 1)
; SI-NEXT: G_STORE [[LSHR22]](s32), [[PTR_ADD29]](p1) :: (store (s8) into unknown-address + 29, addrspace 1)
; SI-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[LSHR21]], [[COPY26]](s32)
+ ; SI-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C3]]
+ ; SI-NEXT: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[COPY26]](s32)
; SI-NEXT: [[PTR_ADD30:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD28]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR21]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
; SI-NEXT: G_STORE [[LSHR23]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
@@ -9009,17 +8745,17 @@ body: |
; SI-NEXT: [[LSHR24:%[0-9]+]]:_(s32) = G_LSHR [[COPY27]], [[C]](s32)
; SI-NEXT: [[PTR_ADD32:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD31]], [[C1]](s64)
; SI-NEXT: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
- ; SI-NEXT: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY28]](s32)
+ ; SI-NEXT: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
+ ; SI-NEXT: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[AND16]], [[COPY28]](s32)
; SI-NEXT: [[PTR_ADD33:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD31]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY27]](s32), [[PTR_ADD31]](p1) :: (store (s8) into unknown-address + 32, addrspace 1)
; SI-NEXT: G_STORE [[LSHR25]](s32), [[PTR_ADD33]](p1) :: (store (s8) into unknown-address + 33, addrspace 1)
; SI-NEXT: [[COPY29:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[LSHR24]], [[COPY29]](s32)
+ ; SI-NEXT: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR24]], [[C3]]
+ ; SI-NEXT: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[AND17]], [[COPY29]](s32)
; SI-NEXT: [[PTR_ADD34:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD32]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR24]](s32), [[PTR_ADD32]](p1) :: (store (s8) into unknown-address + 34, addrspace 1)
; SI-NEXT: G_STORE [[LSHR26]](s32), [[PTR_ADD34]](p1) :: (store (s8) into unknown-address + 35, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v9s32_align1
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; CI-NEXT: {{ $}}
@@ -9039,7 +8775,6 @@ body: |
; CI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; CI-NEXT: G_STORE [[UV8]](s32), [[PTR_ADD1]](p1) :: (store (s32) into unknown-address + 32, align 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v9s32_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; VI-NEXT: {{ $}}
@@ -9202,7 +8937,6 @@ body: |
; VI-NEXT: G_STORE [[LSHR24]](s32), [[PTR_ADD32]](p1) :: (store (s8) into unknown-address + 34, addrspace 1)
; VI-NEXT: [[ANYEXT17:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR26]](s16)
; VI-NEXT: G_STORE [[ANYEXT17]](s32), [[PTR_ADD34]](p1) :: (store (s8) into unknown-address + 35, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v9s32_align1
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; GFX9-NEXT: {{ $}}
@@ -9306,7 +9040,6 @@ body: |
; SI-NEXT: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY12]](s32), [[PTR_ADD15]](p1) :: (store (s16) into unknown-address + 32, addrspace 1)
; SI-NEXT: G_STORE [[LSHR8]](s32), [[PTR_ADD16]](p1) :: (store (s16) into unknown-address + 34, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v9s32_align2
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; CI-NEXT: {{ $}}
@@ -9326,7 +9059,6 @@ body: |
; CI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; CI-NEXT: G_STORE [[UV8]](s32), [[PTR_ADD1]](p1) :: (store (s32) into unknown-address + 32, align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v9s32_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; VI-NEXT: {{ $}}
@@ -9397,7 +9129,6 @@ body: |
; VI-NEXT: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C1]](s64)
; VI-NEXT: G_STORE [[COPY12]](s32), [[PTR_ADD15]](p1) :: (store (s16) into unknown-address + 32, addrspace 1)
; VI-NEXT: G_STORE [[LSHR8]](s32), [[PTR_ADD16]](p1) :: (store (s16) into unknown-address + 34, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v9s32_align2
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; GFX9-NEXT: {{ $}}
@@ -9450,7 +9181,6 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; SI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; SI-NEXT: G_STORE [[UV8]](s32), [[PTR_ADD1]](p1) :: (store (s32) into unknown-address + 32, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v9s32_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; CI-NEXT: {{ $}}
@@ -9470,7 +9200,6 @@ body: |
; CI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; CI-NEXT: G_STORE [[UV8]](s32), [[PTR_ADD1]](p1) :: (store (s32) into unknown-address + 32, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v9s32_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; VI-NEXT: {{ $}}
@@ -9490,7 +9219,6 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; VI-NEXT: G_STORE [[UV8]](s32), [[PTR_ADD1]](p1) :: (store (s32) into unknown-address + 32, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v9s32_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; GFX9-NEXT: {{ $}}
@@ -9543,7 +9271,6 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; SI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; SI-NEXT: G_STORE [[UV8]](s32), [[PTR_ADD1]](p1) :: (store (s32) into unknown-address + 32, align 8, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v9s32_align8
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; CI-NEXT: {{ $}}
@@ -9563,7 +9290,6 @@ body: |
; CI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; CI-NEXT: G_STORE [[UV8]](s32), [[PTR_ADD1]](p1) :: (store (s32) into unknown-address + 32, align 8, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v9s32_align8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; VI-NEXT: {{ $}}
@@ -9583,7 +9309,6 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; VI-NEXT: G_STORE [[UV8]](s32), [[PTR_ADD1]](p1) :: (store (s32) into unknown-address + 32, align 8, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v9s32_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; GFX9-NEXT: {{ $}}
@@ -9636,7 +9361,6 @@ body: |
; SI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; SI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; SI-NEXT: G_STORE [[UV8]](s32), [[PTR_ADD1]](p1) :: (store (s32) into unknown-address + 32, align 16, addrspace 1)
- ;
; CI-LABEL: name: test_store_global_v9s32_align16
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; CI-NEXT: {{ $}}
@@ -9656,7 +9380,6 @@ body: |
; CI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; CI-NEXT: G_STORE [[UV8]](s32), [[PTR_ADD1]](p1) :: (store (s32) into unknown-address + 32, align 16, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v9s32_align16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; VI-NEXT: {{ $}}
@@ -9676,7 +9399,6 @@ body: |
; VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; VI-NEXT: G_STORE [[UV8]](s32), [[PTR_ADD1]](p1) :: (store (s32) into unknown-address + 32, align 16, addrspace 1)
- ;
; GFX9-LABEL: name: test_store_global_v9s32_align16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
index 22d792abe36245c..30c7f4fb3e7d2f2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
@@ -22,7 +22,6 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s32), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_i32
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -46,7 +45,6 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store (s64), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_i64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -70,7 +68,6 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(p1) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](p1), [[COPY]](p1) :: (store (p1), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -94,7 +91,6 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(p4) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](p4), [[COPY]](p1) :: (store (p4), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -118,7 +114,6 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr2
; SI-NEXT: G_STORE [[COPY1]](p3), [[COPY]](p1) :: (store (p3), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_p3
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -142,7 +137,6 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; SI-NEXT: G_STORE [[COPY1]](<2 x s32>), [[COPY]](p1) :: (store (<2 x s32>), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -166,7 +160,6 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
; SI-NEXT: G_STORE [[COPY1]](<2 x s16>), [[COPY]](p1) :: (store (<2 x s16>), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -195,7 +188,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI-NEXT: G_STORE [[UV2]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 8, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v3s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
@@ -220,7 +212,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; SI-NEXT: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
- ;
; VI-LABEL: name: test_truncstore_global_s64_to_s8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -246,7 +237,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; SI-NEXT: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
- ;
; VI-LABEL: name: test_truncstore_global_s64_to_s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -279,7 +269,6 @@ body: |
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI-NEXT: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
- ;
; VI-LABEL: name: test_truncstore_global_s64_to_s16_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -312,7 +301,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; SI-NEXT: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store (s32), addrspace 1)
- ;
; VI-LABEL: name: test_truncstore_global_s64_to_s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -344,7 +332,6 @@ body: |
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
- ;
; VI-LABEL: name: test_truncstore_global_s64_to_s32_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -389,11 +376,11 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
- ;
; VI-LABEL: name: test_truncstore_global_s64_to_s32_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -437,7 +424,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; SI-NEXT: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
- ;
; VI-LABEL: name: test_truncstore_global_s128_to_s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -463,7 +449,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](s128)
; SI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
- ;
; VI-LABEL: name: test_truncstore_global_s128_to_s8
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -491,7 +476,6 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; SI-NEXT: G_STORE [[AND1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_i1
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -519,7 +503,6 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_i8
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -544,7 +527,6 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_i16
; VI: liveins: $vgpr0_vgpr1, $vgpr2
; VI-NEXT: {{ $}}
@@ -575,7 +557,6 @@ body: |
; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY1]], [[C]](s64)
; SI-NEXT: G_STORE [[UV2]](s32), [[PTR_ADD]](p1) :: (store (s32) into unknown-address + 8, align 8, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_96
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4
; VI-NEXT: {{ $}}
@@ -602,7 +583,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](s128)
; SI-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_i128
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -627,7 +607,6 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI-NEXT: G_STORE [[COPY1]](<2 x s64>), [[COPY]](p1) :: (store (<2 x s64>), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -652,8 +631,8 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
@@ -670,15 +649,14 @@ body: |
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; SI-NEXT: G_STORE [[ANYEXT]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s8_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -710,8 +688,8 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -721,15 +699,14 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: G_STORE [[ANYEXT]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s8_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -756,8 +733,8 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -767,15 +744,14 @@ body: |
; SI-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI-NEXT: G_STORE [[ANYEXT]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v2s8_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -803,8 +779,8 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; SI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
@@ -837,7 +813,6 @@ body: |
; SI-NEXT: G_STORE [[COPY4]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v3s8_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
@@ -845,8 +820,8 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -895,8 +870,8 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; SI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
@@ -922,7 +897,6 @@ body: |
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v3s8_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
@@ -930,8 +904,8 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -975,8 +949,8 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; SI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; SI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; SI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; SI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
@@ -1002,7 +976,6 @@ body: |
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v3s8_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
@@ -1010,8 +983,8 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -1080,11 +1053,11 @@ body: |
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY3]](s32)
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; SI-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY3]](s32)
; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C6]](s64)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v4s8_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -1109,8 +1082,8 @@ body: |
; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C2]](s32)
; VI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; VI-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; VI-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C5]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; VI-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C5]]
@@ -1168,7 +1141,6 @@ body: |
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; SI-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v4s8_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -1229,7 +1201,6 @@ body: |
; SI-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; SI-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; SI-NEXT: G_STORE [[OR2]](s32), [[COPY]](p1) :: (store (s32), addrspace 1)
- ;
; VI-LABEL: name: test_store_global_v4s8_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -1270,7 +1241,6 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[DEF:%[0-9]+]]:_(<2 x s8>) = G_IMPLICIT_DEF
; SI-NEXT: G_STORE [[DEF]](<2 x s8>), [[COPY]](p1) :: (store (<2 x s4>), addrspace 1)
- ;
; VI-LABEL: name: test_truncstore_global_v2s8_to_1_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -1296,7 +1266,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(<3 x s8>) = G_TRUNC [[COPY1]](<3 x s32>)
; SI-NEXT: G_STORE [[TRUNC]](<3 x s8>), [[COPY]](p1) :: (store (<3 x s2>), addrspace 1)
- ;
; VI-LABEL: name: test_truncstore_global_v3s8_to_1_align1
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
@@ -1324,7 +1293,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
; SI-NEXT: [[TRUNC:%[0-9]+]]:_(<3 x s8>) = G_TRUNC [[COPY1]](<3 x s32>)
; SI-NEXT: G_STORE [[TRUNC]](<3 x s8>), [[COPY]](p1) :: (store (<3 x s4>), addrspace 1)
- ;
; VI-LABEL: name: test_truncstore_global_v3s8_to_2_align2
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
; VI-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir
index 5205386c8ea7133..b89e5d684b0ff59 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir
@@ -126,8 +126,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
@@ -153,8 +153,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[COPY]](<4 x s64>)
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[UV]](<2 x s64>)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV2]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV2]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
@@ -355,8 +355,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](<2 x s128>)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV]](s128)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV]](s128)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s128)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
@@ -403,8 +403,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s96)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s96)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s96)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
index b2fe9b8ddc903bc..54ce45c0dc0887f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
@@ -139,20 +139,22 @@ body: |
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR1]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD1]](s32), [[AND3]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND3]], [[AND4]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD1]](s32), [[AND5]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND5]](s32)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL]]
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND4]](s32), [[AND5]](s32)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND6]](s32), [[AND7]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; CHECK-NEXT: $vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s16>) = COPY $vgpr0
@@ -188,14 +190,16 @@ body: |
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR1]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD1]](s32), [[AND3]]
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND4]], [[AND5]]
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD2]](s32), [[AND6]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND3]], [[AND4]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD1]](s32), [[AND5]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND6]], [[AND7]]
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD2]](s32), [[AND8]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
@@ -205,25 +209,26 @@ body: |
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND5]](s32)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL]]
; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND6]](s32)
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND8]](s32)
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY4]], [[SHL1]]
; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C]](s32)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL2]]
; CHECK-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
- ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
- ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND9]](s32), [[AND10]](s32), [[AND11]](s32)
+ ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
+ ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
+ ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND12]](s32), [[AND13]](s32), [[AND14]](s32)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
@@ -266,24 +271,28 @@ body: |
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
- ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR2]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD1]](s32), [[AND3]]
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND4]], [[AND5]]
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD2]](s32), [[AND6]]
- ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR3]]
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C1]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD3]](s32), [[AND7]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND3]], [[AND4]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD1]](s32), [[AND5]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND6]], [[AND7]]
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD2]](s32), [[AND8]]
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[AND9]], [[AND10]]
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C1]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD3]](s32), [[AND11]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND5]](s32)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND6]](s32)
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[AND7]](s32)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND8]](s32)
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[AND11]](s32)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY4]], [[SHL1]]
; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -293,11 +302,11 @@ body: |
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP3]](s1)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
- ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
- ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
- ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C2]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND8]](s32), [[AND9]](s32), [[AND10]](s32), [[AND11]](s32)
+ ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
+ ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
+ ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
+ ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C2]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND12]](s32), [[AND13]](s32), [[AND14]](s32), [[AND15]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; CHECK-NEXT: $vgpr2_vgpr3_vgpr4_vgpr5 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
index 0d2366489c2a05b..ca2dacce5457ec9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
@@ -25,7 +25,6 @@ body: |
; GFX6-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[LSHR]](s32)
- ;
; GFX8-LABEL: name: uaddsat_s7
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -40,7 +39,6 @@ body: |
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16)
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: uaddsat_s7
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -84,7 +82,6 @@ body: |
; GFX6-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[LSHR]](s32)
- ;
; GFX8-LABEL: name: uaddsat_s8
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -99,7 +96,6 @@ body: |
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16)
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: uaddsat_s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -151,14 +147,17 @@ body: |
; GFX6-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[XOR1]], [[SHL3]]
; GFX6-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[UMIN1]]
; GFX6-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C1]](s32)
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[COPY2]](s32)
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
+ ; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY2]](s32)
; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC]], [[TRUNC1]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX8-LABEL: name: uaddsat_v2s8
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -180,11 +179,13 @@ body: |
; GFX8-NEXT: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C1]](s16)
; GFX8-NEXT: [[UADDSAT1:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL2]], [[SHL3]]
; GFX8-NEXT: [[LSHR3:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT1]], [[C1]](s16)
- ; GFX8-NEXT: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[LSHR3]], [[C1]](s16)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[LSHR2]], [[SHL4]]
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[LSHR2]], [[C2]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[LSHR3]], [[C2]]
+ ; GFX8-NEXT: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: uaddsat_v2s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -249,7 +250,6 @@ body: |
; GFX6-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[LSHR]](s32)
- ;
; GFX8-LABEL: name: uaddsat_s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -260,7 +260,6 @@ body: |
; GFX8-NEXT: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC1]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UADDSAT]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: uaddsat_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -309,11 +308,13 @@ body: |
; GFX6-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[XOR1]], [[SHL3]]
; GFX6-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[UMIN1]]
; GFX6-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C]](s32)
- ; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[C]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL4]]
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C2]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C2]]
+ ; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL4]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX8-LABEL: name: uaddsat_v2s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -336,7 +337,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: uaddsat_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -392,21 +392,24 @@ body: |
; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
- ; GFX6-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[LSHR4]], [[C]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL6]]
- ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C2]]
- ; GFX6-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
- ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[SHL7]]
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C2]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C2]]
+ ; GFX6-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL6]]
+ ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C2]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C2]]
+ ; GFX6-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL7]]
; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C2]]
- ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR6]], [[SHL8]]
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C2]]
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C2]]
+ ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL8]]
; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX8-LABEL: name: uaddsat_v3s16
; GFX8: liveins: $vgpr0_vgpr1_vgpr2
; GFX8-NEXT: {{ $}}
@@ -444,13 +447,13 @@ body: |
; GFX8-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; GFX8-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
- ; GFX8-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL2]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; GFX8-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; GFX8-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: uaddsat_v3s16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
@@ -545,15 +548,19 @@ body: |
; GFX6-NEXT: [[UMIN3:%[0-9]+]]:_(s32) = G_UMIN [[XOR3]], [[SHL7]]
; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SHL6]], [[UMIN3]]
; GFX6-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ADD3]], [[C]](s32)
- ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[LSHR5]], [[C]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[SHL8]]
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C2]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C2]]
+ ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL8]]
; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[LSHR7]], [[C]](s32)
- ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR6]], [[SHL9]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C2]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C2]]
+ ; GFX6-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL9]]
; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX8-LABEL: name: uaddsat_v4s16
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -594,7 +601,6 @@ body: |
; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: uaddsat_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -628,7 +634,6 @@ body: |
; GFX6-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[COPY1]]
; GFX6-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[UMIN]]
; GFX6-NEXT: $vgpr0 = COPY [[ADD]](s32)
- ;
; GFX8-LABEL: name: uaddsat_s32
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -636,7 +641,6 @@ body: |
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8-NEXT: [[UADDSAT:%[0-9]+]]:_(s32) = G_UADDSAT [[COPY]], [[COPY1]]
; GFX8-NEXT: $vgpr0 = COPY [[UADDSAT]](s32)
- ;
; GFX9-LABEL: name: uaddsat_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -672,7 +676,6 @@ body: |
; GFX6-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UMIN1]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX8-LABEL: name: uaddsat_v2s32
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -684,7 +687,6 @@ body: |
; GFX8-NEXT: [[UADDSAT1:%[0-9]+]]:_(s32) = G_UADDSAT [[UV1]], [[UV3]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UADDSAT]](s32), [[UADDSAT1]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: uaddsat_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -721,7 +723,6 @@ body: |
; GFX6-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[UADDE1]](s1), [[C]], [[MV]]
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; GFX8-LABEL: name: uaddsat_s64
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -735,7 +736,6 @@ body: |
; GFX8-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[UADDE1]](s1), [[C]], [[MV]]
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; GFX9-LABEL: name: uaddsat_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -783,7 +783,6 @@ body: |
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[UADDE3]](s1), [[C]], [[MV1]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT]](s64), [[SELECT1]](s64)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX8-LABEL: name: uaddsat_v2s64
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX8-NEXT: {{ $}}
@@ -806,7 +805,6 @@ body: |
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[UADDE3]](s1), [[C]], [[MV1]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT]](s64), [[SELECT1]](s64)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: uaddsat_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
index bfba201e264b14c..2143d94da2ede6c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
@@ -39,7 +39,6 @@ body: |
; GFX6-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C2]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
; GFX6-NEXT: $vgpr0 = COPY [[SELECT2]](s32)
- ;
; GFX8-LABEL: name: test_udiv_s32
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -68,7 +67,6 @@ body: |
; GFX8-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C2]]
; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
; GFX8-NEXT: $vgpr0 = COPY [[SELECT2]](s32)
- ;
; GFX9-LABEL: name: test_udiv_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -97,7 +95,6 @@ body: |
; GFX9-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C2]]
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
; GFX9-NEXT: $vgpr0 = COPY [[SELECT2]](s32)
- ;
; GFX10-LABEL: name: test_udiv_s32
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
@@ -188,7 +185,6 @@ body: |
; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[ADD5]], [[SELECT3]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT2]](s32), [[SELECT5]](s32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX8-LABEL: name: test_udiv_v2s32
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -239,7 +235,6 @@ body: |
; GFX8-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[ADD5]], [[SELECT3]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT2]](s32), [[SELECT5]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_udiv_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -290,7 +285,6 @@ body: |
; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[ADD5]], [[SELECT3]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT2]](s32), [[SELECT5]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_udiv_v2s32
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX10-NEXT: {{ $}}
@@ -503,7 +497,6 @@ body: |
; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
- ;
; GFX8-LABEL: name: test_udiv_s64
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -654,7 +647,6 @@ body: |
; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]]
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
- ;
; GFX9-LABEL: name: test_udiv_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -805,7 +797,6 @@ body: |
; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]]
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
- ;
; GFX10-LABEL: name: test_udiv_s64
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX10-NEXT: {{ $}}
@@ -1258,7 +1249,6 @@ body: |
; GFX6-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV3]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT3]](s64), [[SELECT7]](s64)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX8-LABEL: name: test_udiv_v2s64
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX8-NEXT: {{ $}}
@@ -1549,7 +1539,6 @@ body: |
; GFX8-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV3]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT3]](s64), [[SELECT7]](s64)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_udiv_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: {{ $}}
@@ -1840,7 +1829,6 @@ body: |
; GFX9-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV3]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT3]](s64), [[SELECT7]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX10-LABEL: name: test_udiv_v2s64
; GFX10: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX10-NEXT: {{ $}}
@@ -2175,7 +2163,6 @@ body: |
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT2]], [[C]]
; GFX6-NEXT: $vgpr0 = COPY [[AND2]](s32)
- ;
; GFX8-LABEL: name: test_udiv_s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -2208,7 +2195,6 @@ body: |
; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT2]], [[C]]
; GFX8-NEXT: $vgpr0 = COPY [[AND2]](s32)
- ;
; GFX9-LABEL: name: test_udiv_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -2241,7 +2227,6 @@ body: |
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT2]], [[C]]
; GFX9-NEXT: $vgpr0 = COPY [[AND2]](s32)
- ;
; GFX10-LABEL: name: test_udiv_s16
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
@@ -2324,32 +2309,33 @@ body: |
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT1]](s32), [[AND1]]
; GFX6-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C4]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
- ; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[LSHR1]](s32)
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[AND3]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG1]], [[C2]]
; GFX6-NEXT: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL1]](s32)
- ; GFX6-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[LSHR1]]
+ ; GFX6-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[AND3]]
; GFX6-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB3]], [[FPTOUI1]]
; GFX6-NEXT: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[MUL2]]
; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[UMULH2]]
- ; GFX6-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[LSHR]], [[ADD3]]
- ; GFX6-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[LSHR1]]
- ; GFX6-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[MUL3]]
- ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB4]](s32), [[LSHR1]]
+ ; GFX6-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[AND2]], [[ADD3]]
+ ; GFX6-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[AND3]]
+ ; GFX6-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[AND2]], [[MUL3]]
+ ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB4]](s32), [[AND3]]
; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[UMULH3]], [[C4]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[ADD4]], [[UMULH3]]
- ; GFX6-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[LSHR1]]
+ ; GFX6-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[AND3]]
; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SUB5]], [[SUB4]]
- ; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT4]](s32), [[LSHR1]]
+ ; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT4]](s32), [[AND3]]
; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[SELECT3]], [[C4]]
; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[ADD5]], [[SELECT3]]
- ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT2]], [[C1]]
- ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SELECT5]], [[C1]]
- ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SELECT2]], [[C1]]
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SELECT5]], [[C1]]
+ ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX8-LABEL: name: test_udiv_v2s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -2385,32 +2371,33 @@ body: |
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT1]](s32), [[AND1]]
; GFX8-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C4]]
; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
- ; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[LSHR1]](s32)
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[AND3]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG1]], [[C2]]
; GFX8-NEXT: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL1]](s32)
- ; GFX8-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[LSHR1]]
+ ; GFX8-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[AND3]]
; GFX8-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB3]], [[FPTOUI1]]
; GFX8-NEXT: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[MUL2]]
; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[UMULH2]]
- ; GFX8-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[LSHR]], [[ADD3]]
- ; GFX8-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[LSHR1]]
- ; GFX8-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[MUL3]]
- ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB4]](s32), [[LSHR1]]
+ ; GFX8-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[AND2]], [[ADD3]]
+ ; GFX8-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[AND3]]
+ ; GFX8-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[AND2]], [[MUL3]]
+ ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB4]](s32), [[AND3]]
; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[UMULH3]], [[C4]]
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[ADD4]], [[UMULH3]]
- ; GFX8-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[LSHR1]]
+ ; GFX8-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[AND3]]
; GFX8-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SUB5]], [[SUB4]]
- ; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT4]](s32), [[LSHR1]]
+ ; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT4]](s32), [[AND3]]
; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[SELECT3]], [[C4]]
; GFX8-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[ADD5]], [[SELECT3]]
- ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT2]], [[C1]]
- ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SELECT5]], [[C1]]
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
+ ; GFX8-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SELECT2]], [[C1]]
+ ; GFX8-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SELECT5]], [[C1]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_udiv_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -2447,29 +2434,30 @@ body: |
; GFX9-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C4]]
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SELECT2]](s32)
- ; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[LSHR1]](s32)
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[AND3]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG1]], [[C2]]
; GFX9-NEXT: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL1]](s32)
- ; GFX9-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[LSHR1]]
+ ; GFX9-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[AND3]]
; GFX9-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB3]], [[FPTOUI1]]
; GFX9-NEXT: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[MUL2]]
; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[UMULH2]]
- ; GFX9-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[LSHR]], [[ADD3]]
- ; GFX9-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[LSHR1]]
- ; GFX9-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[MUL3]]
- ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB4]](s32), [[LSHR1]]
+ ; GFX9-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[AND2]], [[ADD3]]
+ ; GFX9-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[AND3]]
+ ; GFX9-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[AND2]], [[MUL3]]
+ ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB4]](s32), [[AND3]]
; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[UMULH3]], [[C4]]
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[ADD4]], [[UMULH3]]
- ; GFX9-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[LSHR1]]
+ ; GFX9-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[AND3]]
; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SUB5]], [[SUB4]]
- ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT4]](s32), [[LSHR1]]
+ ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT4]](s32), [[AND3]]
; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[SELECT3]], [[C4]]
; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[ADD5]], [[SELECT3]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SELECT5]](s32)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- ;
; GFX10-LABEL: name: test_udiv_v2s16
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
@@ -2506,23 +2494,25 @@ body: |
; GFX10-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C4]]
; GFX10-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SELECT2]](s32)
- ; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[LSHR1]](s32)
+ ; GFX10-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX10-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[AND3]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG1]], [[C2]]
; GFX10-NEXT: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL1]](s32)
- ; GFX10-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[LSHR1]]
+ ; GFX10-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[AND3]]
; GFX10-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB3]], [[FPTOUI1]]
; GFX10-NEXT: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[MUL2]]
; GFX10-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[UMULH2]]
- ; GFX10-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[LSHR]], [[ADD3]]
- ; GFX10-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[LSHR1]]
- ; GFX10-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[MUL3]]
- ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB4]](s32), [[LSHR1]]
+ ; GFX10-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[AND2]], [[ADD3]]
+ ; GFX10-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[AND3]]
+ ; GFX10-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[AND2]], [[MUL3]]
+ ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB4]](s32), [[AND3]]
; GFX10-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[UMULH3]], [[C4]]
; GFX10-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[ADD4]], [[UMULH3]]
- ; GFX10-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[LSHR1]]
+ ; GFX10-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[AND3]]
; GFX10-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SUB5]], [[SUB4]]
- ; GFX10-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT4]](s32), [[LSHR1]]
+ ; GFX10-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT4]](s32), [[AND3]]
; GFX10-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[SELECT3]], [[C4]]
; GFX10-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[ADD5]], [[SELECT3]]
; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SELECT5]](s32)
@@ -2571,7 +2561,6 @@ body: |
; GFX6-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C3]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
; GFX6-NEXT: $vgpr0 = COPY [[SELECT2]](s32)
- ;
; GFX8-LABEL: name: test_udiv_s7
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -2603,7 +2592,6 @@ body: |
; GFX8-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C3]]
; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
; GFX8-NEXT: $vgpr0 = COPY [[SELECT2]](s32)
- ;
; GFX9-LABEL: name: test_udiv_s7
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -2635,7 +2623,6 @@ body: |
; GFX9-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C3]]
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
; GFX9-NEXT: $vgpr0 = COPY [[SELECT2]](s32)
- ;
; GFX10-LABEL: name: test_udiv_s7
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
@@ -2713,7 +2700,6 @@ body: |
; GFX6-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C3]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
; GFX6-NEXT: $vgpr0 = COPY [[SELECT2]](s32)
- ;
; GFX8-LABEL: name: test_udiv_s17
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -2745,7 +2731,6 @@ body: |
; GFX8-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C3]]
; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
; GFX8-NEXT: $vgpr0 = COPY [[SELECT2]](s32)
- ;
; GFX9-LABEL: name: test_udiv_s17
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -2777,7 +2762,6 @@ body: |
; GFX9-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C3]]
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
; GFX9-NEXT: $vgpr0 = COPY [[SELECT2]](s32)
- ;
; GFX10-LABEL: name: test_udiv_s17
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
@@ -2977,7 +2961,6 @@ body: |
; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
- ;
; GFX8-LABEL: name: test_udiv_s33
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -3131,7 +3114,6 @@ body: |
; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
- ;
; GFX9-LABEL: name: test_udiv_s33
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -3285,7 +3267,6 @@ body: |
; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
- ;
; GFX10-LABEL: name: test_udiv_s33
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX10-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
index 3f8bbbce2d31d02..18e24e8105d12fa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
@@ -18,7 +18,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[COPY]], [[COPY1]]
; SI-NEXT: $vgpr0 = COPY [[UMAX]](s32)
- ;
; VI-LABEL: name: test_umax_s32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -26,7 +25,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[COPY]], [[COPY1]]
; VI-NEXT: $vgpr0 = COPY [[UMAX]](s32)
- ;
; GFX9-LABEL: name: test_umax_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -54,7 +52,6 @@ body: |
; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; VI-LABEL: name: test_umax_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -63,7 +60,6 @@ body: |
; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
; VI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; GFX9-LABEL: name: test_umax_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -94,7 +90,6 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
; SI-NEXT: $vgpr0 = COPY [[UMAX]](s32)
- ;
; VI-LABEL: name: test_umax_s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -105,7 +100,6 @@ body: |
; VI-NEXT: [[UMAX:%[0-9]+]]:_(s16) = G_UMAX [[TRUNC]], [[TRUNC1]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMAX]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_umax_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -141,28 +135,26 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
; SI-NEXT: $vgpr0 = COPY [[UMAX]](s32)
- ;
; VI-LABEL: name: test_umax_s8
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI-NEXT: [[UMAX:%[0-9]+]]:_(s16) = G_UMAX [[AND]], [[AND1]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMAX]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_umax_s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -194,7 +186,6 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
; SI-NEXT: $vgpr0 = COPY [[UMAX]](s32)
- ;
; VI-LABEL: name: test_umax_s17
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -205,7 +196,6 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
; VI-NEXT: $vgpr0 = COPY [[UMAX]](s32)
- ;
; GFX9-LABEL: name: test_umax_s17
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -242,7 +232,6 @@ body: |
; SI-NEXT: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[UV1]], [[UV3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMAX]](s32), [[UMAX1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_umax_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -254,7 +243,6 @@ body: |
; VI-NEXT: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[UV1]], [[UV3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMAX]](s32), [[UMAX1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_umax_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -290,7 +278,6 @@ body: |
; SI-NEXT: [[UMAX2:%[0-9]+]]:_(s32) = G_UMAX [[UV2]], [[UV5]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UMAX]](s32), [[UMAX1]](s32), [[UMAX2]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_umax_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -303,7 +290,6 @@ body: |
; VI-NEXT: [[UMAX2:%[0-9]+]]:_(s32) = G_UMAX [[UV2]], [[UV5]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UMAX]](s32), [[UMAX1]](s32), [[UMAX2]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_umax_v3s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -342,12 +328,15 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
- ; SI-NEXT: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[LSHR]], [[LSHR1]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UMAX1]], [[C]](s32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UMAX]], [[SHL]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI-NEXT: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[AND2]], [[AND3]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UMAX]], [[C1]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UMAX1]], [[C1]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; VI-LABEL: name: test_umax_v2s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -370,7 +359,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_umax_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -408,13 +396,14 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
- ; SI-NEXT: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[LSHR]], [[LSHR1]]
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; SI-NEXT: [[UMAX2:%[0-9]+]]:_(s32) = G_UMAX [[AND2]], [[AND3]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI-NEXT: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[AND2]], [[AND3]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI-NEXT: [[UMAX2:%[0-9]+]]:_(s32) = G_UMAX [[AND4]], [[AND5]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UMAX]](s32), [[UMAX1]](s32), [[UMAX2]](s32)
; SI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_umax_v3s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -443,7 +432,6 @@ body: |
; VI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UMAX2]](s16)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
; VI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_umax_v3s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -496,20 +484,27 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
- ; SI-NEXT: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[LSHR]], [[LSHR2]]
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; SI-NEXT: [[UMAX2:%[0-9]+]]:_(s32) = G_UMAX [[AND2]], [[AND3]]
- ; SI-NEXT: [[UMAX3:%[0-9]+]]:_(s32) = G_UMAX [[LSHR1]], [[LSHR3]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UMAX1]], [[C]](s32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UMAX]], [[SHL]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI-NEXT: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[AND2]], [[AND3]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI-NEXT: [[UMAX2:%[0-9]+]]:_(s32) = G_UMAX [[AND4]], [[AND5]]
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; SI-NEXT: [[UMAX3:%[0-9]+]]:_(s32) = G_UMAX [[AND6]], [[AND7]]
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UMAX]], [[C1]]
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[UMAX1]], [[C1]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UMAX3]], [[C]](s32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UMAX2]], [[SHL1]]
+ ; SI-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[UMAX2]], [[C1]]
+ ; SI-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[UMAX3]], [[C1]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C]](s32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL1]]
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_umax_v4s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -550,7 +545,6 @@ body: |
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_umax_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
index f01143f0e0a9bc0..50776dafdb7eb30 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
@@ -18,7 +18,6 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]]
; SI-NEXT: $vgpr0 = COPY [[UMIN]](s32)
- ;
; VI-LABEL: name: test_umin_s32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -26,7 +25,6 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]]
; VI-NEXT: $vgpr0 = COPY [[UMIN]](s32)
- ;
; GFX9-LABEL: name: test_umin_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -54,7 +52,6 @@ body: |
; SI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
; SI-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; VI-LABEL: name: test_umin_s64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -63,7 +60,6 @@ body: |
; VI-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
; VI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
; VI-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; GFX9-LABEL: name: test_umin_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -94,7 +90,6 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
; SI-NEXT: $vgpr0 = COPY [[UMIN]](s32)
- ;
; VI-LABEL: name: test_umin_s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -105,7 +100,6 @@ body: |
; VI-NEXT: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC]], [[TRUNC1]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMIN]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_umin_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -141,28 +135,26 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
; SI-NEXT: $vgpr0 = COPY [[UMIN]](s32)
- ;
; VI-LABEL: name: test_umin_s8
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI-NEXT: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[AND]], [[AND1]]
; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMIN]](s16)
; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_umin_s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -194,7 +186,6 @@ body: |
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
; SI-NEXT: $vgpr0 = COPY [[UMIN]](s32)
- ;
; VI-LABEL: name: test_umin_s17
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -205,7 +196,6 @@ body: |
; VI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
; VI-NEXT: $vgpr0 = COPY [[UMIN]](s32)
- ;
; GFX9-LABEL: name: test_umin_s17
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -242,7 +232,6 @@ body: |
; SI-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[UV1]], [[UV3]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; VI-LABEL: name: test_umin_v2s32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -254,7 +243,6 @@ body: |
; VI-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[UV1]], [[UV3]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_umin_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -290,7 +278,6 @@ body: |
; SI-NEXT: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[UV2]], [[UV5]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32), [[UMIN2]](s32)
; SI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_umin_v3s32
; VI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; VI-NEXT: {{ $}}
@@ -303,7 +290,6 @@ body: |
; VI-NEXT: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[UV2]], [[UV5]]
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32), [[UMIN2]](s32)
; VI-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_umin_v3s32
; GFX9: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; GFX9-NEXT: {{ $}}
@@ -342,12 +328,15 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
- ; SI-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[LSHR]], [[LSHR1]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UMIN1]], [[C]](s32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UMIN]], [[SHL]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AND2]], [[AND3]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UMIN]], [[C1]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UMIN1]], [[C1]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; SI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; VI-LABEL: name: test_umin_v2s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -370,7 +359,6 @@ body: |
; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; VI-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_umin_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -408,13 +396,14 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
- ; SI-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[LSHR]], [[LSHR1]]
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; SI-NEXT: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[AND2]], [[AND3]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AND2]], [[AND3]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI-NEXT: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[AND4]], [[AND5]]
; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32), [[UMIN2]](s32)
; SI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
- ;
; VI-LABEL: name: test_umin_v3s16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
@@ -443,7 +432,6 @@ body: |
; VI-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UMIN2]](s16)
; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
; VI-NEXT: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
- ;
; GFX9-LABEL: name: test_umin_v3s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -496,20 +484,27 @@ body: |
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
- ; SI-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[LSHR]], [[LSHR2]]
- ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; SI-NEXT: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[AND2]], [[AND3]]
- ; SI-NEXT: [[UMIN3:%[0-9]+]]:_(s32) = G_UMIN [[LSHR1]], [[LSHR3]]
- ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UMIN1]], [[C]](s32)
- ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UMIN]], [[SHL]]
+ ; SI-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AND2]], [[AND3]]
+ ; SI-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI-NEXT: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[AND4]], [[AND5]]
+ ; SI-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; SI-NEXT: [[UMIN3:%[0-9]+]]:_(s32) = G_UMIN [[AND6]], [[AND7]]
+ ; SI-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UMIN]], [[C1]]
+ ; SI-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[UMIN1]], [[C1]]
+ ; SI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
+ ; SI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL]]
; SI-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UMIN3]], [[C]](s32)
- ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UMIN2]], [[SHL1]]
+ ; SI-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[UMIN2]], [[C1]]
+ ; SI-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[UMIN3]], [[C1]]
+ ; SI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C]](s32)
+ ; SI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL1]]
; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; VI-LABEL: name: test_umin_v4s16
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
@@ -550,7 +545,6 @@ body: |
; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; VI-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: test_umin_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
index 3a919f004964baa..50deea308909508 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
@@ -15,7 +15,6 @@ body: |
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[COPY1]]
; GFX8-NEXT: $vgpr0 = COPY [[UMULH]](s32)
- ;
; GFX9-LABEL: name: test_umulh_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -46,7 +45,6 @@ body: |
; GFX8-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[UV1]], [[UV3]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMULH]](s32), [[UMULH1]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_umulh_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -100,7 +98,6 @@ body: |
; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UMULH3]], [[ADD2]]
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO8]](s32), [[ADD3]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
- ;
; GFX9-LABEL: name: test_umulh_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -200,7 +197,6 @@ body: |
; GFX8-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO18]](s32), [[ADD7]](s32)
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_umulh_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: {{ $}}
@@ -281,8 +277,8 @@ body: |
; GFX8-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C1]](s32)
- ; GFX8-NEXT: $vgpr0 = COPY [[LSHR]](s32)
- ;
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C]]
+ ; GFX8-NEXT: $vgpr0 = COPY [[AND2]](s32)
; GFX9-LABEL: name: test_umulh_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -294,7 +290,8 @@ body: |
; GFX9-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C1]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[LSHR]](s32)
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[AND2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
@@ -315,34 +312,33 @@ body: |
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX8-NEXT: [[MUL:%[0-9]+]]:_(s16) = G_MUL [[AND]], [[AND1]]
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[MUL]], [[C1]](s16)
- ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; GFX8-NEXT: $vgpr0 = COPY [[AND2]](s32)
- ;
; GFX9-LABEL: name: test_umulh_s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9-NEXT: [[MUL:%[0-9]+]]:_(s16) = G_MUL [[AND]], [[AND1]]
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[MUL]], [[C1]](s16)
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; GFX9-NEXT: $vgpr0 = COPY [[AND2]](s32)
%0:_(s32) = COPY $vgpr0
@@ -376,15 +372,17 @@ body: |
; GFX8-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C]]
; GFX8-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND2]], [[AND3]]
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C1]](s32)
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C1]](s32)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; GFX8-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C]]
+ ; GFX8-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST]](<2 x s16>)
; GFX8-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX8-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C]]
- ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND4]](s32), [[LSHR2]](s32)
+ ; GFX8-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C]]
+ ; GFX8-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C]]
+ ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND6]](s32), [[AND7]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_umulh_v2s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -402,7 +400,9 @@ body: |
; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C]]
; GFX9-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND2]], [[AND3]]
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C1]](s32)
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX9-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C]]
+ ; GFX9-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND4]](s32), [[AND5]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
@@ -427,8 +427,8 @@ body: |
; GFX8-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX8-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX8-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -448,19 +448,21 @@ body: |
; GFX8-NEXT: [[MUL2:%[0-9]+]]:_(s16) = G_MUL [[AND4]], [[AND5]]
; GFX8-NEXT: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[MUL2]], [[C1]](s16)
; GFX8-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[LSHR1]], [[C1]](s16)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[LSHR]], [[SHL]]
+ ; GFX8-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C]]
+ ; GFX8-NEXT: [[AND7:%[0-9]+]]:_(s16) = G_AND [[LSHR1]], [[C]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C1]](s16)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[SHL]]
+ ; GFX8-NEXT: [[AND8:%[0-9]+]]:_(s16) = G_AND [[LSHR2]], [[C]]
; GFX8-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
- ; GFX8-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C]]
- ; GFX8-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND6]], [[C1]](s16)
- ; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[LSHR2]], [[SHL1]]
+ ; GFX8-NEXT: [[AND9:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C]]
+ ; GFX8-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND9]], [[C1]](s16)
+ ; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[SHL1]]
; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; GFX8-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; GFX8-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-LABEL: name: test_umulh_v3s8
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; GFX9-NEXT: {{ $}}
@@ -501,10 +503,11 @@ body: |
; GFX9-NEXT: [[AND7:%[0-9]+]]:_(s16) = G_AND [[TRUNC7]], [[C]]
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C1]](s16)
; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[SHL]]
+ ; GFX9-NEXT: [[AND8:%[0-9]+]]:_(s16) = G_AND [[LSHR1]], [[C]]
; GFX9-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
- ; GFX9-NEXT: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C]]
- ; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND8]], [[C1]](s16)
- ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[LSHR1]], [[SHL1]]
+ ; GFX9-NEXT: [[AND9:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C]]
+ ; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND9]], [[C1]](s16)
+ ; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[SHL1]]
; GFX9-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; GFX9-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX9-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
@@ -543,8 +546,8 @@ body: |
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX8-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
@@ -557,11 +560,12 @@ body: |
; GFX8-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C]]
; GFX8-NEXT: [[MUL1:%[0-9]+]]:_(s16) = G_MUL [[AND2]], [[AND3]]
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[MUL1]], [[C1]](s16)
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[LSHR1]], [[C1]](s16)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[LSHR]], [[SHL]]
+ ; GFX8-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C]]
+ ; GFX8-NEXT: [[AND5:%[0-9]+]]:_(s16) = G_AND [[LSHR1]], [[C]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C1]](s16)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_umulh_v2s8
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX9-NEXT: {{ $}}
@@ -631,8 +635,8 @@ body: |
; GFX8-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX8-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX8-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
@@ -657,8 +661,8 @@ body: |
; GFX8-NEXT: [[AND7:%[0-9]+]]:_(s16) = G_AND [[TRUNC7]], [[C3]]
; GFX8-NEXT: [[MUL3:%[0-9]+]]:_(s16) = G_MUL [[AND6]], [[AND7]]
; GFX8-NEXT: [[LSHR9:%[0-9]+]]:_(s16) = G_LSHR [[MUL3]], [[C4]](s16)
- ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR6]](s16)
; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR6]](s16)
; GFX8-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C5]]
; GFX8-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR7]](s16)
; GFX8-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C5]]
@@ -673,7 +677,6 @@ body: |
; GFX8-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX8-NEXT: $vgpr0 = COPY [[OR2]](s32)
- ;
; GFX9-LABEL: name: test_umulh_v4s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
index 13c52d08b4941ff..7f9993d9fce25f3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
@@ -20,7 +20,6 @@ body: |
; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[MUL]](s32)
; GFX8-NEXT: $vgpr1 = COPY [[ZEXT]](s32)
- ;
; GFX9-LABEL: name: test_umulo_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -70,7 +69,6 @@ body: |
; GFX8-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8-NEXT: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR1]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_umulo_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -86,8 +84,8 @@ body: |
; GFX9-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV3]]
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UMULH1]](s32), [[C]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[MUL]](s32), [[MUL1]](s32)
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
@@ -151,7 +149,6 @@ body: |
; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s64) = G_ZEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[MV1]](s64)
; GFX8-NEXT: $vgpr2_vgpr3 = COPY [[ZEXT5]](s64)
- ;
; GFX9-LABEL: name: test_umulo_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -286,15 +283,14 @@ body: |
; GFX8-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV24]](s32), [[UV26]](s32)
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MV2]](s64), [[C]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV1]](s64), [[MV3]](s64)
- ; GFX8-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s1)
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; GFX8-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s1)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C1]]
; GFX8-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP1]](s1)
; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT3]], [[C1]]
; GFX8-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[AND]](s64), [[AND1]](s64)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
; GFX8-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR1]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_umulo_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: {{ $}}
@@ -372,8 +368,8 @@ body: |
; GFX9-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV24]](s32), [[UV26]](s32)
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MV2]](s64), [[C]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV1]](s64), [[MV3]](s64)
- ; GFX9-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s1)
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; GFX9-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s1)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C1]]
; GFX9-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP1]](s1)
; GFX9-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT3]], [[C1]]
@@ -413,7 +409,6 @@ body: |
; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[AND3]](s32)
; GFX8-NEXT: $vgpr1 = COPY [[ZEXT]](s32)
- ;
; GFX9-LABEL: name: test_umulo_s24
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -466,7 +461,6 @@ body: |
; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[AND3]](s32)
; GFX8-NEXT: $vgpr1 = COPY [[ZEXT]](s32)
- ;
; GFX9-LABEL: name: test_umulo_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -514,7 +508,6 @@ body: |
; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[AND3]](s32)
; GFX8-NEXT: $vgpr1 = COPY [[ZEXT]](s32)
- ;
; GFX9-LABEL: name: test_umulo_s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -579,10 +572,10 @@ body: |
; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST]](<2 x s16>)
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX8-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C]]
- ; GFX8-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND10]](s32), [[LSHR]](s32)
+ ; GFX8-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C]]
+ ; GFX8-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND10]](s32), [[AND11]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR1]](<2 x s32>)
; GFX8-NEXT: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_umulo_v2s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -601,8 +594,8 @@ body: |
; GFX9-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[AND4]]
; GFX9-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C]]
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[AND5]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX9-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
; GFX9-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX9-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
@@ -647,8 +640,8 @@ body: |
; GFX8-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[AND4]]
; GFX8-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C]]
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[AND5]]
- ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[MUL]](s32)
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[MUL]](s32)
; GFX8-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[MUL1]](s32)
; GFX8-NEXT: [[AND7:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
@@ -661,7 +654,6 @@ body: |
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX8-NEXT: $vgpr1 = COPY [[ANYEXT1]](s32)
; GFX8-NEXT: $vgpr2 = COPY [[ANYEXT2]](s32)
- ;
; GFX9-LABEL: name: test_umulo_v2s8
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX9-NEXT: {{ $}}
@@ -680,8 +672,8 @@ body: |
; GFX9-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[AND4]]
; GFX9-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C]]
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[AND5]]
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[MUL]](s32)
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[MUL]](s32)
; GFX9-NEXT: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[MUL1]](s32)
; GFX9-NEXT: [[AND7:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
@@ -748,21 +740,22 @@ body: |
; GFX8-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX8-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX8-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[AND5]], [[AND6]]
- ; GFX8-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[LSHR2]], [[LSHR5]]
- ; GFX8-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C3]]
- ; GFX8-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C3]]
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL]]
- ; GFX8-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[MUL2]], [[C3]]
- ; GFX8-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
+ ; GFX8-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
+ ; GFX8-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
+ ; GFX8-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[AND7]], [[AND8]]
+ ; GFX8-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C3]]
+ ; GFX8-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C3]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C]](s32)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SHL]]
+ ; GFX8-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[MUL2]], [[C3]]
+ ; GFX8-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C1]](s32)
; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX8-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[MUL3]], [[C3]]
- ; GFX8-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C2]](s32)
+ ; GFX8-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[MUL3]], [[C3]]
+ ; GFX8-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C2]](s32)
; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8-NEXT: $vgpr0 = COPY [[OR2]](s32)
; GFX8-NEXT: $vgpr1 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: test_umulo_v4s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -789,16 +782,18 @@ body: |
; GFX9-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX9-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[AND5]], [[AND6]]
- ; GFX9-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[LSHR2]], [[LSHR5]]
- ; GFX9-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C3]]
- ; GFX9-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C3]]
- ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL]]
- ; GFX9-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[MUL2]], [[C3]]
- ; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
+ ; GFX9-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
+ ; GFX9-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
+ ; GFX9-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[AND7]], [[AND8]]
+ ; GFX9-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C3]]
+ ; GFX9-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C3]]
+ ; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C]](s32)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SHL]]
+ ; GFX9-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[MUL2]], [[C3]]
+ ; GFX9-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C1]](s32)
; GFX9-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[MUL3]], [[C3]]
- ; GFX9-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C2]](s32)
+ ; GFX9-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[MUL3]], [[C3]]
+ ; GFX9-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C2]](s32)
; GFX9-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX9-NEXT: $vgpr0 = COPY [[OR2]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
index c231aa8334d4519..cb1112043c21391 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
@@ -263,9 +263,10 @@ body: |
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY2]](s32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
- ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C1]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY2]](s32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C1]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR1]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[LSHR]](s32)
@@ -334,11 +335,13 @@ body: |
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY2]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY2]](s32)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
- ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
- ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[C1]](s32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY3]](s32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C1]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR2]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[LSHR]](s32)
@@ -386,11 +389,13 @@ body: |
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY2]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY2]](s32)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
- ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
- ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[C1]](s32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY3]](s32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C1]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR2]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[LSHR]](s32)
@@ -446,23 +451,29 @@ body: |
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY3]](s32)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY4]](s32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY4]](s32)
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY5]](s32)
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY5]](s32)
; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[COPY6]](s32)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY6]](s32)
; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
- ; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY7]](s32)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY7]](s32)
; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
- ; CHECK-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY8]](s32)
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY8]](s32)
; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
- ; CHECK-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY9]](s32)
- ; CHECK-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[C1]](s32)
- ; CHECK-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[C3]](s32)
- ; CHECK-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[LSHR1]], [[C4]](s32)
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY9]](s32)
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C1]](s32)
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C3]](s32)
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[C4]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[LSHR2]](s32)
; CHECK-NEXT: $vgpr2 = COPY [[LSHR3]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
index 44f44123bb73681..28d5f842140f19f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
@@ -36,7 +36,6 @@ body: |
; GFX6-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY1]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX6-NEXT: $vgpr0 = COPY [[SELECT1]](s32)
- ;
; GFX8-LABEL: name: test_urem_s32
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -62,7 +61,6 @@ body: |
; GFX8-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY1]]
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX8-NEXT: $vgpr0 = COPY [[SELECT1]](s32)
- ;
; GFX9-LABEL: name: test_urem_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -88,7 +86,6 @@ body: |
; GFX9-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY1]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX9-NEXT: $vgpr0 = COPY [[SELECT1]](s32)
- ;
; GFX10-LABEL: name: test_urem_s32
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
@@ -171,7 +168,6 @@ body: |
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SUB7]], [[SELECT2]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT1]](s32), [[SELECT3]](s32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX8-LABEL: name: test_urem_v2s32
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -217,7 +213,6 @@ body: |
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SUB7]], [[SELECT2]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT1]](s32), [[SELECT3]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: test_urem_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -263,7 +258,6 @@ body: |
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SUB7]], [[SELECT2]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT1]](s32), [[SELECT3]](s32)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX10-LABEL: name: test_urem_v2s32
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX10-NEXT: {{ $}}
@@ -467,7 +461,6 @@ body: |
; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
- ;
; GFX8-LABEL: name: test_urem_s64
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -614,7 +607,6 @@ body: |
; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]]
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
- ;
; GFX9-LABEL: name: test_urem_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -761,7 +753,6 @@ body: |
; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]]
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
- ;
; GFX10-LABEL: name: test_urem_s64
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX10-NEXT: {{ $}}
@@ -1203,7 +1194,6 @@ body: |
; GFX6-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV3]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT3]](s64), [[SELECT7]](s64)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX8-LABEL: name: test_urem_v2s64
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX8-NEXT: {{ $}}
@@ -1487,7 +1477,6 @@ body: |
; GFX8-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV3]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT3]](s64), [[SELECT7]](s64)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: test_urem_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: {{ $}}
@@ -1771,7 +1760,6 @@ body: |
; GFX9-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV3]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT3]](s64), [[SELECT7]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX10-LABEL: name: test_urem_v2s64
; GFX10: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX10-NEXT: {{ $}}
@@ -2096,7 +2084,6 @@ body: |
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C]]
; GFX6-NEXT: $vgpr0 = COPY [[AND2]](s32)
- ;
; GFX8-LABEL: name: test_urem_s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -2126,7 +2113,6 @@ body: |
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C]]
; GFX8-NEXT: $vgpr0 = COPY [[AND2]](s32)
- ;
; GFX9-LABEL: name: test_urem_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -2156,7 +2142,6 @@ body: |
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C]]
; GFX9-NEXT: $vgpr0 = COPY [[AND2]](s32)
- ;
; GFX10-LABEL: name: test_urem_s16
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
@@ -2233,30 +2218,31 @@ body: |
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; GFX6-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[LSHR1]](s32)
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; GFX6-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[AND3]](s32)
; GFX6-NEXT: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG1]], [[C2]]
; GFX6-NEXT: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL1]](s32)
- ; GFX6-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[LSHR1]]
+ ; GFX6-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[AND3]]
; GFX6-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
; GFX6-NEXT: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[MUL2]]
; GFX6-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[UMULH2]]
- ; GFX6-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[LSHR]], [[ADD1]]
- ; GFX6-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[LSHR1]]
- ; GFX6-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[MUL3]]
- ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB5]](s32), [[LSHR1]]
- ; GFX6-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[LSHR1]]
+ ; GFX6-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[AND2]], [[ADD1]]
+ ; GFX6-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[AND3]]
+ ; GFX6-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[AND2]], [[MUL3]]
+ ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB5]](s32), [[AND3]]
+ ; GFX6-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND3]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SUB6]], [[SUB5]]
- ; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT2]](s32), [[LSHR1]]
- ; GFX6-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[SELECT2]], [[LSHR1]]
+ ; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT2]](s32), [[AND3]]
+ ; GFX6-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[SELECT2]], [[AND3]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SUB7]], [[SELECT2]]
- ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C1]]
- ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SELECT3]], [[C1]]
- ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C1]]
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SELECT3]], [[C1]]
+ ; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX8-LABEL: name: test_urem_v2s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -2289,30 +2275,31 @@ body: |
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; GFX8-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[LSHR1]](s32)
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; GFX8-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[AND3]](s32)
; GFX8-NEXT: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX8-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG1]], [[C2]]
; GFX8-NEXT: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL1]](s32)
- ; GFX8-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[LSHR1]]
+ ; GFX8-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[AND3]]
; GFX8-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
; GFX8-NEXT: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[MUL2]]
; GFX8-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[UMULH2]]
- ; GFX8-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[LSHR]], [[ADD1]]
- ; GFX8-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[LSHR1]]
- ; GFX8-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[MUL3]]
- ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB5]](s32), [[LSHR1]]
- ; GFX8-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[LSHR1]]
+ ; GFX8-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[AND2]], [[ADD1]]
+ ; GFX8-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[AND3]]
+ ; GFX8-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[AND2]], [[MUL3]]
+ ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB5]](s32), [[AND3]]
+ ; GFX8-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND3]]
; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SUB6]], [[SUB5]]
- ; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT2]](s32), [[LSHR1]]
- ; GFX8-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[SELECT2]], [[LSHR1]]
+ ; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT2]](s32), [[AND3]]
+ ; GFX8-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[SELECT2]], [[AND3]]
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SUB7]], [[SELECT2]]
- ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C1]]
- ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SELECT3]], [[C1]]
- ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
+ ; GFX8-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C1]]
+ ; GFX8-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SELECT3]], [[C1]]
+ ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: test_urem_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -2346,27 +2333,28 @@ body: |
; GFX9-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SELECT1]](s32)
- ; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[LSHR1]](s32)
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; GFX9-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[AND3]](s32)
; GFX9-NEXT: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG1]], [[C2]]
; GFX9-NEXT: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL1]](s32)
- ; GFX9-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[LSHR1]]
+ ; GFX9-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[AND3]]
; GFX9-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
; GFX9-NEXT: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[MUL2]]
; GFX9-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[UMULH2]]
- ; GFX9-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[LSHR]], [[ADD1]]
- ; GFX9-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[LSHR1]]
- ; GFX9-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[MUL3]]
- ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB5]](s32), [[LSHR1]]
- ; GFX9-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[LSHR1]]
+ ; GFX9-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[AND2]], [[ADD1]]
+ ; GFX9-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[AND3]]
+ ; GFX9-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[AND2]], [[MUL3]]
+ ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB5]](s32), [[AND3]]
+ ; GFX9-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND3]]
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SUB6]], [[SUB5]]
- ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT2]](s32), [[LSHR1]]
- ; GFX9-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[SELECT2]], [[LSHR1]]
+ ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT2]](s32), [[AND3]]
+ ; GFX9-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[SELECT2]], [[AND3]]
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SUB7]], [[SELECT2]]
; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SELECT3]](s32)
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
- ;
; GFX10-LABEL: name: test_urem_v2s16
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
@@ -2400,22 +2388,24 @@ body: |
; GFX10-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX10-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SELECT1]](s32)
- ; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[LSHR1]](s32)
+ ; GFX10-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX10-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; GFX10-NEXT: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[AND3]](s32)
; GFX10-NEXT: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX10-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG1]], [[C2]]
; GFX10-NEXT: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL1]](s32)
- ; GFX10-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[LSHR1]]
+ ; GFX10-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[AND3]]
; GFX10-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
; GFX10-NEXT: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[MUL2]]
; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[UMULH2]]
- ; GFX10-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[LSHR]], [[ADD1]]
- ; GFX10-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[LSHR1]]
- ; GFX10-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[MUL3]]
- ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB5]](s32), [[LSHR1]]
- ; GFX10-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[LSHR1]]
+ ; GFX10-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[AND2]], [[ADD1]]
+ ; GFX10-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[UMULH3]], [[AND3]]
+ ; GFX10-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[AND2]], [[MUL3]]
+ ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB5]](s32), [[AND3]]
+ ; GFX10-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND3]]
; GFX10-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SUB6]], [[SUB5]]
- ; GFX10-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT2]](s32), [[LSHR1]]
- ; GFX10-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[SELECT2]], [[LSHR1]]
+ ; GFX10-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT2]](s32), [[AND3]]
+ ; GFX10-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[SELECT2]], [[AND3]]
; GFX10-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SUB7]], [[SELECT2]]
; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SELECT3]](s32)
; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
@@ -2460,7 +2450,6 @@ body: |
; GFX6-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX6-NEXT: $vgpr0 = COPY [[SELECT1]](s32)
- ;
; GFX8-LABEL: name: test_urem_s7
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -2489,7 +2478,6 @@ body: |
; GFX8-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX8-NEXT: $vgpr0 = COPY [[SELECT1]](s32)
- ;
; GFX9-LABEL: name: test_urem_s7
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -2518,7 +2506,6 @@ body: |
; GFX9-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX9-NEXT: $vgpr0 = COPY [[SELECT1]](s32)
- ;
; GFX10-LABEL: name: test_urem_s7
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
@@ -2590,7 +2577,6 @@ body: |
; GFX6-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX6-NEXT: $vgpr0 = COPY [[SELECT1]](s32)
- ;
; GFX8-LABEL: name: test_urem_s17
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -2619,7 +2605,6 @@ body: |
; GFX8-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX8-NEXT: $vgpr0 = COPY [[SELECT1]](s32)
- ;
; GFX9-LABEL: name: test_urem_s17
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -2648,7 +2633,6 @@ body: |
; GFX9-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX9-NEXT: $vgpr0 = COPY [[SELECT1]](s32)
- ;
; GFX10-LABEL: name: test_urem_s17
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
@@ -2841,7 +2825,6 @@ body: |
; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
- ;
; GFX8-LABEL: name: test_urem_s33
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -2991,7 +2974,6 @@ body: |
; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
- ;
; GFX9-LABEL: name: test_urem_s33
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -3141,7 +3123,6 @@ body: |
; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
- ;
; GFX10-LABEL: name: test_urem_s33
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX10-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
index c5bf23a15e1db11..a8a3ab3e79efbd9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
@@ -27,15 +27,14 @@ body: |
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[SHL1]]
; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[C1]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[LSHR1]](s32)
- ;
; GFX8-LABEL: name: ushlsat_s7
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 127
+ ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C1]](s16)
@@ -47,15 +46,14 @@ body: |
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[SELECT]], [[C1]](s16)
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: ushlsat_s7
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 127
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C1]](s16)
@@ -98,15 +96,14 @@ body: |
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[SHL1]]
; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[C1]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[LSHR1]](s32)
- ;
; GFX8-LABEL: name: ushlsat_s8
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C1]](s16)
@@ -118,15 +115,14 @@ body: |
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[SELECT]], [[C1]](s16)
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: ushlsat_s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C1]](s16)
@@ -178,14 +174,16 @@ body: |
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s32), [[LSHR4]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C3]], [[SHL3]]
; GFX6-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SELECT1]], [[C1]](s32)
+ ; GFX6-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[LSHR5]], [[COPY2]](s32)
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C2]]
+ ; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC]], [[TRUNC1]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC1]]
; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX8-LABEL: name: ushlsat_v2s8
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -195,8 +193,8 @@ body: |
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX8-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C2]](s16)
@@ -215,11 +213,12 @@ body: |
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s16), [[LSHR4]]
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP1]](s1), [[C3]], [[SHL3]]
; GFX8-NEXT: [[LSHR5:%[0-9]+]]:_(s16) = G_LSHR [[SELECT1]], [[C2]](s16)
- ; GFX8-NEXT: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[LSHR5]], [[C2]](s16)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[LSHR3]], [[SHL4]]
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[LSHR3]], [[C1]]
+ ; GFX8-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[LSHR5]], [[C1]]
+ ; GFX8-NEXT: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C2]](s16)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL4]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: ushlsat_v2s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -229,8 +228,8 @@ body: |
; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
; GFX9-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C2]](s16)
@@ -249,8 +248,10 @@ body: |
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s16), [[LSHR4]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP1]](s1), [[C3]], [[SHL3]]
; GFX9-NEXT: [[LSHR5:%[0-9]+]]:_(s16) = G_LSHR [[SELECT1]], [[C2]](s16)
- ; GFX9-NEXT: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[LSHR5]], [[C2]](s16)
- ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[LSHR3]], [[SHL4]]
+ ; GFX9-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[LSHR3]], [[C1]]
+ ; GFX9-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[LSHR5]], [[C1]]
+ ; GFX9-NEXT: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C2]](s16)
+ ; GFX9-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL4]]
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -287,7 +288,6 @@ body: |
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[SHL1]]
; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[C1]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[LSHR1]](s32)
- ;
; GFX8-LABEL: name: ushlsat_s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -302,7 +302,6 @@ body: |
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C]], [[SHL]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: ushlsat_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -351,17 +350,19 @@ body: |
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[LSHR2]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[SHL1]]
; GFX6-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[C]](s32)
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX6-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
- ; GFX6-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[LSHR1]](s32)
- ; GFX6-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[LSHR1]](s32)
+ ; GFX6-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND1]](s32)
+ ; GFX6-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[AND1]](s32)
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s32), [[LSHR4]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C2]], [[SHL3]]
; GFX6-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SELECT1]], [[C]](s32)
- ; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[LSHR5]], [[C]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL4]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
+ ; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX8-LABEL: name: ushlsat_v2s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -391,7 +392,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: ushlsat_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -441,46 +441,51 @@ body: |
; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; GFX6-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
- ; GFX6-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[LSHR1]](s32)
- ; GFX6-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SHL1]], [[LSHR1]](s32)
- ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; GFX6-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
+ ; GFX6-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SHL1]], [[AND]](s32)
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[LSHR3]]
- ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[SHL1]]
+ ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[SHL1]]
; GFX6-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[C]](s32)
- ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; GFX6-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
- ; GFX6-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND]](s32)
- ; GFX6-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[AND]](s32)
+ ; GFX6-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND1]](s32)
+ ; GFX6-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[AND1]](s32)
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s32), [[LSHR5]]
- ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[SHL3]]
+ ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C2]], [[SHL3]]
; GFX6-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SELECT1]], [[C]](s32)
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
- ; GFX6-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[SHL4]], [[LSHR2]](s32)
- ; GFX6-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[SHL5]], [[LSHR2]](s32)
+ ; GFX6-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[SHL4]], [[AND2]](s32)
+ ; GFX6-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[SHL5]], [[AND2]](s32)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL4]](s32), [[LSHR7]]
- ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[C1]], [[SHL5]]
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[C2]], [[SHL5]]
; GFX6-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[SELECT2]], [[C]](s32)
; GFX6-NEXT: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; GFX6-NEXT: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
- ; GFX6-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[LSHR6]], [[C]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[SHL6]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
+ ; GFX6-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL6]]
; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C2]]
- ; GFX6-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR8]], [[SHL7]]
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C1]]
+ ; GFX6-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; GFX6-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL7]]
; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C2]]
- ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR9]], [[SHL8]]
+ ; GFX6-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C1]]
+ ; GFX6-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
+ ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL8]]
; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX8-LABEL: name: ushlsat_v3s16
; GFX8: liveins: $vgpr0_vgpr1_vgpr2
; GFX8-NEXT: {{ $}}
@@ -528,13 +533,13 @@ body: |
; GFX8-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; GFX8-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C2]]
- ; GFX8-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR6]], [[SHL5]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C2]]
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C2]]
+ ; GFX8-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL5]]
; GFX8-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: ushlsat_v3s16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
@@ -618,34 +623,39 @@ body: |
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[LSHR4]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[SHL1]]
; GFX6-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[C]](s32)
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; GFX6-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
- ; GFX6-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[LSHR2]](s32)
- ; GFX6-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[LSHR2]](s32)
+ ; GFX6-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND1]](s32)
+ ; GFX6-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[AND1]](s32)
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s32), [[LSHR6]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C2]], [[SHL3]]
; GFX6-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[SELECT1]], [[C]](s32)
- ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
- ; GFX6-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[SHL4]], [[AND1]](s32)
- ; GFX6-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[SHL5]], [[AND1]](s32)
+ ; GFX6-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[SHL4]], [[AND2]](s32)
+ ; GFX6-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[SHL5]], [[AND2]](s32)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL4]](s32), [[LSHR8]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[C2]], [[SHL5]]
; GFX6-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[SELECT2]], [[C]](s32)
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
; GFX6-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
- ; GFX6-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[SHL6]], [[LSHR3]](s32)
- ; GFX6-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[SHL7]], [[LSHR3]](s32)
+ ; GFX6-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[SHL6]], [[AND3]](s32)
+ ; GFX6-NEXT: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[SHL7]], [[AND3]](s32)
; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL6]](s32), [[LSHR10]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[C2]], [[SHL7]]
; GFX6-NEXT: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[SELECT3]], [[C]](s32)
- ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[LSHR7]], [[C]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[SHL8]]
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C1]]
+ ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL8]]
; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[LSHR11]], [[C]](s32)
- ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR9]], [[SHL9]]
+ ; GFX6-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C1]]
+ ; GFX6-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C1]]
+ ; GFX6-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL9]]
; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX8-LABEL: name: ushlsat_v4s16
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -699,7 +709,6 @@ body: |
; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: ushlsat_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -768,7 +777,6 @@ body: |
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[LSHR]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[SHL]]
; GFX6-NEXT: $vgpr0 = COPY [[SELECT]](s32)
- ;
; GFX8-LABEL: name: ushlsat_s32
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -780,7 +788,6 @@ body: |
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[LSHR]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[SHL]]
; GFX8-NEXT: $vgpr0 = COPY [[SELECT]](s32)
- ;
; GFX9-LABEL: name: ushlsat_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -822,7 +829,6 @@ body: |
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C]], [[SHL1]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX8-LABEL: name: ushlsat_v2s32
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -841,7 +847,6 @@ body: |
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C]], [[SHL1]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: ushlsat_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -884,7 +889,6 @@ body: |
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[LSHR]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[C]], [[SHL]]
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; GFX8-LABEL: name: ushlsat_s64
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -897,7 +901,6 @@ body: |
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[LSHR]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[C]], [[SHL]]
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; GFX9-LABEL: name: ushlsat_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -942,7 +945,6 @@ body: |
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[C]], [[SHL1]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT]](s64), [[SELECT1]](s64)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX8-LABEL: name: ushlsat_v2s64
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX8-NEXT: {{ $}}
@@ -963,7 +965,6 @@ body: |
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[C]], [[SHL1]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT]](s64), [[SELECT1]](s64)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: ushlsat_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
index 6aff25387fc3e89..249695a7616369a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
@@ -139,20 +139,22 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
- ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[LSHR1]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB1]](s32), [[AND3]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND3]], [[AND4]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB1]](s32), [[AND5]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND5]](s32)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL]]
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND4]](s32), [[AND5]](s32)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND6]](s32), [[AND7]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; CHECK-NEXT: $vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s16>) = COPY $vgpr0
@@ -188,14 +190,16 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
- ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[LSHR1]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB1]](s32), [[AND3]]
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[AND4]], [[AND5]]
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB2]], [[C1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB2]](s32), [[AND6]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND3]], [[AND4]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB1]](s32), [[AND5]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[AND6]], [[AND7]]
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SUB2]], [[C1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB2]](s32), [[AND8]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
@@ -205,25 +209,26 @@ body: |
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND5]](s32)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL]]
; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND6]](s32)
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND8]](s32)
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY4]], [[SHL1]]
; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C]](s32)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL2]]
; CHECK-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>), [[BITCAST8]](<2 x s16>)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
- ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
- ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND9]](s32), [[AND10]](s32), [[AND11]](s32)
+ ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
+ ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
+ ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND12]](s32), [[AND13]](s32), [[AND14]](s32)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
@@ -266,24 +271,28 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
- ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[LSHR2]]
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C1]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB1]](s32), [[AND3]]
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[AND4]], [[AND5]]
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB2]], [[C1]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB2]](s32), [[AND6]]
- ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LSHR1]], [[LSHR3]]
- ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SUB3]], [[C1]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB3]](s32), [[AND7]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND3]], [[AND4]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB1]](s32), [[AND5]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[AND6]], [[AND7]]
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SUB2]], [[C1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB2]](s32), [[AND8]]
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[AND9]], [[AND10]]
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[SUB3]], [[C1]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB3]](s32), [[AND11]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND5]](s32)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND6]](s32)
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[AND7]](s32)
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND8]](s32)
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[AND11]](s32)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY4]], [[SHL1]]
; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -293,11 +302,11 @@ body: |
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP3]](s1)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
- ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
- ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
- ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C2]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND8]](s32), [[AND9]](s32), [[AND10]](s32), [[AND11]](s32)
+ ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
+ ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
+ ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
+ ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C2]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND12]](s32), [[AND13]](s32), [[AND14]](s32), [[AND15]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; CHECK-NEXT: $vgpr2_vgpr3_vgpr4_vgpr5 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
index 663ffdcd5364cce..4b8a067ab74a95a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
@@ -23,7 +23,6 @@ body: |
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[LSHR]](s32)
- ;
; GFX8-LABEL: name: usubsat_s7
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -38,7 +37,6 @@ body: |
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C]](s16)
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: usubsat_s7
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -80,7 +78,6 @@ body: |
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[LSHR]](s32)
- ;
; GFX8-LABEL: name: usubsat_s8
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -95,7 +92,6 @@ body: |
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C]](s16)
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: usubsat_s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -144,14 +140,17 @@ body: |
; GFX6-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[SHL2]], [[SHL3]]
; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[UMIN1]]
; GFX6-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C1]](s32)
+ ; GFX6-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX6-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[COPY2]](s32)
+ ; GFX6-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY2]](s32)
; GFX6-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC]], [[TRUNC1]]
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; GFX6-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX6-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX8-LABEL: name: usubsat_v2s8
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -173,11 +172,13 @@ body: |
; GFX8-NEXT: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C1]](s16)
; GFX8-NEXT: [[USUBSAT1:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL2]], [[SHL3]]
; GFX8-NEXT: [[LSHR3:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT1]], [[C1]](s16)
- ; GFX8-NEXT: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[LSHR3]], [[C1]](s16)
- ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[LSHR2]], [[SHL4]]
+ ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[LSHR2]], [[C2]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[LSHR3]], [[C2]]
+ ; GFX8-NEXT: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
+ ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: usubsat_v2s8
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -240,7 +241,6 @@ body: |
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[LSHR]](s32)
- ;
; GFX8-LABEL: name: usubsat_s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -251,7 +251,6 @@ body: |
; GFX8-NEXT: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC1]]
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USUBSAT]](s16)
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- ;
; GFX9-LABEL: name: usubsat_s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -297,11 +296,13 @@ body: |
; GFX6-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[SHL2]], [[SHL3]]
; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[UMIN1]]
; GFX6-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C]](s32)
- ; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[C]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL4]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; GFX6-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL4]]
; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX8-LABEL: name: usubsat_v2s16
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -324,7 +325,6 @@ body: |
; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
- ;
; GFX9-LABEL: name: usubsat_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -376,21 +376,24 @@ body: |
; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
- ; GFX6-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[LSHR4]], [[C]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL6]]
- ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; GFX6-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
- ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[SHL7]]
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; GFX6-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL6]]
+ ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; GFX6-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL7]]
; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
- ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR6]], [[SHL8]]
+ ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
+ ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; GFX6-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL8]]
; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX8-LABEL: name: usubsat_v3s16
; GFX8: liveins: $vgpr0_vgpr1_vgpr2
; GFX8-NEXT: {{ $}}
@@ -428,13 +431,13 @@ body: |
; GFX8-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; GFX8-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
- ; GFX8-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL2]]
+ ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; GFX8-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; GFX8-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
+ ; GFX8-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; GFX8-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
- ;
; GFX9-LABEL: name: usubsat_v3s16
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
; GFX9-NEXT: {{ $}}
@@ -524,15 +527,19 @@ body: |
; GFX6-NEXT: [[UMIN3:%[0-9]+]]:_(s32) = G_UMIN [[SHL6]], [[SHL7]]
; GFX6-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SHL6]], [[UMIN3]]
; GFX6-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[SUB3]], [[C]](s32)
- ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[LSHR5]], [[C]](s32)
- ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[SHL8]]
+ ; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX6-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; GFX6-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
+ ; GFX6-NEXT: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
+ ; GFX6-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL8]]
; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[LSHR7]], [[C]](s32)
- ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR6]], [[SHL9]]
+ ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
+ ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C1]]
+ ; GFX6-NEXT: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL9]]
; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX8-LABEL: name: usubsat_v4s16
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -573,7 +580,6 @@ body: |
; GFX8-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX8-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
- ;
; GFX9-LABEL: name: usubsat_v4s16
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -605,7 +611,6 @@ body: |
; GFX6-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]]
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[UMIN]]
; GFX6-NEXT: $vgpr0 = COPY [[SUB]](s32)
- ;
; GFX8-LABEL: name: usubsat_s32
; GFX8: liveins: $vgpr0, $vgpr1
; GFX8-NEXT: {{ $}}
@@ -613,7 +618,6 @@ body: |
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8-NEXT: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[COPY]], [[COPY1]]
; GFX8-NEXT: $vgpr0 = COPY [[USUBSAT]](s32)
- ;
; GFX9-LABEL: name: usubsat_s32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
@@ -646,7 +650,6 @@ body: |
; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV1]], [[UMIN1]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SUB]](s32), [[SUB1]](s32)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX8-LABEL: name: usubsat_v2s32
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -658,7 +661,6 @@ body: |
; GFX8-NEXT: [[USUBSAT1:%[0-9]+]]:_(s32) = G_USUBSAT [[UV1]], [[UV3]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[USUBSAT]](s32), [[USUBSAT1]](s32)
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- ;
; GFX9-LABEL: name: usubsat_v2s32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -695,7 +697,6 @@ body: |
; GFX6-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[USUBE1]](s1), [[C]], [[MV]]
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; GFX8-LABEL: name: usubsat_s64
; GFX8: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX8-NEXT: {{ $}}
@@ -709,7 +710,6 @@ body: |
; GFX8-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[USUBE1]](s1), [[C]], [[MV]]
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
- ;
; GFX9-LABEL: name: usubsat_s64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
@@ -757,7 +757,6 @@ body: |
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[USUBE3]](s1), [[C]], [[MV1]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT]](s64), [[SELECT1]](s64)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX8-LABEL: name: usubsat_v2s64
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX8-NEXT: {{ $}}
@@ -780,7 +779,6 @@ body: |
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[USUBE3]](s1), [[C]], [[MV1]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT]](s64), [[SELECT1]](s64)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
- ;
; GFX9-LABEL: name: usubsat_v2s64
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
index 9353813a8dbfc8f..bfbbf03ebeb2017 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
@@ -472,9 +472,10 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UV6]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS2]](<6 x s16>)
@@ -532,9 +533,10 @@ body: |
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
@@ -543,9 +545,10 @@ body: |
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[SHL1]]
; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS2:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST6]](<2 x s16>), [[BITCAST7]](<2 x s16>)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL2]]
; CHECK-NEXT: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
@@ -560,17 +563,20 @@ body: |
; CHECK-NEXT: [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>), [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF2]](<8 x s16>)
; CHECK-NEXT: [[BITCAST11:%[0-9]+]]:_(s32) = G_BITCAST [[UV12]](<2 x s16>)
; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST11]], [[C]](s32)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C]](s32)
- ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL4]]
; CHECK-NEXT: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST10]], [[C1]]
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
- ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL5]]
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST10]], [[C1]]
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL5]]
; CHECK-NEXT: [[BITCAST13:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[LSHR4]], [[C]](s32)
- ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL6]]
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
+ ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
; CHECK-NEXT: [[BITCAST14:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
; CHECK-NEXT: [[CONCAT_VECTORS4:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST12]](<2 x s16>), [[BITCAST13]](<2 x s16>), [[BITCAST14]](<2 x s16>), [[UV13]](<2 x s16>)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS4]](<8 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
index 8db6a7c78aaa452..98b210cbcdaadd6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
@@ -28,8 +28,8 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(s32) = COPY $vgpr0
@@ -138,7 +138,8 @@ body: |
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[LSHR]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s32>) = G_ZEXT %0
@@ -162,8 +163,9 @@ body: |
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[LSHR]](s32), [[AND1]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<3 x s16>) = G_EXTRACT %0, 0
@@ -189,8 +191,10 @@ body: |
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[LSHR]](s32), [[AND1]](s32), [[LSHR1]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s32>) = G_ZEXT %0
@@ -271,8 +275,8 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; CHECK-NEXT: S_ENDPGM 0, implicit [[AND]](s16)
%0:_(s32) = COPY $vgpr0
@@ -650,8 +654,8 @@ body: |
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
@@ -661,11 +665,13 @@ body: |
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C4]](s16)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C3]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C4]](s16)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[C5]], [[C4]](s16)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[C5]], [[SHL2]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s16) = G_AND [[C5]], [[C3]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND4]], [[C4]](s16)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL2]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY [[OR2]](s16)
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
@@ -709,61 +715,67 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
- ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C2]](s32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64)
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
- ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
- ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[UV]], [[SHL2]]
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
- ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[UV1]], [[SHL3]]
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C2]](s32)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL2]]
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[C2]](s32)
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[C4]], [[SHL3]]
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV1]](s64)
; CHECK-NEXT: [[EXTRACT:%[0-9]+]]:_(s48) = G_EXTRACT [[DEF]](s64), 0
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C3]](s64)
- ; CHECK-NEXT: [[EXTRACT1:%[0-9]+]]:_(s48) = G_EXTRACT [[MV1]](s64), 0
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; CHECK-NEXT: [[EXTRACT1:%[0-9]+]]:_(s48) = G_EXTRACT [[MV]](s64), 0
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT]](s48)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT1]](s48)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[ANYEXT1]]
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND2]](s64)
- ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[ANYEXT1]]
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND6]](s64)
+ ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
- ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C1]]
- ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C]](s32)
- ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL4]]
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C1]]
- ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
+ ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C2]](s32)
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C2]](s32)
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL4]]
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SHL1]]
; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR4]](s32), [[OR5]](s32)
- ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C1]]
- ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C3]]
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C2]](s32)
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[SHL5]]
- ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C1]]
- ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
- ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL6]]
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C3]]
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C2]](s32)
+ ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND11]], [[SHL6]]
; CHECK-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR6]](s32), [[OR7]](s32)
- ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL5]]
+ ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL5]]
; CHECK-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[OR8]](s32)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
; CHECK-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[UV4]](s32)
- ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
- ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[SHL3]]
+ ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL1]]
+ ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[SHL1]]
; CHECK-NEXT: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR9]](s32), [[OR10]](s32)
- ; CHECK-NEXT: [[MV7:%[0-9]+]]:_(s384) = G_MERGE_VALUES [[AND1]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64), [[MV5]](s64), [[MV6]](s64)
+ ; CHECK-NEXT: [[MV7:%[0-9]+]]:_(s384) = G_MERGE_VALUES [[AND5]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64), [[MV5]](s64), [[MV6]](s64)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s112) = G_TRUNC [[MV7]](s384)
; CHECK-NEXT: S_ENDPGM 0, implicit [[TRUNC]](s112)
%0:_(s32) = COPY $vgpr0
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
index 96461e044813d49..782b05d55003008 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
@@ -1117,7 +1117,8 @@ body: |
; SOFT-NOT: G_FCMP
; For soft float we just need to return a '-1' constant, but the truncation
; to 1 bit is converted by the combiner to the following masking sequence.
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = COPY [[R]](s32)
; SOFT-NOT: G_FCMP
; CHECK: $r0 = COPY [[REXT]]
...
@@ -1151,7 +1152,8 @@ body: |
; SOFT-NOT: G_FCMP
; For soft float we just need to return a '0' constant, but the truncation
; to 1 bit is converted by the combiner to the following masking sequence.
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = COPY [[R]](s32)
; SOFT-NOT: G_FCMP
; CHECK: $r0 = COPY [[REXT]]
...
@@ -1823,7 +1825,8 @@ body: |
; SOFT-NOT: G_FCMP
; The result needs to be truncated, and the combiner turns the truncation
; into the following masking sequence.
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = COPY [[MASK]]
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
$r0 = COPY %7(s32)
@@ -1867,9 +1870,11 @@ body: |
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s64), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; The result needs to be truncated, and the combiner turns the truncation
; into the following masking sequence.
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = COPY [[R]]
+ ; SOFT-NOT: G_FCMP
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
$r0 = COPY %7(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
index 52352edbe33921a..8fcdd3fc8da256e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
@@ -24,12 +24,11 @@ body: |
; MIPS32-LABEL: name: add_i32
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[ADD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
+ ; MIPS32: $v0 = COPY [[ADD]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_ADD %0, %1
@@ -47,15 +46,14 @@ body: |
; MIPS32-LABEL: name: add_i8_sext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
- ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; MIPS32: $v0 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -76,14 +74,13 @@ body: |
; MIPS32-LABEL: name: add_i8_zext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
+ ; MIPS32: $v0 = COPY [[AND]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -104,12 +101,11 @@ body: |
; MIPS32-LABEL: name: add_i8_aext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[ADD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[ADD]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -130,15 +126,14 @@ body: |
; MIPS32-LABEL: name: add_i16_sext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
- ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; MIPS32: $v0 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -159,14 +154,13 @@ body: |
; MIPS32-LABEL: name: add_i16_zext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
+ ; MIPS32: $v0 = COPY [[AND]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -187,12 +181,11 @@ body: |
; MIPS32-LABEL: name: add_i16_aext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[ADD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[ADD]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -213,18 +206,19 @@ body: |
; MIPS32-LABEL: name: add_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY1]]
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]]
- ; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY]]
- ; MIPS32-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]]
- ; MIPS32-NEXT: $v0 = COPY [[ADD2]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[ADD]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY1]]
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]]
+ ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
+ ; MIPS32: $v0 = COPY [[ADD2]](s32)
+ ; MIPS32: $v1 = COPY [[ADD]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %3(s32), %2(s32)
@@ -253,44 +247,44 @@ body: |
; MIPS32-LABEL: name: add_i128
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0)
- ; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; MIPS32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1)
- ; MIPS32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
- ; MIPS32-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.2)
- ; MIPS32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
- ; MIPS32-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.3)
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[COPY]]
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY]]
- ; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[COPY1]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[LOAD1]]
- ; MIPS32-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD2]](s32), [[C]]
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[ICMP]]
- ; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[AND]]
- ; MIPS32-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[COPY2]]
- ; MIPS32-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[LOAD2]]
- ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C1]]
- ; MIPS32-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[AND1]]
- ; MIPS32-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD4]](s32), [[C]]
- ; MIPS32-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[OR]]
- ; MIPS32-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ICMP3]], [[AND2]]
- ; MIPS32-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[COPY3]]
- ; MIPS32-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C1]]
- ; MIPS32-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND3]]
- ; MIPS32-NEXT: $v0 = COPY [[ADD]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[ADD2]](s32)
- ; MIPS32-NEXT: $a0 = COPY [[ADD4]](s32)
- ; MIPS32-NEXT: $a1 = COPY [[ADD6]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0)
+ ; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1)
+ ; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.2)
+ ; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.3)
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[COPY]]
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY]]
+ ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[COPY1]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[LOAD1]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD2]](s32), [[C1]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[ICMP]]
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[AND1]]
+ ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[COPY2]]
+ ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[LOAD2]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C]]
+ ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[AND2]]
+ ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD4]](s32), [[C1]]
+ ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[OR]]
+ ; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ICMP3]], [[AND3]]
+ ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[COPY3]]
+ ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C]]
+ ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]]
+ ; MIPS32: $v0 = COPY [[ADD]](s32)
+ ; MIPS32: $v1 = COPY [[ADD2]](s32)
+ ; MIPS32: $a0 = COPY [[ADD4]](s32)
+ ; MIPS32: $a1 = COPY [[ADD6]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%4:_(s32) = COPY $a2
@@ -324,18 +318,18 @@ body: |
; MIPS32-LABEL: name: uadd_with_overflow
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
- ; MIPS32-NEXT: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store (s8) into %ir.pcarry_flag)
- ; MIPS32-NEXT: G_STORE [[ADD]](s32), [[COPY2]](p0) :: (store (s32) into %ir.padd)
- ; MIPS32-NEXT: RetRA
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
+ ; MIPS32: G_STORE [[AND1]](s32), [[COPY3]](p0) :: (store (s8) into %ir.pcarry_flag)
+ ; MIPS32: G_STORE [[ADD]](s32), [[COPY2]](p0) :: (store (s32) into %ir.padd)
+ ; MIPS32: RetRA
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(p0) = COPY $a2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
index ec88831baa72455..ecda48cbb76aabe 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
@@ -42,12 +42,11 @@ body: |
; MIPS32-LABEL: name: and_i1
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[AND]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -68,12 +67,11 @@ body: |
; MIPS32-LABEL: name: and_i8
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[AND]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -94,12 +92,11 @@ body: |
; MIPS32-LABEL: name: and_i16
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[AND]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -120,12 +117,11 @@ body: |
; MIPS32-LABEL: name: and_i32
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[AND]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_AND %1, %0
@@ -143,16 +139,15 @@ body: |
; MIPS32-LABEL: name: and_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY]]
- ; MIPS32-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[AND1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY1]]
+ ; MIPS32: $v0 = COPY [[AND]](s32)
+ ; MIPS32: $v1 = COPY [[AND1]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -176,12 +171,11 @@ body: |
; MIPS32-LABEL: name: or_i1
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[OR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[OR]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -202,12 +196,11 @@ body: |
; MIPS32-LABEL: name: or_i8
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[OR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[OR]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -228,12 +221,11 @@ body: |
; MIPS32-LABEL: name: or_i16
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[OR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[OR]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -254,12 +246,11 @@ body: |
; MIPS32-LABEL: name: or_i32
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[OR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[OR]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_OR %1, %0
@@ -277,16 +268,15 @@ body: |
; MIPS32-LABEL: name: or_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY]]
- ; MIPS32-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[OR]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[OR1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY]]
+ ; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY1]]
+ ; MIPS32: $v0 = COPY [[OR]](s32)
+ ; MIPS32: $v1 = COPY [[OR1]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -310,12 +300,11 @@ body: |
; MIPS32-LABEL: name: xor_i1
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[XOR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[XOR]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -336,12 +325,11 @@ body: |
; MIPS32-LABEL: name: xor_i8
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[XOR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[XOR]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -362,12 +350,11 @@ body: |
; MIPS32-LABEL: name: xor_i16
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[XOR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[XOR]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -388,12 +375,11 @@ body: |
; MIPS32-LABEL: name: xor_i32
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[XOR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[XOR]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_XOR %1, %0
@@ -411,16 +397,15 @@ body: |
; MIPS32-LABEL: name: xor_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY]]
- ; MIPS32-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY3]], [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[XOR]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[XOR1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY]]
+ ; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY3]], [[COPY1]]
+ ; MIPS32: $v0 = COPY [[XOR]](s32)
+ ; MIPS32: $v1 = COPY [[XOR1]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -444,12 +429,11 @@ body: |
; MIPS32-LABEL: name: shl
; MIPS32: liveins: $a0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[SHL]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; MIPS32: $v0 = COPY [[SHL]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_SHL %0, %1
@@ -467,12 +451,11 @@ body: |
; MIPS32-LABEL: name: ashr
; MIPS32: liveins: $a0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
+ ; MIPS32: $v0 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_ASHR %0, %1
@@ -490,12 +473,11 @@ body: |
; MIPS32-LABEL: name: lshr
; MIPS32: liveins: $a0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[LSHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
+ ; MIPS32: $v0 = COPY [[LSHR]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_LSHR %0, %1
@@ -513,12 +495,11 @@ body: |
; MIPS32-LABEL: name: lshr_i64_shift_amount
; MIPS32: liveins: $a0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[LSHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
+ ; MIPS32: $v0 = COPY [[LSHR]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s64) = G_CONSTANT i64 1
%2:_(s32) = G_LSHR %0, %1
@@ -536,12 +517,11 @@ body: |
; MIPS32-LABEL: name: shlv
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[SHL]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; MIPS32: $v0 = COPY [[SHL]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_SHL %0, %1
@@ -559,12 +539,11 @@ body: |
; MIPS32-LABEL: name: ashrv
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
+ ; MIPS32: $v0 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_ASHR %0, %1
@@ -582,12 +561,11 @@ body: |
; MIPS32-LABEL: name: lshrv
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[LSHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
+ ; MIPS32: $v0 = COPY [[LSHR]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_LSHR %0, %1
@@ -605,12 +583,12 @@ body: |
; MIPS32-LABEL: name: shl_i16
; MIPS32: liveins: $a0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[SHL]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; MIPS32: $v0 = COPY [[SHL]](s32)
+ ; MIPS32: RetRA implicit $v0
%1:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s16) = G_CONSTANT i16 2
@@ -630,15 +608,15 @@ body: |
; MIPS32-LABEL: name: ashr_i8
; MIPS32: liveins: $a0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
- ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
- ; MIPS32-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
+ ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[COPY1]](s32)
+ ; MIPS32: $v0 = COPY [[ASHR1]](s32)
+ ; MIPS32: RetRA implicit $v0
%1:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s8) = G_CONSTANT i8 2
@@ -658,14 +636,14 @@ body: |
; MIPS32-LABEL: name: lshr_i16
; MIPS32: liveins: $a0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[LSHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
+ ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
+ ; MIPS32: $v0 = COPY [[LSHR]](s32)
+ ; MIPS32: RetRA implicit $v0
%1:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s16) = G_CONSTANT i16 2
@@ -685,27 +663,30 @@ body: |
; MIPS32-LABEL: name: shl_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[C]]
- ; MIPS32-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]]
- ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C1]]
- ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY2]](s32)
- ; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[SUB1]](s32)
- ; MIPS32-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY2]](s32)
- ; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
- ; MIPS32-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SUB]](s32)
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SHL]], [[C1]]
- ; MIPS32-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[SHL2]]
- ; MIPS32-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[COPY1]], [[SELECT1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[SELECT2]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[C]]
+ ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]]
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C1]]
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY2]](s32)
+ ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[SUB1]](s32)
+ ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY2]](s32)
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
+ ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SUB]](s32)
+ ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[SHL]], [[C1]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[OR]], [[SHL2]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]]
+ ; MIPS32: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[COPY1]], [[SELECT1]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: $v1 = COPY [[SELECT2]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -729,29 +710,32 @@ body: |
; MIPS32-LABEL: name: ashl_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[C]]
- ; MIPS32-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]]
- ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C1]]
- ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[COPY2]](s32)
- ; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY2]](s32)
- ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[SUB1]](s32)
- ; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
- ; MIPS32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; MIPS32-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C2]](s32)
- ; MIPS32-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[SUB]](s32)
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[ASHR2]]
- ; MIPS32-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[COPY]], [[SELECT]]
- ; MIPS32-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ASHR]], [[ASHR1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT1]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[SELECT2]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[C]]
+ ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]]
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C1]]
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[COPY2]](s32)
+ ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY2]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[SUB1]](s32)
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C2]](s32)
+ ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[SUB]](s32)
+ ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[OR]], [[ASHR2]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C3]]
+ ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY]], [[SELECT]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; MIPS32: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ASHR]], [[ASHR1]]
+ ; MIPS32: $v0 = COPY [[SELECT1]](s32)
+ ; MIPS32: $v1 = COPY [[SELECT2]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -775,27 +759,30 @@ body: |
; MIPS32-LABEL: name: lshr_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[C]]
- ; MIPS32-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]]
- ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C1]]
- ; MIPS32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[COPY2]](s32)
- ; MIPS32-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY2]](s32)
- ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[SUB1]](s32)
- ; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL]]
- ; MIPS32-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[SUB]](s32)
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[LSHR2]]
- ; MIPS32-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[COPY]], [[SELECT]]
- ; MIPS32-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[LSHR]], [[C1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT1]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[SELECT2]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[C]]
+ ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]]
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C1]]
+ ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[COPY2]](s32)
+ ; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY2]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[SUB1]](s32)
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL]]
+ ; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[SUB]](s32)
+ ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[OR]], [[LSHR2]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]]
+ ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY]], [[SELECT]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; MIPS32: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[LSHR]], [[C1]]
+ ; MIPS32: $v0 = COPY [[SELECT1]](s32)
+ ; MIPS32: $v1 = COPY [[SELECT2]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
index 0ced5d52d262c4f..9265bae16b899bd 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
@@ -20,10 +20,10 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: any_i64
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; MIPS32-NEXT: $v0 = COPY [[C1]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+ ; MIPS32: $v0 = COPY [[C1]](s32)
+ ; MIPS32: $v1 = COPY [[C]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
%0:_(s64) = G_CONSTANT i64 -9223372036854775808
%1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0(s64)
$v0 = COPY %2(s32)
@@ -39,8 +39,8 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: any_i32
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; MIPS32-NEXT: $v0 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: $v0 = COPY [[C]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = G_CONSTANT i32 -2147483648
$v0 = COPY %0(s32)
RetRA implicit $v0
@@ -54,9 +54,9 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: signed_i16
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[COPY]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; MIPS32: $v0 = COPY [[COPY]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s16) = G_CONSTANT i16 -32768
%1:_(s32) = G_SEXT %0(s16)
$v0 = COPY %1(s32)
@@ -71,9 +71,9 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: signed_i8
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -128
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[COPY]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; MIPS32: $v0 = COPY [[COPY]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s8) = G_CONSTANT i8 -128
%1:_(s32) = G_SEXT %0(s8)
$v0 = COPY %1(s32)
@@ -88,8 +88,8 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: unsigned_i16
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32768
- ; MIPS32-NEXT: $v0 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: $v0 = COPY [[C]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s16) = G_CONSTANT i16 -32768
%1:_(s32) = G_ZEXT %0(s16)
$v0 = COPY %1(s32)
@@ -104,8 +104,8 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: unsigned_i8
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
- ; MIPS32-NEXT: $v0 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: $v0 = COPY [[C]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s8) = G_CONSTANT i8 -128
%1:_(s32) = G_ZEXT %0(s8)
$v0 = COPY %1(s32)
@@ -120,8 +120,9 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: i1_true
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: $v0 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; MIPS32: $v0 = COPY [[COPY]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s1) = G_CONSTANT i1 true
%1:_(s32) = G_ZEXT %0(s1)
$v0 = COPY %1(s32)
@@ -136,8 +137,9 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: i1_false
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: $v0 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; MIPS32: $v0 = COPY [[COPY]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s1) = G_CONSTANT i1 false
%1:_(s32) = G_ZEXT %0(s1)
$v0 = COPY %1(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
index 73ea9338426c24f..f3865435873ada2 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
@@ -10,11 +10,10 @@ body: |
; MIPS32-LABEL: name: ctlz_i32
; MIPS32: liveins: $a0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[CTLZ]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32)
+ ; MIPS32: $v0 = COPY [[CTLZ]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = G_CTLZ %0(s32)
$v0 = COPY %1(s32)
@@ -31,19 +30,20 @@ body: |
; MIPS32-LABEL: name: ctlz_i64
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
- ; MIPS32-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32)
- ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ]], [[C1]]
- ; MIPS32-NEXT: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32)
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD]], [[CTLZ1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32)
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ]], [[C1]]
+ ; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32)
+ ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[CTLZ1]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: $v1 = COPY [[C]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
%1:_(s32) = COPY $a0
%2:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
index 3e7bcdc39d5d902..78a182ff4cfdd2c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
@@ -10,17 +10,16 @@ body: |
; MIPS32-LABEL: name: cttz_i32
; MIPS32: liveins: $a0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]]
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
- ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; MIPS32-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[CTLZ]]
- ; MIPS32-NEXT: $v0 = COPY [[SUB]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]]
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[CTLZ]]
+ ; MIPS32: $v0 = COPY [[SUB]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = G_CTTZ %0(s32)
$v0 = COPY %1(s32)
@@ -37,28 +36,29 @@ body: |
; MIPS32-LABEL: name: cttz_i64
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]]
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C1]]
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
- ; MIPS32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; MIPS32-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ]]
- ; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SUB]], [[C2]]
- ; MIPS32-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]]
- ; MIPS32-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
- ; MIPS32-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]]
- ; MIPS32-NEXT: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32)
- ; MIPS32-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ1]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD1]], [[SUB1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[C]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]]
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C1]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
+ ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ]]
+ ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SUB]], [[C2]]
+ ; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]]
+ ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]]
+ ; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32)
+ ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ1]]
+ ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ADD1]], [[SUB1]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: $v1 = COPY [[C]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
%1:_(s32) = COPY $a0
%2:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
@@ -79,22 +79,22 @@ body: |
; MIPS32-LABEL: name: ffs_i32_expansion
; MIPS32: liveins: $a0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C2]]
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
- ; MIPS32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; MIPS32-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ]]
- ; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = nuw nsw G_ADD [[SUB]], [[C]]
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C1]], [[ADD1]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C2]]
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
+ ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ]]
+ ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = nuw nsw G_ADD [[SUB]], [[C]]
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[C1]], [[ADD1]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%2:_(s32) = G_CONSTANT i32 1
%4:_(s32) = G_CONSTANT i32 0
@@ -116,41 +116,43 @@ body: |
; MIPS32-LABEL: name: ffs_i64_expansion
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C1]](s32)
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
- ; MIPS32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C2]]
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C2]]
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
- ; MIPS32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; MIPS32-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ]]
- ; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SUB]], [[C3]]
- ; MIPS32-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C2]]
- ; MIPS32-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
- ; MIPS32-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]]
- ; MIPS32-NEXT: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32)
- ; MIPS32-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ1]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD1]], [[SUB1]]
- ; MIPS32-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[C]]
- ; MIPS32-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[C1]], [[C1]]
- ; MIPS32-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[ICMP1]]
- ; MIPS32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ADD3]](s32), [[ADD5]](s32)
- ; MIPS32-NEXT: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]]
- ; MIPS32-NEXT: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]]
- ; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR2]], [[XOR3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C1]]
- ; MIPS32-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s32), [[MV]], [[MV1]]
- ; MIPS32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT1]](s64)
- ; MIPS32-NEXT: $v0 = COPY [[UV]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[UV1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C1]](s32)
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
+ ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C2]]
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C2]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
+ ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ]]
+ ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SUB]], [[C3]]
+ ; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C2]]
+ ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]]
+ ; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32)
+ ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ1]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ADD1]], [[SUB1]]
+ ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[C]]
+ ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[C1]], [[C1]]
+ ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[AND3]]
+ ; MIPS32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ADD3]](s32), [[ADD5]](s32)
+ ; MIPS32: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]]
+ ; MIPS32: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]]
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR2]], [[XOR3]]
+ ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C1]]
+ ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C]]
+ ; MIPS32: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s32), [[MV]], [[MV1]]
+ ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT1]](s64)
+ ; MIPS32: $v0 = COPY [[UV]](s32)
+ ; MIPS32: $v1 = COPY [[UV1]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
%1:_(s32) = COPY $a0
%2:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
index 533cf5e13280622..88910e3e19fdfbe 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
@@ -31,31 +31,28 @@ body: |
; FP32-LABEL: name: f32toi64
; FP32: liveins: $f12
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP32-NEXT: $f12 = COPY [[COPY]](s32)
- ; FP32-NEXT: JAL &__fixsfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
- ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
- ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP32-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP32-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP32-NEXT: RetRA implicit $v0, implicit $v1
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $f12 = COPY [[COPY]](s32)
+ ; FP32: JAL &__fixsfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
+ ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
+ ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $v0 = COPY [[COPY1]](s32)
+ ; FP32: $v1 = COPY [[COPY2]](s32)
+ ; FP32: RetRA implicit $v0, implicit $v1
; FP64-LABEL: name: f32toi64
; FP64: liveins: $f12
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP64-NEXT: $f12 = COPY [[COPY]](s32)
- ; FP64-NEXT: JAL &__fixsfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
- ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
- ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP64-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP64-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP64-NEXT: RetRA implicit $v0, implicit $v1
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $f12 = COPY [[COPY]](s32)
+ ; FP64: JAL &__fixsfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
+ ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
+ ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $v0 = COPY [[COPY1]](s32)
+ ; FP64: $v1 = COPY [[COPY2]](s32)
+ ; FP64: RetRA implicit $v0, implicit $v1
%0:_(s32) = COPY $f12
%1:_(s64) = G_FPTOSI %0(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
@@ -74,19 +71,16 @@ body: |
; FP32-LABEL: name: f32toi32
; FP32: liveins: $f12
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP32-NEXT: $v0 = COPY [[FPTOSI]](s32)
- ; FP32-NEXT: RetRA implicit $v0
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; FP32: $v0 = COPY [[FPTOSI]](s32)
+ ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32toi32
; FP64: liveins: $f12
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP64-NEXT: $v0 = COPY [[FPTOSI]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; FP64: $v0 = COPY [[FPTOSI]](s32)
+ ; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
%1:_(s32) = G_FPTOSI %0(s32)
$v0 = COPY %1(s32)
@@ -103,25 +97,22 @@ body: |
; FP32-LABEL: name: f32toi16
; FP32: liveins: $f12
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; FP32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
- ; FP32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP32-NEXT: RetRA implicit $v0
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
+ ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; FP32: $v0 = COPY [[ASHR]](s32)
+ ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32toi16
; FP64: liveins: $f12
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; FP64-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
- ; FP64-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP64-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
+ ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; FP64: $v0 = COPY [[ASHR]](s32)
+ ; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
%1:_(s16) = G_FPTOSI %0(s32)
%2:_(s32) = G_SEXT %1(s16)
@@ -139,25 +130,22 @@ body: |
; FP32-LABEL: name: f32toi8
; FP32: liveins: $f12
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; FP32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
- ; FP32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP32-NEXT: RetRA implicit $v0
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
+ ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; FP32: $v0 = COPY [[ASHR]](s32)
+ ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32toi8
; FP64: liveins: $f12
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; FP64-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
- ; FP64-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP64-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
+ ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; FP64: $v0 = COPY [[ASHR]](s32)
+ ; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
%1:_(s8) = G_FPTOSI %0(s32)
%2:_(s32) = G_SEXT %1(s8)
@@ -175,31 +163,28 @@ body: |
; FP32-LABEL: name: f64toi64
; FP32: liveins: $d6
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP32-NEXT: $d6 = COPY [[COPY]](s64)
- ; FP32-NEXT: JAL &__fixdfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $v0, implicit-def $v1
- ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
- ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP32-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP32-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP32-NEXT: RetRA implicit $v0, implicit $v1
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $d6 = COPY [[COPY]](s64)
+ ; FP32: JAL &__fixdfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $v0, implicit-def $v1
+ ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
+ ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $v0 = COPY [[COPY1]](s32)
+ ; FP32: $v1 = COPY [[COPY2]](s32)
+ ; FP32: RetRA implicit $v0, implicit $v1
; FP64-LABEL: name: f64toi64
; FP64: liveins: $d6
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP64-NEXT: $d12_64 = COPY [[COPY]](s64)
- ; FP64-NEXT: JAL &__fixdfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit-def $v0, implicit-def $v1
- ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
- ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP64-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP64-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP64-NEXT: RetRA implicit $v0, implicit $v1
+ ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $d12_64 = COPY [[COPY]](s64)
+ ; FP64: JAL &__fixdfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit-def $v0, implicit-def $v1
+ ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
+ ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $v0 = COPY [[COPY1]](s32)
+ ; FP64: $v1 = COPY [[COPY2]](s32)
+ ; FP64: RetRA implicit $v0, implicit $v1
%0:_(s64) = COPY $d6
%1:_(s64) = G_FPTOSI %0(s64)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
@@ -218,19 +203,16 @@ body: |
; FP32-LABEL: name: f64toi32
; FP32: liveins: $d6
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP32-NEXT: $v0 = COPY [[FPTOSI]](s32)
- ; FP32-NEXT: RetRA implicit $v0
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; FP32: $v0 = COPY [[FPTOSI]](s32)
+ ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64toi32
; FP64: liveins: $d6
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP64-NEXT: $v0 = COPY [[FPTOSI]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; FP64: $v0 = COPY [[FPTOSI]](s32)
+ ; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
%1:_(s32) = G_FPTOSI %0(s64)
$v0 = COPY %1(s32)
@@ -247,25 +229,22 @@ body: |
; FP32-LABEL: name: f64toi16
; FP32: liveins: $d6
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; FP32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
- ; FP32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP32-NEXT: RetRA implicit $v0
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
+ ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; FP32: $v0 = COPY [[ASHR]](s32)
+ ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64toi16
; FP64: liveins: $d6
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; FP64-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
- ; FP64-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP64-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
+ ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; FP64: $v0 = COPY [[ASHR]](s32)
+ ; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
%1:_(s16) = G_FPTOSI %0(s64)
%2:_(s32) = G_SEXT %1(s16)
@@ -283,25 +262,22 @@ body: |
; FP32-LABEL: name: f64toi8
; FP32: liveins: $d6
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; FP32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
- ; FP32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP32-NEXT: RetRA implicit $v0
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
+ ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; FP32: $v0 = COPY [[ASHR]](s32)
+ ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64toi8
; FP64: liveins: $d6
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; FP64-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
- ; FP64-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; FP64-NEXT: $v0 = COPY [[ASHR]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
+ ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; FP64: $v0 = COPY [[ASHR]](s32)
+ ; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
%1:_(s8) = G_FPTOSI %0(s64)
%2:_(s32) = G_SEXT %1(s8)
@@ -319,31 +295,28 @@ body: |
; FP32-LABEL: name: f32tou64
; FP32: liveins: $f12
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP32-NEXT: $f12 = COPY [[COPY]](s32)
- ; FP32-NEXT: JAL &__fixunssfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
- ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
- ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP32-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP32-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP32-NEXT: RetRA implicit $v0, implicit $v1
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $f12 = COPY [[COPY]](s32)
+ ; FP32: JAL &__fixunssfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
+ ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
+ ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $v0 = COPY [[COPY1]](s32)
+ ; FP32: $v1 = COPY [[COPY2]](s32)
+ ; FP32: RetRA implicit $v0, implicit $v1
; FP64-LABEL: name: f32tou64
; FP64: liveins: $f12
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP64-NEXT: $f12 = COPY [[COPY]](s32)
- ; FP64-NEXT: JAL &__fixunssfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
- ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
- ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP64-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP64-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP64-NEXT: RetRA implicit $v0, implicit $v1
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $f12 = COPY [[COPY]](s32)
+ ; FP64: JAL &__fixunssfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $v0, implicit-def $v1
+ ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
+ ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $v0 = COPY [[COPY1]](s32)
+ ; FP64: $v1 = COPY [[COPY2]](s32)
+ ; FP64: RetRA implicit $v0, implicit $v1
%0:_(s32) = COPY $f12
%1:_(s64) = G_FPTOUI %0(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
@@ -362,33 +335,34 @@ body: |
; FP32-LABEL: name: f32tou32
; FP32: liveins: $f12
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
- ; FP32-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
- ; FP32-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
- ; FP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; FP32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
- ; FP32-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
- ; FP32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; FP32-NEXT: RetRA implicit $v0
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; FP32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
+ ; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
+ ; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
+ ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+ ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
+ ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
+ ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
+ ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
+ ; FP32: $v0 = COPY [[SELECT]](s32)
+ ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32tou32
; FP64: liveins: $f12
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
- ; FP64-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
- ; FP64-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
- ; FP64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; FP64-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
- ; FP64-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
- ; FP64-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP64-NEXT: $v0 = COPY [[SELECT]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; FP64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
+ ; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
+ ; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
+ ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+ ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
+ ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
+ ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
+ ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
+ ; FP64: $v0 = COPY [[SELECT]](s32)
+ ; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
%1:_(s32) = G_FPTOUI %0(s32)
$v0 = COPY %1(s32)
@@ -405,37 +379,38 @@ body: |
; FP32-LABEL: name: f32tou16
; FP32: liveins: $f12
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
- ; FP32-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
- ; FP32-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
- ; FP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; FP32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
- ; FP32-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
- ; FP32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; FP32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP32-NEXT: $v0 = COPY [[AND]](s32)
- ; FP32-NEXT: RetRA implicit $v0
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; FP32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
+ ; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
+ ; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
+ ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+ ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
+ ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
+ ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
+ ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
+ ; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
+ ; FP32: $v0 = COPY [[AND1]](s32)
+ ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32tou16
; FP64: liveins: $f12
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
- ; FP64-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
- ; FP64-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
- ; FP64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; FP64-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
- ; FP64-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
- ; FP64-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; FP64-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP64-NEXT: $v0 = COPY [[AND]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; FP64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
+ ; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
+ ; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
+ ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+ ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
+ ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
+ ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
+ ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
+ ; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
+ ; FP64: $v0 = COPY [[AND1]](s32)
+ ; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
%1:_(s16) = G_FPTOUI %0(s32)
%2:_(s32) = G_ZEXT %1(s16)
@@ -453,37 +428,38 @@ body: |
; FP32-LABEL: name: f32tou8
; FP32: liveins: $f12
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
- ; FP32-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
- ; FP32-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
- ; FP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; FP32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
- ; FP32-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
- ; FP32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; FP32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP32-NEXT: $v0 = COPY [[AND]](s32)
- ; FP32-NEXT: RetRA implicit $v0
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; FP32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
+ ; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
+ ; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
+ ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+ ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
+ ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
+ ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
+ ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
+ ; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
+ ; FP32: $v0 = COPY [[AND1]](s32)
+ ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32tou8
; FP64: liveins: $f12
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
- ; FP64-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
- ; FP64-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
- ; FP64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; FP64-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
- ; FP64-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
- ; FP64-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; FP64-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP64-NEXT: $v0 = COPY [[AND]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+ ; FP64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
+ ; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
+ ; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
+ ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+ ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
+ ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
+ ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
+ ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
+ ; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
+ ; FP64: $v0 = COPY [[AND1]](s32)
+ ; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
%1:_(s8) = G_FPTOUI %0(s32)
%2:_(s32) = G_ZEXT %1(s8)
@@ -501,31 +477,28 @@ body: |
; FP32-LABEL: name: f64tou64
; FP32: liveins: $d6
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP32-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP32-NEXT: $d6 = COPY [[COPY]](s64)
- ; FP32-NEXT: JAL &__fixunsdfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $v0, implicit-def $v1
- ; FP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
- ; FP32-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP32-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP32-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP32-NEXT: RetRA implicit $v0, implicit $v1
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $d6 = COPY [[COPY]](s64)
+ ; FP32: JAL &__fixunsdfdi, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $v0, implicit-def $v1
+ ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
+ ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $v0 = COPY [[COPY1]](s32)
+ ; FP32: $v1 = COPY [[COPY2]](s32)
+ ; FP32: RetRA implicit $v0, implicit $v1
; FP64-LABEL: name: f64tou64
; FP64: liveins: $d6
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP64-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
- ; FP64-NEXT: $d12_64 = COPY [[COPY]](s64)
- ; FP64-NEXT: JAL &__fixunsdfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit-def $v0, implicit-def $v1
- ; FP64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
- ; FP64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
- ; FP64-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
- ; FP64-NEXT: $v0 = COPY [[COPY1]](s32)
- ; FP64-NEXT: $v1 = COPY [[COPY2]](s32)
- ; FP64-NEXT: RetRA implicit $v0, implicit $v1
+ ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $d12_64 = COPY [[COPY]](s64)
+ ; FP64: JAL &__fixunsdfdi, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit-def $v0, implicit-def $v1
+ ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0
+ ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $v1
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $v0 = COPY [[COPY1]](s32)
+ ; FP64: $v1 = COPY [[COPY2]](s32)
+ ; FP64: RetRA implicit $v0, implicit $v1
%0:_(s64) = COPY $d6
%1:_(s64) = G_FPTOUI %0(s64)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
@@ -544,33 +517,34 @@ body: |
; FP32-LABEL: name: f64tou32
; FP32: liveins: $d6
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
- ; FP32-NEXT: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
- ; FP32-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
- ; FP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; FP32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
- ; FP32-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
- ; FP32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; FP32-NEXT: RetRA implicit $v0
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; FP32: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
+ ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
+ ; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
+ ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+ ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
+ ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
+ ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
+ ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
+ ; FP32: $v0 = COPY [[SELECT]](s32)
+ ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64tou32
; FP64: liveins: $d6
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
- ; FP64-NEXT: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
- ; FP64-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
- ; FP64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; FP64-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
- ; FP64-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
- ; FP64-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP64-NEXT: $v0 = COPY [[SELECT]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; FP64: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
+ ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
+ ; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
+ ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+ ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
+ ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
+ ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
+ ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
+ ; FP64: $v0 = COPY [[SELECT]](s32)
+ ; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
%1:_(s32) = G_FPTOUI %0(s64)
$v0 = COPY %1(s32)
@@ -587,37 +561,38 @@ body: |
; FP32-LABEL: name: f64tou16
; FP32: liveins: $d6
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
- ; FP32-NEXT: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
- ; FP32-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
- ; FP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; FP32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
- ; FP32-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
- ; FP32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; FP32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP32-NEXT: $v0 = COPY [[AND]](s32)
- ; FP32-NEXT: RetRA implicit $v0
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; FP32: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
+ ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
+ ; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
+ ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+ ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
+ ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
+ ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
+ ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
+ ; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
+ ; FP32: $v0 = COPY [[AND1]](s32)
+ ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64tou16
; FP64: liveins: $d6
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
- ; FP64-NEXT: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
- ; FP64-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
- ; FP64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; FP64-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
- ; FP64-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
- ; FP64-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; FP64-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP64-NEXT: $v0 = COPY [[AND]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; FP64: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
+ ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
+ ; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
+ ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+ ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
+ ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
+ ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
+ ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
+ ; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
+ ; FP64: $v0 = COPY [[AND1]](s32)
+ ; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
%1:_(s16) = G_FPTOUI %0(s64)
%2:_(s32) = G_ZEXT %1(s16)
@@ -635,37 +610,38 @@ body: |
; FP32-LABEL: name: f64tou8
; FP32: liveins: $d6
- ; FP32-NEXT: {{ $}}
- ; FP32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP32-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
- ; FP32-NEXT: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
- ; FP32-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
- ; FP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; FP32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
- ; FP32-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
- ; FP32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; FP32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP32-NEXT: $v0 = COPY [[AND]](s32)
- ; FP32-NEXT: RetRA implicit $v0
- ;
+ ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; FP32: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
+ ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
+ ; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
+ ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+ ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
+ ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
+ ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
+ ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
+ ; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
+ ; FP32: $v0 = COPY [[AND1]](s32)
+ ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64tou8
; FP64: liveins: $d6
- ; FP64-NEXT: {{ $}}
- ; FP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; FP64-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
- ; FP64-NEXT: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
- ; FP64-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
- ; FP64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; FP64-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
- ; FP64-NEXT: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
- ; FP64-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
- ; FP64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; FP64-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C2]]
- ; FP64-NEXT: $v0 = COPY [[AND]](s32)
- ; FP64-NEXT: RetRA implicit $v0
+ ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+ ; FP64: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
+ ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
+ ; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
+ ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+ ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
+ ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
+ ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
+ ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
+ ; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
+ ; FP64: $v0 = COPY [[AND1]](s32)
+ ; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
%1:_(s8) = G_FPTOUI %0(s64)
%2:_(s32) = G_ZEXT %1(s8)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
index 3c81427231a359b..c7a7a10b3f9218c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
@@ -28,12 +28,11 @@ body: |
; MIPS32-LABEL: name: ne_i32
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[ICMP]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
+ ; MIPS32: $v0 = COPY [[ICMP]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s1) = G_ICMP intpred(ne), %0(s32), %1
@@ -52,12 +51,11 @@ body: |
; MIPS32-LABEL: name: eq_ptr
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[ICMP]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
+ ; MIPS32: $v0 = COPY [[ICMP]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(s1) = G_ICMP intpred(eq), %0(p0), %1
@@ -76,15 +74,14 @@ body: |
; MIPS32-LABEL: name: ult_i8
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; MIPS32-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
- ; MIPS32-NEXT: $v0 = COPY [[ICMP]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
+ ; MIPS32: $v0 = COPY [[ICMP]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -105,17 +102,16 @@ body: |
; MIPS32-LABEL: name: slt_i16
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
- ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
- ; MIPS32-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
- ; MIPS32-NEXT: $v0 = COPY [[ICMP]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
+ ; MIPS32: $v0 = COPY [[ICMP]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -136,18 +132,17 @@ body: |
; MIPS32-LABEL: name: eq_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY2]]
- ; MIPS32-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY3]]
- ; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]]
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[ICMP]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY2]]
+ ; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY3]]
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]]
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C]]
+ ; MIPS32: $v0 = COPY [[ICMP]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -170,18 +165,17 @@ body: |
; MIPS32-LABEL: name: ne_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY2]]
- ; MIPS32-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY3]]
- ; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]]
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s32), [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[ICMP]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY2]]
+ ; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY3]]
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]]
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s32), [[C]]
+ ; MIPS32: $v0 = COPY [[ICMP]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -204,17 +198,18 @@ body: |
; MIPS32-LABEL: name: sgt_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -237,17 +232,18 @@ body: |
; MIPS32-LABEL: name: sge_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -270,17 +266,18 @@ body: |
; MIPS32-LABEL: name: slt_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -303,17 +300,18 @@ body: |
; MIPS32-LABEL: name: sle_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -336,17 +334,18 @@ body: |
; MIPS32-LABEL: name: ugt_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -369,17 +368,18 @@ body: |
; MIPS32-LABEL: name: uge_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -402,17 +402,18 @@ body: |
; MIPS32-LABEL: name: ult_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -435,17 +436,18 @@ body: |
; MIPS32-LABEL: name: ule_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
index 301fd2b9196e9c4..0c36cf6459b6dfb 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
@@ -70,84 +70,69 @@ jumpTable:
body: |
; MIPS32-LABEL: name: mod4_0_to_11
; MIPS32: bb.0.entry:
- ; MIPS32-NEXT: successors: %bb.6(0x40000000), %bb.1(0x40000000)
- ; MIPS32-NEXT: liveins: $a0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; MIPS32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; MIPS32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; MIPS32-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C6]]
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY2]]
- ; MIPS32-NEXT: G_BRCOND [[ICMP]](s32), %bb.6
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: bb.1.entry:
- ; MIPS32-NEXT: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0
- ; MIPS32-NEXT: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[COPY1]](s32)
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: bb.2.sw.bb:
- ; MIPS32-NEXT: $v0 = COPY [[C4]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: bb.3.sw.bb1:
- ; MIPS32-NEXT: $v0 = COPY [[C3]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: bb.4.sw.bb2:
- ; MIPS32-NEXT: $v0 = COPY [[C2]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: bb.5.sw.bb3:
- ; MIPS32-NEXT: $v0 = COPY [[C1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: bb.6.sw.default:
- ; MIPS32-NEXT: successors: %bb.7(0x80000000)
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: bb.7.sw.epilog:
- ; MIPS32-NEXT: successors: %bb.13(0x40000000), %bb.8(0x40000000)
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; MIPS32-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C7]]
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
- ; MIPS32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY3]](s32), [[COPY4]]
- ; MIPS32-NEXT: G_BRCOND [[ICMP1]](s32), %bb.13
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: bb.8.sw.epilog:
- ; MIPS32-NEXT: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[JUMP_TABLE1:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.1
- ; MIPS32-NEXT: G_BRJT [[JUMP_TABLE1]](p0), %jump-table.1, [[COPY3]](s32)
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: bb.9.sw.bb4:
- ; MIPS32-NEXT: $v0 = COPY [[C4]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: bb.10.sw.bb5:
- ; MIPS32-NEXT: $v0 = COPY [[C3]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: bb.11.sw.bb6:
- ; MIPS32-NEXT: $v0 = COPY [[C2]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: bb.12.sw.bb7:
- ; MIPS32-NEXT: $v0 = COPY [[C1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: bb.13.sw.default8:
- ; MIPS32-NEXT: $v0 = COPY [[C5]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: successors: %bb.6(0x40000000), %bb.1(0x40000000)
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C6]]
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY2]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; MIPS32: G_BRCOND [[AND]](s32), %bb.6
+ ; MIPS32: bb.1.entry:
+ ; MIPS32: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
+ ; MIPS32: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0
+ ; MIPS32: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[COPY1]](s32)
+ ; MIPS32: bb.2.sw.bb:
+ ; MIPS32: $v0 = COPY [[C4]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.3.sw.bb1:
+ ; MIPS32: $v0 = COPY [[C3]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.4.sw.bb2:
+ ; MIPS32: $v0 = COPY [[C2]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.5.sw.bb3:
+ ; MIPS32: $v0 = COPY [[C1]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.6.sw.default:
+ ; MIPS32: successors: %bb.7(0x80000000)
+ ; MIPS32: bb.7.sw.epilog:
+ ; MIPS32: successors: %bb.13(0x40000000), %bb.8(0x40000000)
+ ; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C7]]
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
+ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY3]](s32), [[COPY4]]
+ ; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C8]]
+ ; MIPS32: G_BRCOND [[AND1]](s32), %bb.13
+ ; MIPS32: bb.8.sw.epilog:
+ ; MIPS32: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
+ ; MIPS32: [[JUMP_TABLE1:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.1
+ ; MIPS32: G_BRJT [[JUMP_TABLE1]](p0), %jump-table.1, [[COPY3]](s32)
+ ; MIPS32: bb.9.sw.bb4:
+ ; MIPS32: $v0 = COPY [[C4]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.10.sw.bb5:
+ ; MIPS32: $v0 = COPY [[C3]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.11.sw.bb6:
+ ; MIPS32: $v0 = COPY [[C2]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.12.sw.bb7:
+ ; MIPS32: $v0 = COPY [[C1]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.13.sw.default8:
+ ; MIPS32: $v0 = COPY [[C5]](s32)
+ ; MIPS32: RetRA implicit $v0
bb.1.entry:
liveins: $a0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
index 7ad286b952cb120..e96d826638541bd 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
@@ -25,12 +25,11 @@ body: |
; MIPS32-LABEL: name: mul_i32
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[MUL]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
+ ; MIPS32: $v0 = COPY [[MUL]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_MUL %0, %1
@@ -48,15 +47,14 @@ body: |
; MIPS32-LABEL: name: mul_i8_sext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32)
- ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; MIPS32: $v0 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -77,14 +75,13 @@ body: |
; MIPS32-LABEL: name: mul_i8_zext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
+ ; MIPS32: $v0 = COPY [[AND]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -105,12 +102,11 @@ body: |
; MIPS32-LABEL: name: mul_i8_aext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[MUL]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[MUL]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -131,15 +127,14 @@ body: |
; MIPS32-LABEL: name: mul_i16_sext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32)
- ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; MIPS32: $v0 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -160,14 +155,13 @@ body: |
; MIPS32-LABEL: name: mul_i16_zext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
+ ; MIPS32: $v0 = COPY [[AND]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -188,12 +182,11 @@ body: |
; MIPS32-LABEL: name: mul_i16_aext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[MUL]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[MUL]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -214,20 +207,19 @@ body: |
; MIPS32-LABEL: name: mul_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY]]
- ; MIPS32-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY]]
- ; MIPS32-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY1]]
- ; MIPS32-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY]]
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
- ; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
- ; MIPS32-NEXT: $v0 = COPY [[MUL]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[ADD1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY]]
+ ; MIPS32: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY]]
+ ; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY1]]
+ ; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY]]
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
+ ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
+ ; MIPS32: $v0 = COPY [[MUL]](s32)
+ ; MIPS32: $v1 = COPY [[ADD1]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -256,66 +248,73 @@ body: |
; MIPS32-LABEL: name: mul_i128
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
- ; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; MIPS32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1)
- ; MIPS32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
- ; MIPS32-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.2, align 8)
- ; MIPS32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
- ; MIPS32-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.3)
- ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY]]
- ; MIPS32-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY]]
- ; MIPS32-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY1]]
- ; MIPS32-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY]]
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL2]]
- ; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
- ; MIPS32-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ICMP]], [[ICMP1]]
- ; MIPS32-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY]]
- ; MIPS32-NEXT: [[MUL4:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY1]]
- ; MIPS32-NEXT: [[MUL5:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY2]]
- ; MIPS32-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[LOAD1]], [[COPY]]
- ; MIPS32-NEXT: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY1]]
- ; MIPS32-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL3]], [[MUL4]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[MUL4]]
- ; MIPS32-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[MUL5]]
- ; MIPS32-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[MUL5]]
- ; MIPS32-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ICMP2]], [[ICMP3]]
- ; MIPS32-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[UMULH1]]
- ; MIPS32-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[UMULH1]]
- ; MIPS32-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[ICMP4]]
- ; MIPS32-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH2]]
- ; MIPS32-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD8]](s32), [[UMULH2]]
- ; MIPS32-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[ICMP5]]
- ; MIPS32-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD8]], [[ADD2]]
- ; MIPS32-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD10]](s32), [[ADD2]]
- ; MIPS32-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ICMP6]]
- ; MIPS32-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[LOAD3]], [[COPY]]
- ; MIPS32-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY1]]
- ; MIPS32-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY2]]
- ; MIPS32-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY3]]
- ; MIPS32-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[LOAD2]], [[COPY]]
- ; MIPS32-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[LOAD1]], [[COPY1]]
- ; MIPS32-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY2]]
- ; MIPS32-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[MUL6]], [[MUL7]]
- ; MIPS32-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ADD12]], [[MUL8]]
- ; MIPS32-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[MUL9]]
- ; MIPS32-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[UMULH3]]
- ; MIPS32-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[ADD15]], [[UMULH4]]
- ; MIPS32-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH5]]
- ; MIPS32-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[ADD11]]
- ; MIPS32-NEXT: $v0 = COPY [[MUL]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[ADD1]](s32)
- ; MIPS32-NEXT: $a0 = COPY [[ADD10]](s32)
- ; MIPS32-NEXT: $a1 = COPY [[ADD18]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
+ ; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1)
+ ; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.2, align 8)
+ ; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.3)
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY]]
+ ; MIPS32: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY]]
+ ; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY1]]
+ ; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY]]
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL2]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
+ ; MIPS32: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY]]
+ ; MIPS32: [[MUL4:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY1]]
+ ; MIPS32: [[MUL5:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY2]]
+ ; MIPS32: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[LOAD1]], [[COPY]]
+ ; MIPS32: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY1]]
+ ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL3]], [[MUL4]]
+ ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[MUL4]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C]]
+ ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[MUL5]]
+ ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[MUL5]]
+ ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[C]]
+ ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]
+ ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[UMULH1]]
+ ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[UMULH1]]
+ ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[C]]
+ ; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]]
+ ; MIPS32: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH2]]
+ ; MIPS32: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD8]](s32), [[UMULH2]]
+ ; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ICMP5]], [[C]]
+ ; MIPS32: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[AND5]]
+ ; MIPS32: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD8]], [[ADD2]]
+ ; MIPS32: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD10]](s32), [[ADD2]]
+ ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ICMP6]], [[C]]
+ ; MIPS32: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[AND6]]
+ ; MIPS32: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[LOAD3]], [[COPY]]
+ ; MIPS32: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY1]]
+ ; MIPS32: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY2]]
+ ; MIPS32: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY3]]
+ ; MIPS32: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[LOAD2]], [[COPY]]
+ ; MIPS32: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[LOAD1]], [[COPY1]]
+ ; MIPS32: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY2]]
+ ; MIPS32: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[MUL6]], [[MUL7]]
+ ; MIPS32: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ADD12]], [[MUL8]]
+ ; MIPS32: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[MUL9]]
+ ; MIPS32: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[UMULH3]]
+ ; MIPS32: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[ADD15]], [[UMULH4]]
+ ; MIPS32: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH5]]
+ ; MIPS32: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[ADD11]]
+ ; MIPS32: $v0 = COPY [[MUL]](s32)
+ ; MIPS32: $v1 = COPY [[ADD1]](s32)
+ ; MIPS32: $a0 = COPY [[ADD10]](s32)
+ ; MIPS32: $a1 = COPY [[ADD18]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%4:_(s32) = COPY $a2
@@ -349,35 +348,40 @@ body: |
; MIPS32-LABEL: name: umulh_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY]]
- ; MIPS32-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY1]]
- ; MIPS32-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY]]
- ; MIPS32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL]], [[MUL1]]
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL1]]
- ; MIPS32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
- ; MIPS32-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ICMP]], [[ICMP1]]
- ; MIPS32-NEXT: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY1]]
- ; MIPS32-NEXT: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY]]
- ; MIPS32-NEXT: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY1]]
- ; MIPS32-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL2]], [[UMULH1]]
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[UMULH1]]
- ; MIPS32-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[UMULH2]]
- ; MIPS32-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[UMULH2]]
- ; MIPS32-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ICMP2]], [[ICMP3]]
- ; MIPS32-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[ADD2]]
- ; MIPS32-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[ADD2]]
- ; MIPS32-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[ICMP4]]
- ; MIPS32-NEXT: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY1]]
- ; MIPS32-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UMULH3]], [[ADD7]]
- ; MIPS32-NEXT: $v0 = COPY [[ADD6]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[ADD8]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY]]
+ ; MIPS32: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY1]]
+ ; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY]]
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL]], [[MUL1]]
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL1]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
+ ; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY1]]
+ ; MIPS32: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY]]
+ ; MIPS32: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY1]]
+ ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL2]], [[UMULH1]]
+ ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[UMULH1]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C]]
+ ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[UMULH2]]
+ ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[UMULH2]]
+ ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[C]]
+ ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]
+ ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[ADD2]]
+ ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[ADD2]]
+ ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[C]]
+ ; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]]
+ ; MIPS32: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY1]]
+ ; MIPS32: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UMULH3]], [[ADD7]]
+ ; MIPS32: $v0 = COPY [[ADD6]](s32)
+ ; MIPS32: $v1 = COPY [[ADD8]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
@@ -401,20 +405,20 @@ body: |
; MIPS32-LABEL: name: umul_with_overflow
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
- ; MIPS32-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[COPY1]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
- ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
- ; MIPS32-NEXT: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store (s8) into %ir.pcarry_flag)
- ; MIPS32-NEXT: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store (s32) into %ir.pmul)
- ; MIPS32-NEXT: RetRA
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
+ ; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[COPY1]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C1]]
+ ; MIPS32: G_STORE [[AND1]](s32), [[COPY3]](p0) :: (store (s8) into %ir.pcarry_flag)
+ ; MIPS32: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store (s32) into %ir.pmul)
+ ; MIPS32: RetRA
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(p0) = COPY $a2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
index a0bf22dbffd4ba8..60b16cc1f35252e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
@@ -22,15 +22,14 @@ body: |
; MIPS32-LABEL: name: select_i8
; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $v0
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%4:_(s32) = COPY $a1
@@ -53,15 +52,14 @@ body: |
; MIPS32-LABEL: name: select_i16
; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $v0
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%4:_(s32) = COPY $a1
@@ -84,15 +82,14 @@ body: |
; MIPS32-LABEL: name: select_i32
; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $v0
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%1:_(s32) = COPY $a1
@@ -112,15 +109,14 @@ body: |
; MIPS32-LABEL: name: select_ptr
; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](p0)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
+ ; MIPS32: $v0 = COPY [[SELECT]](p0)
+ ; MIPS32: RetRA implicit $v0
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%1:_(p0) = COPY $a1
@@ -140,17 +136,17 @@ body: |
; MIPS32-LABEL: name: select_with_negation
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
- ; MIPS32-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP]], [[C]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[XOR]](s32), [[COPY2]], [[COPY3]]
- ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY2]], [[COPY3]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = COPY $a2
@@ -176,23 +172,22 @@ body: |
; MIPS32-LABEL: name: select_i64
; MIPS32: liveins: $a0, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
- ; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
- ; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; MIPS32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1)
- ; MIPS32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[MV]], [[MV1]]
- ; MIPS32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT]](s64)
- ; MIPS32-NEXT: $v0 = COPY [[UV]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[UV1]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
+ ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
+ ; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1)
+ ; MIPS32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[MV]], [[MV1]]
+ ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT]](s64)
+ ; MIPS32: $v0 = COPY [[UV]](s32)
+ ; MIPS32: $v1 = COPY [[UV1]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%4:_(s32) = COPY $a2
@@ -220,15 +215,14 @@ body: |
; MIPS32-LABEL: name: select_float
; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
- ; MIPS32-NEXT: $f0 = COPY [[SELECT]](s32)
- ; MIPS32-NEXT: RetRA implicit $f0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
+ ; MIPS32: $f0 = COPY [[SELECT]](s32)
+ ; MIPS32: RetRA implicit $f0
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
%1:_(s32) = COPY $a1
@@ -250,16 +244,15 @@ body: |
; MIPS32-LABEL: name: select_double
; MIPS32: liveins: $d6, $d7
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
- ; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
- ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
- ; MIPS32-NEXT: $d0 = COPY [[SELECT]](s64)
- ; MIPS32-NEXT: RetRA implicit $d0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
+ ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
+ ; MIPS32: $d0 = COPY [[SELECT]](s64)
+ ; MIPS32: RetRA implicit $d0
%0:_(s64) = COPY $d6
%1:_(s64) = COPY $d7
%4:_(p0) = G_FRAME_INDEX %fixed-stack.0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
index db62b72be87d8e6..0230eb2c07e8f6e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
@@ -23,12 +23,11 @@ body: |
; MIPS32-LABEL: name: sub_i32
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
- ; MIPS32-NEXT: $v0 = COPY [[SUB]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
+ ; MIPS32: $v0 = COPY [[SUB]](s32)
+ ; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
%2:_(s32) = G_SUB %0, %1
@@ -46,15 +45,14 @@ body: |
; MIPS32-LABEL: name: sub_i8_sext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C]](s32)
- ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; MIPS32: $v0 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -75,14 +73,13 @@ body: |
; MIPS32-LABEL: name: sub_i8_zext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
+ ; MIPS32: $v0 = COPY [[AND]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -103,12 +100,11 @@ body: |
; MIPS32-LABEL: name: sub_i8_aext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[SUB]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[SUB]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -129,15 +125,14 @@ body: |
; MIPS32-LABEL: name: sub_i16_sext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C]](s32)
- ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32-NEXT: $v0 = COPY [[ASHR]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; MIPS32: $v0 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -158,14 +153,13 @@ body: |
; MIPS32-LABEL: name: sub_i16_zext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
- ; MIPS32-NEXT: $v0 = COPY [[AND]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
+ ; MIPS32: $v0 = COPY [[AND]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -186,12 +180,11 @@ body: |
; MIPS32-LABEL: name: sub_i16_aext
; MIPS32: liveins: $a0, $a1
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
- ; MIPS32-NEXT: $v0 = COPY [[SUB]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[SUB]](s32)
+ ; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $a1
@@ -212,18 +205,19 @@ body: |
; MIPS32-LABEL: name: sub_i64
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[COPY1]]
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY3]](s32), [[COPY1]]
- ; MIPS32-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]]
- ; MIPS32-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
- ; MIPS32-NEXT: $v0 = COPY [[SUB2]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[SUB]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[COPY1]]
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY3]](s32), [[COPY1]]
+ ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
+ ; MIPS32: $v0 = COPY [[SUB2]](s32)
+ ; MIPS32: $v1 = COPY [[SUB]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %3(s32), %2(s32)
@@ -252,44 +246,44 @@ body: |
; MIPS32-LABEL: name: sub_i128
; MIPS32: liveins: $a0, $a1, $a2, $a3
- ; MIPS32-NEXT: {{ $}}
- ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
- ; MIPS32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
- ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
- ; MIPS32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
- ; MIPS32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1)
- ; MIPS32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
- ; MIPS32-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.2, align 8)
- ; MIPS32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
- ; MIPS32-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.3)
- ; MIPS32-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[LOAD]], [[COPY]]
- ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD]](s32), [[COPY]]
- ; MIPS32-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LOAD1]], [[COPY1]]
- ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[SUB1]](s32), [[LOAD1]]
- ; MIPS32-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
- ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C]]
- ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[ICMP]]
- ; MIPS32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[AND]]
- ; MIPS32-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LOAD2]], [[COPY2]]
- ; MIPS32-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[SUB3]](s32), [[LOAD2]]
- ; MIPS32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C1]]
- ; MIPS32-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[AND1]]
- ; MIPS32-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB3]](s32), [[C]]
- ; MIPS32-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[OR]]
- ; MIPS32-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ICMP3]], [[AND2]]
- ; MIPS32-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LOAD3]], [[COPY3]]
- ; MIPS32-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C1]]
- ; MIPS32-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND3]]
- ; MIPS32-NEXT: $v0 = COPY [[SUB]](s32)
- ; MIPS32-NEXT: $v1 = COPY [[SUB2]](s32)
- ; MIPS32-NEXT: $a0 = COPY [[SUB4]](s32)
- ; MIPS32-NEXT: $a1 = COPY [[SUB6]](s32)
- ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+ ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
+ ; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1)
+ ; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+ ; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load (s32) from %fixed-stack.2, align 8)
+ ; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+ ; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load (s32) from %fixed-stack.3)
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[LOAD]], [[COPY]]
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD]](s32), [[COPY]]
+ ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LOAD1]], [[COPY1]]
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[SUB1]](s32), [[LOAD1]]
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[ICMP]]
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[AND1]]
+ ; MIPS32: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LOAD2]], [[COPY2]]
+ ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[SUB3]](s32), [[LOAD2]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C]]
+ ; MIPS32: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[AND2]]
+ ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB3]](s32), [[C1]]
+ ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[OR]]
+ ; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ICMP3]], [[AND3]]
+ ; MIPS32: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LOAD3]], [[COPY3]]
+ ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C]]
+ ; MIPS32: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND4]]
+ ; MIPS32: $v0 = COPY [[SUB]](s32)
+ ; MIPS32: $v1 = COPY [[SUB2]](s32)
+ ; MIPS32: $a0 = COPY [[SUB4]](s32)
+ ; MIPS32: $a1 = COPY [[SUB6]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%4:_(s32) = COPY $a2
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
index f76d18b53e59bb8..38d3f00f62db215 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
@@ -89,6 +89,7 @@ define i64 @add_i64(i64 %a, i64 %b) {
; MIPS32-NEXT: addu $2, $6, $4
; MIPS32-NEXT: sltu $3, $2, $4
; MIPS32-NEXT: addu $1, $7, $5
+; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: addu $3, $1, $3
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -114,7 +115,8 @@ define i128 @add_i128(i128 %a, i128 %b) {
; MIPS32-NEXT: sltu $9, $2, $8
; MIPS32-NEXT: addu $3, $4, $3
; MIPS32-NEXT: sltu $4, $3, $4
-; MIPS32-NEXT: addu $3, $3, $9
+; MIPS32-NEXT: andi $8, $9, 1
+; MIPS32-NEXT: addu $3, $3, $8
; MIPS32-NEXT: sltiu $8, $3, 1
; MIPS32-NEXT: and $8, $8, $9
; MIPS32-NEXT: or $8, $4, $8
@@ -176,6 +178,7 @@ define void @uadd_with_overflow(i32 %lhs, i32 %rhs, ptr %padd, ptr %pcarry_flag)
; MIPS32-NEXT: addu $1, $4, $5
; MIPS32-NEXT: sltu $2, $1, $5
; MIPS32-NEXT: andi $2, $2, 1
+; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: sb $2, 0($7)
; MIPS32-NEXT: sw $1, 0($6)
; MIPS32-NEXT: jr $ra
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
index e572551ef4b2a01..26816482306a9ab 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
@@ -306,7 +306,8 @@ entry:
define i16 @shl_i16(i16 %a) {
; MIPS32-LABEL: shl_i16:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: sll $2, $4, 2
+; MIPS32-NEXT: ori $1, $zero, 2
+; MIPS32-NEXT: sllv $2, $4, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -317,9 +318,10 @@ entry:
define i8 @ashr_i8(i8 %a) {
; MIPS32-LABEL: ashr_i8:
; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: ori $2, $zero, 2
; MIPS32-NEXT: sll $1, $4, 24
; MIPS32-NEXT: sra $1, $1, 24
-; MIPS32-NEXT: sra $2, $1, 2
+; MIPS32-NEXT: srav $2, $1, $2
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -330,8 +332,9 @@ entry:
define i16 @lshr_i16(i16 %a) {
; MIPS32-LABEL: lshr_i16:
; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: ori $2, $zero, 2
; MIPS32-NEXT: andi $1, $4, 65535
-; MIPS32-NEXT: srl $2, $1, 2
+; MIPS32-NEXT: srlv $2, $1, $2
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -343,19 +346,24 @@ define i64 @shl_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: shl_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $3, $4
-; MIPS32-NEXT: ori $4, $zero, 32
-; MIPS32-NEXT: subu $8, $6, $4
-; MIPS32-NEXT: subu $1, $4, $6
+; MIPS32-NEXT: move $9, $6
+; MIPS32-NEXT: ori $1, $zero, 32
+; MIPS32-NEXT: subu $8, $9, $1
+; MIPS32-NEXT: subu $4, $1, $9
; MIPS32-NEXT: ori $2, $zero, 0
-; MIPS32-NEXT: sltu $4, $6, $4
-; MIPS32-NEXT: sllv $7, $3, $6
-; MIPS32-NEXT: srlv $1, $3, $1
-; MIPS32-NEXT: sllv $9, $5, $6
-; MIPS32-NEXT: or $1, $1, $9
+; MIPS32-NEXT: sltu $6, $9, $1
+; MIPS32-NEXT: sltiu $1, $9, 1
+; MIPS32-NEXT: sllv $7, $3, $9
+; MIPS32-NEXT: srlv $4, $3, $4
+; MIPS32-NEXT: sllv $9, $5, $9
+; MIPS32-NEXT: or $4, $4, $9
; MIPS32-NEXT: sllv $3, $3, $8
-; MIPS32-NEXT: movn $2, $7, $4
-; MIPS32-NEXT: movn $3, $1, $4
-; MIPS32-NEXT: movz $3, $5, $6
+; MIPS32-NEXT: andi $8, $6, 1
+; MIPS32-NEXT: movn $2, $7, $8
+; MIPS32-NEXT: andi $6, $6, 1
+; MIPS32-NEXT: movn $3, $4, $6
+; MIPS32-NEXT: andi $1, $1, 1
+; MIPS32-NEXT: movn $3, $5, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -371,18 +379,23 @@ define i64 @ashl_i64(i64 %a, i64 %b) {
; MIPS32-NEXT: sw $4, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $2, $5
; MIPS32-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: move $3, $6
; MIPS32-NEXT: ori $1, $zero, 32
-; MIPS32-NEXT: subu $8, $6, $1
-; MIPS32-NEXT: subu $7, $1, $6
-; MIPS32-NEXT: sltu $4, $6, $1
-; MIPS32-NEXT: srav $1, $2, $6
-; MIPS32-NEXT: srlv $3, $5, $6
+; MIPS32-NEXT: subu $8, $3, $1
+; MIPS32-NEXT: subu $7, $1, $3
+; MIPS32-NEXT: sltu $4, $3, $1
+; MIPS32-NEXT: sltiu $6, $3, 1
+; MIPS32-NEXT: srav $1, $2, $3
+; MIPS32-NEXT: srlv $3, $5, $3
; MIPS32-NEXT: sllv $7, $2, $7
; MIPS32-NEXT: or $7, $3, $7
; MIPS32-NEXT: sra $3, $2, 31
; MIPS32-NEXT: srav $2, $2, $8
-; MIPS32-NEXT: movn $2, $7, $4
-; MIPS32-NEXT: movz $2, $5, $6
+; MIPS32-NEXT: andi $8, $4, 1
+; MIPS32-NEXT: movn $2, $7, $8
+; MIPS32-NEXT: andi $6, $6, 1
+; MIPS32-NEXT: movn $2, $5, $6
+; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: movn $3, $1, $4
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
@@ -400,18 +413,23 @@ define i64 @lshr_i64(i64 %a, i64 %b) {
; MIPS32-NEXT: sw $4, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $2, $5
; MIPS32-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: move $7, $6
; MIPS32-NEXT: ori $1, $zero, 32
-; MIPS32-NEXT: subu $8, $6, $1
-; MIPS32-NEXT: subu $9, $1, $6
+; MIPS32-NEXT: subu $8, $7, $1
+; MIPS32-NEXT: subu $9, $1, $7
; MIPS32-NEXT: ori $3, $zero, 0
-; MIPS32-NEXT: sltu $4, $6, $1
-; MIPS32-NEXT: srlv $1, $2, $6
-; MIPS32-NEXT: srlv $7, $5, $6
+; MIPS32-NEXT: sltu $4, $7, $1
+; MIPS32-NEXT: sltiu $6, $7, 1
+; MIPS32-NEXT: srlv $1, $2, $7
+; MIPS32-NEXT: srlv $7, $5, $7
; MIPS32-NEXT: sllv $9, $2, $9
; MIPS32-NEXT: or $7, $7, $9
; MIPS32-NEXT: srlv $2, $2, $8
-; MIPS32-NEXT: movn $2, $7, $4
-; MIPS32-NEXT: movz $2, $5, $6
+; MIPS32-NEXT: andi $8, $4, 1
+; MIPS32-NEXT: movn $2, $7, $8
+; MIPS32-NEXT: andi $6, $6, 1
+; MIPS32-NEXT: movn $2, $5, $6
+; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: movn $3, $1, $4
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctlz.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctlz.ll
index 542a585b50e3dc3..65fce9d4f5d5911 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctlz.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctlz.ll
@@ -17,11 +17,14 @@ declare i32 @llvm.ctlz.i32(i32, i1 immarg)
define i64 @ctlz_i64(i64 %a) {
; MIPS32-LABEL: ctlz_i64:
; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: move $1, $4
; MIPS32-NEXT: ori $3, $zero, 0
-; MIPS32-NEXT: clz $1, $4
+; MIPS32-NEXT: sltiu $4, $5, 1
+; MIPS32-NEXT: clz $1, $1
; MIPS32-NEXT: addiu $1, $1, 32
; MIPS32-NEXT: clz $2, $5
-; MIPS32-NEXT: movz $2, $1, $5
+; MIPS32-NEXT: andi $4, $4, 1
+; MIPS32-NEXT: movn $2, $1, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/cttz.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/cttz.ll
index 6bc4c625d4010f2..44a2e619f715691 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/cttz.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/cttz.ll
@@ -21,7 +21,9 @@ declare i32 @llvm.cttz.i32(i32, i1 immarg)
define i64 @cttz_i64(i64 %a) {
; MIPS32-LABEL: cttz_i64:
; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: move $6, $4
; MIPS32-NEXT: ori $3, $zero, 0
+; MIPS32-NEXT: sltiu $4, $6, 1
; MIPS32-NEXT: not $1, $5
; MIPS32-NEXT: addiu $2, $5, -1
; MIPS32-NEXT: and $1, $1, $2
@@ -29,12 +31,13 @@ define i64 @cttz_i64(i64 %a) {
; MIPS32-NEXT: clz $1, $1
; MIPS32-NEXT: subu $1, $2, $1
; MIPS32-NEXT: addiu $1, $1, 32
-; MIPS32-NEXT: not $5, $4
-; MIPS32-NEXT: addiu $6, $4, -1
+; MIPS32-NEXT: not $5, $6
+; MIPS32-NEXT: addiu $6, $6, -1
; MIPS32-NEXT: and $5, $5, $6
; MIPS32-NEXT: clz $5, $5
; MIPS32-NEXT: subu $2, $2, $5
-; MIPS32-NEXT: movz $2, $1, $4
+; MIPS32-NEXT: andi $4, $4, 1
+; MIPS32-NEXT: movn $2, $1, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -55,7 +58,9 @@ define i32 @ffs_i32_expansion(i32 %a) {
; MIPS32-NEXT: clz $3, $3
; MIPS32-NEXT: subu $2, $2, $3
; MIPS32-NEXT: addiu $2, $2, 1
-; MIPS32-NEXT: movz $2, $1, $4
+; MIPS32-NEXT: sltiu $3, $4, 1
+; MIPS32-NEXT: andi $3, $3, 1
+; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -71,6 +76,7 @@ define i64 @ffs_i64_expansion(i64 %a) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $3, $zero, 1
; MIPS32-NEXT: ori $1, $zero, 0
+; MIPS32-NEXT: sltiu $7, $4, 1
; MIPS32-NEXT: not $2, $5
; MIPS32-NEXT: addiu $6, $5, -1
; MIPS32-NEXT: and $6, $2, $6
@@ -78,21 +84,25 @@ define i64 @ffs_i64_expansion(i64 %a) {
; MIPS32-NEXT: clz $6, $6
; MIPS32-NEXT: subu $6, $2, $6
; MIPS32-NEXT: addiu $6, $6, 32
-; MIPS32-NEXT: not $7, $4
-; MIPS32-NEXT: addiu $8, $4, -1
-; MIPS32-NEXT: and $7, $7, $8
-; MIPS32-NEXT: clz $7, $7
-; MIPS32-NEXT: subu $2, $2, $7
-; MIPS32-NEXT: movz $2, $6, $4
+; MIPS32-NEXT: not $8, $4
+; MIPS32-NEXT: addiu $9, $4, -1
+; MIPS32-NEXT: and $8, $8, $9
+; MIPS32-NEXT: clz $8, $8
+; MIPS32-NEXT: subu $2, $2, $8
+; MIPS32-NEXT: andi $7, $7, 1
+; MIPS32-NEXT: movn $2, $6, $7
; MIPS32-NEXT: addiu $2, $2, 1
; MIPS32-NEXT: sltu $6, $2, $3
; MIPS32-NEXT: addiu $3, $1, 0
+; MIPS32-NEXT: andi $6, $6, 1
; MIPS32-NEXT: addu $3, $3, $6
; MIPS32-NEXT: xori $4, $4, 0
; MIPS32-NEXT: xori $5, $5, 0
; MIPS32-NEXT: or $4, $4, $5
-; MIPS32-NEXT: movz $2, $1, $4
-; MIPS32-NEXT: movz $3, $1, $4
+; MIPS32-NEXT: sltiu $4, $4, 1
+; MIPS32-NEXT: andi $4, $4, 1
+; MIPS32-NEXT: movn $2, $1, $4
+; MIPS32-NEXT: movn $3, $1, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll
index 823e0ecb6e9417b..e9cc0b933f71970 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll
@@ -151,6 +151,7 @@ define i32 @f32tou32(float %a) {
; MIPS32-NEXT: addiu $3, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f0
; MIPS32-NEXT: movf $3, $zero, $fcc0
+; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -174,6 +175,7 @@ define zeroext i16 @f32tou16(float %a) {
; MIPS32-NEXT: addiu $3, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f0
; MIPS32-NEXT: movf $3, $zero, $fcc0
+; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $1, $2, $3
; MIPS32-NEXT: andi $2, $1, 65535
; MIPS32-NEXT: jr $ra
@@ -198,6 +200,7 @@ define zeroext i8 @f32tou8(float %a) {
; MIPS32-NEXT: addiu $3, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f0
; MIPS32-NEXT: movf $3, $zero, $fcc0
+; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $1, $2, $3
; MIPS32-NEXT: andi $2, $1, 255
; MIPS32-NEXT: jr $ra
@@ -242,6 +245,7 @@ define i32 @f64tou32(double %a) {
; FP32-NEXT: addiu $3, $zero, 1
; FP32-NEXT: c.ult.d $f12, $f0
; FP32-NEXT: movf $3, $zero, $fcc0
+; FP32-NEXT: andi $3, $3, 1
; FP32-NEXT: movn $2, $1, $3
; FP32-NEXT: jr $ra
; FP32-NEXT: nop
@@ -262,6 +266,7 @@ define i32 @f64tou32(double %a) {
; FP64-NEXT: addiu $3, $zero, 1
; FP64-NEXT: c.ult.d $f12, $f0
; FP64-NEXT: movf $3, $zero, $fcc0
+; FP64-NEXT: andi $3, $3, 1
; FP64-NEXT: movn $2, $1, $3
; FP64-NEXT: jr $ra
; FP64-NEXT: nop
@@ -287,6 +292,7 @@ define zeroext i16 @f64tou16(double %a) {
; FP32-NEXT: addiu $3, $zero, 1
; FP32-NEXT: c.ult.d $f12, $f0
; FP32-NEXT: movf $3, $zero, $fcc0
+; FP32-NEXT: andi $3, $3, 1
; FP32-NEXT: movn $1, $2, $3
; FP32-NEXT: andi $2, $1, 65535
; FP32-NEXT: jr $ra
@@ -308,6 +314,7 @@ define zeroext i16 @f64tou16(double %a) {
; FP64-NEXT: addiu $3, $zero, 1
; FP64-NEXT: c.ult.d $f12, $f0
; FP64-NEXT: movf $3, $zero, $fcc0
+; FP64-NEXT: andi $3, $3, 1
; FP64-NEXT: movn $1, $2, $3
; FP64-NEXT: andi $2, $1, 65535
; FP64-NEXT: jr $ra
@@ -334,6 +341,7 @@ define zeroext i8 @f64tou8(double %a) {
; FP32-NEXT: addiu $3, $zero, 1
; FP32-NEXT: c.ult.d $f12, $f0
; FP32-NEXT: movf $3, $zero, $fcc0
+; FP32-NEXT: andi $3, $3, 1
; FP32-NEXT: movn $1, $2, $3
; FP32-NEXT: andi $2, $1, 255
; FP32-NEXT: jr $ra
@@ -355,6 +363,7 @@ define zeroext i8 @f64tou8(double %a) {
; FP64-NEXT: addiu $3, $zero, 1
; FP64-NEXT: c.ult.d $f12, $f0
; FP64-NEXT: movf $3, $zero, $fcc0
+; FP64-NEXT: andi $3, $3, 1
; FP64-NEXT: movn $1, $2, $3
; FP64-NEXT: andi $2, $1, 255
; FP64-NEXT: jr $ra
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
index 49f2a78683b0a5e..ab474e1f8e72231 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
@@ -189,9 +189,11 @@ define i1 @sgt_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: sgt_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $2, $7, $5
+; MIPS32-NEXT: xor $1, $5, $7
+; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $6, $4
-; MIPS32-NEXT: xor $3, $5, $7
-; MIPS32-NEXT: movz $2, $1, $3
+; MIPS32-NEXT: andi $3, $3, 1
+; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -204,10 +206,12 @@ define i1 @sge_i64(i64 %a, i64 %b) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $1, $5, $7
; MIPS32-NEXT: xori $2, $1, 1
+; MIPS32-NEXT: xor $1, $5, $7
+; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $4, $6
; MIPS32-NEXT: xori $1, $1, 1
-; MIPS32-NEXT: xor $3, $5, $7
-; MIPS32-NEXT: movz $2, $1, $3
+; MIPS32-NEXT: andi $3, $3, 1
+; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -219,9 +223,11 @@ define i1 @slt_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: slt_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $2, $5, $7
+; MIPS32-NEXT: xor $1, $5, $7
+; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $4, $6
-; MIPS32-NEXT: xor $3, $5, $7
-; MIPS32-NEXT: movz $2, $1, $3
+; MIPS32-NEXT: andi $3, $3, 1
+; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -234,10 +240,12 @@ define i1 @sle_i64(i64 %a, i64 %b) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $1, $7, $5
; MIPS32-NEXT: xori $2, $1, 1
+; MIPS32-NEXT: xor $1, $5, $7
+; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $6, $4
; MIPS32-NEXT: xori $1, $1, 1
-; MIPS32-NEXT: xor $3, $5, $7
-; MIPS32-NEXT: movz $2, $1, $3
+; MIPS32-NEXT: andi $3, $3, 1
+; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -249,9 +257,11 @@ define i1 @ugt_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: ugt_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $2, $7, $5
+; MIPS32-NEXT: xor $1, $5, $7
+; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $6, $4
-; MIPS32-NEXT: xor $3, $5, $7
-; MIPS32-NEXT: movz $2, $1, $3
+; MIPS32-NEXT: andi $3, $3, 1
+; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -264,10 +274,12 @@ define i1 @uge_i64(i64 %a, i64 %b) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $1, $5, $7
; MIPS32-NEXT: xori $2, $1, 1
+; MIPS32-NEXT: xor $1, $5, $7
+; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $4, $6
; MIPS32-NEXT: xori $1, $1, 1
-; MIPS32-NEXT: xor $3, $5, $7
-; MIPS32-NEXT: movz $2, $1, $3
+; MIPS32-NEXT: andi $3, $3, 1
+; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -279,9 +291,11 @@ define i1 @ult_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: ult_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $2, $5, $7
+; MIPS32-NEXT: xor $1, $5, $7
+; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $4, $6
-; MIPS32-NEXT: xor $3, $5, $7
-; MIPS32-NEXT: movz $2, $1, $3
+; MIPS32-NEXT: andi $3, $3, 1
+; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -294,10 +308,12 @@ define i1 @ule_i64(i64 %a, i64 %b) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $1, $7, $5
; MIPS32-NEXT: xori $2, $1, 1
+; MIPS32-NEXT: xor $1, $5, $7
+; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $6, $4
; MIPS32-NEXT: xori $1, $1, 1
-; MIPS32-NEXT: xor $3, $5, $7
-; MIPS32-NEXT: movz $2, $1, $3
+; MIPS32-NEXT: andi $3, $3, 1
+; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
index 4c10fedaa4a8849..30a1b514ddafe54 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
@@ -23,6 +23,7 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32-NEXT: subu $2, $4, $2
; MIPS32-NEXT: sw $2, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sltu $1, $1, $2
+; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB0_6
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_1: # %entry
@@ -63,6 +64,7 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32-NEXT: subu $2, $2, $3
; MIPS32-NEXT: sw $2, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sltu $1, $1, $2
+; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB0_13
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_8: # %sw.epilog
@@ -123,6 +125,7 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32_PIC-NEXT: subu $2, $4, $2
; MIPS32_PIC-NEXT: sw $2, 36($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sltu $1, $1, $2
+; MIPS32_PIC-NEXT: andi $1, $1, 1
; MIPS32_PIC-NEXT: bnez $1, $BB0_6
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_1: # %entry
@@ -165,6 +168,7 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32_PIC-NEXT: subu $2, $2, $3
; MIPS32_PIC-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sltu $1, $1, $2
+; MIPS32_PIC-NEXT: andi $1, $1, 1
; MIPS32_PIC-NEXT: bnez $1, $BB0_13
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_8: # %sw.epilog
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
index c8c66fabf202bf5..44266f84379e10e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
@@ -123,8 +123,10 @@ define i128 @mul_i128(i128 %a, i128 %b) {
; MIPS32-NEXT: mfhi $5
; MIPS32-NEXT: addu $3, $3, $4
; MIPS32-NEXT: sltu $4, $3, $4
+; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: addu $3, $3, $5
; MIPS32-NEXT: sltu $5, $3, $5
+; MIPS32-NEXT: andi $5, $5, 1
; MIPS32-NEXT: addu $10, $4, $5
; MIPS32-NEXT: mul $4, $8, $14
; MIPS32-NEXT: mul $5, $7, $13
@@ -135,17 +137,22 @@ define i128 @mul_i128(i128 %a, i128 %b) {
; MIPS32-NEXT: mfhi $11
; MIPS32-NEXT: addu $4, $4, $5
; MIPS32-NEXT: sltu $5, $4, $5
+; MIPS32-NEXT: andi $5, $5, 1
; MIPS32-NEXT: addu $4, $4, $24
; MIPS32-NEXT: sltu $24, $4, $24
+; MIPS32-NEXT: andi $24, $24, 1
; MIPS32-NEXT: addu $5, $5, $24
; MIPS32-NEXT: addu $4, $4, $15
; MIPS32-NEXT: sltu $15, $4, $15
+; MIPS32-NEXT: andi $15, $15, 1
; MIPS32-NEXT: addu $5, $5, $15
; MIPS32-NEXT: addu $4, $4, $11
; MIPS32-NEXT: sltu $11, $4, $11
+; MIPS32-NEXT: andi $11, $11, 1
; MIPS32-NEXT: addu $5, $5, $11
; MIPS32-NEXT: addu $4, $4, $10
; MIPS32-NEXT: sltu $10, $4, $10
+; MIPS32-NEXT: andi $10, $10, 1
; MIPS32-NEXT: addu $5, $5, $10
; MIPS32-NEXT: mul $1, $1, $14
; MIPS32-NEXT: mul $11, $8, $13
@@ -180,6 +187,7 @@ define void @umul_with_overflow(i32 %lhs, i32 %rhs, ptr %pmul, ptr %pcarry_flag)
; MIPS32-NEXT: mul $1, $4, $5
; MIPS32-NEXT: sltu $2, $zero, $2
; MIPS32-NEXT: andi $2, $2, 1
+; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: sb $2, 0($7)
; MIPS32-NEXT: sw $1, 0($6)
; MIPS32-NEXT: jr $ra
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
index 7aba3bc18f63f31..30076a5ec7187a8 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
@@ -59,6 +59,7 @@ define i32 @select_with_negation(i32 %a, i32 %b, i32 %x, i32 %y) {
; MIPS32-NEXT: move $2, $7
; MIPS32-NEXT: slt $1, $4, $5
; MIPS32-NEXT: xori $1, $1, 1
+; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: movn $2, $6, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
index b7f42c2912132a2..07d094604684d9b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
@@ -173,9 +173,10 @@ entry:
define float @u16tof32(i16 zeroext %a) {
; FP32-LABEL: u16tof32:
; FP32: # %bb.0: # %entry
-; FP32-NEXT: lui $1, 17200
-; FP32-NEXT: mtc1 $4, $f0
-; FP32-NEXT: mtc1 $1, $f1
+; FP32-NEXT: andi $1, $4, 65535
+; FP32-NEXT: lui $2, 17200
+; FP32-NEXT: mtc1 $1, $f0
+; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: lui $2, 17200
; FP32-NEXT: ori $1, $zero, 0
; FP32-NEXT: mtc1 $1, $f2
@@ -187,9 +188,10 @@ define float @u16tof32(i16 zeroext %a) {
;
; FP64-LABEL: u16tof32:
; FP64: # %bb.0: # %entry
-; FP64-NEXT: lui $1, 17200
-; FP64-NEXT: mtc1 $4, $f0
-; FP64-NEXT: mthc1 $1, $f0
+; FP64-NEXT: andi $1, $4, 65535
+; FP64-NEXT: lui $2, 17200
+; FP64-NEXT: mtc1 $1, $f0
+; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: lui $2, 17200
; FP64-NEXT: ori $1, $zero, 0
; FP64-NEXT: mtc1 $1, $f1
@@ -206,9 +208,10 @@ entry:
define float @u8tof32(i8 zeroext %a) {
; FP32-LABEL: u8tof32:
; FP32: # %bb.0: # %entry
-; FP32-NEXT: lui $1, 17200
-; FP32-NEXT: mtc1 $4, $f0
-; FP32-NEXT: mtc1 $1, $f1
+; FP32-NEXT: andi $1, $4, 255
+; FP32-NEXT: lui $2, 17200
+; FP32-NEXT: mtc1 $1, $f0
+; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: lui $2, 17200
; FP32-NEXT: ori $1, $zero, 0
; FP32-NEXT: mtc1 $1, $f2
@@ -220,9 +223,10 @@ define float @u8tof32(i8 zeroext %a) {
;
; FP64-LABEL: u8tof32:
; FP64: # %bb.0: # %entry
-; FP64-NEXT: lui $1, 17200
-; FP64-NEXT: mtc1 $4, $f0
-; FP64-NEXT: mthc1 $1, $f0
+; FP64-NEXT: andi $1, $4, 255
+; FP64-NEXT: lui $2, 17200
+; FP64-NEXT: mtc1 $1, $f0
+; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: lui $2, 17200
; FP64-NEXT: ori $1, $zero, 0
; FP64-NEXT: mtc1 $1, $f1
@@ -288,9 +292,10 @@ entry:
define double @u16tof64(i16 zeroext %a) {
; FP32-LABEL: u16tof64:
; FP32: # %bb.0: # %entry
-; FP32-NEXT: lui $1, 17200
-; FP32-NEXT: mtc1 $4, $f0
-; FP32-NEXT: mtc1 $1, $f1
+; FP32-NEXT: andi $1, $4, 65535
+; FP32-NEXT: lui $2, 17200
+; FP32-NEXT: mtc1 $1, $f0
+; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: lui $2, 17200
; FP32-NEXT: ori $1, $zero, 0
; FP32-NEXT: mtc1 $1, $f2
@@ -301,9 +306,10 @@ define double @u16tof64(i16 zeroext %a) {
;
; FP64-LABEL: u16tof64:
; FP64: # %bb.0: # %entry
-; FP64-NEXT: lui $1, 17200
-; FP64-NEXT: mtc1 $4, $f0
-; FP64-NEXT: mthc1 $1, $f0
+; FP64-NEXT: andi $1, $4, 65535
+; FP64-NEXT: lui $2, 17200
+; FP64-NEXT: mtc1 $1, $f0
+; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: lui $2, 17200
; FP64-NEXT: ori $1, $zero, 0
; FP64-NEXT: mtc1 $1, $f1
@@ -319,9 +325,10 @@ entry:
define double @u8tof64(i8 zeroext %a) {
; FP32-LABEL: u8tof64:
; FP32: # %bb.0: # %entry
-; FP32-NEXT: lui $1, 17200
-; FP32-NEXT: mtc1 $4, $f0
-; FP32-NEXT: mtc1 $1, $f1
+; FP32-NEXT: andi $1, $4, 255
+; FP32-NEXT: lui $2, 17200
+; FP32-NEXT: mtc1 $1, $f0
+; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: lui $2, 17200
; FP32-NEXT: ori $1, $zero, 0
; FP32-NEXT: mtc1 $1, $f2
@@ -332,9 +339,10 @@ define double @u8tof64(i8 zeroext %a) {
;
; FP64-LABEL: u8tof64:
; FP64: # %bb.0: # %entry
-; FP64-NEXT: lui $1, 17200
-; FP64-NEXT: mtc1 $4, $f0
-; FP64-NEXT: mthc1 $1, $f0
+; FP64-NEXT: andi $1, $4, 255
+; FP64-NEXT: lui $2, 17200
+; FP64-NEXT: mtc1 $1, $f0
+; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: lui $2, 17200
; FP64-NEXT: ori $1, $zero, 0
; FP64-NEXT: mtc1 $1, $f1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
index e9ada30d43825d6..87df1d20349002e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
@@ -90,6 +90,7 @@ define i64 @sub_i64(i64 %a, i64 %b) {
; MIPS32-NEXT: subu $2, $6, $4
; MIPS32-NEXT: sltu $3, $6, $4
; MIPS32-NEXT: subu $1, $7, $5
+; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: subu $3, $1, $3
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -114,7 +115,8 @@ define i128 @sub_i128(i128 %a, i128 %b) {
; MIPS32-NEXT: sltu $9, $8, $9
; MIPS32-NEXT: subu $8, $3, $5
; MIPS32-NEXT: sltu $5, $3, $8
-; MIPS32-NEXT: subu $3, $8, $9
+; MIPS32-NEXT: andi $3, $9, 1
+; MIPS32-NEXT: subu $3, $8, $3
; MIPS32-NEXT: sltiu $8, $8, 1
; MIPS32-NEXT: and $8, $8, $9
; MIPS32-NEXT: or $8, $5, $8
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-abs.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-abs.mir
index 71817809b399df1..ca4d5a526d474bd 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-abs.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-abs.mir
@@ -84,7 +84,9 @@ body: |
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ASHR]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[ASHR]]
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[ASHR1]]
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]]
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD2]], [[ASHR1]]
; CHECK-NEXT: $x10 = COPY [[XOR]](s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-add.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-add.mir
index d169eb316dfcb7a..097f96a4f0566ff 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-add.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-add.mir
@@ -90,7 +90,9 @@ body: |
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD %xlo, %ylo
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), %ylo
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD %xhi, %yhi
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s32)
; CHECK-NEXT: $x11 = COPY [[ADD2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -122,7 +124,9 @@ body: |
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD %lo1, %lo2
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), %lo2
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD %hi1, %hi2
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s32)
; CHECK-NEXT: $x11 = COPY [[ADD2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -154,13 +158,17 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), %lo2
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD %mid1, %mid2
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), %mid1
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD2]](s32), [[C]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[ICMP]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[AND]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ADD2]](s32), [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[AND1]]
; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD %hi1, %hi2
- ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[OR]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C2]]
+ ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[AND2]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s32)
; CHECK-NEXT: $x11 = COPY [[ADD2]](s32)
; CHECK-NEXT: $x12 = COPY [[ADD4]](s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir
index e24c7ad53913375..468077e51c3bfc1 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir
@@ -117,9 +117,15 @@ body: |
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C3]](s32)
; CHECK-NEXT: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[SUB]](s32)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[ASHR3]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %xlo, [[SELECT]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ASHR1]], [[ASHR2]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C4]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[OR]], [[ASHR3]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C5]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), %xlo, [[SELECT]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C6]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ASHR1]], [[ASHR2]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -160,9 +166,15 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR %hi1, [[C2]](s32)
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR %hi1, [[SUB]](s32)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[ASHR2]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %lo1, [[SELECT]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ASHR]], [[ASHR1]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[OR]], [[ASHR2]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C4]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), %lo1, [[SELECT]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C5]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ASHR]], [[ASHR1]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -206,63 +218,95 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASHR]], [[SUB3]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[SUB2]](s32)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[OR]], [[ASHR1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), %hi1, [[SELECT]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB %lo2, [[C5]]
- ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C5]], %lo2
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C5]]
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %lo2(s32), [[C6]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C5]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[OR]], [[ASHR1]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[C6]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), %hi1, [[SELECT]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB %lo2, [[C7]]
+ ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C7]], %lo2
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C7]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %lo2(s32), [[C8]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR %mid1, %lo2(s32)
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %lo1, %lo2(s32)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %mid1, [[SUB5]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL1]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR %mid1, [[SUB4]](s32)
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[OR1]], [[LSHR3]]
- ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s32), %lo1, [[SELECT2]]
- ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[LSHR1]], [[C7]]
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C8]]
- ; CHECK-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[SUB1]]
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB1]](s32), [[C8]]
- ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C9]]
+ ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR %mid1, [[SUB4]](s32)
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[C10]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[OR1]], [[LSHR3]]
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP5]], [[C11]]
+ ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), %lo1, [[SELECT2]]
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[C12]]
+ ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[AND4]](s32), [[LSHR1]], [[C9]]
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C13]]
+ ; CHECK-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C13]], [[SUB1]]
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB1]](s32), [[C13]]
+ ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C14]]
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL %hi1, [[SUB1]](s32)
; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR %hi1, [[SUB7]](s32)
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ASHR]], [[SUB1]](s32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[SHL3]]
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL %hi1, [[SUB6]](s32)
- ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[SHL2]], [[C10]]
- ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[OR2]], [[SHL4]]
- ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s32), [[ASHR]], [[SELECT6]]
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ICMP6]], [[C16]]
+ ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[AND5]](s32), [[SHL2]], [[C15]]
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ICMP6]], [[C17]]
+ ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND6]](s32), [[OR2]], [[SHL4]]
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ICMP7]], [[C18]]
+ ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[AND7]](s32), [[ASHR]], [[SELECT6]]
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SELECT3]], [[SELECT5]]
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[SELECT4]], [[SELECT7]]
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C11]](s32)
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C12]]
- ; CHECK-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C12]], [[SUB]]
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[C12]]
- ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB]](s32), [[C13]]
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C19]](s32)
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C20]]
+ ; CHECK-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C20]], [[SUB]]
+ ; CHECK-NEXT: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[C20]]
+ ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB]](s32), [[C21]]
; CHECK-NEXT: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[SUB]](s32)
; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR %hi1, [[SUB]](s32)
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ASHR]], [[SUB9]](s32)
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[SHL5]]
- ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; CHECK-NEXT: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C14]](s32)
+ ; CHECK-NEXT: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C22]](s32)
; CHECK-NEXT: [[ASHR5:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[SUB8]](s32)
- ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s32) = G_SELECT [[ICMP8]](s32), [[OR5]], [[ASHR5]]
- ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s32) = G_SELECT [[ICMP9]](s32), %hi1, [[SELECT8]]
- ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s32) = G_SELECT [[ICMP8]](s32), [[ASHR3]], [[ASHR4]]
- ; CHECK-NEXT: [[SELECT11:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR3]], [[SELECT9]]
- ; CHECK-NEXT: [[SELECT12:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR4]], [[SELECT10]]
- ; CHECK-NEXT: [[SELECT13:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %lo1, [[SELECT11]]
- ; CHECK-NEXT: [[SELECT14:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %mid1, [[SELECT12]]
- ; CHECK-NEXT: [[SELECT15:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SELECT1]], [[ASHR2]]
+ ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ICMP8]], [[C23]]
+ ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s32) = G_SELECT [[AND8]](s32), [[OR5]], [[ASHR5]]
+ ; CHECK-NEXT: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ICMP9]], [[C24]]
+ ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s32) = G_SELECT [[AND9]](s32), %hi1, [[SELECT8]]
+ ; CHECK-NEXT: [[C25:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[ICMP8]], [[C25]]
+ ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s32) = G_SELECT [[AND10]](s32), [[ASHR3]], [[ASHR4]]
+ ; CHECK-NEXT: [[C26:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C26]]
+ ; CHECK-NEXT: [[SELECT11:%[0-9]+]]:_(s32) = G_SELECT [[AND11]](s32), [[OR3]], [[SELECT9]]
+ ; CHECK-NEXT: [[C27:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C27]]
+ ; CHECK-NEXT: [[SELECT12:%[0-9]+]]:_(s32) = G_SELECT [[AND12]](s32), [[OR4]], [[SELECT10]]
+ ; CHECK-NEXT: [[C28:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C28]]
+ ; CHECK-NEXT: [[SELECT13:%[0-9]+]]:_(s32) = G_SELECT [[AND13]](s32), %lo1, [[SELECT11]]
+ ; CHECK-NEXT: [[C29:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C29]]
+ ; CHECK-NEXT: [[SELECT14:%[0-9]+]]:_(s32) = G_SELECT [[AND14]](s32), %mid1, [[SELECT12]]
+ ; CHECK-NEXT: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C30]]
+ ; CHECK-NEXT: [[SELECT15:%[0-9]+]]:_(s32) = G_SELECT [[AND15]](s32), [[SELECT1]], [[ASHR2]]
; CHECK-NEXT: $x10 = COPY [[SELECT13]](s32)
; CHECK-NEXT: $x11 = COPY [[SELECT14]](s32)
; CHECK-NEXT: $x12 = COPY [[SELECT15]](s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-icmp.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-icmp.mir
index 894a6a0aa954ab7..62a77ea069ad54d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-icmp.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-icmp.mir
@@ -115,7 +115,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -144,7 +146,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -273,7 +277,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -302,7 +308,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -431,7 +439,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -460,7 +470,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -589,7 +601,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -618,7 +632,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -743,7 +759,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND1]](s32), [[AND3]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[AND2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C4]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND4]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -772,7 +790,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -897,7 +917,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND1]](s32), [[AND3]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C4]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND4]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -926,7 +948,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -1051,7 +1075,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[AND1]](s32), [[AND3]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[AND]](s32), [[AND2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C4]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND4]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -1080,7 +1106,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -1205,7 +1233,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[AND1]](s32), [[AND3]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[AND3]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[AND]](s32), [[AND2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C4]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND4]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
@@ -1234,7 +1264,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %xlo(s32), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xhi(s32), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-lshr.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-lshr.mir
index 604ae2a4b7928fe..da6fb7802bd4201 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-lshr.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-lshr.mir
@@ -114,9 +114,15 @@ body: |
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL]]
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[SUB]](s32)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[LSHR2]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[AND]], [[SELECT]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[LSHR]], [[C4]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C5]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[OR]], [[LSHR2]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C6]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[AND]], [[SELECT]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C7]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND4]](s32), [[LSHR]], [[C4]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -156,9 +162,15 @@ body: |
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %hi1, [[SUB]](s32)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[LSHR2]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %lo1, [[SELECT]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[LSHR]], [[C2]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[OR]], [[LSHR2]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C4]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), %lo1, [[SELECT]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C5]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[LSHR]], [[C2]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -201,61 +213,93 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[SUB3]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[C]], [[SUB2]](s32)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[OR]], [[LSHR1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), %hi1, [[SELECT]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB %lo2, [[C5]]
- ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C5]], %lo2
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C5]]
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %lo2(s32), [[C6]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C5]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[OR]], [[LSHR1]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[C6]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), %hi1, [[SELECT]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB %lo2, [[C7]]
+ ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C7]], %lo2
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C7]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %lo2(s32), [[C8]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %mid1, %lo2(s32)
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR %lo1, %lo2(s32)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %mid1, [[SUB5]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL1]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR %mid1, [[SUB4]](s32)
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[OR1]], [[LSHR4]]
- ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s32), %lo1, [[SELECT2]]
- ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[LSHR2]], [[C7]]
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C8]]
- ; CHECK-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[SUB1]]
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB1]](s32), [[C8]]
- ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C9]]
+ ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR %mid1, [[SUB4]](s32)
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[C10]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[OR1]], [[LSHR4]]
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP5]], [[C11]]
+ ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), %lo1, [[SELECT2]]
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[C12]]
+ ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[AND4]](s32), [[LSHR2]], [[C9]]
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C13]]
+ ; CHECK-NEXT: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C13]], [[SUB1]]
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB1]](s32), [[C13]]
+ ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C14]]
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL %hi1, [[SUB1]](s32)
; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR %hi1, [[SUB7]](s32)
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[C]], [[SUB1]](s32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[SHL3]]
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL %hi1, [[SUB6]](s32)
- ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[SHL2]], [[C10]]
- ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[OR2]], [[SHL4]]
- ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s32), [[C]], [[SELECT6]]
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ICMP6]], [[C16]]
+ ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[AND5]](s32), [[SHL2]], [[C15]]
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ICMP6]], [[C17]]
+ ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND6]](s32), [[OR2]], [[SHL4]]
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ICMP7]], [[C18]]
+ ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[AND7]](s32), [[C]], [[SELECT6]]
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SELECT3]], [[SELECT5]]
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[SELECT4]], [[SELECT7]]
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C12]]
- ; CHECK-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C12]], [[SUB]]
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[C12]]
- ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB]](s32), [[C13]]
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C20]]
+ ; CHECK-NEXT: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[C20]], [[SUB]]
+ ; CHECK-NEXT: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[C20]]
+ ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB]](s32), [[C21]]
; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[C]], [[SUB]](s32)
; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR %hi1, [[SUB]](s32)
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[C]], [[SUB9]](s32)
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR7]], [[SHL5]]
- ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[C]], [[SUB8]](s32)
- ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s32) = G_SELECT [[ICMP8]](s32), [[OR5]], [[LSHR8]]
- ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s32) = G_SELECT [[ICMP9]](s32), %hi1, [[SELECT8]]
- ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s32) = G_SELECT [[ICMP8]](s32), [[LSHR6]], [[C14]]
- ; CHECK-NEXT: [[SELECT11:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR3]], [[SELECT9]]
- ; CHECK-NEXT: [[SELECT12:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR4]], [[SELECT10]]
- ; CHECK-NEXT: [[SELECT13:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %lo1, [[SELECT11]]
- ; CHECK-NEXT: [[SELECT14:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %mid1, [[SELECT12]]
- ; CHECK-NEXT: [[SELECT15:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SELECT1]], [[C11]]
+ ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ICMP8]], [[C23]]
+ ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s32) = G_SELECT [[AND8]](s32), [[OR5]], [[LSHR8]]
+ ; CHECK-NEXT: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ICMP9]], [[C24]]
+ ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s32) = G_SELECT [[AND9]](s32), %hi1, [[SELECT8]]
+ ; CHECK-NEXT: [[C25:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[ICMP8]], [[C25]]
+ ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s32) = G_SELECT [[AND10]](s32), [[LSHR6]], [[C22]]
+ ; CHECK-NEXT: [[C26:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C26]]
+ ; CHECK-NEXT: [[SELECT11:%[0-9]+]]:_(s32) = G_SELECT [[AND11]](s32), [[OR3]], [[SELECT9]]
+ ; CHECK-NEXT: [[C27:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C27]]
+ ; CHECK-NEXT: [[SELECT12:%[0-9]+]]:_(s32) = G_SELECT [[AND12]](s32), [[OR4]], [[SELECT10]]
+ ; CHECK-NEXT: [[C28:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C28]]
+ ; CHECK-NEXT: [[SELECT13:%[0-9]+]]:_(s32) = G_SELECT [[AND13]](s32), %lo1, [[SELECT11]]
+ ; CHECK-NEXT: [[C29:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C29]]
+ ; CHECK-NEXT: [[SELECT14:%[0-9]+]]:_(s32) = G_SELECT [[AND14]](s32), %mid1, [[SELECT12]]
+ ; CHECK-NEXT: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C30]]
+ ; CHECK-NEXT: [[SELECT15:%[0-9]+]]:_(s32) = G_SELECT [[AND15]](s32), [[SELECT1]], [[C19]]
; CHECK-NEXT: $x10 = COPY [[SELECT13]](s32)
; CHECK-NEXT: $x11 = COPY [[SELECT14]](s32)
; CHECK-NEXT: $x12 = COPY [[SELECT15]](s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul-ext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul-ext.mir
index 433d6e6b821f327..04e99d7407f050a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul-ext.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul-ext.mir
@@ -162,9 +162,13 @@ body: |
; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH %lo1, %lo2
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL2]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C1]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK-NEXT: [[MUL3:%[0-9]+]]:_(s32) = G_MUL %hi1, %lo2
; CHECK-NEXT: [[MUL4:%[0-9]+]]:_(s32) = G_MUL %mid1, %mid2
; CHECK-NEXT: [[MUL5:%[0-9]+]]:_(s32) = G_MUL %lo1, %hi2
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-shl.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-shl.mir
index ce00388c61dbe1b..bc18361555c5fa6 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-shl.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-shl.mir
@@ -104,9 +104,15 @@ body: |
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL %xlo, [[SUB]](s32)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SHL]], [[C2]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[SHL2]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %xhi, [[SELECT1]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[SHL]], [[C2]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C4]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[OR]], [[SHL2]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C5]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), %xhi, [[SELECT1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -146,9 +152,15 @@ body: |
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL %lo1, [[SUB]](s32)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SHL]], [[C2]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[SHL2]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %hi1, [[SELECT1]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[SHL]], [[C2]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C4]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[OR]], [[SHL2]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C5]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), %hi1, [[SELECT1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -192,38 +204,60 @@ body: |
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL %lo1, [[SUB2]](s32)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[SHL]], [[C4]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[OR]], [[SHL2]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), %mid1, [[SELECT1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C5]]
- ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C5]], [[SUB1]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB1]](s32), [[C5]]
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C6]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C5]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[SHL]], [[C4]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C6]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[OR]], [[SHL2]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[C7]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), %mid1, [[SELECT1]]
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C8]]
+ ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[SUB1]]
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB1]](s32), [[C8]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C9]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR %lo1, [[SUB1]](s32)
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL %mid1, [[SUB5]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL3]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %mid1, [[SUB4]](s32)
- ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[OR1]], [[LSHR2]]
- ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s32), %lo1, [[SELECT3]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C7]]
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[C10]]
+ ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[OR1]], [[LSHR2]]
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP5]], [[C11]]
+ ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[AND4]](s32), %lo1, [[SELECT3]]
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo2(s32), [[C12]]
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL %hi1, %lo2(s32)
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[SHL4]], [[C8]]
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ICMP6]], [[C14]]
+ ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[AND5]](s32), [[SHL4]], [[C13]]
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT4]], [[SELECT5]]
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[C11]]
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[C17]]
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL %lo1, [[SUB]](s32)
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s32), [[SHL5]], [[C12]]
- ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SELECT]], [[C9]]
- ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SELECT2]], [[C10]]
- ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR2]], [[SELECT6]]
- ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), %hi1, [[SELECT9]]
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ICMP7]], [[C19]]
+ ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[AND6]](s32), [[SHL5]], [[C18]]
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C20]]
+ ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[AND7]](s32), [[SELECT]], [[C15]]
+ ; CHECK-NEXT: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C21]]
+ ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s32) = G_SELECT [[AND8]](s32), [[SELECT2]], [[C16]]
+ ; CHECK-NEXT: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C22]]
+ ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s32) = G_SELECT [[AND9]](s32), [[OR2]], [[SELECT6]]
+ ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C23]]
+ ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s32) = G_SELECT [[AND10]](s32), %hi1, [[SELECT9]]
; CHECK-NEXT: $x10 = COPY [[SELECT7]](s32)
; CHECK-NEXT: $x11 = COPY [[SELECT8]](s32)
; CHECK-NEXT: $x12 = COPY [[SELECT10]](s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-store.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-store.mir
index 2ece5a8c9d41426..fb3367fcd30473d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-store.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-store.mir
@@ -232,9 +232,11 @@ body: |
; CHECK-NEXT: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store (s8))
; CHECK-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 1)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[C5]](s32)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C6]](s32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C6]]
+ ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C5]](s32)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C7]](s32)
; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 2)
; CHECK-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p0) :: (store (s8) into unknown-address + 3)
; CHECK-NEXT: PseudoRET
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-sub.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-sub.mir
index 258d02646186cdf..bb3a68fa01142fb 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-sub.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-sub.mir
@@ -90,7 +90,9 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %xlo, %ylo
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %xlo(s32), %ylo
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB %xhi, %yhi
- ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
; CHECK-NEXT: $x11 = COPY [[SUB2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -122,7 +124,9 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB %lo1, %lo2
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo1(s32), %lo2
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB %hi1, %hi2
- ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
; CHECK-NEXT: $x11 = COPY [[SUB2]](s32)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -154,13 +158,17 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %lo1(s32), %lo2
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB %mid1, %mid2
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[SUB1]](s32), %mid1
- ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[ICMP]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[AND]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB1]](s32), [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[AND1]]
; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB %hi1, %hi2
- ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[OR]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C2]]
+ ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[AND2]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
; CHECK-NEXT: $x11 = COPY [[SUB2]](s32)
; CHECK-NEXT: $x12 = COPY [[SUB4]](s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir
index cf266bd8a17d8c1..4a406fbe76cd3d7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir
@@ -122,7 +122,9 @@ body: |
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD %x00, %y00
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), %y00
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD %x01, %y01
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ADD1]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ADD1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
; CHECK-NEXT: $x11 = COPY [[ADD2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -154,7 +156,9 @@ body: |
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD %lo1, %lo2
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), %lo2
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD %hi1, %hi2
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ADD1]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ADD1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
; CHECK-NEXT: $x11 = COPY [[ADD2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -186,13 +190,17 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), %lo2
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD %mid1, %mid2
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD1]](s64), %mid1
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ADD1]], [[ICMP]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ADD2]](s64), [[C]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP2]], [[ICMP]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ICMP1]], [[AND]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ADD1]], [[AND]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ADD2]](s64), [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ICMP1]], [[AND1]]
; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s64) = G_ADD %hi1, %hi2
- ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s64) = G_ADD [[ADD3]], [[OR]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C2]]
+ ; CHECK-NEXT: [[ADD4:%[0-9]+]]:_(s64) = G_ADD [[ADD3]], [[AND2]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
; CHECK-NEXT: $x11 = COPY [[ADD2]](s64)
; CHECK-NEXT: $x12 = COPY [[ADD4]](s64)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ashr.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ashr.mir
index 5b811c8e6c3c9fb..711364e06c90f1b 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ashr.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ashr.mir
@@ -149,9 +149,15 @@ body: |
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C3]](s64)
; CHECK-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[SUB]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR]], [[ASHR3]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %x00, [[SELECT]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[ASHR1]], [[ASHR2]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C4]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[OR]], [[ASHR3]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C5]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s64), %x00, [[SELECT]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C6]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s64), [[ASHR1]], [[ASHR2]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s64)
; CHECK-NEXT: $x11 = COPY [[SELECT2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -192,9 +198,15 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR %hi1, [[C2]](s64)
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR %hi1, [[SUB]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR]], [[ASHR2]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %lo1, [[SELECT]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[ASHR]], [[ASHR1]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[OR]], [[ASHR2]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C4]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s64), %lo1, [[SELECT]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C5]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s64), [[ASHR]], [[ASHR1]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s64)
; CHECK-NEXT: $x11 = COPY [[SELECT2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -238,63 +250,95 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASHR]], [[SUB3]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[SUB2]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s64), [[OR]], [[ASHR1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s64), %hi1, [[SELECT]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB %lo2, [[C5]]
- ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s64) = G_SUB [[C5]], %lo2
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C5]]
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %lo2(s64), [[C6]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP2]], [[C5]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[OR]], [[ASHR1]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP3]], [[C6]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s64), %hi1, [[SELECT]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB %lo2, [[C7]]
+ ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s64) = G_SUB [[C7]], %lo2
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C7]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %lo2(s64), [[C8]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR %mid1, %lo2(s64)
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR %lo1, %lo2(s64)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %mid1, [[SUB5]](s64)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[SHL1]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR %mid1, [[SUB4]](s64)
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s64), [[OR1]], [[LSHR3]]
- ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s64), %lo1, [[SELECT2]]
- ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s64), [[LSHR1]], [[C7]]
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[SUB6:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[C8]]
- ; CHECK-NEXT: [[SUB7:%[0-9]+]]:_(s64) = G_SUB [[C8]], [[SUB1]]
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB1]](s64), [[C8]]
- ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB1]](s64), [[C9]]
+ ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR %mid1, [[SUB4]](s64)
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ICMP4]], [[C10]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s64), [[OR1]], [[LSHR3]]
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ICMP5]], [[C11]]
+ ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[AND3]](s64), %lo1, [[SELECT2]]
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ICMP4]], [[C12]]
+ ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s64), [[LSHR1]], [[C9]]
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[SUB6:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[C13]]
+ ; CHECK-NEXT: [[SUB7:%[0-9]+]]:_(s64) = G_SUB [[C13]], [[SUB1]]
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB1]](s64), [[C13]]
+ ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB1]](s64), [[C14]]
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL %hi1, [[SUB1]](s64)
; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR %hi1, [[SUB7]](s64)
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[ASHR]], [[SUB1]](s64)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[SHL3]]
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL %hi1, [[SUB6]](s64)
- ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s64), [[SHL2]], [[C10]]
- ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s64), [[OR2]], [[SHL4]]
- ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s64), [[ASHR]], [[SELECT6]]
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ICMP6]], [[C16]]
+ ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[AND5]](s64), [[SHL2]], [[C15]]
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ICMP6]], [[C17]]
+ ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[AND6]](s64), [[OR2]], [[SHL4]]
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ICMP7]], [[C18]]
+ ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[AND7]](s64), [[ASHR]], [[SELECT6]]
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT3]], [[SELECT5]]
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT7]]
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
- ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C11]](s64)
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[SUB8:%[0-9]+]]:_(s64) = G_SUB [[SUB]], [[C12]]
- ; CHECK-NEXT: [[SUB9:%[0-9]+]]:_(s64) = G_SUB [[C12]], [[SUB]]
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB]](s64), [[C12]]
- ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB]](s64), [[C13]]
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
+ ; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C19]](s64)
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[SUB8:%[0-9]+]]:_(s64) = G_SUB [[SUB]], [[C20]]
+ ; CHECK-NEXT: [[SUB9:%[0-9]+]]:_(s64) = G_SUB [[C20]], [[SUB]]
+ ; CHECK-NEXT: [[C21:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB]](s64), [[C20]]
+ ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB]](s64), [[C21]]
; CHECK-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[SUB]](s64)
; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR %hi1, [[SUB]](s64)
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[ASHR]], [[SUB9]](s64)
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR5]], [[SHL5]]
- ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
- ; CHECK-NEXT: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C14]](s64)
+ ; CHECK-NEXT: [[C22:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
+ ; CHECK-NEXT: [[ASHR4:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C22]](s64)
; CHECK-NEXT: [[ASHR5:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[SUB8]](s64)
- ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s64), [[OR5]], [[ASHR5]]
- ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s64), %hi1, [[SELECT8]]
- ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s64), [[ASHR3]], [[ASHR4]]
- ; CHECK-NEXT: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR3]], [[SELECT9]]
- ; CHECK-NEXT: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR4]], [[SELECT10]]
- ; CHECK-NEXT: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %lo1, [[SELECT11]]
- ; CHECK-NEXT: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %mid1, [[SELECT12]]
- ; CHECK-NEXT: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SELECT1]], [[ASHR2]]
+ ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[ICMP8]], [[C23]]
+ ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[AND8]](s64), [[OR5]], [[ASHR5]]
+ ; CHECK-NEXT: [[C24:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ICMP9]], [[C24]]
+ ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[AND9]](s64), %hi1, [[SELECT8]]
+ ; CHECK-NEXT: [[C25:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ICMP8]], [[C25]]
+ ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[AND10]](s64), [[ASHR3]], [[ASHR4]]
+ ; CHECK-NEXT: [[C26:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C26]]
+ ; CHECK-NEXT: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[AND11]](s64), [[OR3]], [[SELECT9]]
+ ; CHECK-NEXT: [[C27:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C27]]
+ ; CHECK-NEXT: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[AND12]](s64), [[OR4]], [[SELECT10]]
+ ; CHECK-NEXT: [[C28:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C28]]
+ ; CHECK-NEXT: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[AND13]](s64), %lo1, [[SELECT11]]
+ ; CHECK-NEXT: [[C29:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C29]]
+ ; CHECK-NEXT: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[AND14]](s64), %mid1, [[SELECT12]]
+ ; CHECK-NEXT: [[C30:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C30]]
+ ; CHECK-NEXT: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[AND15]](s64), [[SELECT1]], [[ASHR2]]
; CHECK-NEXT: $x10 = COPY [[SELECT13]](s64)
; CHECK-NEXT: $x11 = COPY [[SELECT14]](s64)
; CHECK-NEXT: $x12 = COPY [[SELECT15]](s64)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-icmp.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-icmp.mir
index de47b1493e4daf5..351fdf18bfc95e1 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-icmp.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-icmp.mir
@@ -137,7 +137,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xhi(s64), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
@@ -166,7 +168,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xhi(s64), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
@@ -317,7 +321,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
@@ -346,7 +352,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %xhi(s64), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
@@ -497,7 +505,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
@@ -526,7 +536,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
@@ -677,7 +689,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xhi(s64), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C2]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
@@ -706,7 +720,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xhi(s64), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
@@ -855,7 +871,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[AND1]](s64), [[AND3]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[AND]](s64), [[AND2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C4]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
@@ -884,7 +902,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xhi(s64), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
@@ -1033,7 +1053,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND1]](s64), [[AND3]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[AND]](s64), [[AND2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C4]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
@@ -1062,7 +1084,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
@@ -1211,7 +1235,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), [[AND1]](s64), [[AND3]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), [[AND]](s64), [[AND2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C4]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
@@ -1240,7 +1266,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
@@ -1389,7 +1417,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), [[AND1]](s64), [[AND3]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[AND1]](s64), [[AND3]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), [[AND]](s64), [[AND2]]
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C4]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
@@ -1418,7 +1448,9 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %xlo(s64), %ylo
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xhi(s64), %yhi
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-lshr.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-lshr.mir
index 3b8d0575db846e8..dba70d816034cda 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-lshr.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-lshr.mir
@@ -146,9 +146,15 @@ body: |
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[SUB]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR]], [[LSHR2]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), [[AND]], [[SELECT]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[LSHR]], [[C4]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C5]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s64), [[OR]], [[LSHR2]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C6]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND3]](s64), [[AND]], [[SELECT]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C7]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s64), [[LSHR]], [[C4]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s64)
; CHECK-NEXT: $x11 = COPY [[SELECT2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -188,9 +194,15 @@ body: |
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR %hi1, [[SUB]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR]], [[LSHR2]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %lo1, [[SELECT]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[LSHR]], [[C2]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[OR]], [[LSHR2]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C4]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s64), %lo1, [[SELECT]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C5]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s64), [[LSHR]], [[C2]]
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s64)
; CHECK-NEXT: $x11 = COPY [[SELECT2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -233,61 +245,93 @@ body: |
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[C]], [[SUB3]](s64)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[C]], [[SUB2]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s64), [[OR]], [[LSHR1]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s64), %hi1, [[SELECT]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB %lo2, [[C5]]
- ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s64) = G_SUB [[C5]], %lo2
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C5]]
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %lo2(s64), [[C6]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP2]], [[C5]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[OR]], [[LSHR1]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP3]], [[C6]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s64), %hi1, [[SELECT]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB %lo2, [[C7]]
+ ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s64) = G_SUB [[C7]], %lo2
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C7]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), %lo2(s64), [[C8]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR %mid1, %lo2(s64)
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR %lo1, %lo2(s64)
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %mid1, [[SUB5]](s64)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL1]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR %mid1, [[SUB4]](s64)
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s64), [[OR1]], [[LSHR4]]
- ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s64), %lo1, [[SELECT2]]
- ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s64), [[LSHR2]], [[C7]]
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[SUB6:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[C8]]
- ; CHECK-NEXT: [[SUB7:%[0-9]+]]:_(s64) = G_SUB [[C8]], [[SUB1]]
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB1]](s64), [[C8]]
- ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB1]](s64), [[C9]]
+ ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR %mid1, [[SUB4]](s64)
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ICMP4]], [[C10]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s64), [[OR1]], [[LSHR4]]
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ICMP5]], [[C11]]
+ ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[AND3]](s64), %lo1, [[SELECT2]]
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ICMP4]], [[C12]]
+ ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s64), [[LSHR2]], [[C9]]
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[SUB6:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[C13]]
+ ; CHECK-NEXT: [[SUB7:%[0-9]+]]:_(s64) = G_SUB [[C13]], [[SUB1]]
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB1]](s64), [[C13]]
+ ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB1]](s64), [[C14]]
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL %hi1, [[SUB1]](s64)
; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR %hi1, [[SUB7]](s64)
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[C]], [[SUB1]](s64)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR5]], [[SHL3]]
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL %hi1, [[SUB6]](s64)
- ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s64), [[SHL2]], [[C10]]
- ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s64), [[OR2]], [[SHL4]]
- ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s64), [[C]], [[SELECT6]]
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ICMP6]], [[C16]]
+ ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[AND5]](s64), [[SHL2]], [[C15]]
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ICMP6]], [[C17]]
+ ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[AND6]](s64), [[OR2]], [[SHL4]]
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ICMP7]], [[C18]]
+ ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[AND7]](s64), [[C]], [[SELECT6]]
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SELECT3]], [[SELECT5]]
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT7]]
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[SUB8:%[0-9]+]]:_(s64) = G_SUB [[SUB]], [[C12]]
- ; CHECK-NEXT: [[SUB9:%[0-9]+]]:_(s64) = G_SUB [[C12]], [[SUB]]
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB]](s64), [[C12]]
- ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB]](s64), [[C13]]
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[SUB8:%[0-9]+]]:_(s64) = G_SUB [[SUB]], [[C20]]
+ ; CHECK-NEXT: [[SUB9:%[0-9]+]]:_(s64) = G_SUB [[C20]], [[SUB]]
+ ; CHECK-NEXT: [[C21:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB]](s64), [[C20]]
+ ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB]](s64), [[C21]]
; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[C]], [[SUB]](s64)
; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR %hi1, [[SUB]](s64)
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[C]], [[SUB9]](s64)
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR7]], [[SHL5]]
- ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C22:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[C]], [[SUB8]](s64)
- ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s64), [[OR5]], [[LSHR8]]
- ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP9]](s64), %hi1, [[SELECT8]]
- ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP8]](s64), [[LSHR6]], [[C14]]
- ; CHECK-NEXT: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR3]], [[SELECT9]]
- ; CHECK-NEXT: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR4]], [[SELECT10]]
- ; CHECK-NEXT: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %lo1, [[SELECT11]]
- ; CHECK-NEXT: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %mid1, [[SELECT12]]
- ; CHECK-NEXT: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SELECT1]], [[C11]]
+ ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[ICMP8]], [[C23]]
+ ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[AND8]](s64), [[OR5]], [[LSHR8]]
+ ; CHECK-NEXT: [[C24:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ICMP9]], [[C24]]
+ ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[AND9]](s64), %hi1, [[SELECT8]]
+ ; CHECK-NEXT: [[C25:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ICMP8]], [[C25]]
+ ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[AND10]](s64), [[LSHR6]], [[C22]]
+ ; CHECK-NEXT: [[C26:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C26]]
+ ; CHECK-NEXT: [[SELECT11:%[0-9]+]]:_(s64) = G_SELECT [[AND11]](s64), [[OR3]], [[SELECT9]]
+ ; CHECK-NEXT: [[C27:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C27]]
+ ; CHECK-NEXT: [[SELECT12:%[0-9]+]]:_(s64) = G_SELECT [[AND12]](s64), [[OR4]], [[SELECT10]]
+ ; CHECK-NEXT: [[C28:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C28]]
+ ; CHECK-NEXT: [[SELECT13:%[0-9]+]]:_(s64) = G_SELECT [[AND13]](s64), %lo1, [[SELECT11]]
+ ; CHECK-NEXT: [[C29:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C29]]
+ ; CHECK-NEXT: [[SELECT14:%[0-9]+]]:_(s64) = G_SELECT [[AND14]](s64), %mid1, [[SELECT12]]
+ ; CHECK-NEXT: [[C30:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C30]]
+ ; CHECK-NEXT: [[SELECT15:%[0-9]+]]:_(s64) = G_SELECT [[AND15]](s64), [[SELECT1]], [[C19]]
; CHECK-NEXT: $x10 = COPY [[SELECT13]](s64)
; CHECK-NEXT: $x11 = COPY [[SELECT14]](s64)
; CHECK-NEXT: $x12 = COPY [[SELECT15]](s64)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul-ext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul-ext.mir
index 09e002e8428d79b..8d8c23e25d172d9 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul-ext.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul-ext.mir
@@ -194,9 +194,13 @@ body: |
; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s64) = G_UMULH %lo1, %lo2
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[MUL1]], [[MUL2]]
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD]](s64), [[MUL2]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[UMULH]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[ADD1]](s64), [[UMULH]]
- ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C1]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[AND]], [[AND1]]
; CHECK-NEXT: [[MUL3:%[0-9]+]]:_(s64) = G_MUL %hi1, %lo2
; CHECK-NEXT: [[MUL4:%[0-9]+]]:_(s64) = G_MUL %mid1, %mid2
; CHECK-NEXT: [[MUL5:%[0-9]+]]:_(s64) = G_MUL %lo1, %hi2
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-shl.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-shl.mir
index 8114ea488ac2968..9e3ae701fe16f46 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-shl.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-shl.mir
@@ -136,9 +136,15 @@ body: |
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL %x00, [[SUB]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SHL]], [[C2]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR]], [[SHL2]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %x01, [[SELECT1]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[SHL]], [[C2]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C4]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s64), [[OR]], [[SHL2]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C5]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s64), %x01, [[SELECT1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: $x11 = COPY [[SELECT2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -178,9 +184,15 @@ body: |
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL %lo1, [[SUB]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SHL]], [[C2]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR]], [[SHL2]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %hi1, [[SELECT1]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[SHL]], [[C2]]
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C4]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s64), [[OR]], [[SHL2]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C5]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s64), %hi1, [[SELECT1]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: $x11 = COPY [[SELECT2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -224,38 +236,60 @@ body: |
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL1]]
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL %lo1, [[SUB2]](s64)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s64), [[SHL]], [[C4]]
- ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s64), [[OR]], [[SHL2]]
- ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s64), %mid1, [[SELECT1]]
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[C5]]
- ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s64) = G_SUB [[C5]], [[SUB1]]
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB1]](s64), [[C5]]
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB1]](s64), [[C6]]
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP2]], [[C5]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[SHL]], [[C4]]
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP2]], [[C6]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND1]](s64), [[OR]], [[SHL2]]
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ICMP3]], [[C7]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s64), %mid1, [[SELECT1]]
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[C8]]
+ ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s64) = G_SUB [[C8]], [[SUB1]]
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB1]](s64), [[C8]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB1]](s64), [[C9]]
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR %lo1, [[SUB1]](s64)
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL %mid1, [[SUB5]](s64)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL3]]
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR %mid1, [[SUB4]](s64)
- ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP4]](s64), [[OR1]], [[LSHR2]]
- ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP5]](s64), %lo1, [[SELECT3]]
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C7]]
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ICMP4]], [[C10]]
+ ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[AND3]](s64), [[OR1]], [[LSHR2]]
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ICMP5]], [[C11]]
+ ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s64), %lo1, [[SELECT3]]
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo2(s64), [[C12]]
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL %hi1, %lo2(s64)
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s64), [[SHL4]], [[C8]]
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ICMP6]], [[C14]]
+ ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[AND5]](s64), [[SHL4]], [[C13]]
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SELECT4]], [[SELECT5]]
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
- ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB]](s64), [[C11]]
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
+ ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SUB]](s64), [[C17]]
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL %lo1, [[SUB]](s64)
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s64), [[SHL5]], [[C12]]
- ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SELECT]], [[C9]]
- ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SELECT2]], [[C10]]
- ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[OR2]], [[SELECT6]]
- ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s64), %hi1, [[SELECT9]]
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ICMP7]], [[C19]]
+ ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[AND6]](s64), [[SHL5]], [[C18]]
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C20]]
+ ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[AND7]](s64), [[SELECT]], [[C15]]
+ ; CHECK-NEXT: [[C21:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C21]]
+ ; CHECK-NEXT: [[SELECT8:%[0-9]+]]:_(s64) = G_SELECT [[AND8]](s64), [[SELECT2]], [[C16]]
+ ; CHECK-NEXT: [[C22:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C22]]
+ ; CHECK-NEXT: [[SELECT9:%[0-9]+]]:_(s64) = G_SELECT [[AND9]](s64), [[OR2]], [[SELECT6]]
+ ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C23]]
+ ; CHECK-NEXT: [[SELECT10:%[0-9]+]]:_(s64) = G_SELECT [[AND10]](s64), %hi1, [[SELECT9]]
; CHECK-NEXT: $x10 = COPY [[SELECT7]](s64)
; CHECK-NEXT: $x11 = COPY [[SELECT8]](s64)
; CHECK-NEXT: $x12 = COPY [[SELECT10]](s64)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-store.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-store.mir
index e549b16c17cc8fb..0cba84fad1e2a66 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-store.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-store.mir
@@ -263,9 +263,13 @@ body: |
; CHECK-NEXT: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store (s8))
; CHECK-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 1)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[C5]](s32)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C6]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C6]]
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64)
+ ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C5]](s32)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C7]](s64)
; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 2)
; CHECK-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p0) :: (store (s8) into unknown-address + 3)
; CHECK-NEXT: PseudoRET
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir
index 10b89530512863d..81c4edf2add7c85 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir
@@ -122,7 +122,9 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %x00, %y00
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %x00(s64), %y00
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB %x01, %y01
- ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s64)
; CHECK-NEXT: $x11 = COPY [[SUB2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -154,7 +156,9 @@ body: |
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %lo1, %lo2
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo1(s64), %lo2
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB %hi1, %hi2
- ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[ICMP]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s64)
; CHECK-NEXT: $x11 = COPY [[SUB2]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
@@ -186,13 +190,17 @@ body: |
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), %lo1(s64), %lo2
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB %mid1, %mid2
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[SUB1]](s64), %mid1
- ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[ICMP]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB1]](s64), [[C]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP2]], [[ICMP]]
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ICMP1]], [[AND]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP]], [[C]]
+ ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s64) = G_SUB [[SUB1]], [[AND]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SUB1]](s64), [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ICMP2]], [[ICMP]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ICMP1]], [[AND1]]
; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s64) = G_SUB %hi1, %hi2
- ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB [[SUB3]], [[OR]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C2]]
+ ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s64) = G_SUB [[SUB3]], [[AND2]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s64)
; CHECK-NEXT: $x11 = COPY [[SUB2]](s64)
; CHECK-NEXT: $x12 = COPY [[SUB4]](s64)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll b/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
index fd096365f088083..28a29cc8fb4122b 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
@@ -167,7 +167,8 @@ define i1 @test_ashr_i1_imm1(i32 %arg1) {
; X64-NEXT: movl %edi, %eax
; X64-NEXT: shlb $7, %al
; X64-NEXT: sarb $7, %al
-; X64-NEXT: sarb %al
+; X64-NEXT: movb $1, %cl
+; X64-NEXT: sarb %cl, %al
; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
%a = trunc i32 %arg1 to i1
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir
index 1184c075f42205b..32afcb2db4dadd5 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir
@@ -48,16 +48,14 @@ body: |
liveins: $edi, $esi
; CHECK-LABEL: name: test_cmp_i8
- ; CHECK: liveins: $edi, $esi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $sil
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(ult), [[COPY]](s8), [[COPY1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: $eax = COPY [[AND]](s32)
- ; CHECK-NEXT: RET 0, implicit $eax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY $sil
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(ult), [[COPY]](s8), [[COPY1]]
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK: $eax = COPY [[AND]](s32)
+ ; CHECK: RET 0, implicit $eax
%0(s8) = COPY $dil
%1(s8) = COPY $sil
%2(s1) = G_ICMP intpred(ult), %0(s8), %1
@@ -81,16 +79,14 @@ body: |
liveins: $edi, $esi
; CHECK-LABEL: name: test_cmp_i16
- ; CHECK: liveins: $edi, $esi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $si
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(ult), [[COPY]](s16), [[COPY1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: $eax = COPY [[AND]](s32)
- ; CHECK-NEXT: RET 0, implicit $eax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY $si
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(ult), [[COPY]](s16), [[COPY1]]
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK: $eax = COPY [[AND]](s32)
+ ; CHECK: RET 0, implicit $eax
%0(s16) = COPY $di
%1(s16) = COPY $si
%2(s1) = G_ICMP intpred(ult), %0(s16), %1
@@ -114,16 +110,14 @@ body: |
liveins: $edi, $esi
; CHECK-LABEL: name: test_cmp_i32
- ; CHECK: liveins: $edi, $esi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: $eax = COPY [[AND]](s32)
- ; CHECK-NEXT: RET 0, implicit $eax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK: $eax = COPY [[AND]](s32)
+ ; CHECK: RET 0, implicit $eax
%0(s32) = COPY $edi
%1(s32) = COPY $esi
%2(s1) = G_ICMP intpred(ult), %0(s32), %1
@@ -147,16 +141,14 @@ body: |
liveins: $rdi, $rsi
; CHECK-LABEL: name: test_cmp_i64
- ; CHECK: liveins: $rdi, $rsi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: $eax = COPY [[AND]](s32)
- ; CHECK-NEXT: RET 0, implicit $eax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK: $eax = COPY [[AND]](s32)
+ ; CHECK: RET 0, implicit $eax
%0(s64) = COPY $rdi
%1(s64) = COPY $rsi
%2(s1) = G_ICMP intpred(ult), %0(s64), %1
@@ -180,16 +172,14 @@ body: |
liveins: $rdi, $rsi
; CHECK-LABEL: name: test_cmp_p0
- ; CHECK: liveins: $rdi, $rsi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $rsi
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(ult), [[COPY]](p0), [[COPY1]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: $eax = COPY [[AND]](s32)
- ; CHECK-NEXT: RET 0, implicit $eax
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $rsi
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(ult), [[COPY]](p0), [[COPY1]]
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK: $eax = COPY [[AND]](s32)
+ ; CHECK: RET 0, implicit $eax
%0(p0) = COPY $rdi
%1(p0) = COPY $rsi
%2(s1) = G_ICMP intpred(ult), %0(p0), %1
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
index 1ea2da9757f1adb..60c21e40a5ec85f 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
@@ -76,16 +76,14 @@ body: |
liveins: $edi
; CHECK-LABEL: name: test_sext_i1
- ; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 63
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s8)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY [[C]](s8)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s8)
- ; CHECK-NEXT: $rax = COPY [[ASHR]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
+ ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 63
+ ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s8)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[C]](s8)
+ ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s8)
+ ; CHECK: $rax = COPY [[ASHR]](s64)
+ ; CHECK: RET 0, implicit $rax
%0(s8) = COPY $dil
%1(s1) = G_TRUNC %0(s8)
%2(s64) = G_SEXT %1(s1)
@@ -106,12 +104,10 @@ body: |
liveins: $edi
; CHECK-LABEL: name: test_sext_i8
- ; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s8)
- ; CHECK-NEXT: $rax = COPY [[SEXT]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s8)
+ ; CHECK: $rax = COPY [[SEXT]](s64)
+ ; CHECK: RET 0, implicit $rax
%0(s8) = COPY $dil
%1(s64) = G_SEXT %0(s8)
$rax = COPY %1(s64)
@@ -131,12 +127,10 @@ body: |
liveins: $edi
; CHECK-LABEL: name: test_sext_i16
- ; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
- ; CHECK-NEXT: $rax = COPY [[SEXT]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
+ ; CHECK: $rax = COPY [[SEXT]](s64)
+ ; CHECK: RET 0, implicit $rax
%0(s16) = COPY $di
%1(s64) = G_SEXT %0(s16)
$rax = COPY %1(s64)
@@ -156,12 +150,10 @@ body: |
liveins: $edi
; CHECK-LABEL: name: test_sext_i32
- ; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)
- ; CHECK-NEXT: $rax = COPY [[SEXT]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)
+ ; CHECK: $rax = COPY [[SEXT]](s64)
+ ; CHECK: RET 0, implicit $rax
%0(s32) = COPY $edi
%1(s64) = G_SEXT %0(s32)
$rax = COPY %1(s64)
@@ -182,14 +174,12 @@ body: |
liveins: $edi
; CHECK-LABEL: name: test_zext_i1
- ; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: $rax = COPY [[AND]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
+ ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK: $rax = COPY [[AND]](s64)
+ ; CHECK: RET 0, implicit $rax
%0(s8) = COPY $dil
%1(s1) = G_TRUNC %0(s8)
%2(s64) = G_ZEXT %1(s1)
@@ -210,12 +200,10 @@ body: |
liveins: $edi
; CHECK-LABEL: name: test_zext_i8
- ; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s8)
- ; CHECK-NEXT: $rax = COPY [[ZEXT]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s8)
+ ; CHECK: $rax = COPY [[ZEXT]](s64)
+ ; CHECK: RET 0, implicit $rax
%0(s8) = COPY $dil
%1(s64) = G_ZEXT %0(s8)
$rax = COPY %1(s64)
@@ -235,12 +223,10 @@ body: |
liveins: $edi
; CHECK-LABEL: name: test_zext_i16
- ; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
- ; CHECK-NEXT: $rax = COPY [[ZEXT]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
+ ; CHECK: $rax = COPY [[ZEXT]](s64)
+ ; CHECK: RET 0, implicit $rax
%0(s16) = COPY $di
%1(s64) = G_ZEXT %0(s16)
$rax = COPY %1(s64)
@@ -260,12 +246,10 @@ body: |
liveins: $edi
; CHECK-LABEL: name: test_zext_i32
- ; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
- ; CHECK-NEXT: $rax = COPY [[ZEXT]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
+ ; CHECK: $rax = COPY [[ZEXT]](s64)
+ ; CHECK: RET 0, implicit $rax
%0(s32) = COPY $edi
%1(s64) = G_ZEXT %0(s32)
$rax = COPY %1(s64)
@@ -286,12 +270,10 @@ body: |
liveins: $edi
; CHECK-LABEL: name: test_anyext_i1
- ; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
- ; CHECK-NEXT: $rax = COPY [[ANYEXT]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
+ ; CHECK: $rax = COPY [[ANYEXT]](s64)
+ ; CHECK: RET 0, implicit $rax
%0(s8) = COPY $dil
%1(s1) = G_TRUNC %0(s8)
%2(s64) = G_ANYEXT %1(s1)
@@ -312,12 +294,10 @@ body: |
liveins: $edi
; CHECK-LABEL: name: test_anyext_i8
- ; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
- ; CHECK-NEXT: $rax = COPY [[ANYEXT]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
+ ; CHECK: $rax = COPY [[ANYEXT]](s64)
+ ; CHECK: RET 0, implicit $rax
%0(s8) = COPY $dil
%1(s64) = G_ANYEXT %0(s8)
$rax = COPY %1(s64)
@@ -337,12 +317,10 @@ body: |
liveins: $edi
; CHECK-LABEL: name: test_anyext_i16
- ; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s16)
- ; CHECK-NEXT: $rax = COPY [[ANYEXT]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s16)
+ ; CHECK: $rax = COPY [[ANYEXT]](s64)
+ ; CHECK: RET 0, implicit $rax
%0(s16) = COPY $di
%1(s64) = G_ANYEXT %0(s16)
$rax = COPY %1(s64)
@@ -362,12 +340,10 @@ body: |
liveins: $edi
; CHECK-LABEL: name: test_anyext_i32
- ; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
- ; CHECK-NEXT: $rax = COPY [[ANYEXT]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
+ ; CHECK: $rax = COPY [[ANYEXT]](s64)
+ ; CHECK: RET 0, implicit $rax
%0(s32) = COPY $edi
%1(s64) = G_ANYEXT %0(s32)
$rax = COPY %1(s64)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-ext.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-ext.mir
index bf625cf7eeb9957..58c9880023c8804 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-ext.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-ext.mir
@@ -104,24 +104,19 @@ body: |
liveins: $edi
; X32-LABEL: name: test_zext_i1toi8
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; X32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; X32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
- ; X32-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
- ; X32-NEXT: $al = COPY [[AND]](s8)
- ; X32-NEXT: RET 0, implicit $al
- ;
+ ; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
+ ; X32: $al = COPY [[AND]](s8)
+ ; X32: RET 0, implicit $al
; X64-LABEL: name: test_zext_i1toi8
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; X64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; X64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
- ; X64-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
- ; X64-NEXT: $al = COPY [[AND]](s8)
- ; X64-NEXT: RET 0, implicit $al
+ ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
+ ; X64: $al = COPY [[AND]](s8)
+ ; X64: RET 0, implicit $al
%1:_(s32) = COPY $edi
%0:_(s1) = G_TRUNC %1(s32)
%2:_(s8) = G_ZEXT %0(s1)
@@ -142,24 +137,19 @@ body: |
liveins: $edi
; X32-LABEL: name: test_zext_i1toi16
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; X32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; X32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; X32-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
- ; X32-NEXT: $ax = COPY [[AND]](s16)
- ; X32-NEXT: RET 0, implicit $ax
- ;
+ ; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; X32: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; X32: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; X32: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
+ ; X32: $ax = COPY [[AND]](s16)
+ ; X32: RET 0, implicit $ax
; X64-LABEL: name: test_zext_i1toi16
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; X64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; X64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; X64-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
- ; X64-NEXT: $ax = COPY [[AND]](s16)
- ; X64-NEXT: RET 0, implicit $ax
+ ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; X64: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; X64: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; X64: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
+ ; X64: $ax = COPY [[AND]](s16)
+ ; X64: RET 0, implicit $ax
%1:_(s32) = COPY $edi
%0:_(s1) = G_TRUNC %1(s32)
%2:_(s16) = G_ZEXT %0(s1)
@@ -181,24 +171,19 @@ body: |
liveins: $edi
; X32-LABEL: name: test_zext_i1
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
- ; X32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; X32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
- ; X32-NEXT: $eax = COPY [[AND]](s32)
- ; X32-NEXT: RET 0, implicit $eax
- ;
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; X32: $eax = COPY [[AND]](s32)
+ ; X32: RET 0, implicit $eax
; X64-LABEL: name: test_zext_i1
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X64-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
- ; X64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; X64-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
- ; X64-NEXT: $eax = COPY [[AND]](s32)
- ; X64-NEXT: RET 0, implicit $eax
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X64: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; X64: $eax = COPY [[AND]](s32)
+ ; X64: RET 0, implicit $eax
%0(s8) = COPY $dil
%1(s1) = G_TRUNC %0(s8)
%2(s32) = G_ZEXT %1(s1)
@@ -219,20 +204,15 @@ body: |
liveins: $edi
; X32-LABEL: name: test_zext_i8toi16
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X32-NEXT: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s8)
- ; X32-NEXT: $ax = COPY [[ZEXT]](s16)
- ; X32-NEXT: RET 0, implicit $ax
- ;
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X32: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s8)
+ ; X32: $ax = COPY [[ZEXT]](s16)
+ ; X32: RET 0, implicit $ax
; X64-LABEL: name: test_zext_i8toi16
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X64-NEXT: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s8)
- ; X64-NEXT: $ax = COPY [[ZEXT]](s16)
- ; X64-NEXT: RET 0, implicit $ax
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X64: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s8)
+ ; X64: $ax = COPY [[ZEXT]](s16)
+ ; X64: RET 0, implicit $ax
%0(s8) = COPY $dil
%1(s16) = G_ZEXT %0(s8)
$ax = COPY %1(s16)
@@ -252,20 +232,15 @@ body: |
liveins: $edi
; X32-LABEL: name: test_zext_i8
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X32-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s8)
- ; X32-NEXT: $eax = COPY [[ZEXT]](s32)
- ; X32-NEXT: RET 0, implicit $eax
- ;
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X32: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s8)
+ ; X32: $eax = COPY [[ZEXT]](s32)
+ ; X32: RET 0, implicit $eax
; X64-LABEL: name: test_zext_i8
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X64-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s8)
- ; X64-NEXT: $eax = COPY [[ZEXT]](s32)
- ; X64-NEXT: RET 0, implicit $eax
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X64: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s8)
+ ; X64: $eax = COPY [[ZEXT]](s32)
+ ; X64: RET 0, implicit $eax
%0(s8) = COPY $dil
%1(s32) = G_ZEXT %0(s8)
$eax = COPY %1(s32)
@@ -285,20 +260,15 @@ body: |
liveins: $edi
; X32-LABEL: name: test_zext_i16
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di
- ; X32-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s16)
- ; X32-NEXT: $eax = COPY [[ZEXT]](s32)
- ; X32-NEXT: RET 0, implicit $eax
- ;
+ ; X32: [[COPY:%[0-9]+]]:_(s16) = COPY $di
+ ; X32: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s16)
+ ; X32: $eax = COPY [[ZEXT]](s32)
+ ; X32: RET 0, implicit $eax
; X64-LABEL: name: test_zext_i16
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di
- ; X64-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s16)
- ; X64-NEXT: $eax = COPY [[ZEXT]](s32)
- ; X64-NEXT: RET 0, implicit $eax
+ ; X64: [[COPY:%[0-9]+]]:_(s16) = COPY $di
+ ; X64: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s16)
+ ; X64: $eax = COPY [[ZEXT]](s32)
+ ; X64: RET 0, implicit $eax
%0(s16) = COPY $di
%1(s32) = G_ZEXT %0(s16)
$eax = COPY %1(s32)
@@ -318,18 +288,13 @@ body: |
liveins: $edi
; X32-LABEL: name: test_sext_i1toi8
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
- ; X32-NEXT: $al = COPY [[C]](s8)
- ; X32-NEXT: RET 0, implicit $al
- ;
+ ; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
+ ; X32: $al = COPY [[C]](s8)
+ ; X32: RET 0, implicit $al
; X64-LABEL: name: test_sext_i1toi8
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
- ; X64-NEXT: $al = COPY [[C]](s8)
- ; X64-NEXT: RET 0, implicit $al
+ ; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
+ ; X64: $al = COPY [[C]](s8)
+ ; X64: RET 0, implicit $al
%0(s1) = G_IMPLICIT_DEF
%1(s8) = G_SEXT %0(s1)
$al = COPY %1(s8)
@@ -349,18 +314,13 @@ body: |
liveins: $edi
; X32-LABEL: name: test_sext_i1toi16
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; X32-NEXT: $ax = COPY [[C]](s16)
- ; X32-NEXT: RET 0, implicit $ax
- ;
+ ; X32: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+ ; X32: $ax = COPY [[C]](s16)
+ ; X32: RET 0, implicit $ax
; X64-LABEL: name: test_sext_i1toi16
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; X64-NEXT: $ax = COPY [[C]](s16)
- ; X64-NEXT: RET 0, implicit $ax
+ ; X64: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+ ; X64: $ax = COPY [[C]](s16)
+ ; X64: RET 0, implicit $ax
%0(s1) = G_IMPLICIT_DEF
%1(s16) = G_SEXT %0(s1)
$ax = COPY %1(s16)
@@ -381,18 +341,13 @@ body: |
liveins: $edi
; X32-LABEL: name: test_sext_i1
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; X32-NEXT: $eax = COPY [[C]](s32)
- ; X32-NEXT: RET 0, implicit $eax
- ;
+ ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; X32: $eax = COPY [[C]](s32)
+ ; X32: RET 0, implicit $eax
; X64-LABEL: name: test_sext_i1
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; X64-NEXT: $eax = COPY [[C]](s32)
- ; X64-NEXT: RET 0, implicit $eax
+ ; X64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; X64: $eax = COPY [[C]](s32)
+ ; X64: RET 0, implicit $eax
%0(s1) = G_IMPLICIT_DEF
%2(s32) = G_SEXT %0(s1)
$eax = COPY %2(s32)
@@ -412,20 +367,15 @@ body: |
liveins: $edi
; X32-LABEL: name: test_sext_i8toi16
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X32-NEXT: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[COPY]](s8)
- ; X32-NEXT: $ax = COPY [[SEXT]](s16)
- ; X32-NEXT: RET 0, implicit $ax
- ;
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X32: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[COPY]](s8)
+ ; X32: $ax = COPY [[SEXT]](s16)
+ ; X32: RET 0, implicit $ax
; X64-LABEL: name: test_sext_i8toi16
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X64-NEXT: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[COPY]](s8)
- ; X64-NEXT: $ax = COPY [[SEXT]](s16)
- ; X64-NEXT: RET 0, implicit $ax
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X64: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[COPY]](s8)
+ ; X64: $ax = COPY [[SEXT]](s16)
+ ; X64: RET 0, implicit $ax
%0(s8) = COPY $dil
%1(s16) = G_SEXT %0(s8)
$ax = COPY %1(s16)
@@ -445,20 +395,15 @@ body: |
liveins: $edi
; X32-LABEL: name: test_sext_i8
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X32-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s8)
- ; X32-NEXT: $eax = COPY [[SEXT]](s32)
- ; X32-NEXT: RET 0, implicit $eax
- ;
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s8)
+ ; X32: $eax = COPY [[SEXT]](s32)
+ ; X32: RET 0, implicit $eax
; X64-LABEL: name: test_sext_i8
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X64-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s8)
- ; X64-NEXT: $eax = COPY [[SEXT]](s32)
- ; X64-NEXT: RET 0, implicit $eax
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X64: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s8)
+ ; X64: $eax = COPY [[SEXT]](s32)
+ ; X64: RET 0, implicit $eax
%0(s8) = COPY $dil
%1(s32) = G_SEXT %0(s8)
$eax = COPY %1(s32)
@@ -478,20 +423,15 @@ body: |
liveins: $edi
; X32-LABEL: name: test_sext_i16
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di
- ; X32-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s16)
- ; X32-NEXT: $eax = COPY [[SEXT]](s32)
- ; X32-NEXT: RET 0, implicit $eax
- ;
+ ; X32: [[COPY:%[0-9]+]]:_(s16) = COPY $di
+ ; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s16)
+ ; X32: $eax = COPY [[SEXT]](s32)
+ ; X32: RET 0, implicit $eax
; X64-LABEL: name: test_sext_i16
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di
- ; X64-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s16)
- ; X64-NEXT: $eax = COPY [[SEXT]](s32)
- ; X64-NEXT: RET 0, implicit $eax
+ ; X64: [[COPY:%[0-9]+]]:_(s16) = COPY $di
+ ; X64: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s16)
+ ; X64: $eax = COPY [[SEXT]](s32)
+ ; X64: RET 0, implicit $eax
%0(s16) = COPY $di
%1(s32) = G_SEXT %0(s16)
$eax = COPY %1(s32)
@@ -512,20 +452,15 @@ body: |
liveins: $edi
; X32-LABEL: name: test_anyext_i1toi8
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; X32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; X32-NEXT: $al = COPY [[TRUNC]](s8)
- ; X32-NEXT: RET 0, implicit $al
- ;
+ ; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; X32: $al = COPY [[TRUNC]](s8)
+ ; X32: RET 0, implicit $al
; X64-LABEL: name: test_anyext_i1toi8
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; X64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; X64-NEXT: $al = COPY [[TRUNC]](s8)
- ; X64-NEXT: RET 0, implicit $al
+ ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; X64: $al = COPY [[TRUNC]](s8)
+ ; X64: RET 0, implicit $al
%0(s32) = COPY $edi
%1(s1) = G_TRUNC %0(s32)
%2(s8) = G_ANYEXT %1(s1)
@@ -547,20 +482,15 @@ body: |
liveins: $edi
; X32-LABEL: name: test_anyext_i1toi16
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; X32-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; X32-NEXT: $ax = COPY [[TRUNC]](s16)
- ; X32-NEXT: RET 0, implicit $ax
- ;
+ ; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; X32: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; X32: $ax = COPY [[TRUNC]](s16)
+ ; X32: RET 0, implicit $ax
; X64-LABEL: name: test_anyext_i1toi16
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; X64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; X64-NEXT: $ax = COPY [[TRUNC]](s16)
- ; X64-NEXT: RET 0, implicit $ax
+ ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; X64: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; X64: $ax = COPY [[TRUNC]](s16)
+ ; X64: RET 0, implicit $ax
%0(s32) = COPY $edi
%1(s1) = G_TRUNC %0(s32)
%2(s16) = G_ANYEXT %1(s1)
@@ -582,20 +512,15 @@ body: |
liveins: $edi
; X32-LABEL: name: test_anyext_i1
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
- ; X32-NEXT: $eax = COPY [[ANYEXT]](s32)
- ; X32-NEXT: RET 0, implicit $eax
- ;
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X32: $eax = COPY [[ANYEXT]](s32)
+ ; X32: RET 0, implicit $eax
; X64-LABEL: name: test_anyext_i1
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X64-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
- ; X64-NEXT: $eax = COPY [[ANYEXT]](s32)
- ; X64-NEXT: RET 0, implicit $eax
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X64: $eax = COPY [[ANYEXT]](s32)
+ ; X64: RET 0, implicit $eax
%0(s8) = COPY $dil
%1(s1) = G_TRUNC %0(s8)
%2(s32) = G_ANYEXT %1(s1)
@@ -616,20 +541,15 @@ body: |
liveins: $edi
; X32-LABEL: name: test_anyext_i8toi16
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X32-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
- ; X32-NEXT: $ax = COPY [[ANYEXT]](s16)
- ; X32-NEXT: RET 0, implicit $ax
- ;
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
+ ; X32: $ax = COPY [[ANYEXT]](s16)
+ ; X32: RET 0, implicit $ax
; X64-LABEL: name: test_anyext_i8toi16
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X64-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
- ; X64-NEXT: $ax = COPY [[ANYEXT]](s16)
- ; X64-NEXT: RET 0, implicit $ax
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
+ ; X64: $ax = COPY [[ANYEXT]](s16)
+ ; X64: RET 0, implicit $ax
%0(s8) = COPY $dil
%1(s16) = G_ANYEXT %0(s8)
$ax = COPY %1(s16)
@@ -649,20 +569,15 @@ body: |
liveins: $edi
; X32-LABEL: name: test_anyext_i8
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
- ; X32-NEXT: $eax = COPY [[ANYEXT]](s32)
- ; X32-NEXT: RET 0, implicit $eax
- ;
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X32: $eax = COPY [[ANYEXT]](s32)
+ ; X32: RET 0, implicit $eax
; X64-LABEL: name: test_anyext_i8
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
- ; X64-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
- ; X64-NEXT: $eax = COPY [[ANYEXT]](s32)
- ; X64-NEXT: RET 0, implicit $eax
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X64: $eax = COPY [[ANYEXT]](s32)
+ ; X64: RET 0, implicit $eax
%0(s8) = COPY $dil
%1(s32) = G_ANYEXT %0(s8)
$eax = COPY %1(s32)
@@ -682,20 +597,15 @@ body: |
liveins: $edi
; X32-LABEL: name: test_anyext_i16
- ; X32: liveins: $edi
- ; X32-NEXT: {{ $}}
- ; X32-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di
- ; X32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s16)
- ; X32-NEXT: $eax = COPY [[ANYEXT]](s32)
- ; X32-NEXT: RET 0, implicit $eax
- ;
+ ; X32: [[COPY:%[0-9]+]]:_(s16) = COPY $di
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s16)
+ ; X32: $eax = COPY [[ANYEXT]](s32)
+ ; X32: RET 0, implicit $eax
; X64-LABEL: name: test_anyext_i16
- ; X64: liveins: $edi
- ; X64-NEXT: {{ $}}
- ; X64-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $di
- ; X64-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s16)
- ; X64-NEXT: $eax = COPY [[ANYEXT]](s32)
- ; X64-NEXT: RET 0, implicit $eax
+ ; X64: [[COPY:%[0-9]+]]:_(s16) = COPY $di
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s16)
+ ; X64: $eax = COPY [[ANYEXT]](s32)
+ ; X64: RET 0, implicit $eax
%0(s16) = COPY $di
%1(s32) = G_ANYEXT %0(s16)
$eax = COPY %1(s32)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir
index 9807d13e3235a36..059479323079072 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir
@@ -21,7 +21,6 @@ body: |
; X64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738367
; X64-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[CTTZ_ZERO_UNDEF]], [[C1]]
; X64-NEXT: RET 0, implicit [[AND]](s64)
- ;
; X86-LABEL: name: test_cttz35
; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X86-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -35,8 +34,8 @@ body: |
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C2]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
; X86-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
- ; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF1]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
@@ -89,7 +88,6 @@ body: |
; X64-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_UNDEF [[DEF]](s64)
; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[CTTZ_ZERO_UNDEF]](s64)
; X64-NEXT: RET 0, implicit [[COPY]](s64)
- ;
; X86-LABEL: name: test_cttz64
; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
@@ -100,8 +98,8 @@ body: |
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C1]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
; X86-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV]](s32)
- ; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF1]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir
index e2d10423dbec51c..9459b2ff19dac2f 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir
@@ -21,7 +21,6 @@ body: |
; X64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738367
; X64-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[CTTZ_ZERO_UNDEF]], [[C1]]
; X64-NEXT: RET 0, implicit [[AND]](s64)
- ;
; X86-LABEL: name: test_cttz35
; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X86-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -35,8 +34,8 @@ body: |
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C2]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
; X86-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
- ; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF1]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
@@ -91,7 +90,6 @@ body: |
; X64-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[DEF]](s64)
; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[CTTZ]](s64)
; X64-NEXT: RET 0, implicit [[COPY]](s64)
- ;
; X86-LABEL: name: test_cttz64
; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
@@ -102,8 +100,8 @@ body: |
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ]], [[C1]]
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV]](s32)
- ; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-trunc.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-trunc.mir
index 9a2414a4eb7558b..e0fcce270e27451 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-trunc.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-trunc.mir
@@ -18,29 +18,28 @@ body: |
bb.1 (%ir-block.0):
; X32-LABEL: name: trunc_check
; X32: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
- ; X32-NEXT: [[DEF1:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; X32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
- ; X32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
- ; X32-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
- ; X32-NEXT: G_STORE [[AND]](s8), [[DEF1]](p0) :: (store (s1))
- ; X32-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
- ; X32-NEXT: G_STORE [[TRUNC1]](s8), [[DEF1]](p0) :: (store (s8))
- ; X32-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
- ; X32-NEXT: G_STORE [[TRUNC2]](s16), [[DEF1]](p0) :: (store (s16))
- ; X32-NEXT: RET 0
- ;
+ ; X32: [[DEF1:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+ ; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
+ ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
+ ; X32: G_STORE [[AND]](s8), [[DEF1]](p0) :: (store (s1))
+ ; X32: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
+ ; X32: G_STORE [[TRUNC1]](s8), [[DEF1]](p0) :: (store (s8))
+ ; X32: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
+ ; X32: G_STORE [[TRUNC2]](s16), [[DEF1]](p0) :: (store (s16))
+ ; X32: RET 0
; X64-LABEL: name: trunc_check
; X64: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
- ; X64-NEXT: [[DEF1:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
- ; X64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
- ; X64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
- ; X64-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
- ; X64-NEXT: G_STORE [[AND]](s8), [[DEF1]](p0) :: (store (s1))
- ; X64-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
- ; X64-NEXT: G_STORE [[TRUNC1]](s8), [[DEF1]](p0) :: (store (s8))
- ; X64-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
- ; X64-NEXT: G_STORE [[TRUNC2]](s16), [[DEF1]](p0) :: (store (s16))
- ; X64-NEXT: RET 0
+ ; X64: [[DEF1:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+ ; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
+ ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
+ ; X64: G_STORE [[AND]](s8), [[DEF1]](p0) :: (store (s1))
+ ; X64: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
+ ; X64: G_STORE [[TRUNC1]](s8), [[DEF1]](p0) :: (store (s8))
+ ; X64: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
+ ; X64: G_STORE [[TRUNC2]](s16), [[DEF1]](p0) :: (store (s16))
+ ; X64: RET 0
%0(s32) = IMPLICIT_DEF
%1(s1) = G_TRUNC %0(s32)
%4:_(p0) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll b/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
index 8a6215e07ebf6d0..fe5c78cd0767f33 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
@@ -165,7 +165,8 @@ define i1 @test_lshr_i1_imm1(i32 %arg1) {
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andb $1, %al
-; X64-NEXT: shrb %al
+; X64-NEXT: movb $1, %cl
+; X64-NEXT: shrb %cl, %al
; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
%a = trunc i32 %arg1 to i1
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir
index e3074c3e01f5475..b071c29e0d1970a 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir
@@ -68,13 +68,12 @@ body: |
; CHECK-LABEL: name: zext_i1_to_i8
; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: $al = COPY [[AND]](s8)
- ; CHECK-NEXT: RET 0, implicit $al
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
+ ; CHECK: $al = COPY [[AND]](s8)
+ ; CHECK: RET 0, implicit $al
%1:_(s32) = COPY $edi
%0:_(s1) = G_TRUNC %1(s32)
%2:_(s8) = G_ZEXT %0(s1)
@@ -96,13 +95,12 @@ body: |
; CHECK-LABEL: name: zext_i1_to_i16
; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: $ax = COPY [[AND]](s16)
- ; CHECK-NEXT: RET 0, implicit $ax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
+ ; CHECK: $ax = COPY [[AND]](s16)
+ ; CHECK: RET 0, implicit $ax
%1:_(s32) = COPY $edi
%0:_(s1) = G_TRUNC %1(s32)
%2:_(s16) = G_ZEXT %0(s1)
@@ -124,12 +122,11 @@ body: |
; CHECK-LABEL: name: zext_i1_to_i32
; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK-NEXT: $eax = COPY [[AND]](s32)
- ; CHECK-NEXT: RET 0, implicit $eax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: $eax = COPY [[AND]](s32)
+ ; CHECK: RET 0, implicit $eax
%1:_(s32) = COPY $edi
%0:_(s1) = G_TRUNC %1(s32)
%2:_(s32) = G_ZEXT %0(s1)
@@ -151,13 +148,12 @@ body: |
; CHECK-LABEL: name: zext_i1_to_i64
; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: $rax = COPY [[AND]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK: $rax = COPY [[AND]](s64)
+ ; CHECK: RET 0, implicit $rax
%1:_(s32) = COPY $edi
%0:_(s1) = G_TRUNC %1(s32)
%2:_(s64) = G_ZEXT %0(s1)
@@ -179,13 +175,12 @@ body: |
; CHECK-LABEL: name: zext_i8_to_i16
; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
- ; CHECK-NEXT: $ax = COPY [[AND]](s16)
- ; CHECK-NEXT: RET 0, implicit $ax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
+ ; CHECK: $ax = COPY [[AND]](s16)
+ ; CHECK: RET 0, implicit $ax
%1:_(s32) = COPY $edi
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s16) = G_ZEXT %0(s8)
@@ -207,12 +202,11 @@ body: |
; CHECK-LABEL: name: zext_i8_to_i32
; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK-NEXT: $eax = COPY [[AND]](s32)
- ; CHECK-NEXT: RET 0, implicit $eax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: $eax = COPY [[AND]](s32)
+ ; CHECK: RET 0, implicit $eax
%1:_(s32) = COPY $edi
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s32) = G_ZEXT %0(s8)
@@ -234,13 +228,12 @@ body: |
; CHECK-LABEL: name: zext_i8_to_i64
; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: $rax = COPY [[AND]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK: $rax = COPY [[AND]](s64)
+ ; CHECK: RET 0, implicit $rax
%1:_(s32) = COPY $edi
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s64) = G_ZEXT %0(s8)
@@ -262,12 +255,11 @@ body: |
; CHECK-LABEL: name: zext_i16_to_i32
; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK-NEXT: $eax = COPY [[AND]](s32)
- ; CHECK-NEXT: RET 0, implicit $eax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: $eax = COPY [[AND]](s32)
+ ; CHECK: RET 0, implicit $eax
%1:_(s32) = COPY $edi
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s32) = G_ZEXT %0(s16)
@@ -289,13 +281,12 @@ body: |
; CHECK-LABEL: name: zext_i16_to_i64
; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: $rax = COPY [[AND]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK: $rax = COPY [[AND]](s64)
+ ; CHECK: RET 0, implicit $rax
%1:_(s32) = COPY $edi
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s64) = G_ZEXT %0(s16)
@@ -316,11 +307,10 @@ body: |
; CHECK-LABEL: name: zext_i32_to_i64
; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
- ; CHECK-NEXT: $rax = COPY [[ZEXT]](s64)
- ; CHECK-NEXT: RET 0, implicit $rax
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
+ ; CHECK: $rax = COPY [[ZEXT]](s64)
+ ; CHECK: RET 0, implicit $rax
%0:_(s32) = COPY $edi
%1:_(s64) = G_ZEXT %0(s32)
$rax = COPY %1(s64)
diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
index 401d04954a669a4..b829df42dc401d3 100644
--- a/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
@@ -212,8 +212,8 @@ TEST_F(AArch64GISelMITest, UnorderedArtifactCombiningManyCopiesTest) {
CHECK-NEXT: [[OFFSET_1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
CHECK-NEXT: [[VPTR_1:%[0-9]+]]:_(p0) = G_PTR_ADD %vptr:_, [[OFFSET_1]]:_(s64)
CHECK-NEXT: [[LOAD_1:%[0-9]+]]:_(s16) = G_LOAD [[VPTR_1]]:_(p0) :: (load (s8) from unknown-address + 1)
- CHECK-NEXT: [[V0_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD_0]]:_(s16)
CHECK-NEXT: [[FF_MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ CHECK-NEXT: [[V0_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD_0]]:_(s16)
CHECK-NEXT: %v0_zext:_(s32) = G_AND [[V0_EXT]]:_, [[FF_MASK]]:_
CHECK-NEXT: [[V1_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD_1]]:_(s16)
CHECK-NEXT: [[SHAMNT:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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