[llvm] extend the computeOverflowForSignedSub/computeOverflowForUnsignedSub implementations with ConstantRange, and add tests (PR #67724)
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Thu Sep 28 11:58:10 PDT 2023
https://github.com/elhewaty created https://github.com/llvm/llvm-project/pull/67724
None
>From ce60f1d42d79151dfcf604a6ed056f27e5f4ccae Mon Sep 17 00:00:00 2001
From: Mohamed Atef <mohamedatef1698 at gmail.com>
Date: Thu, 28 Sep 2023 21:47:52 +0300
Subject: [PATCH] extend the
computeOverflowForSignedSub/computeOverflowForUnsignedSub implementations
with ConstantRange, and add tests
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 14 ++-
llvm/test/CodeGen/X86/combine-subo.ll | 106 ++++++++++++++++++
llvm/test/CodeGen/X86/or-with-overflow.ll | 12 +-
3 files changed, 119 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index cd21af770e1a4d9..0a61920b7c079ba 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4091,8 +4091,11 @@ SelectionDAG::computeOverflowForSignedSub(SDValue N0, SDValue N1) const {
if (ComputeNumSignBits(N0) > 1 && ComputeNumSignBits(N1) > 1)
return OFK_Never;
- // TODO: Add ConstantRange::signedSubMayOverflow handling.
- return OFK_Sometime;
+ KnownBits N0Known = computeKnownBits(N0);
+ KnownBits N1Known = computeKnownBits(N1);
+ ConstantRange N0Range = ConstantRange::fromKnownBits(N0Known, true);
+ ConstantRange N1Range = ConstantRange::fromKnownBits(N1Known, true);
+ return mapOverflowResult(N0Range.signedSubMayOverflow(N1Range));
}
SelectionDAG::OverflowKind
@@ -4101,8 +4104,11 @@ SelectionDAG::computeOverflowForUnsignedSub(SDValue N0, SDValue N1) const {
if (isNullConstant(N1))
return OFK_Never;
- // TODO: Add ConstantRange::unsignedSubMayOverflow handling.
- return OFK_Sometime;
+ KnownBits N0Known = computeKnownBits(N0);
+ KnownBits N1Known = computeKnownBits(N1);
+ ConstantRange N0Range = ConstantRange::fromKnownBits(N0Known, false);
+ ConstantRange N1Range = ConstantRange::fromKnownBits(N1Known, false);
+ return mapOverflowResult(N0Range.unsignedSubMayOverflow(N1Range));
}
SelectionDAG::OverflowKind
diff --git a/llvm/test/CodeGen/X86/combine-subo.ll b/llvm/test/CodeGen/X86/combine-subo.ll
index 5113c95f9208207..be9bd8ce5027f82 100644
--- a/llvm/test/CodeGen/X86/combine-subo.ll
+++ b/llvm/test/CodeGen/X86/combine-subo.ll
@@ -4,9 +4,12 @@
declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
+declare { i8, i1 } @llvm.usub.with.overflow.i8(i8, i8) nounwind readnone
+declare { i8, i1 } @llvm.ssub.with.overflow.i8(i8, i8) nounwind readnone
declare {<4 x i32>, <4 x i1>} @llvm.ssub.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
declare {<4 x i32>, <4 x i1>} @llvm.usub.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare { <4 x i8>, <4 x i1> } @llvm.usub.with.overflow.v4i8(<4 x i8>, <4 x i8>) nounwind readnone
; fold (ssub x, 0) -> x
define i32 @combine_ssub_zero(i32 %a0, i32 %a1) {
@@ -182,3 +185,106 @@ define <4 x i32> @combine_vec_usub_negone(<4 x i32> %a0, <4 x i32> %a1) {
%4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2
ret <4 x i32> %4
}
+
+define { i32, i1 } @combine_usub_nuw(i32 %a, i32 %b) {
+; SSE-LABEL: combine_usub_nuw:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: orl $-2147483648, %eax # imm = 0x80000000
+; SSE-NEXT: andl $2147483647, %esi # imm = 0x7FFFFFFF
+; SSE-NEXT: subl %esi, %eax
+; SSE-NEXT: xorl %edx, %edx
+; SSE-NEXT: retq
+;
+; AVX-LABEL: combine_usub_nuw:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: orl $-2147483648, %eax # imm = 0x80000000
+; AVX-NEXT: andl $2147483647, %esi # imm = 0x7FFFFFFF
+; AVX-NEXT: subl %esi, %eax
+; AVX-NEXT: xorl %edx, %edx
+; AVX-NEXT: retq
+ %aa = or i32 %a, 2147483648
+ %bb = and i32 %b, 2147483647
+ %x = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %aa, i32 %bb)
+ ret { i32, i1 } %x
+}
+
+define { i8, i1 } @usub_always_overflow(i8 %x) nounwind {
+; SSE-LABEL: usub_always_overflow:
+; SSE: # %bb.0:
+; SSE-NEXT: orb $64, %dil
+; SSE-NEXT: movb $63, %al
+; SSE-NEXT: subb %dil, %al
+; SSE-NEXT: setb %dl
+; SSE-NEXT: retq
+;
+; AVX-LABEL: usub_always_overflow:
+; AVX: # %bb.0:
+; AVX-NEXT: orb $64, %dil
+; AVX-NEXT: movb $63, %al
+; AVX-NEXT: subb %dil, %al
+; AVX-NEXT: setb %dl
+; AVX-NEXT: retq
+ %y = or i8 %x, 64
+ %a = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 63, i8 %y)
+ ret { i8, i1 } %a
+}
+
+define { i8, i1 } @ssub_always_overflow(i8 %x) nounwind {
+; SSE-LABEL: ssub_always_overflow:
+; SSE: # %bb.0:
+; SSE-NEXT: cmpb $30, %dil
+; SSE-NEXT: movl $29, %ecx
+; SSE-NEXT: cmovgel %edi, %ecx
+; SSE-NEXT: movb $-100, %al
+; SSE-NEXT: subb %cl, %al
+; SSE-NEXT: seto %dl
+; SSE-NEXT: retq
+;
+; AVX-LABEL: ssub_always_overflow:
+; AVX: # %bb.0:
+; AVX-NEXT: cmpb $30, %dil
+; AVX-NEXT: movl $29, %ecx
+; AVX-NEXT: cmovgel %edi, %ecx
+; AVX-NEXT: movb $-100, %al
+; AVX-NEXT: subb %cl, %al
+; AVX-NEXT: seto %dl
+; AVX-NEXT: retq
+ %c = icmp sgt i8 %x, 29
+ %y = select i1 %c, i8 %x, i8 29
+ %a = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 -100, i8 %y)
+ ret { i8, i1 } %a
+}
+
+define { <4 x i8>, <4 x i1> } @always_usub_const_vector() nounwind {
+; SSE-LABEL: always_usub_const_vector:
+; SSE: # %bb.0:
+; SSE-NEXT: pcmpeqd %xmm0, %xmm0
+; SSE-NEXT: pcmpeqd %xmm1, %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: always_usub_const_vector:
+; AVX: # %bb.0:
+; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX-NEXT: retq
+ %x = call { <4 x i8>, <4 x i1> } @llvm.usub.with.overflow.v4i8(<4 x i8> <i8 0, i8 0, i8 0, i8 0>, <4 x i8> <i8 1, i8 1, i8 1, i8 1>)
+ ret { <4 x i8>, <4 x i1> } %x
+}
+
+define { <4 x i8>, <4 x i1> } @never_usub_const_vector() nounwind {
+; SSE-LABEL: never_usub_const_vector:
+; SSE: # %bb.0:
+; SSE-NEXT: movaps {{.*#+}} xmm0 = <127,255,0,254,u,u,u,u,u,u,u,u,u,u,u,u>
+; SSE-NEXT: xorps %xmm1, %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: never_usub_const_vector:
+; AVX: # %bb.0:
+; AVX-NEXT: vbroadcastss {{.*#+}} xmm0 = [127,255,0,254,127,255,0,254,127,255,0,254,127,255,0,254]
+; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; AVX-NEXT: retq
+ %x = call { <4 x i8>, <4 x i1> } @llvm.usub.with.overflow.v4i8(<4 x i8> <i8 255, i8 255, i8 255, i8 255>, <4 x i8> <i8 128, i8 0, i8 255, i8 1>)
+ ret { <4 x i8>, <4 x i1> } %x
+}
diff --git a/llvm/test/CodeGen/X86/or-with-overflow.ll b/llvm/test/CodeGen/X86/or-with-overflow.ll
index 4440485af54bbaa..b3ffa209bc7004e 100644
--- a/llvm/test/CodeGen/X86/or-with-overflow.ll
+++ b/llvm/test/CodeGen/X86/or-with-overflow.ll
@@ -161,19 +161,13 @@ define i32 @or_i32_rr(i32 %0, i32 %1) {
define i64 @or_i64_ri(i64 %0, i64 %1) nounwind {
; X86-LABEL: or_i64_ri:
; X86: # %bb.0:
-; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: movl %eax, %ecx
-; X86-NEXT: orl $17, %ecx
-; X86-NEXT: cmpl $1, %ecx
-; X86-NEXT: movl %edx, %esi
-; X86-NEXT: sbbl $0, %esi
-; X86-NEXT: jl .LBB6_2
+; X86-NEXT: testl %edx, %edx
+; X86-NEXT: js .LBB6_2
; X86-NEXT: # %bb.1:
-; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: orl $17, %eax
; X86-NEXT: .LBB6_2:
-; X86-NEXT: popl %esi
; X86-NEXT: retl
;
; X64-LABEL: or_i64_ri:
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