[llvm] [RISCV] Add more prefetch tests (PR #67644)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 28 01:32:20 PDT 2023
https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/67644
We should be able to merge the offset later.
>From 8f18079edfb639a43b5632a2ac109ad12f7fa930 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Tue, 12 Sep 2023 19:17:49 +0800
Subject: [PATCH] [RISCV] Add more prefetch tests
We should be able to merge the offset later.
---
llvm/test/CodeGen/RISCV/prefetch.ll | 1262 ++++++++++++++++++++++++++-
1 file changed, 1261 insertions(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/RISCV/prefetch.ll b/llvm/test/CodeGen/RISCV/prefetch.ll
index 39732636d298b0f..42a86b99e2abe2e 100644
--- a/llvm/test/CodeGen/RISCV/prefetch.ll
+++ b/llvm/test/CodeGen/RISCV/prefetch.ll
@@ -5,7 +5,7 @@
; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv32 -mattr=+zicbop -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32ZICBOP %s
-; RUN: llc -mtriple=riscv64 -mattr=zicbop -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zicbop -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64ZICBOP %s
; RUN: llc -mtriple=riscv64 -mattr=+zicbop,+zihintntl -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64ZICBOPZIHINTNTL %s
@@ -345,3 +345,1263 @@ define void @test_prefetch_instruction_locality_3(ptr %a) nounwind {
call void @llvm.prefetch(ptr %a, i32 0, i32 3, i32 0)
ret void
}
+
+define void @test_prefetch_offsetable_0(ptr %a) nounwind {
+; RV32I-LABEL: test_prefetch_offsetable_0:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_offsetable_0:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_offsetable_0:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi a0, a0, 2016
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_offsetable_0:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi a0, a0, 2016
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_0:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 2016
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %addr = getelementptr i8, ptr %a, i64 2016
+ call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_offsetable_1(ptr %a) nounwind {
+; RV32I-LABEL: test_prefetch_offsetable_1:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_offsetable_1:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_offsetable_1:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi a0, a0, -2048
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_offsetable_1:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi a0, a0, -2048
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_1:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, -2048
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %addr = getelementptr i8, ptr %a, i64 -2048
+ call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_offsetable_2(ptr %a) nounwind {
+; RV32I-LABEL: test_prefetch_offsetable_2:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_offsetable_2:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_offsetable_2:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi a0, a0, 32
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_offsetable_2:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi a0, a0, 32
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_2:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 32
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %addr = getelementptr i8, ptr %a, i64 32
+ call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_offsetable_3(ptr %a) nounwind {
+; RV32I-LABEL: test_prefetch_offsetable_3:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_offsetable_3:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_offsetable_3:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi a0, a0, -32
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_offsetable_3:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi a0, a0, -32
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_3:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, -32
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %addr = getelementptr i8, ptr %a, i64 -32
+ call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_offsetable_4(ptr %a) nounwind {
+; RV32I-LABEL: test_prefetch_offsetable_4:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_offsetable_4:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_offsetable_4:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi a0, a0, 2047
+; RV32ZICBOP-NEXT: addi a0, a0, 1
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_offsetable_4:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi a0, a0, 2047
+; RV64ZICBOP-NEXT: addi a0, a0, 1
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_4:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 2047
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 1
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %addr = getelementptr i8, ptr %a, i64 2048
+ call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_offsetable_5(ptr %a) nounwind {
+; RV32I-LABEL: test_prefetch_offsetable_5:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_offsetable_5:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_offsetable_5:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi a0, a0, -2048
+; RV32ZICBOP-NEXT: addi a0, a0, -1
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_offsetable_5:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi a0, a0, -2048
+; RV64ZICBOP-NEXT: addi a0, a0, -1
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_5:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, -2048
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, -1
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %addr = getelementptr i8, ptr %a, i64 -2049
+ call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_offsetable_6(ptr %a) nounwind {
+; RV32I-LABEL: test_prefetch_offsetable_6:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_offsetable_6:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_offsetable_6:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi a0, a0, 16
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_offsetable_6:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi a0, a0, 16
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_6:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 16
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %addr = getelementptr i8, ptr %a, i64 16
+ call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_offsetable_7(ptr %a) nounwind {
+; RV32I-LABEL: test_prefetch_offsetable_7:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_offsetable_7:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_offsetable_7:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi a0, a0, -16
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_offsetable_7:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi a0, a0, -16
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_7:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, -16
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %addr = getelementptr i8, ptr %a, i64 -16
+ call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_offsetable_9(ptr %a) nounwind {
+; RV32I-LABEL: test_prefetch_offsetable_9:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_offsetable_9:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_offsetable_9:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a1, 1
+; RV32ZICBOP-NEXT: addi a1, a1, 64
+; RV32ZICBOP-NEXT: add a0, a0, a1
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_offsetable_9:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a1, 1
+; RV64ZICBOP-NEXT: addiw a1, a1, 64
+; RV64ZICBOP-NEXT: add a0, a0, a1
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_9:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a1, 1
+; RV64ZICBOPZIHINTNTL-NEXT: addiw a1, a1, 64
+; RV64ZICBOPZIHINTNTL-NEXT: add a0, a0, a1
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %addr = getelementptr i8, ptr %a, i64 4160
+ call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_offsetable_8(ptr %a) nounwind {
+; RV32I-LABEL: test_prefetch_offsetable_8:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_offsetable_8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_offsetable_8:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a1, 1048575
+; RV32ZICBOP-NEXT: addi a1, a1, -64
+; RV32ZICBOP-NEXT: add a0, a0, a1
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_offsetable_8:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a1, 1048575
+; RV64ZICBOP-NEXT: addiw a1, a1, -64
+; RV64ZICBOP-NEXT: add a0, a0, a1
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_8:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a1, 1048575
+; RV64ZICBOPZIHINTNTL-NEXT: addiw a1, a1, -64
+; RV64ZICBOPZIHINTNTL-NEXT: add a0, a0, a1
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %addr = getelementptr i8, ptr %a, i64 -4160
+ call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_frameindex_0() nounwind {
+; RV32I-LABEL: test_prefetch_frameindex_0:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -512
+; RV32I-NEXT: addi sp, sp, 512
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_frameindex_0:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -512
+; RV64I-NEXT: addi sp, sp, 512
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_frameindex_0:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi sp, sp, -512
+; RV32ZICBOP-NEXT: mv a0, sp
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: addi sp, sp, 512
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_frameindex_0:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi sp, sp, -512
+; RV64ZICBOP-NEXT: mv a0, sp
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: addi sp, sp, 512
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_0:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
+; RV64ZICBOPZIHINTNTL-NEXT: mv a0, sp
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %data = alloca [128 x i32], align 4
+ %base = bitcast [128 x i32]* %data to i8*
+ %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 0
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_frameindex_1() nounwind {
+; RV32I-LABEL: test_prefetch_frameindex_1:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a0, 1
+; RV32I-NEXT: addi a0, a0, 16
+; RV32I-NEXT: sub sp, sp, a0
+; RV32I-NEXT: lui a0, 1
+; RV32I-NEXT: addi a0, a0, 16
+; RV32I-NEXT: add sp, sp, a0
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_frameindex_1:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a0, 1
+; RV64I-NEXT: addiw a0, a0, 16
+; RV64I-NEXT: sub sp, sp, a0
+; RV64I-NEXT: lui a0, 1
+; RV64I-NEXT: addiw a0, a0, 16
+; RV64I-NEXT: add sp, sp, a0
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_frameindex_1:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a0, 1
+; RV32ZICBOP-NEXT: addi a0, a0, 16
+; RV32ZICBOP-NEXT: sub sp, sp, a0
+; RV32ZICBOP-NEXT: addi a0, sp, 16
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: lui a0, 1
+; RV32ZICBOP-NEXT: addi a0, a0, 16
+; RV32ZICBOP-NEXT: add sp, sp, a0
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_frameindex_1:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a0, 1
+; RV64ZICBOP-NEXT: addiw a0, a0, 16
+; RV64ZICBOP-NEXT: sub sp, sp, a0
+; RV64ZICBOP-NEXT: addi a0, sp, 16
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: lui a0, 1
+; RV64ZICBOP-NEXT: addiw a0, a0, 16
+; RV64ZICBOP-NEXT: add sp, sp, a0
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_1:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1
+; RV64ZICBOPZIHINTNTL-NEXT: addiw a0, a0, 16
+; RV64ZICBOPZIHINTNTL-NEXT: sub sp, sp, a0
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, 16
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1
+; RV64ZICBOPZIHINTNTL-NEXT: addiw a0, a0, 16
+; RV64ZICBOPZIHINTNTL-NEXT: add sp, sp, a0
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %data = alloca [1024 x i32], align 4
+ %ptr = bitcast [1024 x i32]* %data to i8*
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_frameindex_2() nounwind {
+; RV32I-LABEL: test_prefetch_frameindex_2:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -512
+; RV32I-NEXT: addi sp, sp, 512
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_frameindex_2:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -512
+; RV64I-NEXT: addi sp, sp, 512
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_frameindex_2:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi sp, sp, -512
+; RV32ZICBOP-NEXT: addi a0, sp, 16
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: addi sp, sp, 512
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_frameindex_2:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi sp, sp, -512
+; RV64ZICBOP-NEXT: addi a0, sp, 16
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: addi sp, sp, 512
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_2:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, 16
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %data = alloca [128 x i32], align 4
+ %base = bitcast [128 x i32]* %data to i8*
+ %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 4
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_frameindex_3() nounwind {
+; RV32I-LABEL: test_prefetch_frameindex_3:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -512
+; RV32I-NEXT: addi sp, sp, 512
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_frameindex_3:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -512
+; RV64I-NEXT: addi sp, sp, 512
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_frameindex_3:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi sp, sp, -512
+; RV32ZICBOP-NEXT: addi a0, sp, -16
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: addi sp, sp, 512
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_frameindex_3:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi sp, sp, -512
+; RV64ZICBOP-NEXT: addi a0, sp, -16
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: addi sp, sp, 512
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_3:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, -16
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %data = alloca [128 x i32], align 4
+ %base = bitcast [128 x i32]* %data to i8*
+ %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -4
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_frameindex_4() nounwind {
+; RV32I-LABEL: test_prefetch_frameindex_4:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -512
+; RV32I-NEXT: addi sp, sp, 512
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_frameindex_4:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -512
+; RV64I-NEXT: addi sp, sp, 512
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_frameindex_4:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi sp, sp, -512
+; RV32ZICBOP-NEXT: addi a0, sp, 32
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: addi sp, sp, 512
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_frameindex_4:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi sp, sp, -512
+; RV64ZICBOP-NEXT: addi a0, sp, 32
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: addi sp, sp, 512
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_4:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, 32
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %data = alloca [128 x i32], align 4
+ %base = bitcast [128 x i32]* %data to i8*
+ %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 8
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_frameindex_5() nounwind {
+; RV32I-LABEL: test_prefetch_frameindex_5:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -512
+; RV32I-NEXT: addi sp, sp, 512
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_frameindex_5:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -512
+; RV64I-NEXT: addi sp, sp, 512
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_frameindex_5:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi sp, sp, -512
+; RV32ZICBOP-NEXT: addi a0, sp, -32
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: addi sp, sp, 512
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_frameindex_5:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi sp, sp, -512
+; RV64ZICBOP-NEXT: addi a0, sp, -32
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: addi sp, sp, 512
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_5:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, -32
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %data = alloca [128 x i32], align 4
+ %base = bitcast [128 x i32]* %data to i8*
+ %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -8
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_frameindex_6() nounwind {
+; RV32I-LABEL: test_prefetch_frameindex_6:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -512
+; RV32I-NEXT: addi sp, sp, 512
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_frameindex_6:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -512
+; RV64I-NEXT: addi sp, sp, 512
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_frameindex_6:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi sp, sp, -512
+; RV32ZICBOP-NEXT: addi a0, sp, 2016
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: addi sp, sp, 512
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_frameindex_6:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi sp, sp, -512
+; RV64ZICBOP-NEXT: addi a0, sp, 2016
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: addi sp, sp, 512
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_6:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, 2016
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %data = alloca [128 x i32], align 4
+ %base = bitcast [128 x i32]* %data to i8*
+ %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 504
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_frameindex_7() nounwind {
+; RV32I-LABEL: test_prefetch_frameindex_7:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -512
+; RV32I-NEXT: addi sp, sp, 512
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_frameindex_7:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -512
+; RV64I-NEXT: addi sp, sp, 512
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_frameindex_7:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi sp, sp, -512
+; RV32ZICBOP-NEXT: addi a0, sp, -2048
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: addi sp, sp, 512
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_frameindex_7:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi sp, sp, -512
+; RV64ZICBOP-NEXT: addi a0, sp, -2048
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: addi sp, sp, 512
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_7:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, -2048
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %data = alloca [128 x i32], align 4
+ %base = bitcast [128 x i32]* %data to i8*
+ %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -512
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_frameindex_8() nounwind {
+; RV32I-LABEL: test_prefetch_frameindex_8:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -512
+; RV32I-NEXT: addi sp, sp, 512
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_frameindex_8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -512
+; RV64I-NEXT: addi sp, sp, 512
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_frameindex_8:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi sp, sp, -512
+; RV32ZICBOP-NEXT: addi a0, sp, 2020
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: addi sp, sp, 512
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_frameindex_8:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi sp, sp, -512
+; RV64ZICBOP-NEXT: addi a0, sp, 2020
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: addi sp, sp, 512
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_8:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, 2020
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %data = alloca [128 x i32], align 4
+ %base = bitcast [128 x i32]* %data to i8*
+ %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 505
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_frameindex_9() nounwind {
+; RV32I-LABEL: test_prefetch_frameindex_9:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -512
+; RV32I-NEXT: addi sp, sp, 512
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_frameindex_9:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -512
+; RV64I-NEXT: addi sp, sp, 512
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_frameindex_9:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: addi sp, sp, -512
+; RV32ZICBOP-NEXT: mv a0, sp
+; RV32ZICBOP-NEXT: addi a0, a0, -2048
+; RV32ZICBOP-NEXT: addi a0, a0, -4
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: addi sp, sp, 512
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_frameindex_9:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: addi sp, sp, -512
+; RV64ZICBOP-NEXT: mv a0, sp
+; RV64ZICBOP-NEXT: addi a0, a0, -2048
+; RV64ZICBOP-NEXT: addi a0, a0, -4
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: addi sp, sp, 512
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_9:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
+; RV64ZICBOPZIHINTNTL-NEXT: mv a0, sp
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, -2048
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, -4
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %data = alloca [128 x i32], align 4
+ %base = bitcast [128 x i32]* %data to i8*
+ %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -513
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_constant_address_0() nounwind {
+; RV32I-LABEL: test_prefetch_constant_address_0:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_constant_address_0:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_constant_address_0:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a0, 1
+; RV32ZICBOP-NEXT: addi a0, a0, 32
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_constant_address_0:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a0, 1
+; RV64ZICBOP-NEXT: addiw a0, a0, 32
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_constant_address_0:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1
+; RV64ZICBOPZIHINTNTL-NEXT: addiw a0, a0, 32
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %ptr = inttoptr i64 4128 to i8*
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_constant_address_1() nounwind {
+; RV32I-LABEL: test_prefetch_constant_address_1:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_constant_address_1:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_constant_address_1:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a0, 1
+; RV32ZICBOP-NEXT: addi a0, a0, 31
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_constant_address_1:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a0, 1
+; RV64ZICBOP-NEXT: addiw a0, a0, 31
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_constant_address_1:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1
+; RV64ZICBOPZIHINTNTL-NEXT: addiw a0, a0, 31
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %ptr = inttoptr i64 4127 to i8*
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_constant_address_2() nounwind {
+; RV32I-LABEL: test_prefetch_constant_address_2:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_constant_address_2:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_constant_address_2:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a0, 1048561
+; RV32ZICBOP-NEXT: addi a0, a0, 32
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_constant_address_2:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a0, 1048561
+; RV64ZICBOP-NEXT: addiw a0, a0, 32
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_constant_address_2:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1048561
+; RV64ZICBOPZIHINTNTL-NEXT: addiw a0, a0, 32
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %ptr = inttoptr i64 18446744073709490208 to i8*
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_constant_address_3() nounwind {
+; RV32I-LABEL: test_prefetch_constant_address_3:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_constant_address_3:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_constant_address_3:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a0, 1048561
+; RV32ZICBOP-NEXT: addi a0, a0, 31
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_constant_address_3:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a0, 1048561
+; RV64ZICBOP-NEXT: addiw a0, a0, 31
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_constant_address_3:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1048561
+; RV64ZICBOPZIHINTNTL-NEXT: addiw a0, a0, 31
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %ptr = inttoptr i64 18446744073709490207 to i8*
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+ at g = external global [1024 x i32], align 4
+
+define void @test_prefetch_global_0() nounwind {
+; RV32I-LABEL: test_prefetch_global_0:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_global_0:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_global_0:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a0, %hi(g)
+; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_global_0:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a0, %hi(g)
+; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_0:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g)
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g)
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 0
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_global_1() nounwind {
+; RV32I-LABEL: test_prefetch_global_1:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_global_1:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_global_1:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a0, %hi(g+16)
+; RV32ZICBOP-NEXT: addi a0, a0, %lo(g+16)
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_global_1:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a0, %hi(g+16)
+; RV64ZICBOP-NEXT: addi a0, a0, %lo(g+16)
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_1:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g+16)
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g+16)
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 4
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_global_2() nounwind {
+; RV32I-LABEL: test_prefetch_global_2:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_global_2:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_global_2:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a0, %hi(g-16)
+; RV32ZICBOP-NEXT: addi a0, a0, %lo(g-16)
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_global_2:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a0, %hi(g-16)
+; RV64ZICBOP-NEXT: addi a0, a0, %lo(g-16)
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_2:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g-16)
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g-16)
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 -4
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_global_3() nounwind {
+; RV32I-LABEL: test_prefetch_global_3:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_global_3:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_global_3:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a0, %hi(g+32)
+; RV32ZICBOP-NEXT: addi a0, a0, %lo(g+32)
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_global_3:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a0, %hi(g+32)
+; RV64ZICBOP-NEXT: addi a0, a0, %lo(g+32)
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_3:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g+32)
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g+32)
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 8
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_global_4() nounwind {
+; RV32I-LABEL: test_prefetch_global_4:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_global_4:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_global_4:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a0, %hi(g-32)
+; RV32ZICBOP-NEXT: addi a0, a0, %lo(g-32)
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_global_4:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a0, %hi(g-32)
+; RV64ZICBOP-NEXT: addi a0, a0, %lo(g-32)
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_4:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g-32)
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g-32)
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 -8
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_global_5() nounwind {
+; RV32I-LABEL: test_prefetch_global_5:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_global_5:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_global_5:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a0, %hi(g+2016)
+; RV32ZICBOP-NEXT: addi a0, a0, %lo(g+2016)
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_global_5:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a0, %hi(g+2016)
+; RV64ZICBOP-NEXT: addi a0, a0, %lo(g+2016)
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_5:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g+2016)
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g+2016)
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 504
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_global_6() nounwind {
+; RV32I-LABEL: test_prefetch_global_6:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_global_6:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_global_6:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a0, %hi(g-2048)
+; RV32ZICBOP-NEXT: addi a0, a0, %lo(g-2048)
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_global_6:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a0, %hi(g-2048)
+; RV64ZICBOP-NEXT: addi a0, a0, %lo(g-2048)
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_6:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g-2048)
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g-2048)
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 -512
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_global_7() nounwind {
+; RV32I-LABEL: test_prefetch_global_7:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_global_7:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_global_7:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a0, %hi(g+2020)
+; RV32ZICBOP-NEXT: addi a0, a0, %lo(g+2020)
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_global_7:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a0, %hi(g+2020)
+; RV64ZICBOP-NEXT: addi a0, a0, %lo(g+2020)
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_7:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g+2020)
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g+2020)
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 505
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @test_prefetch_global_8() nounwind {
+; RV32I-LABEL: test_prefetch_global_8:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_prefetch_global_8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ret
+;
+; RV32ZICBOP-LABEL: test_prefetch_global_8:
+; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: lui a0, %hi(g-2052)
+; RV32ZICBOP-NEXT: addi a0, a0, %lo(g-2052)
+; RV32ZICBOP-NEXT: prefetch.r 0(a0)
+; RV32ZICBOP-NEXT: ret
+;
+; RV64ZICBOP-LABEL: test_prefetch_global_8:
+; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: lui a0, %hi(g-2052)
+; RV64ZICBOP-NEXT: addi a0, a0, %lo(g-2052)
+; RV64ZICBOP-NEXT: prefetch.r 0(a0)
+; RV64ZICBOP-NEXT: ret
+;
+; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_8:
+; RV64ZICBOPZIHINTNTL: # %bb.0:
+; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g-2052)
+; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g-2052)
+; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
+; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
+; RV64ZICBOPZIHINTNTL-NEXT: ret
+ %ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 -513
+ call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+ ret void
+}
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