[llvm] [RISCV][WIP] Enable sink-and-fold for RISC-V. (PR #67602)

[Craig Topper via llvm-commits]

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@@ -275,7 +275,7 @@ bool RISCVInitUndef::processBasicBlock(MachineFunction &MF,
       Changed |= handleSubReg(MF, MI, DLD);
     if (MI.isImplicitDef()) {
       auto DstReg = MI.getOperand(0).getReg();
-      if (isVectorRegClass(DstReg))
+      if (DstReg.isVirtual() && isVectorRegClass(DstReg))
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topperc wrote:

The MachineSink change causes COPY and IMPLICIT_DEF to get merged, creating IMPLICIT_DEF with physical register Def. I'm assuming we don't need to worry about those since they shouldn't be used by a vector instruction.

https://github.com/llvm/llvm-project/pull/67602