[llvm] [RISCV] Support floating point VCIX (PR #67094)
Kito Cheng via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 25 14:17:09 PDT 2023
================
@@ -3006,3 +3006,2187 @@ entry:
}
declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.fv.nxv8i64.iXLen.f64.iXLen(iXLen, <vscale x 8 x i64>, double, iXLen)
+
+define void @test_f_sf_vc_vv_se_e16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_vv_se_e16mf4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: sf.vc.vv 3, 31, v8, v9
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv1f16.nxv1f16.iXLen(iXLen 3, iXLen 31, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, iXLen %vl)
+ ret void
+}
+
+declare void @llvm.riscv.sf.vc.vv.se.iXLen.nxv1f16.nxv1f16.iXLen(iXLen, iXLen, <vscale x 1 x half>, <vscale x 1 x half>, iXLen)
+
+define void @test_f_sf_vc_vv_se_e16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_vv_se_e16mf2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: sf.vc.vv 3, 31, v8, v9
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv2f16.nxv2f16.iXLen(iXLen 3, iXLen 31, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, iXLen %vl)
+ ret void
+}
+
+declare void @llvm.riscv.sf.vc.vv.se.iXLen.nxv2f16.nxv2f16.iXLen(iXLen, iXLen, <vscale x 2 x half>, <vscale x 2 x half>, iXLen)
+
+define void @test_f_sf_vc_vv_se_e16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_vv_se_e16m1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: sf.vc.vv 3, 31, v8, v9
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv4f16.nxv4f16.iXLen(iXLen 3, iXLen 31, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, iXLen %vl)
+ ret void
+}
+
+declare void @llvm.riscv.sf.vc.vv.se.iXLen.nxv4f16.nxv4f16.iXLen(iXLen, iXLen, <vscale x 4 x half>, <vscale x 4 x half>, iXLen)
+
+define void @test_f_sf_vc_vv_se_e16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_vv_se_e16m2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: sf.vc.vv 3, 31, v8, v10
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv8f16.nxv8f16.iXLen(iXLen 3, iXLen 31, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, iXLen %vl)
+ ret void
+}
+
+declare void @llvm.riscv.sf.vc.vv.se.iXLen.nxv8f16.nxv8f16.iXLen(iXLen, iXLen, <vscale x 8 x half>, <vscale x 8 x half>, iXLen)
+
+define void @test_f_sf_vc_vv_se_e16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_vv_se_e16m4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: sf.vc.vv 3, 31, v8, v12
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv16f16.nxv16f16.iXLen(iXLen 3, iXLen 31, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, iXLen %vl)
+ ret void
+}
+
+declare void @llvm.riscv.sf.vc.vv.se.iXLen.nxv16f16.nxv16f16.iXLen(iXLen, iXLen, <vscale x 16 x half>, <vscale x 16 x half>, iXLen)
+
+define void @test_f_sf_vc_vv_se_e16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_vv_se_e16m8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: sf.vc.vv 3, 31, v8, v16
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv32f16.nxv32f16.iXLen(iXLen 3, iXLen 31, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, iXLen %vl)
+ ret void
+}
+
+declare void @llvm.riscv.sf.vc.vv.se.iXLen.nxv32f16.nxv32f16.iXLen(iXLen, iXLen, <vscale x 32 x half>, <vscale x 32 x half>, iXLen)
+
+define void @test_f_sf_vc_vv_se_e32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_vv_se_e32mf2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: sf.vc.vv 3, 31, v8, v9
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv1f32.nxv1f32.iXLen(iXLen 3, iXLen 31, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, iXLen %vl)
+ ret void
+}
+
+declare void @llvm.riscv.sf.vc.vv.se.iXLen.nxv1f32.nxv1f32.iXLen(iXLen, iXLen, <vscale x 1 x float>, <vscale x 1 x float>, iXLen)
+
+define void @test_f_sf_vc_vv_se_e32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_vv_se_e32m1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: sf.vc.vv 3, 31, v8, v9
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv2f32.nxv2f32.iXLen(iXLen 3, iXLen 31, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, iXLen %vl)
+ ret void
+}
+
+declare void @llvm.riscv.sf.vc.vv.se.iXLen.nxv2f32.nxv2f32.iXLen(iXLen, iXLen, <vscale x 2 x float>, <vscale x 2 x float>, iXLen)
+
+define void @test_f_sf_vc_vv_se_e32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_vv_se_e32m2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: sf.vc.vv 3, 31, v8, v10
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv4f32.nxv4f32.iXLen(iXLen 3, iXLen 31, <vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, iXLen %vl)
+ ret void
+}
+
+declare void @llvm.riscv.sf.vc.vv.se.iXLen.nxv4f32.nxv4f32.iXLen(iXLen, iXLen, <vscale x 4 x float>, <vscale x 4 x float>, iXLen)
+
+define void @test_f_sf_vc_vv_se_e32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_vv_se_e32m4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: sf.vc.vv 3, 31, v8, v12
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv8f32.nxv8f32.iXLen(iXLen 3, iXLen 31, <vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, iXLen %vl)
+ ret void
+}
+
+declare void @llvm.riscv.sf.vc.vv.se.iXLen.nxv8f32.nxv8f32.iXLen(iXLen, iXLen, <vscale x 8 x float>, <vscale x 8 x float>, iXLen)
+
+define void @test_f_sf_vc_vv_se_e32m8(<vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_vv_se_e32m8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: sf.vc.vv 3, 31, v8, v16
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv16f32.nxv16f32.iXLen(iXLen 3, iXLen 31, <vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, iXLen %vl)
+ ret void
+}
+
+declare void @llvm.riscv.sf.vc.vv.se.iXLen.nxv16f32.nxv16f32.iXLen(iXLen, iXLen, <vscale x 16 x float>, <vscale x 16 x float>, iXLen)
+
+define void @test_f_sf_vc_vv_se_e64m1(<vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_vv_se_e64m1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: sf.vc.vv 3, 31, v8, v9
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv1f64.nxv1f64.iXLen(iXLen 3, iXLen 31, <vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, iXLen %vl)
+ ret void
+}
+
+declare void @llvm.riscv.sf.vc.vv.se.iXLen.nxv1f64.nxv1f64.iXLen(iXLen, iXLen, <vscale x 1 x double>, <vscale x 1 x double>, iXLen)
+
+define void @test_f_sf_vc_vv_se_e64m2(<vscale x 2 x double> %vs2, <vscale x 2 x double> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_vv_se_e64m2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: sf.vc.vv 3, 31, v8, v10
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv2f64.nxv2f64.iXLen(iXLen 3, iXLen 31, <vscale x 2 x double> %vs2, <vscale x 2 x double> %vs1, iXLen %vl)
+ ret void
+}
+
+declare void @llvm.riscv.sf.vc.vv.se.iXLen.nxv2f64.nxv2f64.iXLen(iXLen, iXLen, <vscale x 2 x double>, <vscale x 2 x double>, iXLen)
+
+define void @test_f_sf_vc_vv_se_e64m4(<vscale x 4 x double> %vs2, <vscale x 4 x double> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_vv_se_e64m4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: sf.vc.vv 3, 31, v8, v12
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv4f64.nxv4f64.iXLen(iXLen 3, iXLen 31, <vscale x 4 x double> %vs2, <vscale x 4 x double> %vs1, iXLen %vl)
+ ret void
+}
+
+declare void @llvm.riscv.sf.vc.vv.se.iXLen.nxv4f64.nxv4f64.iXLen(iXLen, iXLen, <vscale x 4 x double>, <vscale x 4 x double>, iXLen)
+
+define void @test_f_sf_vc_vv_se_e64m8(<vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_vv_se_e64m8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: sf.vc.vv 3, 31, v8, v16
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv8f64.nxv8f64.iXLen(iXLen 3, iXLen 31, <vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, iXLen %vl)
+ ret void
+}
+
+declare void @llvm.riscv.sf.vc.vv.se.iXLen.nxv8f64.nxv8f64.iXLen(iXLen, iXLen, <vscale x 8 x double>, <vscale x 8 x double>, iXLen)
+
+define <vscale x 1 x half> @test_f_sf_vc_v_vv_se_e16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_se_e16mf4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 1 x half> @llvm.riscv.sf.vc.v.vv.se.nxv1f16.iXLen.nxv1f16.iXLen(iXLen 3, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, iXLen %vl)
+ ret <vscale x 1 x half> %0
+}
+
+declare <vscale x 1 x half> @llvm.riscv.sf.vc.v.vv.se.nxv1f16.iXLen.nxv1f16.iXLen(iXLen, <vscale x 1 x half>, <vscale x 1 x half>, iXLen)
+
+define <vscale x 2 x half> @test_f_sf_vc_v_vv_se_e16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_se_e16mf2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 2 x half> @llvm.riscv.sf.vc.v.vv.se.nxv2f16.iXLen.nxv2f16.iXLen(iXLen 3, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, iXLen %vl)
+ ret <vscale x 2 x half> %0
+}
+
+declare <vscale x 2 x half> @llvm.riscv.sf.vc.v.vv.se.nxv2f16.iXLen.nxv2f16.iXLen(iXLen, <vscale x 2 x half>, <vscale x 2 x half>, iXLen)
+
+define <vscale x 4 x half> @test_f_sf_vc_v_vv_se_e16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_se_e16m1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 4 x half> @llvm.riscv.sf.vc.v.vv.se.nxv4f16.iXLen.nxv4f16.iXLen(iXLen 3, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, iXLen %vl)
+ ret <vscale x 4 x half> %0
+}
+
+declare <vscale x 4 x half> @llvm.riscv.sf.vc.v.vv.se.nxv4f16.iXLen.nxv4f16.iXLen(iXLen, <vscale x 4 x half>, <vscale x 4 x half>, iXLen)
+
+define <vscale x 8 x half> @test_f_sf_vc_v_vv_se_e16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_se_e16m2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v10
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 8 x half> @llvm.riscv.sf.vc.v.vv.se.nxv8f16.iXLen.nxv8f16.iXLen(iXLen 3, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, iXLen %vl)
+ ret <vscale x 8 x half> %0
+}
+
+declare <vscale x 8 x half> @llvm.riscv.sf.vc.v.vv.se.nxv8f16.iXLen.nxv8f16.iXLen(iXLen, <vscale x 8 x half>, <vscale x 8 x half>, iXLen)
+
+define <vscale x 16 x half> @test_f_sf_vc_v_vv_se_e16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_se_e16m4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v12
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 16 x half> @llvm.riscv.sf.vc.v.vv.se.nxv16f16.iXLen.nxv16f16.iXLen(iXLen 3, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, iXLen %vl)
+ ret <vscale x 16 x half> %0
+}
+
+declare <vscale x 16 x half> @llvm.riscv.sf.vc.v.vv.se.nxv16f16.iXLen.nxv16f16.iXLen(iXLen, <vscale x 16 x half>, <vscale x 16 x half>, iXLen)
+
+define <vscale x 32 x half> @test_f_sf_vc_v_vv_se_e16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_se_e16m8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v16
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 32 x half> @llvm.riscv.sf.vc.v.vv.se.nxv32f16.iXLen.nxv32f16.iXLen(iXLen 3, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, iXLen %vl)
+ ret <vscale x 32 x half> %0
+}
+
+declare <vscale x 32 x half> @llvm.riscv.sf.vc.v.vv.se.nxv32f16.iXLen.nxv32f16.iXLen(iXLen, <vscale x 32 x half>, <vscale x 32 x half>, iXLen)
+
+define <vscale x 1 x float> @test_f_sf_vc_v_vv_se_e32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_se_e32mf2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.vv.se.nxv1f32.iXLen.nxv1f32.iXLen(iXLen 3, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, iXLen %vl)
+ ret <vscale x 1 x float> %0
+}
+
+declare <vscale x 1 x float> @llvm.riscv.sf.vc.v.vv.se.nxv1f32.iXLen.nxv1f32.iXLen(iXLen, <vscale x 1 x float>, <vscale x 1 x float>, iXLen)
+
+define <vscale x 2 x float> @test_f_sf_vc_v_vv_se_e32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_se_e32m1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.vv.se.nxv2f32.iXLen.nxv2f32.iXLen(iXLen 3, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, iXLen %vl)
+ ret <vscale x 2 x float> %0
+}
+
+declare <vscale x 2 x float> @llvm.riscv.sf.vc.v.vv.se.nxv2f32.iXLen.nxv2f32.iXLen(iXLen, <vscale x 2 x float>, <vscale x 2 x float>, iXLen)
+
+define <vscale x 4 x float> @test_f_sf_vc_v_vv_se_e32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_se_e32m2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v10
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.vv.se.nxv4f32.iXLen.nxv4f32.iXLen(iXLen 3, <vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, iXLen %vl)
+ ret <vscale x 4 x float> %0
+}
+
+declare <vscale x 4 x float> @llvm.riscv.sf.vc.v.vv.se.nxv4f32.iXLen.nxv4f32.iXLen(iXLen, <vscale x 4 x float>, <vscale x 4 x float>, iXLen)
+
+define <vscale x 8 x float> @test_f_sf_vc_v_vv_se_e32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_se_e32m4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v12
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.vv.se.nxv8f32.iXLen.nxv8f32.iXLen(iXLen 3, <vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, iXLen %vl)
+ ret <vscale x 8 x float> %0
+}
+
+declare <vscale x 8 x float> @llvm.riscv.sf.vc.v.vv.se.nxv8f32.iXLen.nxv8f32.iXLen(iXLen, <vscale x 8 x float>, <vscale x 8 x float>, iXLen)
+
+define <vscale x 16 x float> @test_f_sf_vc_v_vv_se_e32m8(<vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_se_e32m8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v16
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.vv.se.nxv16f32.iXLen.nxv16f32.iXLen(iXLen 3, <vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, iXLen %vl)
+ ret <vscale x 16 x float> %0
+}
+
+declare <vscale x 16 x float> @llvm.riscv.sf.vc.v.vv.se.nxv16f32.iXLen.nxv16f32.iXLen(iXLen, <vscale x 16 x float>, <vscale x 16 x float>, iXLen)
+
+define <vscale x 1 x double> @test_f_sf_vc_v_vv_se_e64m1(<vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_se_e64m1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 1 x double> @llvm.riscv.sf.vc.v.vv.se.nxv1f64.iXLen.nxv1f64.iXLen(iXLen 3, <vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, iXLen %vl)
+ ret <vscale x 1 x double> %0
+}
+
+declare <vscale x 1 x double> @llvm.riscv.sf.vc.v.vv.se.nxv1f64.iXLen.nxv1f64.iXLen(iXLen, <vscale x 1 x double>, <vscale x 1 x double>, iXLen)
+
+define <vscale x 2 x double> @test_f_sf_vc_v_vv_se_e64m2(<vscale x 2 x double> %vs2, <vscale x 2 x double> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_se_e64m2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v10
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 2 x double> @llvm.riscv.sf.vc.v.vv.se.nxv2f64.iXLen.nxv2f64.iXLen(iXLen 3, <vscale x 2 x double> %vs2, <vscale x 2 x double> %vs1, iXLen %vl)
+ ret <vscale x 2 x double> %0
+}
+
+declare <vscale x 2 x double> @llvm.riscv.sf.vc.v.vv.se.nxv2f64.iXLen.nxv2f64.iXLen(iXLen, <vscale x 2 x double>, <vscale x 2 x double>, iXLen)
+
+define <vscale x 4 x double> @test_f_sf_vc_v_vv_se_e64m4(<vscale x 4 x double> %vs2, <vscale x 4 x double> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_se_e64m4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v12
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 4 x double> @llvm.riscv.sf.vc.v.vv.se.nxv4f64.iXLen.nxv4f64.iXLen(iXLen 3, <vscale x 4 x double> %vs2, <vscale x 4 x double> %vs1, iXLen %vl)
+ ret <vscale x 4 x double> %0
+}
+
+declare <vscale x 4 x double> @llvm.riscv.sf.vc.v.vv.se.nxv4f64.iXLen.nxv4f64.iXLen(iXLen, <vscale x 4 x double>, <vscale x 4 x double>, iXLen)
+
+define <vscale x 8 x double> @test_f_sf_vc_v_vv_se_e64m8(<vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_se_e64m8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v16
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 8 x double> @llvm.riscv.sf.vc.v.vv.se.nxv8f64.iXLen.nxv8f64.iXLen(iXLen 3, <vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, iXLen %vl)
+ ret <vscale x 8 x double> %0
+}
+
+declare <vscale x 8 x double> @llvm.riscv.sf.vc.v.vv.se.nxv8f64.iXLen.nxv8f64.iXLen(iXLen, <vscale x 8 x double>, <vscale x 8 x double>, iXLen)
+
+define <vscale x 1 x half> @test_f_sf_vc_v_vv_e16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_e16mf4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 1 x half> @llvm.riscv.sf.vc.v.vv.nxv1f16.iXLen.nxv1f16.iXLen(iXLen 3, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, iXLen %vl)
+ ret <vscale x 1 x half> %0
+}
+
+declare <vscale x 1 x half> @llvm.riscv.sf.vc.v.vv.nxv1f16.iXLen.nxv1f16.iXLen(iXLen, <vscale x 1 x half>, <vscale x 1 x half>, iXLen)
+
+define <vscale x 2 x half> @test_f_sf_vc_v_vv_e16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_e16mf2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 2 x half> @llvm.riscv.sf.vc.v.vv.nxv2f16.iXLen.nxv2f16.iXLen(iXLen 3, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, iXLen %vl)
+ ret <vscale x 2 x half> %0
+}
+
+declare <vscale x 2 x half> @llvm.riscv.sf.vc.v.vv.nxv2f16.iXLen.nxv2f16.iXLen(iXLen, <vscale x 2 x half>, <vscale x 2 x half>, iXLen)
+
+define <vscale x 4 x half> @test_f_sf_vc_v_vv_e16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_e16m1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 4 x half> @llvm.riscv.sf.vc.v.vv.nxv4f16.iXLen.nxv4f16.iXLen(iXLen 3, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, iXLen %vl)
+ ret <vscale x 4 x half> %0
+}
+
+declare <vscale x 4 x half> @llvm.riscv.sf.vc.v.vv.nxv4f16.iXLen.nxv4f16.iXLen(iXLen, <vscale x 4 x half>, <vscale x 4 x half>, iXLen)
+
+define <vscale x 8 x half> @test_f_sf_vc_v_vv_e16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_e16m2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v10
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 8 x half> @llvm.riscv.sf.vc.v.vv.nxv8f16.iXLen.nxv8f16.iXLen(iXLen 3, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, iXLen %vl)
+ ret <vscale x 8 x half> %0
+}
+
+declare <vscale x 8 x half> @llvm.riscv.sf.vc.v.vv.nxv8f16.iXLen.nxv8f16.iXLen(iXLen, <vscale x 8 x half>, <vscale x 8 x half>, iXLen)
+
+define <vscale x 16 x half> @test_f_sf_vc_v_vv_e16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_e16m4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v12
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 16 x half> @llvm.riscv.sf.vc.v.vv.nxv16f16.iXLen.nxv16f16.iXLen(iXLen 3, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, iXLen %vl)
+ ret <vscale x 16 x half> %0
+}
+
+declare <vscale x 16 x half> @llvm.riscv.sf.vc.v.vv.nxv16f16.iXLen.nxv16f16.iXLen(iXLen, <vscale x 16 x half>, <vscale x 16 x half>, iXLen)
+
+define <vscale x 32 x half> @test_f_sf_vc_v_vv_e16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_e16m8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v16
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 32 x half> @llvm.riscv.sf.vc.v.vv.nxv32f16.iXLen.nxv32f16.iXLen(iXLen 3, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, iXLen %vl)
+ ret <vscale x 32 x half> %0
+}
+
+declare <vscale x 32 x half> @llvm.riscv.sf.vc.v.vv.nxv32f16.iXLen.nxv32f16.iXLen(iXLen, <vscale x 32 x half>, <vscale x 32 x half>, iXLen)
+
+define <vscale x 1 x float> @test_f_sf_vc_v_vv_e32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_e32mf2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.vv.nxv1f32.iXLen.nxv1f32.iXLen(iXLen 3, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, iXLen %vl)
+ ret <vscale x 1 x float> %0
+}
+
+declare <vscale x 1 x float> @llvm.riscv.sf.vc.v.vv.nxv1f32.iXLen.nxv1f32.iXLen(iXLen, <vscale x 1 x float>, <vscale x 1 x float>, iXLen)
+
+define <vscale x 2 x float> @test_f_sf_vc_v_vv_e32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_e32m1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.vv.nxv2f32.iXLen.nxv2f32.iXLen(iXLen 3, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, iXLen %vl)
+ ret <vscale x 2 x float> %0
+}
+
+declare <vscale x 2 x float> @llvm.riscv.sf.vc.v.vv.nxv2f32.iXLen.nxv2f32.iXLen(iXLen, <vscale x 2 x float>, <vscale x 2 x float>, iXLen)
+
+define <vscale x 4 x float> @test_f_sf_vc_v_vv_e32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_e32m2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v10
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.vv.nxv4f32.iXLen.nxv4f32.iXLen(iXLen 3, <vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, iXLen %vl)
+ ret <vscale x 4 x float> %0
+}
+
+declare <vscale x 4 x float> @llvm.riscv.sf.vc.v.vv.nxv4f32.iXLen.nxv4f32.iXLen(iXLen, <vscale x 4 x float>, <vscale x 4 x float>, iXLen)
+
+define <vscale x 8 x float> @test_f_sf_vc_v_vv_e32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_e32m4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v12
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.vv.nxv8f32.iXLen.nxv8f32.iXLen(iXLen 3, <vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, iXLen %vl)
+ ret <vscale x 8 x float> %0
+}
+
+declare <vscale x 8 x float> @llvm.riscv.sf.vc.v.vv.nxv8f32.iXLen.nxv8f32.iXLen(iXLen, <vscale x 8 x float>, <vscale x 8 x float>, iXLen)
+
+define <vscale x 16 x float> @test_f_sf_vc_v_vv_e32m8(<vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_e32m8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v16
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.vv.nxv16f32.iXLen.nxv16f32.iXLen(iXLen 3, <vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, iXLen %vl)
+ ret <vscale x 16 x float> %0
+}
+
+declare <vscale x 16 x float> @llvm.riscv.sf.vc.v.vv.nxv16f32.iXLen.nxv16f32.iXLen(iXLen, <vscale x 16 x float>, <vscale x 16 x float>, iXLen)
+
+define <vscale x 1 x double> @test_f_sf_vc_v_vv_e64m1(<vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_e64m1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 1 x double> @llvm.riscv.sf.vc.v.vv.nxv1f64.iXLen.nxv1f64.iXLen(iXLen 3, <vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, iXLen %vl)
+ ret <vscale x 1 x double> %0
+}
+
+declare <vscale x 1 x double> @llvm.riscv.sf.vc.v.vv.nxv1f64.iXLen.nxv1f64.iXLen(iXLen, <vscale x 1 x double>, <vscale x 1 x double>, iXLen)
+
+define <vscale x 2 x double> @test_f_sf_vc_v_vv_e64m2(<vscale x 2 x double> %vs2, <vscale x 2 x double> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_e64m2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v10
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 2 x double> @llvm.riscv.sf.vc.v.vv.nxv2f64.iXLen.nxv2f64.iXLen(iXLen 3, <vscale x 2 x double> %vs2, <vscale x 2 x double> %vs1, iXLen %vl)
+ ret <vscale x 2 x double> %0
+}
+
+declare <vscale x 2 x double> @llvm.riscv.sf.vc.v.vv.nxv2f64.iXLen.nxv2f64.iXLen(iXLen, <vscale x 2 x double>, <vscale x 2 x double>, iXLen)
+
+define <vscale x 4 x double> @test_f_sf_vc_v_vv_e64m4(<vscale x 4 x double> %vs2, <vscale x 4 x double> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_e64m4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v12
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 4 x double> @llvm.riscv.sf.vc.v.vv.nxv4f64.iXLen.nxv4f64.iXLen(iXLen 3, <vscale x 4 x double> %vs2, <vscale x 4 x double> %vs1, iXLen %vl)
+ ret <vscale x 4 x double> %0
+}
+
+declare <vscale x 4 x double> @llvm.riscv.sf.vc.v.vv.nxv4f64.iXLen.nxv4f64.iXLen(iXLen, <vscale x 4 x double>, <vscale x 4 x double>, iXLen)
+
+define <vscale x 8 x double> @test_f_sf_vc_v_vv_e64m8(<vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_v_vv_e64m8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: sf.vc.v.vv 3, v8, v8, v16
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <vscale x 8 x double> @llvm.riscv.sf.vc.v.vv.nxv8f64.iXLen.nxv8f64.iXLen(iXLen 3, <vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, iXLen %vl)
+ ret <vscale x 8 x double> %0
+}
+
+declare <vscale x 8 x double> @llvm.riscv.sf.vc.v.vv.nxv8f64.iXLen.nxv8f64.iXLen(iXLen, <vscale x 8 x double>, <vscale x 8 x double>, iXLen)
+
+define void @test_f_sf_vc_xv_se_e16mf4(<vscale x 1 x half> %vs2, i16 zeroext %rs1, iXLen %vl) {
+; CHECK-LABEL: test_f_sf_vc_xv_se_e16mf4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
+; CHECK-NEXT: sf.vc.xv 3, 31, v8, a0
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv1f16.i16.iXLen(iXLen 3, iXLen 31, <vscale x 1 x half> %vs2, i16 %rs1, iXLen %vl)
----------------
kito-cheng wrote:
Oh, okay, I got your point, I am thinking does it possible to convert those intrinsic to integer variant during lowering instead of expanding those combination in td?
https://github.com/llvm/llvm-project/pull/67094
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