[PATCH] D159533: [DAG] getNode() - fold (zext (trunc x)) -> x iff the upper bits are known zero - add SRL support

Fri Sep 22 17:02:16 PDT 2023

jrbyrnes added a comment.

In D159533#4649980 <https://reviews.llvm.org/D159533#4649980>, @foad wrote:

> @jrbyrnes shouldn't we land the AMDGPU changes separately first? Or would it all be dead code without the rest of this patch?

The changes to `calculateByteProvider` may actually be NFC because sub 32bit `ISD::FSHR`s get legalized into `ISD::OR` which are already handled, but enabling `ISD::FSHR` combine and installing `matchPERM` there is not.

The changes look okay, but it seems it would be best to land them separately first.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D159533/new/

https://reviews.llvm.org/D159533