[llvm] 46d5d26 - [PowerPC] Improve kill flag computation and add verification after MI peephole
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 22 12:26:45 PDT 2023
Author: Nemanja Ivanovic
Date: 2023-09-22T15:26:39-04:00
New Revision: 46d5d264fc66a017bbd0182b2b5fcc0f3f23d3be
URL: https://github.com/llvm/llvm-project/commit/46d5d264fc66a017bbd0182b2b5fcc0f3f23d3be
DIFF: https://github.com/llvm/llvm-project/commit/46d5d264fc66a017bbd0182b2b5fcc0f3f23d3be.diff
LOG: [PowerPC] Improve kill flag computation and add verification after MI peephole
The MI Peephole pass has grown to include a large number of transformations over the years. Many of the transformations require re-computation of kill flags but don't do a good job of re-computing them. This causes us to have very common failures when the compiler is built with expensive checks. Over time, we added and augmented a function that is supposed to go and fix up kill flags after each transformation but we keep missing cases.
This patch does the following:
- Removes the function to re-compute kill flags
- Adds LiveVariables to compute and maintain kill flags while transforming code
- Adds re-computation of kill flags for the post-RA peepholes for each block that contains a transformed instruction
Reviewed By: stefanp
Differential Revision: https://reviews.llvm.org/D133103
Added:
Modified:
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
llvm/test/CodeGen/PowerPC/O3-pipeline.ll
llvm/test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll
llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-kill-flag.mir
llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir
llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
llvm/test/CodeGen/PowerPC/mi-peephole.mir
llvm/test/CodeGen/PowerPC/opt-cmp-rec-postra.mir
llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
llvm/test/CodeGen/PowerPC/peephole-phi-acc.mir
llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir
llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
llvm/test/CodeGen/PowerPC/sext_elimination.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 854034b38637a9a..75c6399fe7e16b1 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -22,6 +22,7 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LiveIntervals.h"
+#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -2833,10 +2834,6 @@ bool PPCInstrInfo::optimizeCmpPostRA(MachineInstr &CmpMI) const {
.addReg(CRReg, RegState::ImplicitDefine);
SrcMI->clearRegisterDeads(CRReg);
- // Fix up killed/dead flag for SrcReg after transformation.
- if (SrcRegHasOtherUse || CmpMI.getOperand(1).isKill())
- fixupIsDeadOrKill(SrcMI, &CmpMI, SrcReg);
-
assert(SrcMI->definesRegister(PPC::CR0) &&
"Record-form instruction does not define cr0?");
@@ -3467,101 +3464,6 @@ ArrayRef<unsigned> PPCInstrInfo::getLoadOpcodesForSpillArray() const {
return {LoadSpillOpcodesArray[getSpillTarget()], SOK_LastOpcodeSpill};
}
-void PPCInstrInfo::fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI,
- unsigned RegNo) const {
- // Conservatively clear kill flag for the register if the instructions are in
- //
diff erent basic blocks and in SSA form, because the kill flag may no longer
- // be right. There is no need to bother with dead flags since defs with no
- // uses will be handled by DCE.
- MachineRegisterInfo &MRI = StartMI->getParent()->getParent()->getRegInfo();
- if (MRI.isSSA() && (StartMI->getParent() != EndMI->getParent())) {
- MRI.clearKillFlags(RegNo);
- return;
- }
-
- // Instructions between [StartMI, EndMI] should be in same basic block.
- assert((StartMI->getParent() == EndMI->getParent()) &&
- "Instructions are not in same basic block");
-
- // If before RA, StartMI may be def through COPY, we need to adjust it to the
- // real def. See function getForwardingDefMI.
- if (MRI.isSSA()) {
- bool Reads, Writes;
- std::tie(Reads, Writes) = StartMI->readsWritesVirtualRegister(RegNo);
- if (!Reads && !Writes) {
- assert(Register::isVirtualRegister(RegNo) &&
- "Must be a virtual register");
- // Get real def and ignore copies.
- StartMI = MRI.getVRegDef(RegNo);
- }
- }
-
- bool IsKillSet = false;
-
- auto clearOperandKillInfo = [=] (MachineInstr &MI, unsigned Index) {
- MachineOperand &MO = MI.getOperand(Index);
- if (MO.isReg() && MO.isUse() && MO.isKill() &&
- getRegisterInfo().regsOverlap(MO.getReg(), RegNo))
- MO.setIsKill(false);
- };
-
- // Set killed flag for EndMI.
- // No need to do anything if EndMI defines RegNo.
- int UseIndex =
- EndMI->findRegisterUseOperandIdx(RegNo, false, &getRegisterInfo());
- if (UseIndex != -1) {
- EndMI->getOperand(UseIndex).setIsKill(true);
- IsKillSet = true;
- // Clear killed flag for other EndMI operands related to RegNo. In some
- // upexpected cases, killed may be set multiple times for same register
- // operand in same MI.
- for (int i = 0, e = EndMI->getNumOperands(); i != e; ++i)
- if (i != UseIndex)
- clearOperandKillInfo(*EndMI, i);
- }
-
- // Walking the inst in reverse order (EndMI -> StartMI].
- MachineBasicBlock::reverse_iterator It = *EndMI;
- MachineBasicBlock::reverse_iterator E = EndMI->getParent()->rend();
- // EndMI has been handled above, skip it here.
- It++;
- MachineOperand *MO = nullptr;
- for (; It != E; ++It) {
- // Skip insturctions which could not be a def/use of RegNo.
- if (It->isDebugInstr() || It->isPosition())
- continue;
-
- // Clear killed flag for all It operands related to RegNo. In some
- // upexpected cases, killed may be set multiple times for same register
- // operand in same MI.
- for (int i = 0, e = It->getNumOperands(); i != e; ++i)
- clearOperandKillInfo(*It, i);
-
- // If killed is not set, set killed for its last use or set dead for its def
- // if no use found.
- if (!IsKillSet) {
- if ((MO = It->findRegisterUseOperand(RegNo, false, &getRegisterInfo()))) {
- // Use found, set it killed.
- IsKillSet = true;
- MO->setIsKill(true);
- continue;
- } else if ((MO = It->findRegisterDefOperand(RegNo, false, true,
- &getRegisterInfo()))) {
- // No use found, set dead for its def.
- assert(&*It == StartMI && "No new def between StartMI and EndMI.");
- MO->setIsDead(true);
- break;
- }
- }
-
- if ((&*It) == StartMI)
- break;
- }
- // Ensure RegMo liveness is killed after EndMI.
- assert((IsKillSet || (MO && MO->isDead())) &&
- "RegNo should be killed or dead");
-}
-
// This opt tries to convert the following imm form to an index form to save an
// add for stack variables.
// Return false if no such pattern found.
@@ -3796,6 +3698,7 @@ bool PPCInstrInfo::isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
// result of a load-immediate or an add-immediate, convert it to
// the immediate form if the constant is in range.
bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
+ SmallSet<Register, 4> &RegsToUpdate,
MachineInstr **KilledDef) const {
MachineFunction *MF = MI.getParent()->getParent();
MachineRegisterInfo *MRI = &MF->getRegInfo();
@@ -3813,6 +3716,15 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
if (KilledDef && KillFwdDefMI)
*KilledDef = DefMI;
+ // Conservatively add defs from DefMI and defs/uses from MI to the set of
+ // registers that need their kill flags updated.
+ for (const MachineOperand &MO : DefMI->operands())
+ if (MO.isReg() && MO.isDef())
+ RegsToUpdate.insert(MO.getReg());
+ for (const MachineOperand &MO : MI.operands())
+ if (MO.isReg())
+ RegsToUpdate.insert(MO.getReg());
+
// If this is a imm instruction and its register operands is produced by ADDI,
// put the imm into imm inst directly.
if (RI.getMappedIdxOpcForImmOpc(MI.getOpcode()) !=
@@ -4615,9 +4527,6 @@ bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
// Sign-extend to 64-bits.
int64_t SExtImm = SignExtend64<16>(Immediate);
- bool IsForwardingOperandKilled = MI.getOperand(OpNoForForwarding).isKill();
- Register ForwardingOperandReg = MI.getOperand(OpNoForForwarding).getReg();
-
bool ReplaceWithLI = false;
bool Is64BitLI = false;
int64_t NewImm = 0;
@@ -4829,12 +4738,8 @@ bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
*KilledDef = nullptr;
replaceInstrWithLI(MI, LII);
- // Fixup killed/dead flag after transformation.
- // Pattern:
- // ForwardingOperandReg = LI imm1
- // y = op2 imm2, ForwardingOperandReg(killed)
- if (IsForwardingOperandKilled)
- fixupIsDeadOrKill(&DefMI, &MI, ForwardingOperandReg);
+ if (PostRA)
+ recomputeLivenessFlags(*MI.getParent());
LLVM_DEBUG(dbgs() << "With:\n");
LLVM_DEBUG(MI.dump());
@@ -4895,11 +4800,6 @@ bool PPCInstrInfo::transformToNewImmFormFedByAdd(
if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm, ImmBase))
return false;
- // Get killed info in case fixup needed after transformation.
- unsigned ForwardKilledOperandReg = ~0U;
- if (MI.getOperand(III.OpNoForForwarding).isKill())
- ForwardKilledOperandReg = MI.getOperand(III.OpNoForForwarding).getReg();
-
// Do the transform
LLVM_DEBUG(dbgs() << "Replacing existing reg+imm instruction:\n");
LLVM_DEBUG(MI.dump());
@@ -4907,35 +4807,8 @@ bool PPCInstrInfo::transformToNewImmFormFedByAdd(
LLVM_DEBUG(DefMI.dump());
MI.getOperand(III.OpNoForForwarding).setReg(RegMO->getReg());
- if (RegMO->isKill()) {
- MI.getOperand(III.OpNoForForwarding).setIsKill(true);
- // Clear the killed flag in RegMO. Doing this here can handle some cases
- // that DefMI and MI are not in same basic block.
- RegMO->setIsKill(false);
- }
MI.getOperand(III.ImmOpNo).setImm(Imm);
- // FIXME: fix kill/dead flag if MI and DefMI are not in same basic block.
- if (DefMI.getParent() == MI.getParent()) {
- // Check if reg is killed between MI and DefMI.
- auto IsKilledFor = [&](unsigned Reg) {
- MachineBasicBlock::const_reverse_iterator It = MI;
- MachineBasicBlock::const_reverse_iterator E = DefMI;
- It++;
- for (; It != E; ++It) {
- if (It->killsRegister(Reg))
- return true;
- }
- return false;
- };
-
- // Update kill flag
- if (RegMO->isKill() || IsKilledFor(RegMO->getReg()))
- fixupIsDeadOrKill(&DefMI, &MI, RegMO->getReg());
- if (ForwardKilledOperandReg != ~0U)
- fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
- }
-
LLVM_DEBUG(dbgs() << "With:\n");
LLVM_DEBUG(MI.dump());
return true;
@@ -4979,12 +4852,8 @@ bool PPCInstrInfo::transformToImmFormFedByAdd(
IsFwdFeederRegKilled, SeenIntermediateUse))
return false;
- // Get killed info in case fixup needed after transformation.
- unsigned ForwardKilledOperandReg = ~0U;
MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
bool PostRA = !MRI.isSSA();
- if (PostRA && MI.getOperand(OpNoForForwarding).isKill())
- ForwardKilledOperandReg = MI.getOperand(OpNoForForwarding).getReg();
// We know that, the MI and DefMI both meet the pattern, and
// the Imm also meet the requirement with the new Imm-form.
@@ -5036,22 +4905,8 @@ bool PPCInstrInfo::transformToImmFormFedByAdd(
// Update the opcode.
MI.setDesc(get(III.ImmOpcode));
- // Fix up killed/dead flag after transformation.
- // Pattern 1:
- // x = ADD KilledFwdFeederReg, imm
- // n = opn KilledFwdFeederReg(killed), regn
- // y = XOP 0, x
- // Pattern 2:
- // x = ADD reg(killed), imm
- // y = XOP 0, x
- if (IsFwdFeederRegKilled || RegMO->isKill())
- fixupIsDeadOrKill(&DefMI, &MI, RegMO->getReg());
- // Pattern 3:
- // ForwardKilledOperandReg = ADD reg, imm
- // y = XOP 0, ForwardKilledOperandReg(killed)
- if (ForwardKilledOperandReg != ~0U)
- fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
-
+ if (PostRA)
+ recomputeLivenessFlags(*MI.getParent());
LLVM_DEBUG(dbgs() << "With:\n");
LLVM_DEBUG(MI.dump());
@@ -5107,11 +4962,6 @@ bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
return false;
}
- // Get killed info in case fixup needed after transformation.
- unsigned ForwardKilledOperandReg = ~0U;
- if (PostRA && MI.getOperand(ConstantOpNo).isKill())
- ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg();
-
unsigned Opc = MI.getOpcode();
bool SpecialShift32 = Opc == PPC::SLW || Opc == PPC::SLW_rec ||
Opc == PPC::SRW || Opc == PPC::SRW_rec ||
@@ -5205,12 +5055,8 @@ bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
}
}
- // Fix up killed/dead flag after transformation.
- // Pattern:
- // ForwardKilledOperandReg = LI imm
- // y = XOP reg, ForwardKilledOperandReg(killed)
- if (ForwardKilledOperandReg != ~0U)
- fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
+ if (PostRA)
+ recomputeLivenessFlags(*MI.getParent());
LLVM_DEBUG(dbgs() << "With: ");
LLVM_DEBUG(MI.dump());
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 93d2a58aa39023a..1f59e994d9cb1ad 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -15,6 +15,7 @@
#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "PPCRegisterInfo.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
@@ -585,6 +586,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
}
bool convertToImmediateForm(MachineInstr &MI,
+ SmallSet<Register, 4> &RegsToUpdate,
MachineInstr **KilledDef = nullptr) const;
bool foldFrameOffset(MachineInstr &MI) const;
bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const;
@@ -598,23 +600,6 @@ class PPCInstrInfo : public PPCGenInstrInfo {
MachineInstr *&ADDIMI, int64_t &OffsetAddi,
int64_t OffsetImm) const;
- /// Fixup killed/dead flag for register \p RegNo between instructions [\p
- /// StartMI, \p EndMI]. Some pre-RA or post-RA transformations may violate
- /// register killed/dead flags semantics, this function can be called to fix
- /// up. Before calling this function,
- /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI.
- /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI)
- /// and possible definition for \p RegNo is \p StartMI or \p EndMI. For
- /// pre-RA cases, definition may be \p StartMI through COPY, \p StartMI
- /// will be adjust to true definition.
- /// 3. We can do accurate fixup for the case when all instructions between
- /// [\p StartMI, \p EndMI] are in same basic block.
- /// 4. For the case when \p StartMI and \p EndMI are not in same basic block,
- /// we conservatively clear kill flag for all uses of \p RegNo for pre-RA
- /// and for post-RA, we give an assertion as without reaching definition
- /// analysis post-RA, \p StartMI and \p EndMI are hard to keep right.
- void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI,
- unsigned RegNo) const;
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
int64_t Imm) const;
diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
index 410f4cba97c6218..9ad319d334354a8 100644
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -16,6 +16,15 @@
// removal, and it would miss cleanups made possible following VSX
// swap removal.
//
+// NOTE: We run the verifier after this pass in Asserts/Debug builds so it
+// is important to keep the code valid after transformations.
+// Common causes of errors stem from violating the contract specified
+// by kill flags. Whenever a transformation changes the live range of
+// a register, that register should be added to the work list using
+// addRegToUpdate(RegsToUpdate, <Reg>). Furthermore, if a transformation
+// is changing the definition of a register (i.e. removing the single
+// definition of the original vreg), it needs to provide a dummy
+// definition of that register using addDummyDef(<MBB>, <Reg>).
//===---------------------------------------------------------------------===//
#include "MCTargetDesc/PPCMCTargetDesc.h"
@@ -26,6 +35,7 @@
#include "PPCMachineFunctionInfo.h"
#include "PPCTargetMachine.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -93,6 +103,7 @@ struct PPCMIPeephole : public MachineFunctionPass {
const PPCInstrInfo *TII;
MachineFunction *MF;
MachineRegisterInfo *MRI;
+ LiveVariables *LV;
PPCMIPeephole() : MachineFunctionPass(ID) {
initializePPCMIPeepholePass(*PassRegistry::getPassRegistry());
@@ -103,6 +114,7 @@ struct PPCMIPeephole : public MachineFunctionPass {
MachinePostDominatorTree *MPDT;
MachineBlockFrequencyInfo *MBFI;
uint64_t EntryFreq;
+ SmallSet<Register, 16> RegsToUpdate;
// Initialize class variables.
void initialize(MachineFunction &MFParm);
@@ -114,16 +126,32 @@ struct PPCMIPeephole : public MachineFunctionPass {
bool eliminateRedundantCompare();
bool eliminateRedundantTOCSaves(std::map<MachineInstr *, bool> &TOCSaves);
bool combineSEXTAndSHL(MachineInstr &MI, MachineInstr *&ToErase);
- bool emitRLDICWhenLoweringJumpTables(MachineInstr &MI);
+ bool emitRLDICWhenLoweringJumpTables(MachineInstr &MI,
+ MachineInstr *&ToErase);
void UpdateTOCSaves(std::map<MachineInstr *, bool> &TOCSaves,
MachineInstr *MI);
+ // A number of transformations will eliminate the definition of a register
+ // as all of its uses will be removed. However, this leaves a register
+ // without a definition for LiveVariables. Such transformations should
+ // use this function to provide a dummy definition of the register that
+ // will simply be removed by DCE.
+ void addDummyDef(MachineBasicBlock &MBB, MachineInstr *At, Register Reg) {
+ BuildMI(MBB, At, At->getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), Reg);
+ }
+ void addRegToUpdateWithLine(Register Reg, int Line);
+ void convertUnprimedAccPHIs(const PPCInstrInfo *TII, MachineRegisterInfo *MRI,
+ SmallVectorImpl<MachineInstr *> &PHIs,
+ Register Dst);
+
public:
void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.addRequired<LiveVariables>();
AU.addRequired<MachineDominatorTree>();
AU.addRequired<MachinePostDominatorTree>();
AU.addRequired<MachineBlockFrequencyInfo>();
+ AU.addPreserved<LiveVariables>();
AU.addPreserved<MachineDominatorTree>();
AU.addPreserved<MachinePostDominatorTree>();
AU.addPreserved<MachineBlockFrequencyInfo>();
@@ -140,10 +168,26 @@ struct PPCMIPeephole : public MachineFunctionPass {
"TOC pointer used in a function using PC-Relative addressing!");
if (skipFunction(MF.getFunction()))
return false;
- return simplifyCode();
+ bool Changed = simplifyCode();
+#ifndef NDEBUG
+ if (Changed)
+ MF.verify(this, "Error in PowerPC MI Peephole optimization, compile with "
+ "-mllvm -disable-ppc-peephole");
+#endif
+ return Changed;
}
};
+#define addRegToUpdate(R) addRegToUpdateWithLine(R, __LINE__)
+void PPCMIPeephole::addRegToUpdateWithLine(Register Reg, int Line) {
+ if (!Register::isVirtualRegister(Reg))
+ return;
+ if (RegsToUpdate.insert(Reg).second)
+ LLVM_DEBUG(dbgs() << "Adding register: " << Register::virtReg2Index(Reg)
+ << " on line " << Line
+ << " for re-computation of kill flags\n");
+}
+
// Initialize class variables.
void PPCMIPeephole::initialize(MachineFunction &MFParm) {
MF = &MFParm;
@@ -151,8 +195,10 @@ void PPCMIPeephole::initialize(MachineFunction &MFParm) {
MDT = &getAnalysis<MachineDominatorTree>();
MPDT = &getAnalysis<MachinePostDominatorTree>();
MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
+ LV = &getAnalysis<LiveVariables>();
EntryFreq = MBFI->getEntryFreq();
TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
+ RegsToUpdate.clear();
LLVM_DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n");
LLVM_DEBUG(MF->dump());
}
@@ -338,10 +384,9 @@ static bool collectUnprimedAccPHIs(MachineRegisterInfo *MRI,
// primed accumulator PHI nodes. The list is traversed in reverse order to
// change all the PHI operands of a PHI node before changing the node itself.
// We keep a map to associate each changed PHI node to its non-changed form.
-static void convertUnprimedAccPHIs(const PPCInstrInfo *TII,
- MachineRegisterInfo *MRI,
- SmallVectorImpl<MachineInstr *> &PHIs,
- Register Dst) {
+void PPCMIPeephole::convertUnprimedAccPHIs(
+ const PPCInstrInfo *TII, MachineRegisterInfo *MRI,
+ SmallVectorImpl<MachineInstr *> &PHIs, Register Dst) {
DenseMap<MachineInstr *, MachineInstr *> ChangedPHIMap;
for (MachineInstr *PHI : llvm::reverse(PHIs)) {
SmallVector<std::pair<MachineOperand, MachineOperand>, 4> PHIOps;
@@ -390,8 +435,11 @@ static void convertUnprimedAccPHIs(const PPCInstrInfo *TII,
AccReg = MRI->createVirtualRegister(&PPC::ACCRCRegClass);
MachineInstrBuilder NewPHI = BuildMI(
*PHI->getParent(), PHI, PHI->getDebugLoc(), TII->get(PPC::PHI), AccReg);
- for (auto RegMBB : PHIOps)
+ for (auto RegMBB : PHIOps) {
NewPHI.add(RegMBB.first).add(RegMBB.second);
+ if (MRI->isSSA())
+ addRegToUpdate(RegMBB.first.getReg());
+ }
ChangedPHIMap[PHI] = NewPHI.getInstr();
LLVM_DEBUG(dbgs() << "Converting PHI: ");
LLVM_DEBUG(PHI->dump());
@@ -421,21 +469,51 @@ bool PPCMIPeephole::simplifyCode() {
if (MI.isDebugInstr())
continue;
- if (TII->convertToImmediateForm(MI)) {
- // We don't erase anything in case the def has other uses. Let DCE
- // remove it if it can be removed.
- LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
- LLVM_DEBUG(MI.dump());
- NumConvertedToImmediateForm++;
- SomethingChanged = true;
- Simplified = true;
+ SmallSet<Register, 4> RRToRIRegsToUpdate;
+ if (!TII->convertToImmediateForm(MI, RRToRIRegsToUpdate))
continue;
- }
+ for (Register R : RRToRIRegsToUpdate)
+ addRegToUpdate(R);
+ // The updated instruction may now have new register operands.
+ // Conservatively add them to recompute the flags as well.
+ for (const MachineOperand &MO : MI.operands())
+ if (MO.isReg())
+ addRegToUpdate(MO.getReg());
+ // We don't erase anything in case the def has other uses. Let DCE
+ // remove it if it can be removed.
+ LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
+ LLVM_DEBUG(MI.dump());
+ NumConvertedToImmediateForm++;
+ SomethingChanged = true;
+ Simplified = true;
+ continue;
}
}
} while (SomethingChanged && FixedPointRegToImm);
}
+ // Since we are deleting this instruction, we need to run LiveVariables
+ // on any of its definitions that are marked as needing an update since
+ // we can't run LiveVariables on a deleted register. This only needs
+ // to be done for defs since uses will have their own defining
+ // instructions so we won't be running LiveVariables on a deleted reg.
+ auto recomputeLVForDyingInstr = [&]() {
+ if (RegsToUpdate.empty())
+ return;
+ for (MachineOperand &MO : ToErase->operands()) {
+ if (!MO.isReg() || !MO.isDef() || !RegsToUpdate.count(MO.getReg()))
+ continue;
+ Register RegToUpdate = MO.getReg();
+ RegsToUpdate.erase(RegToUpdate);
+ // If some transformation has introduced an additional definition of
+ // this register (breaking SSA), we can safely convert this def to
+ // a def of an invalid register as the instruction is going away.
+ if (!MRI->getUniqueVRegDef(RegToUpdate))
+ MO.setReg(PPC::NoRegister);
+ LV->recomputeForSingleDefVirtReg(RegToUpdate);
+ }
+ };
+
for (MachineBasicBlock &MBB : *MF) {
for (MachineInstr &MI : MBB) {
@@ -444,6 +522,7 @@ bool PPCMIPeephole::simplifyCode() {
if (ToErase) {
LLVM_DEBUG(dbgs() << "Deleting instruction: ");
LLVM_DEBUG(ToErase->dump());
+ recomputeLVForDyingInstr();
ToErase->eraseFromParent();
ToErase = nullptr;
}
@@ -503,12 +582,16 @@ bool PPCMIPeephole::simplifyCode() {
if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != 0)
break;
Register MIDestReg = MI.getOperand(0).getReg();
+ bool Folded = false;
for (MachineInstr& UseMI : MRI->use_instructions(MIDestReg))
- Simplified |= TII->onlyFoldImmediate(UseMI, MI, MIDestReg);
+ Folded |= TII->onlyFoldImmediate(UseMI, MI, MIDestReg);
if (MRI->use_nodbg_empty(MIDestReg)) {
++NumLoadImmZeroFoldedAndRemoved;
ToErase = &MI;
}
+ if (Folded)
+ addRegToUpdate(MIDestReg);
+ Simplified |= Folded;
break;
}
case PPC::STW:
@@ -579,6 +662,7 @@ bool PPCMIPeephole::simplifyCode() {
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
MI.getOperand(0).getReg())
.add(MI.getOperand(1));
+ addRegToUpdate(MI.getOperand(1).getReg());
ToErase = &MI;
Simplified = true;
}
@@ -608,6 +692,7 @@ bool PPCMIPeephole::simplifyCode() {
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
MI.getOperand(0).getReg())
.add(MI.getOperand(1));
+ addRegToUpdate(MI.getOperand(1).getReg());
ToErase = &MI;
Simplified = true;
}
@@ -618,9 +703,13 @@ bool PPCMIPeephole::simplifyCode() {
else if ((Immed == 0 || Immed == 3) && DefImmed == 2) {
LLVM_DEBUG(dbgs() << "Optimizing swap/splat => splat: ");
LLVM_DEBUG(MI.dump());
+ addRegToUpdate(MI.getOperand(1).getReg());
+ addRegToUpdate(MI.getOperand(2).getReg());
MI.getOperand(1).setReg(DefReg1);
MI.getOperand(2).setReg(DefReg2);
MI.getOperand(3).setImm(3 - Immed);
+ addRegToUpdate(DefReg1);
+ addRegToUpdate(DefReg2);
Simplified = true;
}
@@ -629,9 +718,12 @@ bool PPCMIPeephole::simplifyCode() {
else if (Immed == 2 && DefImmed == 2) {
LLVM_DEBUG(dbgs() << "Optimizing swap/swap => copy: ");
LLVM_DEBUG(MI.dump());
+ addRegToUpdate(MI.getOperand(1).getReg());
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
MI.getOperand(0).getReg())
.add(DefMI->getOperand(1));
+ addRegToUpdate(DefMI->getOperand(0).getReg());
+ addRegToUpdate(DefMI->getOperand(1).getReg());
ToErase = &MI;
Simplified = true;
}
@@ -648,6 +740,7 @@ bool PPCMIPeephole::simplifyCode() {
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
MI.getOperand(0).getReg())
.add(MI.getOperand(1));
+ addRegToUpdate(MI.getOperand(1).getReg());
break;
}
// Splat fed by another splat - switch the output of the first
@@ -669,6 +762,7 @@ bool PPCMIPeephole::simplifyCode() {
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
MI.getOperand(0).getReg())
.add(MI.getOperand(1));
+ addRegToUpdate(MI.getOperand(1).getReg());
} else if ((Immed == 0 || Immed == 3 || Immed == 2) &&
TII->isLoadFromConstantPool(DefMI)) {
const Constant *C = TII->getConstantFromConstantPool(DefMI);
@@ -682,6 +776,7 @@ bool PPCMIPeephole::simplifyCode() {
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
MI.getOperand(0).getReg())
.add(MI.getOperand(1));
+ addRegToUpdate(MI.getOperand(1).getReg());
}
}
break;
@@ -724,6 +819,7 @@ bool PPCMIPeephole::simplifyCode() {
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
MI.getOperand(0).getReg())
.add(MI.getOperand(OpNo));
+ addRegToUpdate(MI.getOperand(OpNo).getReg());
ToErase = &MI;
Simplified = true;
}
@@ -747,7 +843,9 @@ bool PPCMIPeephole::simplifyCode() {
LLVM_DEBUG(dbgs() << "Changing splat immediate from " << SplatImm
<< " to " << NewElem << " in instruction: ");
LLVM_DEBUG(MI.dump());
- MI.getOperand(1).setReg(ShiftOp1);
+ addRegToUpdate(MI.getOperand(OpNo).getReg());
+ addRegToUpdate(ShiftOp1);
+ MI.getOperand(OpNo).setReg(ShiftOp1);
MI.getOperand(2).setImm(NewElem);
}
}
@@ -798,6 +896,7 @@ bool PPCMIPeephole::simplifyCode() {
LLVM_DEBUG(dbgs() << "Through instruction:\n");
LLVM_DEBUG(DefMI->dump());
RoundInstr->eraseFromParent();
+ addRegToUpdate(ConvReg1);
}
};
@@ -844,6 +943,13 @@ bool PPCMIPeephole::simplifyCode() {
else if (MIIs64Bit)
Opc = PPC::LHA8;
+ addRegToUpdate(NarrowReg);
+ addRegToUpdate(MI.getOperand(0).getReg());
+
+ // We are removing a definition of NarrowReg which will cause
+ // problems in AliveBlocks. Add an implicit def that will be
+ // removed so that AliveBlocks are updated correctly.
+ addDummyDef(MBB, &MI, NarrowReg);
LLVM_DEBUG(dbgs() << "Zero-extending load\n");
LLVM_DEBUG(SrcMI->dump());
LLVM_DEBUG(dbgs() << "and sign-extension\n");
@@ -909,6 +1015,13 @@ bool PPCMIPeephole::simplifyCode() {
if (!IsWordAligned && (Opc == PPC::LWA || Opc == PPC::LWA_32))
break;
+ addRegToUpdate(NarrowReg);
+ addRegToUpdate(MI.getOperand(0).getReg());
+
+ // We are removing a definition of NarrowReg which will cause
+ // problems in AliveBlocks. Add an implicit def that will be
+ // removed so that AliveBlocks are updated correctly.
+ addDummyDef(MBB, &MI, NarrowReg);
LLVM_DEBUG(dbgs() << "Zero-extending load\n");
LLVM_DEBUG(SrcMI->dump());
LLVM_DEBUG(dbgs() << "and sign-extension\n");
@@ -981,6 +1094,7 @@ bool PPCMIPeephole::simplifyCode() {
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
MI.getOperand(0).getReg())
.addReg(SrcReg);
+ addRegToUpdate(SrcReg);
ToErase = &MI;
Simplified = true;
NumEliminatedZExt++;
@@ -1071,13 +1185,15 @@ bool PPCMIPeephole::simplifyCode() {
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
MI.getOperand(0).getReg())
.add(Op1);
+ addRegToUpdate(Op1.getReg());
+ addRegToUpdate(Op2.getReg());
ToErase = &MI;
Simplified = true;
NumOptADDLIs++;
break;
}
case PPC::RLDICR: {
- Simplified |= emitRLDICWhenLoweringJumpTables(MI) ||
+ Simplified |= emitRLDICWhenLoweringJumpTables(MI, ToErase) ||
combineSEXTAndSHL(MI, ToErase);
break;
}
@@ -1085,9 +1201,18 @@ bool PPCMIPeephole::simplifyCode() {
case PPC::RLWINM_rec:
case PPC::RLWINM8:
case PPC::RLWINM8_rec: {
+ // We might replace operand 1 of the instruction which will
+ // require we recompute kill flags for it.
+ Register OrigOp1Reg = MI.getOperand(1).isReg()
+ ? MI.getOperand(1).getReg()
+ : PPC::NoRegister;
Simplified = TII->combineRLWINM(MI, &ToErase);
- if (Simplified)
+ if (Simplified) {
+ addRegToUpdate(OrigOp1Reg);
+ if (MI.getOperand(1).isReg())
+ addRegToUpdate(MI.getOperand(1).getReg());
++NumRotatesCollapsed;
+ }
break;
}
// We will replace TD/TW/TDI/TWI with an unconditional trap if it will
@@ -1141,6 +1266,7 @@ bool PPCMIPeephole::simplifyCode() {
// If the last instruction was marked for elimination,
// remove it now.
if (ToErase) {
+ recomputeLVForDyingInstr();
ToErase->eraseFromParent();
ToErase = nullptr;
}
@@ -1158,6 +1284,13 @@ bool PPCMIPeephole::simplifyCode() {
// We try to eliminate redundant compare instruction.
Simplified |= eliminateRedundantCompare();
+ // If we have made any modifications and added any registers to the set of
+ // registers for which we need to update the kill flags, do so by recomputing
+ // LiveVariables for those registers.
+ for (Register Reg : RegsToUpdate) {
+ if (!MRI->reg_empty(Reg))
+ LV->recomputeForSingleDefVirtReg(Reg);
+ }
return Simplified;
}
@@ -1586,6 +1719,12 @@ bool PPCMIPeephole::eliminateRedundantCompare() {
LLVM_DEBUG(BI1->dump());
LLVM_DEBUG(CMPI2->dump());
LLVM_DEBUG(BI2->dump());
+ for (const MachineOperand &MO : CMPI1->operands())
+ if (MO.isReg())
+ addRegToUpdate(MO.getReg());
+ for (const MachineOperand &MO : CMPI2->operands())
+ if (MO.isReg())
+ addRegToUpdate(MO.getReg());
// We adjust opcode, predicates and immediate as we determined above.
if (NewOpCode != 0 && NewOpCode != CMPI1->getOpcode()) {
@@ -1623,6 +1762,7 @@ bool PPCMIPeephole::eliminateRedundantCompare() {
"We cannot support if an operand comes from this BB.");
unsigned SrcReg = getIncomingRegForBlock(Inst, MBBtoMoveCmp);
CMPI2->getOperand(I).setReg(SrcReg);
+ addRegToUpdate(SrcReg);
}
}
auto I = MachineBasicBlock::iterator(MBBtoMoveCmp->getFirstTerminator());
@@ -1635,14 +1775,20 @@ bool PPCMIPeephole::eliminateRedundantCompare() {
.addReg(BI1->getOperand(1).getReg()).addMBB(MBB1)
.addReg(BI2->getOperand(1).getReg()).addMBB(MBBtoMoveCmp);
BI2->getOperand(1).setReg(NewVReg);
+ addRegToUpdate(NewVReg);
}
else {
// We finally eliminate compare instruction in MBB2.
+ // We do not need to treat CMPI2 specially here in terms of re-computing
+ // live variables even though it is being deleted because:
+ // - It defines a register that has a single use (already checked in
+ // eligibleForCompareElimination())
+ // - The only user (BI2) is no longer using it so the register is dead (no
+ // def, no uses)
+ // - We do not attempt to recompute live variables for dead registers
BI2->getOperand(1).setReg(BI1->getOperand(1).getReg());
CMPI2->eraseFromParent();
}
- BI2->getOperand(1).setIsKill(true);
- BI1->getOperand(1).setIsKill(false);
LLVM_DEBUG(dbgs() << "into a compare and two branches:\n");
LLVM_DEBUG(CMPI1->dump());
@@ -1654,7 +1800,6 @@ bool PPCMIPeephole::eliminateRedundantCompare() {
<< " to handle partial redundancy.\n");
LLVM_DEBUG(CMPI2->dump());
}
-
Simplified = true;
}
@@ -1664,7 +1809,8 @@ bool PPCMIPeephole::eliminateRedundantCompare() {
// We miss the opportunity to emit an RLDIC when lowering jump tables
// since ISEL sees only a single basic block. When selecting, the clear
// and shift left will be in
diff erent blocks.
-bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) {
+bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI,
+ MachineInstr *&ToErase) {
if (MI.getOpcode() != PPC::RLDICR)
return false;
@@ -1710,8 +1856,8 @@ bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) {
MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
MI.getOperand(2).setImm(NewSH);
MI.getOperand(3).setImm(NewMB);
- MI.getOperand(1).setIsKill(SrcMI->getOperand(1).isKill());
- SrcMI->getOperand(1).setIsKill(false);
+ addRegToUpdate(MI.getOperand(1).getReg());
+ addRegToUpdate(SrcMI->getOperand(0).getReg());
LLVM_DEBUG(dbgs() << "To: ");
LLVM_DEBUG(MI.dump());
@@ -1720,7 +1866,7 @@ bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) {
if (MRI->use_nodbg_empty(SrcReg)) {
assert(!SrcMI->hasImplicitDef() &&
"Not expecting an implicit def with this instr.");
- SrcMI->eraseFromParent();
+ ToErase = SrcMI;
}
return true;
}
@@ -1793,8 +1939,11 @@ bool PPCMIPeephole::combineSEXTAndSHL(MachineInstr &MI,
LLVM_DEBUG(NewInstr->dump());
++NumEXTSWAndSLDICombined;
ToErase = &MI;
- // SrcMI, which is extsw, is of no use now, erase it.
- SrcMI->eraseFromParent();
+ // SrcMI, which is extsw, is of no use now, but we don't erase it here so we
+ // can recompute its kill flags. We run DCE immediately after this pass
+ // to clean up dead instructions such as this.
+ addRegToUpdate(NewInstr->getOperand(1).getReg());
+ addRegToUpdate(SrcMI->getOperand(0).getReg());
return true;
}
@@ -1805,6 +1954,7 @@ INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE,
INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfo)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree)
+INITIALIZE_PASS_DEPENDENCY(LiveVariables)
INITIALIZE_PASS_END(PPCMIPeephole, DEBUG_TYPE,
"PowerPC MI Peephole Optimization", false, false)
diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
index 6f1b34843343a8f..647f8a7475813bd 100644
--- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
@@ -495,7 +495,8 @@ static bool hasPCRelativeForm(MachineInstr &Use) {
}
}
MachineInstr *DefMIToErase = nullptr;
- if (TII->convertToImmediateForm(MI, &DefMIToErase)) {
+ SmallSet<Register, 4> UpdatedRegs;
+ if (TII->convertToImmediateForm(MI, UpdatedRegs, &DefMIToErase)) {
Changed = true;
NumRRConvertedInPreEmit++;
LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
diff --git a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
index 16cb7596cd6057d..6ce4416211cc4d1 100644
--- a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
+++ b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
@@ -127,6 +127,8 @@
; CHECK-NEXT: Remove dead machine instructions
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: PowerPC Reduce CR logical Operation
+; CHECK-NEXT: Remove unreachable machine basic blocks
+; CHECK-NEXT: Live Variable Analysis
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: MachinePostDominator Tree Construction
; CHECK-NEXT: Machine Natural Loop Construction
diff --git a/llvm/test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll b/llvm/test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll
index f65f189b9568c10..00a77f92c0413ad 100644
--- a/llvm/test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll
@@ -200,3 +200,212 @@ true:
false:
ret i64 %iconv
}
+
+define hidden void @testCaller(i1 %incond) local_unnamed_addr align 2 nounwind {
+; CHECK-LABEL: testCaller:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mfocrf r12, 32
+; CHECK-NEXT: stw r12, 8(r1)
+; CHECK-NEXT: mflr r0
+; CHECK-NEXT: stdu r1, -64(r1)
+; CHECK-NEXT: std r0, 80(r1)
+; CHECK-NEXT: std r30, 48(r1) # 8-byte Folded Spill
+; CHECK-NEXT: andi. r3, r3, 1
+; CHECK-NEXT: li r3, -1
+; CHECK-NEXT: li r30, 0
+; CHECK-NEXT: crmove 4*cr2+lt, gt
+; CHECK-NEXT: std r29, 40(r1) # 8-byte Folded Spill
+; CHECK-NEXT: b .LBB3_2
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB3_1: # %if.end116
+; CHECK-NEXT: #
+; CHECK-NEXT: bl callee
+; CHECK-NEXT: nop
+; CHECK-NEXT: mr r3, r29
+; CHECK-NEXT: .LBB3_2: # %cond.end.i.i
+; CHECK-NEXT: # =>This Loop Header: Depth=1
+; CHECK-NEXT: # Child Loop BB3_3 Depth 2
+; CHECK-NEXT: lwz r29, 0(r3)
+; CHECK-NEXT: li r5, 0
+; CHECK-NEXT: extsw r4, r29
+; CHECK-NEXT: .p2align 5
+; CHECK-NEXT: .LBB3_3: # %while.body5.i
+; CHECK-NEXT: # Parent Loop BB3_2 Depth=1
+; CHECK-NEXT: # => This Inner Loop Header: Depth=2
+; CHECK-NEXT: addi r5, r5, -1
+; CHECK-NEXT: cmpwi r5, 0
+; CHECK-NEXT: bgt cr0, .LBB3_3
+; CHECK-NEXT: # %bb.4: # %while.cond12.preheader.i
+; CHECK-NEXT: #
+; CHECK-NEXT: bc 12, 4*cr2+lt, .LBB3_1
+; CHECK-NEXT: # %bb.5: # %for.cond99.preheader
+; CHECK-NEXT: #
+; CHECK-NEXT: ld r5, 0(r3)
+; CHECK-NEXT: sldi r4, r4, 2
+; CHECK-NEXT: stw r3, 0(r3)
+; CHECK-NEXT: stwx r30, r5, r4
+; CHECK-NEXT: b .LBB3_1
+;
+; CHECK-BE-LABEL: testCaller:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: mfcr r12
+; CHECK-BE-NEXT: stw r12, 8(r1)
+; CHECK-BE-NEXT: mflr r0
+; CHECK-BE-NEXT: stdu r1, -80(r1)
+; CHECK-BE-NEXT: std r0, 96(r1)
+; CHECK-BE-NEXT: std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT: andi. r3, r3, 1
+; CHECK-BE-NEXT: li r3, -1
+; CHECK-BE-NEXT: li r30, 0
+; CHECK-BE-NEXT: crmove 4*cr2+lt, gt
+; CHECK-BE-NEXT: std r29, 56(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT: b .LBB3_2
+; CHECK-BE-NEXT: .p2align 4
+; CHECK-BE-NEXT: .LBB3_1: # %if.end116
+; CHECK-BE-NEXT: #
+; CHECK-BE-NEXT: bl callee
+; CHECK-BE-NEXT: nop
+; CHECK-BE-NEXT: mr r3, r29
+; CHECK-BE-NEXT: .LBB3_2: # %cond.end.i.i
+; CHECK-BE-NEXT: # =>This Loop Header: Depth=1
+; CHECK-BE-NEXT: # Child Loop BB3_3 Depth 2
+; CHECK-BE-NEXT: lwz r29, 0(r3)
+; CHECK-BE-NEXT: li r5, 0
+; CHECK-BE-NEXT: extsw r4, r29
+; CHECK-BE-NEXT: .p2align 5
+; CHECK-BE-NEXT: .LBB3_3: # %while.body5.i
+; CHECK-BE-NEXT: # Parent Loop BB3_2 Depth=1
+; CHECK-BE-NEXT: # => This Inner Loop Header: Depth=2
+; CHECK-BE-NEXT: addi r5, r5, -1
+; CHECK-BE-NEXT: cmpwi r5, 0
+; CHECK-BE-NEXT: bgt cr0, .LBB3_3
+; CHECK-BE-NEXT: # %bb.4: # %while.cond12.preheader.i
+; CHECK-BE-NEXT: #
+; CHECK-BE-NEXT: bc 12, 4*cr2+lt, .LBB3_1
+; CHECK-BE-NEXT: # %bb.5: # %for.cond99.preheader
+; CHECK-BE-NEXT: #
+; CHECK-BE-NEXT: ld r5, 0(r3)
+; CHECK-BE-NEXT: sldi r4, r4, 2
+; CHECK-BE-NEXT: stw r3, 0(r3)
+; CHECK-BE-NEXT: stwx r30, r5, r4
+; CHECK-BE-NEXT: b .LBB3_1
+;
+; CHECK-P9-LABEL: testCaller:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: mfocrf r12, 32
+; CHECK-P9-NEXT: mflr r0
+; CHECK-P9-NEXT: stw r12, 8(r1)
+; CHECK-P9-NEXT: stdu r1, -64(r1)
+; CHECK-P9-NEXT: andi. r3, r3, 1
+; CHECK-P9-NEXT: std r0, 80(r1)
+; CHECK-P9-NEXT: std r30, 48(r1) # 8-byte Folded Spill
+; CHECK-P9-NEXT: li r3, -1
+; CHECK-P9-NEXT: li r30, 0
+; CHECK-P9-NEXT: std r29, 40(r1) # 8-byte Folded Spill
+; CHECK-P9-NEXT: crmove 4*cr2+lt, gt
+; CHECK-P9-NEXT: b .LBB3_2
+; CHECK-P9-NEXT: .p2align 4
+; CHECK-P9-NEXT: .LBB3_1: # %if.end116
+; CHECK-P9-NEXT: #
+; CHECK-P9-NEXT: bl callee
+; CHECK-P9-NEXT: nop
+; CHECK-P9-NEXT: mr r3, r29
+; CHECK-P9-NEXT: .LBB3_2: # %cond.end.i.i
+; CHECK-P9-NEXT: # =>This Loop Header: Depth=1
+; CHECK-P9-NEXT: # Child Loop BB3_3 Depth 2
+; CHECK-P9-NEXT: lwz r29, 0(r3)
+; CHECK-P9-NEXT: li r4, 0
+; CHECK-P9-NEXT: .p2align 5
+; CHECK-P9-NEXT: .LBB3_3: # %while.body5.i
+; CHECK-P9-NEXT: # Parent Loop BB3_2 Depth=1
+; CHECK-P9-NEXT: # => This Inner Loop Header: Depth=2
+; CHECK-P9-NEXT: addi r4, r4, -1
+; CHECK-P9-NEXT: cmpwi r4, 0
+; CHECK-P9-NEXT: bgt cr0, .LBB3_3
+; CHECK-P9-NEXT: # %bb.4: # %while.cond12.preheader.i
+; CHECK-P9-NEXT: #
+; CHECK-P9-NEXT: bc 12, 4*cr2+lt, .LBB3_1
+; CHECK-P9-NEXT: # %bb.5: # %for.cond99.preheader
+; CHECK-P9-NEXT: #
+; CHECK-P9-NEXT: ld r4, 0(r3)
+; CHECK-P9-NEXT: extswsli r5, r29, 2
+; CHECK-P9-NEXT: stw r3, 0(r3)
+; CHECK-P9-NEXT: stwx r30, r4, r5
+; CHECK-P9-NEXT: b .LBB3_1
+;
+; CHECK-P9-BE-LABEL: testCaller:
+; CHECK-P9-BE: # %bb.0: # %entry
+; CHECK-P9-BE-NEXT: mfcr r12
+; CHECK-P9-BE-NEXT: mflr r0
+; CHECK-P9-BE-NEXT: stw r12, 8(r1)
+; CHECK-P9-BE-NEXT: stdu r1, -80(r1)
+; CHECK-P9-BE-NEXT: andi. r3, r3, 1
+; CHECK-P9-BE-NEXT: std r0, 96(r1)
+; CHECK-P9-BE-NEXT: std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-P9-BE-NEXT: li r3, -1
+; CHECK-P9-BE-NEXT: li r30, 0
+; CHECK-P9-BE-NEXT: std r29, 56(r1) # 8-byte Folded Spill
+; CHECK-P9-BE-NEXT: crmove 4*cr2+lt, gt
+; CHECK-P9-BE-NEXT: b .LBB3_2
+; CHECK-P9-BE-NEXT: .p2align 4
+; CHECK-P9-BE-NEXT: .LBB3_1: # %if.end116
+; CHECK-P9-BE-NEXT: #
+; CHECK-P9-BE-NEXT: bl callee
+; CHECK-P9-BE-NEXT: nop
+; CHECK-P9-BE-NEXT: mr r3, r29
+; CHECK-P9-BE-NEXT: .LBB3_2: # %cond.end.i.i
+; CHECK-P9-BE-NEXT: # =>This Loop Header: Depth=1
+; CHECK-P9-BE-NEXT: # Child Loop BB3_3 Depth 2
+; CHECK-P9-BE-NEXT: lwz r29, 0(r3)
+; CHECK-P9-BE-NEXT: li r4, 0
+; CHECK-P9-BE-NEXT: .p2align 5
+; CHECK-P9-BE-NEXT: .LBB3_3: # %while.body5.i
+; CHECK-P9-BE-NEXT: # Parent Loop BB3_2 Depth=1
+; CHECK-P9-BE-NEXT: # => This Inner Loop Header: Depth=2
+; CHECK-P9-BE-NEXT: addi r4, r4, -1
+; CHECK-P9-BE-NEXT: cmpwi r4, 0
+; CHECK-P9-BE-NEXT: bgt cr0, .LBB3_3
+; CHECK-P9-BE-NEXT: # %bb.4: # %while.cond12.preheader.i
+; CHECK-P9-BE-NEXT: #
+; CHECK-P9-BE-NEXT: bc 12, 4*cr2+lt, .LBB3_1
+; CHECK-P9-BE-NEXT: # %bb.5: # %for.cond99.preheader
+; CHECK-P9-BE-NEXT: #
+; CHECK-P9-BE-NEXT: ld r4, 0(r3)
+; CHECK-P9-BE-NEXT: extswsli r5, r29, 2
+; CHECK-P9-BE-NEXT: stw r3, 0(r3)
+; CHECK-P9-BE-NEXT: stwx r30, r4, r5
+; CHECK-P9-BE-NEXT: b .LBB3_1
+entry:
+ br label %exit
+
+exit: ; preds = %entry
+ br label %cond.end.i.i
+
+cond.end.i.i: ; preds = %if.end116, %exit
+ %CurrentState.0566 = phi i32 [ %CurrentState.2, %if.end116 ], [ -1, %exit ]
+ %0 = load i32, ptr poison, align 8
+ br label %while.body5.i
+
+while.cond12.preheader.i: ; preds = %while.body5.i
+ br i1 %incond, label %if.end116, label %for.cond99.preheader
+
+while.body5.i: ; preds = %while.body5.i, %cond.end.i.i
+ %Test.012.i = phi i32 [ 0, %cond.end.i.i ], [ %dec10.i, %while.body5.i ]
+ %dec10.i = add nsw i32 %Test.012.i, -1
+ %cmp4.i = icmp slt i32 0, %dec10.i
+ br i1 %cmp4.i, label %while.body5.i, label %while.cond12.preheader.i
+
+for.cond99.preheader: ; preds = %while.cond12.preheader.i
+ %1 = load ptr, ptr poison, align 8
+ %conv103 = sext i32 %0 to i64
+ %arrayidx.i426 = getelementptr inbounds i32, ptr %1, i64 %conv103
+ store i32 0, ptr %arrayidx.i426, align 4
+ store i32 %CurrentState.0566, ptr poison, align 8
+ br label %if.end116
+
+if.end116: ; preds = %for.cond99.preheader, %while.cond12.preheader.i
+ %CurrentState.2 = phi i32 [ %0, %while.cond12.preheader.i ], [ poison, %for.cond99.preheader ]
+ call fastcc void @callee()
+ br label %cond.end.i.i
+}
+declare dso_local fastcc void @callee() unnamed_addr align 2
diff --git a/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir b/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
index 3a1a131af51e613..2432f4245b46d9a 100644
--- a/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
@@ -12,7 +12,7 @@ body: |
%0:g8rc_and_g8rc_nox0 = COPY $x3
%1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 144
%2:g8rc = LI8 0
- ; CHECK: STD killed %2, 160, %0
+ ; CHECK: STD killed %2, 160, killed %0
STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
BLR8 implicit $lr8, implicit $rm
...
@@ -27,7 +27,7 @@ body: |
%0:g8rc_and_g8rc_nox0 = COPY $x3
%1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 141
%2:g8rc = LI8 0
- ; CHECK: STD killed %2, 16, %1
+ ; CHECK: STD killed %2, 16, killed %1
STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
BLR8 implicit $lr8, implicit $rm
...
@@ -42,7 +42,7 @@ body: |
%0:g8rc_and_g8rc_nox0 = COPY $x3
%1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 144
%2:g8rc = LI8 0
- ; CHECK: STD %1, 0, %0
+ ; CHECK: STD killed %1, 0, %0
STD %1:g8rc_and_g8rc_nox0, 0, killed %0:g8rc_and_g8rc_nox0
; CHECK: STD killed %2, 160, killed %0
STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-kill-flag.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-kill-flag.mir
index 4b31cf2bf262943..34de071c4159523 100644
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-kill-flag.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-kill-flag.mir
@@ -47,7 +47,7 @@ body: |
STFSX killed $f1, killed $x3, $x5
; CHECK: STFS killed $f1, 100, $x5
STD killed $x5, $x5, 100
- ; CHECK: STD killed $x5, $x5, 100
+ ; CHECK: STD killed $x5, killed $x5, 100
BLR8 implicit $lr8, implicit $rm
...
@@ -100,7 +100,7 @@ body: |
STFSX killed $f1, $zero8, killed $x3
; CHECK: STFS killed $f1, 100, $x5
STD killed $x5, $x5, 100
- ; CHECK: STD killed $x5, $x5, 100
+ ; CHECK: STD killed $x5, killed $x5, 100
BLR8 implicit $lr8, implicit $rm
...
@@ -119,7 +119,7 @@ body: |
STFSX killed $f1, $zero8, $x3
; CHECK: STFS killed $f1, 100, killed $x5
STD killed $x3, $x3, 100
- ; CHECK: STD killed $x3, $x3, 100
+ ; CHECK: STD killed $x3, killed $x3, 100
BLR8 implicit $lr8, implicit $rm
...
@@ -154,9 +154,9 @@ body: |
$x3 = LDX $zero8, killed $x3
; CHECK: $x3 = LD 100, $x5
STD killed $x5, $x5, 100
- ; CHECK: STD killed $x5, $x5, 100
+ ; CHECK: STD killed $x5, killed $x5, 100
STD killed $x3, $x3, 200
- ; CHECK: STD killed $x3, $x3, 200
+ ; CHECK: STD killed $x3, killed $x3, 200
BLR8 implicit $lr8, implicit $rm
...
@@ -175,7 +175,7 @@ body: |
STD killed $x5, $x5, 100
; CHECK: STD $x5, $x5, 100
STD $x3, $x3, 200
- ; CHECK: STD killed $x3, $x3, 200
+ ; CHECK: STD killed $x3, killed $x3, 200
STFSX killed $f1, $zero8, killed $x3
; CHECK: STFS killed $f1, 100, killed $x5
BLR8 implicit $lr8, implicit $rm
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
index f46d4fc0a42a4c0..dfbf412a9392125 100644
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
@@ -304,7 +304,7 @@ body: |
%0 = LI8 234
%1 = COPY $x3
%2 = RLWNM8 %1, %0, 20, 27
- ; CHECK: RLWINM8 %1, 10, 20, 27
+ ; CHECK: RLWINM8 killed %1, 10, 20, 27
; CHECK-LATE: rlwinm 3, 3, 10, 20, 27
$x3 = COPY %2
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -835,7 +835,7 @@ body: |
%2 = COPY %1.sub_32
%3 = LI 140
%4 = RLDCL %0, killed %3, 0
- ; CHECK: RLDICL %0, 12, 0
+ ; CHECK: RLDICL killed %0, 12, 0
; CHECK-LATE: rotldi 3, 3, 12
$x3 = COPY %4
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -945,7 +945,7 @@ body: |
%2 = COPY %1.sub_32
%3 = LI 300
%4 = RLDCR %0, killed %3, 0
- ; CHECK: RLDICR %0, 44, 0
+ ; CHECK: RLDICR killed %0, 44, 0
; CHECK-LATE: rldicr 3, 3, 44, 0
$x3 = COPY %4
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1159,7 +1159,7 @@ body: |
%0 = COPY $x3
%2 = LI 400
%3 = SRD %0, killed %2
- ; CHECK: RLDICL %0, 48, 16
+ ; CHECK: RLDICL killed %0, 48, 16
; CHECK-LATE: rldicl 3, 3, 48, 16
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1265,7 +1265,7 @@ body: |
%0 = COPY $x3
%2 = LI -44
%3 = SRAD %0, killed %2, implicit-def dead $carry
- ; CHECK: SRAD %0, killed %2, implicit-def dead $carry
+ ; CHECK: SRAD killed %0, killed %2, implicit-def dead $carry
; CHECK-LATE: srad 3, 3, 4
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1318,7 +1318,7 @@ body: |
%0 = COPY $x3
%2 = LI 68
%3 = SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
- ; CHECK: SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
+ ; CHECK: SRAD_rec killed %0, killed %2, implicit-def dead $carry, implicit-def $cr0
; CHECK-LATE: srad. 3, 3, 5
%4 = COPY killed $cr0
%5 = ISEL8 %1, %3, %4.sub_eq
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
index eb93a5188722205..b62616ddead7554 100644
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
@@ -1113,7 +1113,7 @@ body: |
%0 = COPY $x3
%2 = ADD8 %0, %1
%3 = ADD8 killed %1, killed %2
- ; CHECK: ADDI8 %0, 33
+ ; CHECK: ADDI8 killed %0, 33
; CHECK: ADDI8 killed %2, 33
; CHECK-LATE: addi 3, 3, 33
; CHECK-LATE: addi 3, 3, 33
@@ -1176,7 +1176,7 @@ body: |
%4 = COPY %0.sub_32
%5 = LI 55
%6 = ADDC %5, %4, implicit-def $carry
- ; CHECK: ADDIC %4, 55, implicit-def $carry
+ ; CHECK: ADDIC killed %4, 55, implicit-def $carry
; CHECK-LATE: addic 3, 3, 55
%7 = ADDE8 %3, %1, implicit-def dead $carry, implicit $carry
%8 = EXTSW_32_64 %6
@@ -1235,7 +1235,7 @@ body: |
%1 = COPY $x4
%0 = LI8 777
%4 = ADDC8 %2, %0, implicit-def $carry
- ; CHECK: ADDIC8 %2, 777, implicit-def $carry
+ ; CHECK: ADDIC8 killed %2, 777, implicit-def $carry
; CHECK-LATE: addic 3, 5, 777
%5 = ADDE8 %3, %1, implicit-def dead $carry, implicit $carry
$x3 = COPY %4
@@ -1293,7 +1293,7 @@ body: |
%0 = COPY $x3
%2 = COPY %0.sub_32
%3 = ADDC_rec %1, %2, implicit-def $cr0, implicit-def $carry
- ; CHECK: ADDIC_rec %2, 433, implicit-def $cr0, implicit-def $carry
+ ; CHECK: ADDIC_rec killed %2, 433, implicit-def $cr0, implicit-def dead $carry
; CHECK-LATE: addic. 3, 3, 433
%4 = COPY killed $cr0
%5 = COPY %4.sub_eq
@@ -1615,7 +1615,7 @@ body: |
%0 = LI8 89
%2 = CMPDI %0, 87
%4 = ISEL8 $zero8, %0, %2.sub_gt
- ; CHECK: ADDI8 %1, 0
+ ; CHECK: ADDI8 killed %1, 0
%5 = ADD8 killed %4, %1
$x3 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1668,7 +1668,7 @@ body: |
%0 = LI8 87
%2 = CMPDI %0, 87
%4 = ISEL8 $zero8, %0, %2.sub_gt
- ; CHECK: COPY %0
+ ; CHECK: COPY killed %0
%5 = ADD8 killed %4, %1
$x3 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1775,7 +1775,7 @@ body: |
%0 = LI8 65534
%2 = CMPLDI %0, 65535
%4 = ISEL8 $zero8, %0, %2.sub_gt
- ; CHECK: COPY %0
+ ; CHECK: COPY killed %0
%5 = ADD8 killed %4, %1
$x3 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1892,7 +1892,7 @@ body: |
%3 = LI -3
%4 = CMPWI %3, 87
%6 = ISEL $zero, %3, %4.sub_gt
- ; CHECK: COPY %3
+ ; CHECK: COPY killed %3
%7 = ADD4 killed %6, killed %2
%8 = EXTSW_32_64 killed %7
$x3 = COPY %8
@@ -2094,7 +2094,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 -15
%12,%17 = LBZUX %0, killed %11 :: (load (s8) from %ir.arrayidx3, !tbaa !3)
- ; CHECK: LBZU -15, %0
+ ; CHECK: LBZU -15, killed %0
; CHECK-LATE: lbzu 5, -15(3)
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
@@ -2251,7 +2251,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 31440
%12,%17 = LHZUX %0, killed %11 :: (load (s16) from %ir.arrayidx3, !tbaa !6)
- ; CHECK: LHZU 31440, %0
+ ; CHECK: LHZU 31440, killed %0
; CHECK-LATE: lhzu 5, 31440(3)
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
@@ -2328,7 +2328,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 882
%12 = LHZX %0, killed %11 :: (load (s16) from %ir.arrayidx3, !tbaa !6)
- ; CHECK: LHZ 882, %0
+ ; CHECK: LHZ 882, killed %0
; CHECK-LATE: lhz 3, 882(3)
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
@@ -2406,7 +2406,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 400
%12,%17 = LHAUX %0, killed %11 :: (load (s16) from %ir.arrayidx3, !tbaa !6)
- ; CHECK: LHAU 400, %0
+ ; CHECK: LHAU 400, killed %0
; CHECK-LATE: lhau 5, 400(3)
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
@@ -2485,7 +2485,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 999
%12 = LHAX %0, killed %11 :: (load (s16) from %ir.arrayidx3, !tbaa !6)
- ; CHECK: LHA 999, %0
+ ; CHECK: LHA 999, killed %0
; CHECK-LATE: lha 3, 999(3)
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
@@ -2566,7 +2566,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 -2
%12,%18 = LWZUX %0, killed %11 :: (load (s32) from %ir.arrayidx3, !tbaa !8)
- ; CHECK: LWZU -2, %0
+ ; CHECK: LWZU -2, killed %0
; CHECK-LATE: lwzu {{[0-9]+}}, -2({{[0-9]+}})
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
@@ -2796,7 +2796,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 200
%12,%15 = LDUX %0, killed %11 :: (load (s64) from %ir.arrayidx3, !tbaa !10)
- ; CHECK: LDU 200, %0
+ ; CHECK: LDU 200, killed %0
; CHECK-LATE: ldu {{[0-9]+}}, 200({{[0-9]+}})
%13 = ADD8 killed %12, killed %7
$x3 = COPY %13
@@ -2869,7 +2869,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 280
%12 = LDX %0, killed %11 :: (load (s64) from %ir.arrayidx3, !tbaa !10)
- ; CHECK: LD 280, %0
+ ; CHECK: LD 280, killed %0
; CHECK-LATE: ld 3, 280(3)
%13 = ADD8 killed %12, killed %7
$x3 = COPY %13
@@ -2944,7 +2944,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 16
%12,%15 = LFDUX %0, killed %11 :: (load (s64) from %ir.arrayidx3, !tbaa !12)
- ; CHECK: LFDU 16, %0
+ ; CHECK: LFDU 16, killed %0
; CHECK-LATE: lfdu {{[0-9]+}}, 16({{[0-9]+}})
%13 = FADD killed %7, killed %12, implicit $rm
$f1 = COPY %13
@@ -3110,7 +3110,7 @@ body: |
%0 = COPY $x3
%2 = LI8 72
%3, %4 = LFSUX %0, killed %2 :: (load (s32) from %ir.arrayidx, !tbaa !14)
- ; CHECK: LFSU 72, %0
+ ; CHECK: LFSU 72, killed %0
; CHECK-LATE: lfsu 0, 72(3)
%5 = FCTIWUZ killed %3, implicit $rm
%6 = ADDI8 %stack.4, 0
@@ -3207,7 +3207,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 -88
%12 = LFSX %0, killed %11 :: (load (s32) from %ir.arrayidx3, !tbaa !14)
- ; CHECK: LFS -88, %0
+ ; CHECK: LFS -88, killed %0
; CHECK-LATE: lfs 1, -88(3)
%13 = FADDS killed %7, killed %12, implicit $rm
$f1 = COPY %13
@@ -3280,7 +3280,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 -120
%12 = LXSDX %0, killed %11, implicit $rm :: (load (s64) from %ir.arrayidx3, !tbaa !12)
- ; CHECK: DFLOADf64 -120, %0
+ ; CHECK: DFLOADf64 -120, killed %0
; CHECK-LATE: lfd 1, -120(3)
%13 = XSADDDP killed %7, killed %12, implicit $rm
$f1 = COPY %13
@@ -3353,7 +3353,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 -92
%12 = LXSSPX %0, killed %11 :: (load (s32) from %ir.arrayidx3, !tbaa !14)
- ; CHECK: DFLOADf32 -92, %0
+ ; CHECK: DFLOADf32 -92, killed %0
; CHECK-LATE: lfs 1, -92(3)
%13 = XSADDSP killed %7, killed %12
$f1 = COPY %13
@@ -3426,7 +3426,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 -16
%12 = LXVX %0, killed %11 :: (load (s128) from %ir.arrayidx3, !tbaa !3)
- ; CHECK: LXV -16, %0
+ ; CHECK: LXV -16, killed %0
; CHECK-LATE: lxv 35, -16(3)
%13 = VADDUWM killed %12, killed %7
$v2 = COPY %13
@@ -3478,7 +3478,7 @@ body: |
%0 = LI 99
%3 = COPY %1.sub_32
%2 = OR %0, %3
- ; CHECK: ORI %3, 99
+ ; CHECK: ORI killed %3, 99
; CHECK-LATE: ori 3, 4, 99
$x3 = EXTSW_32_64 %2
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -3527,7 +3527,7 @@ body: |
%1 = COPY $x4
%0 = LI8 777
%2 = OR8 %1, %0
- ; CHECK: ORI8 %1, 777
+ ; CHECK: ORI8 killed %1, 777
; CHECK-LATE: ori 3, 4, 777
$x3 = COPY %2
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -3672,7 +3672,7 @@ body: |
%2 = COPY %1.sub_32
%3 = LI 14
%4 = RLDCL %0, killed %3, 0
- ; CHECK: RLDICL %0, 14, 0
+ ; CHECK: RLDICL killed %0, 14, 0
; CHECK-LATE: rotldi 3, 3, 14
$x3 = COPY %4
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -3782,7 +3782,7 @@ body: |
%2 = COPY %1.sub_32
%3 = LI 0
%4 = RLDCR %0, killed %3, 0
- ; CHECK: RLDICR %0, 0, 0
+ ; CHECK: RLDICR killed %0, 0, 0
; CHECK-LATE: rldicr 3, 3, 0, 0
$x3 = COPY %4
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -3982,7 +3982,7 @@ body: |
%1 = COPY $x4
%0 = LI8 -1
%2 = RLDICL_rec %0, 53, 48, implicit-def $cr0
- ; CHECK: ANDI8_rec %0, 65535
+ ; CHECK: ANDI8_rec killed %0, 65535
; CHECK-LATE: li 3, -1
; CHECK-LATE: andi. 3, 3, 65535
%3 = COPY killed $cr0
@@ -4037,7 +4037,7 @@ body: |
%0 = LI8 200
%2 = RLDICL_rec %0, 61, 3, implicit-def $cr0
; CHECK: LI8 25
- ; CHECK: ANDI8_rec %0, 25
+ ; CHECK: ANDI8_rec killed %0, 25
; CHECK-LATE-NOT: andi.
%3 = COPY killed $cr0
%4 = ISEL8 %1, %2, %3.sub_eq
@@ -4090,7 +4090,7 @@ body: |
%1 = COPY $x4
%0 = LI8 2
%2 = RLDICL_rec %0, 32, 32, implicit-def $cr0
- ; CHECK: ANDI8_rec %0, 0
+ ; CHECK: ANDI8_rec killed %0, 0
; CHECK-LATE: li 3, 2
; CHECK-LATE: andi. 3, 3, 0
%3 = COPY killed $cr0
@@ -4480,7 +4480,7 @@ body: |
%0 = COPY $x3
%2 = LI8 -18
%3 = RLWINM8_rec %2, 4, 20, 27, implicit-def $cr0
- ; CHECK: ANDI8_rec %2, 3808
+ ; CHECK: ANDI8_rec killed %2, 3808
; CHECK-LATE: li 3, -18
; CHECK-LATE: andi. 3, 3, 3808
%7 = COPY killed $cr0
@@ -4535,7 +4535,7 @@ body: |
%0 = COPY $x3
%2 = LI 13
%3 = SLD %0, killed %2
- ; CHECK: RLDICR %0, 13, 50
+ ; CHECK: RLDICR killed %0, 13, 50
; CHECK-LATE: sldi 3, 3, 13
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -4641,7 +4641,7 @@ body: |
%0 = COPY $x3
%2 = LI 4
%3 = SRD %0, killed %2
- ; CHECK: RLDICL %0, 60, 4
+ ; CHECK: RLDICL killed %0, 60, 4
; CHECK-LATE: rldicl 3, 3, 60, 4
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -5101,7 +5101,7 @@ body: |
%0 = COPY $x3
%2 = LI 44
%3 = SRAD %0, killed %2, implicit-def dead $carry
- ; CHECK: SRADI %0, 44, implicit-def dead $carry
+ ; CHECK: SRADI killed %0, 44, implicit-def dead $carry
; CHECK-LATE: sradi 3, 3, 44
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -5154,7 +5154,7 @@ body: |
%0 = COPY $x3
%2 = LI 61
%3 = SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
- ; CHECK: SRADI_rec %0, 61, implicit-def dead $carry, implicit-def $cr0
+ ; CHECK: SRADI_rec killed %0, 61, implicit-def dead $carry, implicit-def $cr0
; CHECK-LATE: sradi. 3, 3, 61
%4 = COPY killed $cr0
%5 = ISEL8 %1, %3, %4.sub_eq
@@ -5232,7 +5232,7 @@ body: |
%10 = INSERT_SUBREG %11, killed %9, 1
%12 = LI8 777
%14 = STBUX %3, %0, killed %12 :: (store (s8) into %ir.arrayidx3, !tbaa !3)
- ; CHECK: STBU %3, 777, %0
+ ; CHECK: STBU killed %3, 777, killed %0
; CHECK-LATE: {{[0-9]+}}, 777({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -5305,7 +5305,7 @@ body: |
%10 = INSERT_SUBREG %11, killed %9, 1
%12 = RLDICL killed %10, 0, 32
STBX %3, %0, killed %12 :: (store (s8) into %ir.arrayidx3, !tbaa !3)
- ; CHECK: STB %3, 975, killed %12
+ ; CHECK: STB killed %3, 975, killed %12
; CHECK-LATE: stb 4, 975(5)
BLR8 implicit $lr8, implicit $rm
@@ -5380,7 +5380,7 @@ body: |
%10 = INSERT_SUBREG %11, killed %9, 1
%12 = LI8 -761
%14 = STHUX %3, %0, killed %12 :: (store (s16) into %ir.arrayidx3, !tbaa !6)
- ; CHECK: STHU %3, -761, %0
+ ; CHECK: STHU killed %3, -761, killed %0
; CHECK-LATE: sthu {{[0-9]+}}, -761({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -5453,7 +5453,7 @@ body: |
%10 = INSERT_SUBREG %11, killed %9, 1
%12 = LI8 -900
STHX %3, %0, killed %12 :: (store (s8) into %ir.arrayidx3, !tbaa !3)
- ; CHECK: STH %3, -900, %0
+ ; CHECK: STH killed %3, -900, killed %0
; CHECK-LATE: sth {{[0-9]+}}, -900({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -5528,7 +5528,7 @@ body: |
%10 = INSERT_SUBREG %11, killed %9, 1
%12 = LI8 0
%14 = STWUX %3, %0, killed %12 :: (store (s32) into %ir.arrayidx3, !tbaa !8)
- ; CHECK: STWU %3, 0, %0
+ ; CHECK: STWU killed %3, 0, killed %0
; CHECK-LATE: stwu {{[0-9]+}}, 0({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -5601,7 +5601,7 @@ body: |
%10 = INSERT_SUBREG %11, killed %9, 1
%12 = LI8 99
STWX %3, %0, killed %12 :: (store (s32) into %ir.arrayidx3, !tbaa !8)
- ; CHECK: STW %3, 99, %0
+ ; CHECK: STW killed %3, 99, killed %0
; CHECK-LATE: stw 4, 99(3)
BLR8 implicit $lr8, implicit $rm
@@ -5674,7 +5674,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 -8
%13 = STDUX %1, %0, killed %11 :: (store (s64) into %ir.arrayidx3, !tbaa !10)
- ; CHECK: STDU %1, -8, %0
+ ; CHECK: STDU killed %1, -8, killed %0
; CHECK-LATE: stdu {{[0-9]+}}, -8({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -5745,7 +5745,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 -900
STDX %1, %0, killed %11 :: (store (s64) into %ir.arrayidx3, !tbaa !10)
- ; CHECK: STD %1, 1000, killed %11
+ ; CHECK: STD killed %1, 1000, killed %11
; CHECK-LATE: {{[0-9]+}}, 1000({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -5816,7 +5816,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 -401
STFSX %1, %0, killed %11 :: (store (s32) into %ir.arrayidx3, !tbaa !14)
- ; CHECK: STFS %1, -401, %0
+ ; CHECK: STFS killed %1, -401, killed %0
; CHECK-LATE: stfs 1, -401(3)
BLR8 implicit $lr8, implicit $rm
@@ -5889,7 +5889,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 987
%13 = STFSUX %1, %0, killed %11 :: (store (s32) into %ir.arrayidx3, !tbaa !14)
- ; CHECK: STFSU %1, 987, %0
+ ; CHECK: STFSU killed %1, 987, killed %0
; CHECK-LATE: stfsu {{[0-9]+}}, 987({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -5960,7 +5960,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 -873
STFDX %1, %0, killed %11 :: (store (s64) into %ir.arrayidx3, !tbaa !12)
- ; CHECK: STFD %1, -873, %0
+ ; CHECK: STFD killed %1, -873, killed %0
; CHECK-LATE: stfd 1, -873(3)
BLR8 implicit $lr8, implicit $rm
@@ -6033,7 +6033,7 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 6477
%13 = STFDUX %1, %0, killed %11 :: (store (s64) into %ir.arrayidx3, !tbaa !12)
- ; CHECK: STFDU %1, 6477, %0
+ ; CHECK: STFDU killed %1, 6477, killed %0
; CHECK-LATE: stfdu {{[0-9]+}}, 6477({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -6085,7 +6085,7 @@ body: |
%0 = COPY $x3
%3 = LI8 444
STXSSPX %1, %0, killed %3 :: (store (s32) into %ir.arrayidx, !tbaa !14)
- ; CHECK: DFSTOREf32 %1, 444, %0
+ ; CHECK: DFSTOREf32 killed %1, 444, killed %0
; CHECK-LATE: stfs 1, 444(3)
BLR8 implicit $lr8, implicit $rm
@@ -6137,7 +6137,7 @@ body: |
%0 = COPY $x3
%3 = LI8 4
STXSDX %1, %0, killed %3, implicit $rm :: (store (s64) into %ir.arrayidx, !tbaa !12)
- ; CHECK: DFSTOREf64 %1, 4, %0
+ ; CHECK: DFSTOREf64 killed %1, 4, killed %0
; CHECK-LATE: stfd 1, 4(3)
BLR8 implicit $lr8, implicit $rm
@@ -6189,7 +6189,7 @@ body: |
%0 = LI8 16
%3 = RLDICR %2, 4, 59
STXVX %1, %0, killed %3 :: (store (s128) into %ir.arrayidx, !tbaa !3)
- ; CHECK: STXV %1, 16, killed %3
+ ; CHECK: STXV killed %1, 16, killed %3
; CHECK-LATE: stxv 34, 16(4)
BLR8 implicit $lr8, implicit $rm
@@ -6250,7 +6250,7 @@ body: |
%8 = COPY %1.sub_32
%0 = LI 55
%4 = SUBFC %7, %0, implicit-def $carry
- ; CHECK: SUBFIC %7, 55
+ ; CHECK: SUBFIC killed %7, 55
; CHECK-LATE: subfic 3, 5, 55
%5 = SUBFE %6, %8, implicit-def dead $carry, implicit $carry
$x3 = EXTSW_32_64 %4
@@ -6308,7 +6308,7 @@ body: |
%1 = COPY $x4
%0 = LI8 7635
%4 = SUBFC8 %2, %0, implicit-def $carry
- ; CHECK: SUBFIC8 %2, 7635
+ ; CHECK: SUBFIC8 killed %2, 7635
; CHECK-LATE: subfic 3, 5, 7635
%5 = SUBFE8 %3, %1, implicit-def dead $carry, implicit $carry
$x3 = COPY %4
@@ -6361,7 +6361,7 @@ body: |
%0 = COPY $x3
%3 = COPY %0.sub_32
%2 = XOR %1, %3
- ; CHECK: XORI %3, 10101
+ ; CHECK: XORI killed %3, 10101
; CHECK-LATE: 3, 3, 10101
$x3 = EXTSW_32_64 %2
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -6410,7 +6410,7 @@ body: |
%1 = COPY $x4
%0 = LI8 5535
%2 = XOR8 %1, %0
- ; CHECK: XORI8 %1, 5535
+ ; CHECK: XORI8 killed %1, 5535
; CHECK-LATE: xori 3, 4, 5535
$x3 = COPY %2
BLR8 implicit $lr8, implicit $rm, implicit $x3
diff --git a/llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir b/llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir
index 84c9b183e86df83..66a266e89a9f728 100644
--- a/llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir
+++ b/llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir
@@ -28,11 +28,11 @@ body: |
liveins: $r3
%0:gprc = COPY $r3
%1:gprc_and_gprc_nor0 = LI 0
- ; CHECK: dead %2:gprc = COPY %1
+ ; CHECK-NOT: COPY %1
%2:gprc = COPY %1:gprc_and_gprc_nor0
; CHECK: %3:gprc = LI 1
%3:gprc = ORI killed %2:gprc, 1
- ; CHECK: STW killed %3, %0, 100
+ ; CHECK: STW killed %3, killed %0, 100
STW killed %3:gprc, %0:gprc, 100
BLR8 implicit $lr8, implicit $rm
...
diff --git a/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir b/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
index 7a220964b0fd14c..729895efb11bb32 100644
--- a/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
+++ b/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
@@ -13,7 +13,7 @@ body: |
%2:gprc = RLWINM %1:gprc, 27, 5, 31
; CHECK-NOT: %2:gprc = RLWINM %1, 27, 5, 31
%3:gprc = RLWINM %2:gprc, 19, 0, 12
- ; CHECK: %3:gprc = RLWINM %1, 14, 0, 12
+ ; CHECK: %3:gprc = RLWINM killed %1, 14, 0, 12
BLR8 implicit $lr8, implicit $rm
...
---
@@ -28,7 +28,7 @@ body: |
%2:gprc = RLWINM %1:gprc, 27, 0, 31
; CHECK-NOT: %2:gprc = RLWINM %1, 27, 0, 31
%3:gprc = RLWINM %2:gprc, 19, 0, 12
- ; CHECK: %3:gprc = RLWINM %1, 14, 0, 12
+ ; CHECK: %3:gprc = RLWINM killed %1, 14, 0, 12
BLR8 implicit $lr8, implicit $rm
...
---
@@ -43,7 +43,7 @@ body: |
%2:gprc = RLWINM %1:gprc, 27, 10, 9
; CHECK-NOT: %2:gprc = RLWINM %1, 27, 10, 9
%3:gprc = RLWINM %2:gprc, 19, 10, 1
- ; CHECK: %3:gprc = RLWINM %1, 14, 10, 1
+ ; CHECK: %3:gprc = RLWINM killed %1, 14, 10, 1
BLR8 implicit $lr8, implicit $rm
...
---
@@ -58,7 +58,7 @@ body: |
%2:gprc = RLWINM %1:gprc, 27, 30, 10
; CHECK-NOT: %2:gprc = RLWINM %1, 27, 30, 10
%3:gprc = RLWINM %2:gprc, 19, 0, 12
- ; CHECK: %3:gprc = RLWINM %1, 14, 11, 12
+ ; CHECK: %3:gprc = RLWINM killed %1, 14, 11, 12
BLR8 implicit $lr8, implicit $rm
...
---
@@ -71,9 +71,9 @@ body: |
%0:g8rc = COPY $x3
%1:gprc = COPY %0.sub_32:g8rc
%2:gprc = RLWINM %1:gprc, 10, 5, 31
- ; CHECK: %2:gprc = RLWINM %1, 10, 5, 31
+ ; CHECK: %2:gprc = RLWINM killed %1, 10, 5, 31
%3:gprc = RLWINM %2:gprc, 10, 30, 5
- ; CHECK: %3:gprc = RLWINM %2, 10, 30, 5
+ ; CHECK: %3:gprc = RLWINM killed %2, 10, 30, 5
BLR8 implicit $lr8, implicit $rm
...
---
@@ -85,10 +85,10 @@ body: |
liveins: $x3
%0:g8rc = COPY $x3
%1:gprc = COPY %0.sub_32:g8rc
- %2:gprc = RLWINM %1:gprc, 10, 20, 10
- ; CHECK: %2:gprc = RLWINM %1, 10, 20, 10
- %3:gprc = RLWINM %2:gprc, 10, 0, 31
- ; CHECK: %3:gprc = RLWINM %2, 10, 0, 31
+ %2:gprc = RLWINM killed %1:gprc, 10, 20, 10
+ ; CHECK: %2:gprc = RLWINM killed %1, 10, 20, 10
+ %3:gprc = RLWINM killed %2:gprc, 10, 0, 31
+ ; CHECK: %3:gprc = RLWINM killed %2, 10, 0, 31
BLR8 implicit $lr8, implicit $rm
...
---
@@ -105,7 +105,7 @@ body: |
%3:gprc = RLWINM %2:gprc, 19, 0, 12
; CHECK: %3:gprc = RLWINM killed %1, 14, 0, 12
STW %3:gprc, %2:gprc, 100
- ; CHECK: STW %3, %2, 100
+ ; CHECK: STW killed %3, killed %2, 100
BLR8 implicit $lr8, implicit $rm
...
---
@@ -135,7 +135,7 @@ body: |
%2:gprc = RLWINM %1:gprc, 27, 5, 10
; CHECK-NOT: RLWINM %1,
%3:gprc = RLWINM_rec %2:gprc, 8, 5, 10, implicit-def $cr0
- ; CHECK: %3:gprc = ANDI_rec %1, 0, implicit-def $cr0
+ ; CHECK: %3:gprc = ANDI_rec killed %1, 0, implicit-def dead $cr0
BLR8 implicit $lr8, implicit $rm
...
---
@@ -147,10 +147,10 @@ body: |
liveins: $x3
%0:g8rc = COPY $x3
%1:gprc = COPY %0.sub_32:g8rc
- %2:gprc = RLWINM_rec %1:gprc, 27, 5, 10, implicit-def $cr0
- ; CHECK: %2:gprc = RLWINM_rec %1, 27, 5, 10, implicit-def $cr0
- %3:gprc = RLWINM_rec %2:gprc, 8, 5, 10, implicit-def $cr0
- ; CHECK: %3:gprc = ANDI_rec %1, 0, implicit-def $cr0
+ %2:gprc = RLWINM_rec killed %1:gprc, 27, 5, 10, implicit-def $cr0
+ ; CHECK: %2:gprc = RLWINM_rec %1, 27, 5, 10, implicit-def dead $cr0
+ %3:gprc = RLWINM_rec killed %2:gprc, 8, 5, 10, implicit-def $cr0
+ ; CHECK: %3:gprc = ANDI_rec killed %1, 0, implicit-def dead $cr0
BLR8 implicit $lr8, implicit $rm
...
---
@@ -163,9 +163,9 @@ body: |
%0:g8rc = COPY $x3
%1:gprc = COPY %0.sub_32:g8rc
%2:gprc = RLWINM %1:gprc, 20, 5, 31
- ; CHECK: %2:gprc = RLWINM %1, 20, 5, 31
+ ; CHECK: %2:gprc = RLWINM killed %1, 20, 5, 31
%3:gprc = RLWINM %2:gprc, 19, 10, 20
- ; CHECK: %3:gprc = RLWINM %2, 19, 10, 20
+ ; CHECK: %3:gprc = RLWINM killed %2, 19, 10, 20
BLR8 implicit $lr8, implicit $rm
...
---
@@ -190,10 +190,10 @@ body: |
liveins: $x3
; CHECK-LABEL: name: testFoldRLWINMAndANDI
; CHECK: liveins: $x3
- ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x3
- ; CHECK: [[COPY1:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
- ; CHECK: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 4, 28, 31
- ; CHECK: [[ANDI_rec:%[0-9]+]]:gprc = ANDI_rec [[RLWINM]], 4, implicit-def $cr0
+ ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
+ ; CHECK: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32
+ ; CHECK: [[RLWINM:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 4, 28, 31
+ ; CHECK: [[ANDI_rec:%[0-9]+]]:gprc = ANDI_rec killed [[RLWINM]], 4, implicit-def dead $cr0
; CHECK: BLR8 implicit $lr8, implicit $rm
%0:g8rc = COPY $x3
%1:gprc = COPY %0.sub_32:g8rc
diff --git a/llvm/test/CodeGen/PowerPC/mi-peephole.mir b/llvm/test/CodeGen/PowerPC/mi-peephole.mir
index 7bedc05de2df192..a2cc364e28ab7f5 100644
--- a/llvm/test/CodeGen/PowerPC/mi-peephole.mir
+++ b/llvm/test/CodeGen/PowerPC/mi-peephole.mir
@@ -28,9 +28,9 @@ body: |
; CHECK-LABEL: testRLDIC
; CHECK: bb.0.entry:
- ; CHECK: %1:g8rc = COPY $x4
- ; CHECK: %0:g8rc = COPY $x3
+ ; CHECK: %1:g8rc = COPY killed $x4
+ ; CHECK: %0:g8rc = COPY killed $x3
; CHECK: %3:g8rc = RLDIC killed %1, 2, 30
- ; CHECK: $x3 = COPY %3
- ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ; CHECK: $x3 = COPY killed %3
+ ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
...
diff --git a/llvm/test/CodeGen/PowerPC/opt-cmp-rec-postra.mir b/llvm/test/CodeGen/PowerPC/opt-cmp-rec-postra.mir
index 1c00df2d26cfab1..5a842c44b60b066 100644
--- a/llvm/test/CodeGen/PowerPC/opt-cmp-rec-postra.mir
+++ b/llvm/test/CodeGen/PowerPC/opt-cmp-rec-postra.mir
@@ -11,7 +11,7 @@ body: |
renamable $x3 = OR8 killed renamable $x3, killed renamable $x4
renamable $cr0 = CMPDI renamable $x3, 0, implicit killed $x3
; CHECK-LABEL: name: test1
- ; CHECK: renamable $x3 = OR8_rec renamable $x3, killed renamable $x4, implicit-def $cr0
+ ; CHECK: renamable $x3 = OR8_rec killed renamable $x3, killed renamable $x4, implicit-def $cr0
; CHECK-NOT: CMPDI
BCC 68, killed renamable $cr0, %bb.2
diff --git a/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir b/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
index 86dcda229f0819f..739bad616610c47 100644
--- a/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
+++ b/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
@@ -8,31 +8,35 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: poc
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1, %bb.2
- ; CHECK: liveins: $x3, $x4, $x5, $x6
- ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x6
- ; CHECK: [[COPY1:%[0-9]+]]:g8rc = COPY $x5
- ; CHECK: [[COPY2:%[0-9]+]]:g8rc = COPY $x4
- ; CHECK: [[COPY3:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
- ; CHECK: [[ANDI8_rec_:%[0-9]+]]:g8rc = ANDI8_rec [[COPY1]], 1, implicit-def $cr0
- ; CHECK: [[COPY4:%[0-9]+]]:crbitrc = COPY $cr0gt
- ; CHECK: BCn killed [[COPY4]], %bb.2
- ; CHECK: B %bb.1
- ; CHECK: bb.1:
- ; CHECK: liveins: $x3
- ; CHECK: [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
- ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
- ; CHECK: $x3 = COPY [[RLDICR]]
- ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
- ; CHECK: [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
- ; CHECK: $x3 = COPY [[ADD8_]]
- ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
- ; CHECK: bb.2:
- ; CHECK: [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
- ; CHECK: [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
- ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[COPY5]], %subreg.sub_32
- ; CHECK: $x3 = COPY [[INSERT_SUBREG]]
- ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ ; CHECK-NEXT: successors: %bb.1, %bb.2
+ ; CHECK-NEXT: liveins: $x3, $x4, $x5, $x6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x6
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc = COPY killed $x5
+ ; CHECK-NEXT: dead %2:g8rc = COPY killed $x4
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3
+ ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec killed [[COPY1]], 1, implicit-def dead $cr0, implicit-def $cr0gt
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:crbitrc = COPY killed $cr0gt
+ ; CHECK-NEXT: BCn killed [[COPY3]], %bb.2
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[EXTSW:%[0-9]+]]:g8rc = EXTSW killed $x3
+ ; CHECK-NEXT: [[RLDICR:%[0-9]+]]:g8rc = RLDICR killed [[ANDI8_rec]], 2, 61
+ ; CHECK-NEXT: dead $x3 = COPY killed [[RLDICR]]
+ ; CHECK-NEXT: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR killed [[EXTSW]], 2, 61
+ ; CHECK-NEXT: [[ADD8_:%[0-9]+]]:g8rc = ADD8 killed [[COPY2]], killed [[RLDICR1]]
+ ; CHECK-NEXT: $x3 = COPY killed [[ADD8_]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG killed [[DEF]], killed [[COPY4]], %subreg.sub_32
+ ; CHECK-NEXT: $x3 = COPY killed [[INSERT_SUBREG]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
bb.0.entry:
successors: %bb.1, %bb.2
liveins: $x3, $x4, $x5, $x6
diff --git a/llvm/test/CodeGen/PowerPC/peephole-phi-acc.mir b/llvm/test/CodeGen/PowerPC/peephole-phi-acc.mir
index 116a9529d280e03..f615fcf9f8157f5 100644
--- a/llvm/test/CodeGen/PowerPC/peephole-phi-acc.mir
+++ b/llvm/test/CodeGen/PowerPC/peephole-phi-acc.mir
@@ -674,6 +674,7 @@ registers:
- { id: 52, class: vsrprc, preferred-register: '' }
- { id: 53, class: vsrc, preferred-register: '' }
- { id: 54, class: vsrprc, preferred-register: '' }
+ - { id: 55, class: crrc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%7' }
- { reg: '$v2', virtual-reg: '%8' }
@@ -767,22 +768,24 @@ body: |
%37:g8rc_and_g8rc_nox0 = RLDICL killed %35, 0, 32
%38:g8rc = nuw nsw ADDI8 killed %37, 1
MTCTR8loop killed %38, implicit-def dead $ctr8
+ B %bb.5
bb.5.for.body.epil:
successors: %bb.3(0x40000000), %bb.5(0x7c000000)
- ; We check that no phi node is inserted in the block.
+ ; We check that no [u]acc phi node is inserted in the block.
; CHECK-LABEL: bb.{{[0-9]}}.for.body.epil:
; CHECK-NEXT: successors: %bb.{{[0-9]}}(0x{{[0-9a-f]+}}), %bb.{{[0-9]}}(0x{{[0-9a-f]+}})
- ; CHECK-NEXT: {{ }}
- ; CHECK-NEXT: %2:uaccrc = PHI
+ ; CHECK-NOT: uaccrc = PHI
+ ; CHECK-NOT: accrc = PHI
+ ; CHECK: %2:uaccrc = PHI
; CHECK-NEXT: %39:vsrc
%2:uaccrc = PHI %1, %bb.4, %3, %bb.5
%39:vsrc = COPY %8
%41:accrc = COPY %2
%40:accrc = XVF32GERPP %41, %39, %39
%3:uaccrc = COPY %40
- %15:crrc = CMPLWI %14, 7
- BCC 12, killed %15, %bb.5
+ %55:crrc = CMPLWI %14, 7
+ BCC 12, killed %55, %bb.5
B %bb.3
bb.6.for.cond.cleanup:
diff --git a/llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir b/llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir
index 90acaa8780ff62f..ffe0c6144aa1073 100644
--- a/llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir
+++ b/llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir
@@ -18,5 +18,5 @@ body: |
; CHECK: bb.0.entry:
; CHECK: STW killed $r3, killed $x5, 100
; CHECK: renamable $x4 = exact RLDICL killed renamable $x4, 62, 2
- ; CHECK: STD killed $x4, $x4, 100
+ ; CHECK: STD killed $x4, killed $x4, 100
; CHECK: BLR8 implicit $lr8, implicit $rm
diff --git a/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir b/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
index dbe314b5251fe83..a1d8539dd8cb6b0 100644
--- a/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
+++ b/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
@@ -122,7 +122,7 @@ body: |
%3:gprc = LI -11
%4:gprc_and_gprc_nor0 = RLWINM_rec %3, 2, 20, 31, implicit-def $cr0
; CHECK: LI 4055
- ; CHECK: ANDI_rec %3, 4055
+ ; CHECK: ANDI_rec killed %3, 4055
; CHECK-LATE-NOT: andi.
; CHECK-LATE: rlwinm.
%5:crrc = COPY killed $cr0
@@ -297,7 +297,7 @@ body: |
%0:g8rc = LI8 -11
%2:g8rc_and_g8rc_nox0 = RLDICL_rec %0, 2, 49, implicit-def $cr0
; CHECK: LI8 32727
- ; CHECK: ANDI8_rec %0, 32727
+ ; CHECK: ANDI8_rec killed %0, 32727
; CHECK-LATE-NOT: andi.
; CHECK-LATE: rldicl.
%3:crrc = COPY killed $cr0
diff --git a/llvm/test/CodeGen/PowerPC/sext_elimination.mir b/llvm/test/CodeGen/PowerPC/sext_elimination.mir
index cafcdc3e76ca29b..e920848a4137cdb 100644
--- a/llvm/test/CodeGen/PowerPC/sext_elimination.mir
+++ b/llvm/test/CodeGen/PowerPC/sext_elimination.mir
@@ -38,12 +38,12 @@ body: |
liveins: $x3
; CHECK-LABEL: bb.0.entry:
- ; CHECK: %4:g8rc = EXTSW_32_64 %3
+ ; CHECK: %4:g8rc = EXTSW_32_64 killed %3
; CHECK: %5:g8rc = INSERT_SUBREG %15, %1, %subreg.sub_32
- ; CHECK: %7:g8rc = EXTSW_32_64 %6
+ ; CHECK: %7:g8rc = EXTSW_32_64 killed %6
; CHECK: %9:g8rc = INSERT_SUBREG %16, %8, %subreg.sub_32
; CHECK: %11:g8rc = INSERT_SUBREG %17, %10, %subreg.sub_32
- ; CHECK: %14:g8rc = COPY %1
+ ; CHECK: %14:g8rc = COPY killed %13
%0:g8rc_nox0 = COPY $x3
%1:gprc, %2:g8rc_nox0 = LBZU 0, %0:g8rc_nox0
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