[llvm] [RISCV][GISel] Implement instruction selection for G_PHI and G_BRCOND. (PR #66970)

[Amara Emerson via llvm-commits]

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@@ -0,0 +1,88 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: | FileCheck -check-prefix=RV32I %s
+
+---
+name:            phi_i32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; RV32I-LABEL: name: phi_i32
+  ; RV32I: bb.0:
+  ; RV32I-NEXT:   liveins: $x10, $x11, $x12
+  ; RV32I-NEXT: {{  $}}
+  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
+  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV32I-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x12
+  ; RV32I-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
+  ; RV32I-NEXT:   BNE [[ANDI]], $x0, %bb.2
+  ; RV32I-NEXT:   PseudoBR %bb.1
+  ; RV32I-NEXT: {{  $}}
+  ; RV32I-NEXT: bb.1:
+  ; RV32I-NEXT: {{  $}}
+  ; RV32I-NEXT: bb.2:
+  ; RV32I-NEXT:   [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.1, [[COPY1]], %bb.0
+  ; RV32I-NEXT:   $x10 = COPY [[PHI]]
+  ; RV32I-NEXT:   PseudoRET implicit $x10
+  bb.0:
+    liveins: $x10, $x11, $x12
+
+    %0:gprb(s32) = COPY $x10
+    %1:gprb(s32) = COPY $x11
+    %2:gprb(s32) = COPY $x12
+    %3:gprb(s32) = G_CONSTANT i32 1
+    %4:gprb(s32) = G_AND %0, %3
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aemerson wrote:

It's fine, they're harmless.

https://github.com/llvm/llvm-project/pull/66970