[llvm] ISel/RISCV: remove dead code corresponding to VP_FSH[L|R] (PR #67035)

via llvm-commits llvm-commits at lists.llvm.org
Thu Sep 21 09:14:32 PDT 2023


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

<details>
<summary>Changes</summary>

70de0e ([VP][RISCV] Add vp.fshl/fshr and RISC-V support.) introduced VP_FSHL and VP_FSHR, by using a generic expansion for all targets: the core of this change is in TargetLowering. However, the commit erroneously introduced dead code in RISCVISelLowering. Remove this dead code.

---
Full diff: https://github.com/llvm/llvm-project/pull/67035.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (-2) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f1cea6c6756f4fc..9533f746305c3ae 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -715,8 +715,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
       setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT,
                          Legal);
 
-      setOperationAction({ISD::VP_FSHL, ISD::VP_FSHR}, VT, Expand);
-
       // Custom-lower extensions and truncations from/to mask types.
       setOperationAction({ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND},
                          VT, Custom);

``````````

</details>


https://github.com/llvm/llvm-project/pull/67035


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