Author: Simon Pilgrim
Date: 2023-09-21T12:07:49+01:00
New Revision: 05926a5a557878aa233ac8431b3acddf54422e58
URL: https://github.com/llvm/llvm-project/commit/05926a5a557878aa233ac8431b3acddf54422e58
DIFF: https://github.com/llvm/llvm-project/commit/05926a5a557878aa233ac8431b3acddf54422e58.diff
LOG: [DAG] getNode() - remove oneuse limit from (zext (trunc (assertzext x))) -> (assertzext x) fold
Noticed on D159533 and I've finally deal with the x86 regressions - MatchingStackOffset wasn't peeking through AssertZext nodes while trying to find CopyFromReg/Load sources, it was only removing them if they were part of a (trunc (assertzext x)) pattern.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/Target/X86/X86ISelLoweringCall.cpp
llvm/test/CodeGen/AArch64/setcc_knownbits.ll
llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index c15f056551b93fd..f12db53c7f08738 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5700,7 +5700,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
if (OpOpcode == ISD::TRUNCATE) {
SDValue OpOp = N1.getOperand(0);
if (OpOp.getValueType() == VT) {
- if (OpOp.getOpcode() == ISD::AssertZext && N1->hasOneUse()) {
+ if (OpOp.getOpcode() == ISD::AssertZext) {
APInt HiBits = APInt::getBitsSetFrom(VT.getScalarSizeInBits(),
N1.getScalarValueSizeInBits());
if (MaskedValueIsZero(OpOp, HiBits)) {
diff --git a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
index 754d2042105e57d..c47ddae072b4fe8 100644
--- a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+++ b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
@@ -2645,7 +2645,8 @@ bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
for (;;) {
// Look through nodes that don't alter the bits of the incoming value.
unsigned Op = Arg.getOpcode();
- if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) {
+ if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST ||
+ Op == ISD::AssertZext) {
Arg = Arg.getOperand(0);
continue;
}
diff --git a/llvm/test/CodeGen/AArch64/setcc_knownbits.ll b/llvm/test/CodeGen/AArch64/setcc_knownbits.ll
index aa62a7aa176c81d..af5c1586a4c6712 100644
--- a/llvm/test/CodeGen/AArch64/setcc_knownbits.ll
+++ b/llvm/test/CodeGen/AArch64/setcc_knownbits.ll
@@ -4,8 +4,6 @@
define i1 @load_bv_v4i8(i1 zeroext %a) {
; CHECK-LABEL: load_bv_v4i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp w0, #0
-; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%b = zext i1 %a to i32
%c = icmp eq i32 %b, 1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll b/llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll
index 1eccaaa26154f7b..f773de3b518c6d4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll
@@ -62,9 +62,9 @@ define <vscale x 1 x double> @fma_reassociate(<vscale x 1 x double> %a, <vscale
; CHECK-LABEL: fma_reassociate:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vfmadd.vv v9, v8, v12, v0.t
-; CHECK-NEXT: vfmadd.vv v11, v10, v9, v0.t
-; CHECK-NEXT: vmv.v.v v8, v11
+; CHECK-NEXT: vfmadd.vv v11, v10, v12, v0.t
+; CHECK-NEXT: vfmadd.vv v9, v8, v11, v0.t
+; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
%1 = call fast <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, <vscale x 1 x i1> %m, i32 %vl)
%2 = call fast <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %c, <vscale x 1 x double> %d, <vscale x 1 x i1> %m, i32 %vl)