[llvm] [RISCV] Improve constant materialization by using a sequence that end… (PR #66943)

[Craig Topper via llvm-commits]

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@@ -206,10 +206,25 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
   assert(ActiveFeatures[RISCV::Feature64Bit] &&
          "Expected RV32 to only need 2 instructions");
 
+  // If the lower 13 bits are something like 0x17ff, try to turn it into 0x1800
+  // and use a final addi to correct it back to 0x17ff. This will create a
+  // sequence ending in 2 addis.
+  if ((Val & 0xfff) != 0 && (Val & 0x1800) == 0x1000) {
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topperc wrote:

Based on the example cases I had, it looked like what I wanted to do was make bit 12 and 13 to both be set so that the lower bits were at least the start of a simm12. Once we have 0x800 in the lower 12 bits, the first thing generateInstSeqImpl is going to do is try to clear the low 12 bits by adding 0x800. (or subtract 0xfffffffffffff800) to make an ADDI. If bit 13 is set this will propagate the carry from bit 12 to bit 14. If bit 13 is 0, the add would set bit 13 and stop.

I guess doesn't hurt anything to try it, I was just trying to limit compile time a little.

https://github.com/llvm/llvm-project/pull/66943