[llvm] [RISCV] Fix bad isel predicate handling for Ztso. (PR #66739)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 18 22:58:45 PDT 2023
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/66739
>From e88653a3824f407208c71ca8eb14978b774cee30 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 18 Sep 2023 22:42:11 -0700
Subject: [PATCH 1/2] [RISCV] Fix bad isel predicate handling for Ztso.
The predicates inside the AMOPat class were being overridden by
the Predicates = [HasStdExtA] at the instantiation.
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 4 +-
llvm/test/CodeGen/RISCV/atomic-rmw.ll | 3674 +++++++++++++++-------
3 files changed, 2504 insertions(+), 1176 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 6381263b37613b3..5231f3c3cf3df2d 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -549,7 +549,7 @@ def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
def FeatureStdExtZtso
: SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
"'Ztso' (Memory Model - Total Store Order)">;
-def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZTso()">,
+def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
AssemblerPredicate<(all_of FeatureStdExtZtso),
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
index d7314866789ce47..5d4fb31d967b931 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
@@ -156,8 +156,6 @@ let Predicates = [HasStdExtA, HasStdExtZtso] in {
}
}
-let Predicates = [HasStdExtA] in {
-
defm : AMOPat<"atomic_swap_32", "AMOSWAP_W">;
defm : AMOPat<"atomic_load_add_32", "AMOADD_W">;
defm : AMOPat<"atomic_load_and_32", "AMOAND_W">;
@@ -168,6 +166,8 @@ defm : AMOPat<"atomic_load_min_32", "AMOMIN_W">;
defm : AMOPat<"atomic_load_umax_32", "AMOMAXU_W">;
defm : AMOPat<"atomic_load_umin_32", "AMOMINU_W">;
+let Predicates = [HasStdExtA] in {
+
/// Pseudo AMOs
class PseudoAMO : Pseudo<(outs GPR:$res, GPR:$scratch),
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
index c47d4484d8c0d80..53702403879c758 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -515,16 +515,27 @@ define i8 @atomicrmw_xchg_0_i8_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_0_i8_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: not a2, a2
-; RV32IA-NEXT: amoand.w.aq a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: not a2, a2
+; RV32IA-WMO-NEXT: amoand.w.aq a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a2, 255
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: not a2, a2
+; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_0_i8_acquire:
; RV64I: # %bb.0:
@@ -537,16 +548,27 @@ define i8 @atomicrmw_xchg_0_i8_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_0_i8_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: not a2, a2
-; RV64IA-NEXT: amoand.w.aq a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.aq a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 acquire
ret i8 %1
}
@@ -563,16 +585,27 @@ define i8 @atomicrmw_xchg_0_i8_release(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_0_i8_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: not a2, a2
-; RV32IA-NEXT: amoand.w.rl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i8_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: not a2, a2
+; RV32IA-WMO-NEXT: amoand.w.rl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i8_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a2, 255
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: not a2, a2
+; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_0_i8_release:
; RV64I: # %bb.0:
@@ -585,16 +618,27 @@ define i8 @atomicrmw_xchg_0_i8_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_0_i8_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: not a2, a2
-; RV64IA-NEXT: amoand.w.rl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.rl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 release
ret i8 %1
}
@@ -611,16 +655,27 @@ define i8 @atomicrmw_xchg_0_i8_acq_rel(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_0_i8_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: not a2, a2
-; RV32IA-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: not a2, a2
+; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a2, 255
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: not a2, a2
+; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_0_i8_acq_rel:
; RV64I: # %bb.0:
@@ -633,16 +688,27 @@ define i8 @atomicrmw_xchg_0_i8_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_0_i8_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: not a2, a2
-; RV64IA-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 acq_rel
ret i8 %1
}
@@ -659,16 +725,27 @@ define i8 @atomicrmw_xchg_0_i8_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_0_i8_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: not a2, a2
-; RV32IA-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: not a2, a2
+; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a2, 255
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: not a2, a2
+; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_0_i8_seq_cst:
; RV64I: # %bb.0:
@@ -681,16 +758,27 @@ define i8 @atomicrmw_xchg_0_i8_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_0_i8_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: not a2, a2
-; RV64IA-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 seq_cst
ret i8 %1
}
@@ -753,15 +841,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: amoor.w.aq a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: amoor.w.aq a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a2, 255
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
; RV64I: # %bb.0:
@@ -774,15 +872,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: amoor.w.aq a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.aq a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 acquire
ret i8 %1
}
@@ -799,15 +907,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_release(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_minus_1_i8_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: amoor.w.rl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: amoor.w.rl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a2, 255
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_minus_1_i8_release:
; RV64I: # %bb.0:
@@ -820,15 +938,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_minus_1_i8_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: amoor.w.rl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.rl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 release
ret i8 %1
}
@@ -845,15 +973,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_acq_rel(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a2, 255
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
; RV64I: # %bb.0:
@@ -866,15 +1004,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 acq_rel
ret i8 %1
}
@@ -891,15 +1039,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a2, 255
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
; RV64I: # %bb.0:
@@ -912,15 +1070,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 seq_cst
ret i8 %1
}
@@ -1868,43 +2036,71 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_and_i8_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a3, 255
-; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: not a3, a3
-; RV32IA-NEXT: andi a1, a1, 255
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: or a1, a3, a1
-; RV32IA-NEXT: amoand.w.aq a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_and_i8_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a3, 255
+; RV32IA-WMO-NEXT: sll a3, a3, a0
+; RV32IA-WMO-NEXT: not a3, a3
+; RV32IA-WMO-NEXT: andi a1, a1, 255
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: or a1, a3, a1
+; RV32IA-WMO-NEXT: amoand.w.aq a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
;
-; RV64I-LABEL: atomicrmw_and_i8_acquire:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV32IA-TSO-LABEL: atomicrmw_and_i8_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a3, 255
+; RV32IA-TSO-NEXT: sll a3, a3, a0
+; RV32IA-TSO-NEXT: not a3, a3
+; RV32IA-TSO-NEXT: andi a1, a1, 255
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: or a1, a3, a1
+; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
+;
+; RV64I-LABEL: atomicrmw_and_i8_acquire:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: li a2, 2
; RV64I-NEXT: call __atomic_fetch_and_1 at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i8_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: not a3, a3
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: or a1, a3, a1
-; RV64IA-NEXT: amoand.w.aq a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: not a3, a3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a3, a1
+; RV64IA-WMO-NEXT: amoand.w.aq a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: not a3, a3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a3, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i8 %b acquire
ret i8 %1
}
@@ -1920,19 +2116,33 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_and_i8_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a3, 255
-; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: not a3, a3
-; RV32IA-NEXT: andi a1, a1, 255
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: or a1, a3, a1
-; RV32IA-NEXT: amoand.w.rl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_and_i8_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a3, 255
+; RV32IA-WMO-NEXT: sll a3, a3, a0
+; RV32IA-WMO-NEXT: not a3, a3
+; RV32IA-WMO-NEXT: andi a1, a1, 255
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: or a1, a3, a1
+; RV32IA-WMO-NEXT: amoand.w.rl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_and_i8_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a3, 255
+; RV32IA-TSO-NEXT: sll a3, a3, a0
+; RV32IA-TSO-NEXT: not a3, a3
+; RV32IA-TSO-NEXT: andi a1, a1, 255
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: or a1, a3, a1
+; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_and_i8_release:
; RV64I: # %bb.0:
@@ -1944,19 +2154,33 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i8_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: not a3, a3
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: or a1, a3, a1
-; RV64IA-NEXT: amoand.w.rl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: not a3, a3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a3, a1
+; RV64IA-WMO-NEXT: amoand.w.rl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: not a3, a3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a3, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i8 %b release
ret i8 %1
}
@@ -1972,19 +2196,33 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_and_i8_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a3, 255
-; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: not a3, a3
-; RV32IA-NEXT: andi a1, a1, 255
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: or a1, a3, a1
-; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_and_i8_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a3, 255
+; RV32IA-WMO-NEXT: sll a3, a3, a0
+; RV32IA-WMO-NEXT: not a3, a3
+; RV32IA-WMO-NEXT: andi a1, a1, 255
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: or a1, a3, a1
+; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_and_i8_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a3, 255
+; RV32IA-TSO-NEXT: sll a3, a3, a0
+; RV32IA-TSO-NEXT: not a3, a3
+; RV32IA-TSO-NEXT: andi a1, a1, 255
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: or a1, a3, a1
+; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_and_i8_acq_rel:
; RV64I: # %bb.0:
@@ -1996,19 +2234,33 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i8_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: not a3, a3
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: or a1, a3, a1
-; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: not a3, a3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a3, a1
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: not a3, a3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a3, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -2024,19 +2276,33 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_and_i8_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a3, 255
-; RV32IA-NEXT: sll a3, a3, a0
-; RV32IA-NEXT: not a3, a3
-; RV32IA-NEXT: andi a1, a1, 255
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: or a1, a3, a1
-; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_and_i8_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a3, 255
+; RV32IA-WMO-NEXT: sll a3, a3, a0
+; RV32IA-WMO-NEXT: not a3, a3
+; RV32IA-WMO-NEXT: andi a1, a1, 255
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: or a1, a3, a1
+; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_and_i8_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a3, 255
+; RV32IA-TSO-NEXT: sll a3, a3, a0
+; RV32IA-TSO-NEXT: not a3, a3
+; RV32IA-TSO-NEXT: andi a1, a1, 255
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: or a1, a3, a1
+; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_and_i8_seq_cst:
; RV64I: # %bb.0:
@@ -2048,19 +2314,33 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i8_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: not a3, a3
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: or a1, a3, a1
-; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i8_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: not a3, a3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a3, a1
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i8_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: not a3, a3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a3, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -2576,15 +2856,25 @@ define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_or_i8_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: andi a1, a1, 255
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoor.w.aq a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_or_i8_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: andi a1, a1, 255
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoor.w.aq a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_or_i8_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: andi a1, a1, 255
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_or_i8_acquire:
; RV64I: # %bb.0:
@@ -2596,15 +2886,25 @@ define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i8_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoor.w.aq a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.aq a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i8 %b acquire
ret i8 %1
}
@@ -2620,15 +2920,25 @@ define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_or_i8_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: andi a1, a1, 255
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoor.w.rl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_or_i8_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: andi a1, a1, 255
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoor.w.rl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_or_i8_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: andi a1, a1, 255
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_or_i8_release:
; RV64I: # %bb.0:
@@ -2640,15 +2950,25 @@ define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i8_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoor.w.rl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.rl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i8 %b release
ret i8 %1
}
@@ -2664,15 +2984,25 @@ define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_or_i8_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: andi a1, a1, 255
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_or_i8_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: andi a1, a1, 255
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_or_i8_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: andi a1, a1, 255
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_or_i8_acq_rel:
; RV64I: # %bb.0:
@@ -2684,15 +3014,25 @@ define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i8_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -2708,15 +3048,25 @@ define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_or_i8_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: andi a1, a1, 255
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_or_i8_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: andi a1, a1, 255
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_or_i8_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: andi a1, a1, 255
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_or_i8_seq_cst:
; RV64I: # %bb.0:
@@ -2728,15 +3078,25 @@ define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i8_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i8_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i8_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -2796,15 +3156,25 @@ define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xor_i8_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: andi a1, a1, 255
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xor_i8_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: andi a1, a1, 255
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoxor.w.aq a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xor_i8_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: andi a1, a1, 255
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xor_i8_acquire:
; RV64I: # %bb.0:
@@ -2816,15 +3186,25 @@ define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i8_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.aq a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i8 %b acquire
ret i8 %1
}
@@ -2840,15 +3220,25 @@ define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xor_i8_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: andi a1, a1, 255
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xor_i8_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: andi a1, a1, 255
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoxor.w.rl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xor_i8_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: andi a1, a1, 255
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xor_i8_release:
; RV64I: # %bb.0:
@@ -2860,15 +3250,25 @@ define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i8_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.rl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i8 %b release
ret i8 %1
}
@@ -2884,15 +3284,25 @@ define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xor_i8_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: andi a1, a1, 255
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: andi a1, a1, 255
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: andi a1, a1, 255
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xor_i8_acq_rel:
; RV64I: # %bb.0:
@@ -2904,15 +3314,25 @@ define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i8_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -2928,15 +3348,25 @@ define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xor_i8_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: andi a1, a1, 255
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: andi a1, a1, 255
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: andi a1, a1, 255
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xor_i8_seq_cst:
; RV64I: # %bb.0:
@@ -2948,15 +3378,25 @@ define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i8_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -6898,17 +7338,29 @@ define i16 @atomicrmw_xchg_0_i16_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_0_i16_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: lui a2, 16
-; RV32IA-NEXT: addi a2, a2, -1
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: not a2, a2
-; RV32IA-NEXT: amoand.w.aq a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i16_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: lui a2, 16
+; RV32IA-WMO-NEXT: addi a2, a2, -1
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: not a2, a2
+; RV32IA-WMO-NEXT: amoand.w.aq a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i16_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: lui a2, 16
+; RV32IA-TSO-NEXT: addi a2, a2, -1
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: not a2, a2
+; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_0_i16_acquire:
; RV64I: # %bb.0:
@@ -6921,17 +7373,29 @@ define i16 @atomicrmw_xchg_0_i16_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_0_i16_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a2, 16
-; RV64IA-NEXT: addiw a2, a2, -1
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: not a2, a2
-; RV64IA-NEXT: amoand.w.aq a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addiw a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.aq a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addiw a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 0 acquire
ret i16 %1
}
@@ -6948,17 +7412,29 @@ define i16 @atomicrmw_xchg_0_i16_release(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_0_i16_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: lui a2, 16
-; RV32IA-NEXT: addi a2, a2, -1
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: not a2, a2
-; RV32IA-NEXT: amoand.w.rl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i16_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: lui a2, 16
+; RV32IA-WMO-NEXT: addi a2, a2, -1
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: not a2, a2
+; RV32IA-WMO-NEXT: amoand.w.rl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i16_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: lui a2, 16
+; RV32IA-TSO-NEXT: addi a2, a2, -1
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: not a2, a2
+; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_0_i16_release:
; RV64I: # %bb.0:
@@ -6971,17 +7447,29 @@ define i16 @atomicrmw_xchg_0_i16_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_0_i16_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a2, 16
-; RV64IA-NEXT: addiw a2, a2, -1
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: not a2, a2
-; RV64IA-NEXT: amoand.w.rl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addiw a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.rl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addiw a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 0 release
ret i16 %1
}
@@ -6998,17 +7486,29 @@ define i16 @atomicrmw_xchg_0_i16_acq_rel(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_0_i16_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: lui a2, 16
-; RV32IA-NEXT: addi a2, a2, -1
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: not a2, a2
-; RV32IA-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i16_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: lui a2, 16
+; RV32IA-WMO-NEXT: addi a2, a2, -1
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: not a2, a2
+; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i16_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: lui a2, 16
+; RV32IA-TSO-NEXT: addi a2, a2, -1
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: not a2, a2
+; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_0_i16_acq_rel:
; RV64I: # %bb.0:
@@ -7021,17 +7521,29 @@ define i16 @atomicrmw_xchg_0_i16_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_0_i16_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a2, 16
-; RV64IA-NEXT: addiw a2, a2, -1
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: not a2, a2
-; RV64IA-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addiw a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addiw a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 0 acq_rel
ret i16 %1
}
@@ -7048,17 +7560,29 @@ define i16 @atomicrmw_xchg_0_i16_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_0_i16_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: lui a2, 16
-; RV32IA-NEXT: addi a2, a2, -1
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: not a2, a2
-; RV32IA-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i16_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: lui a2, 16
+; RV32IA-WMO-NEXT: addi a2, a2, -1
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: not a2, a2
+; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i16_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: lui a2, 16
+; RV32IA-TSO-NEXT: addi a2, a2, -1
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: not a2, a2
+; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_0_i16_seq_cst:
; RV64I: # %bb.0:
@@ -7070,18 +7594,30 @@ define i16 @atomicrmw_xchg_0_i16_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
-;
-; RV64IA-LABEL: atomicrmw_xchg_0_i16_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a2, 16
-; RV64IA-NEXT: addiw a2, a2, -1
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: not a2, a2
-; RV64IA-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+;
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i16_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addiw a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i16_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addiw a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 0 seq_cst
ret i16 %1
}
@@ -7149,16 +7685,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: lui a2, 16
-; RV32IA-NEXT: addi a2, a2, -1
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: amoor.w.aq a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: lui a2, 16
+; RV32IA-WMO-NEXT: addi a2, a2, -1
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: amoor.w.aq a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: lui a2, 16
+; RV32IA-TSO-NEXT: addi a2, a2, -1
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
; RV64I: # %bb.0:
@@ -7172,16 +7719,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a2, 16
-; RV64IA-NEXT: addiw a2, a2, -1
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: amoor.w.aq a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addiw a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.aq a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addiw a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 -1 acquire
ret i16 %1
}
@@ -7199,16 +7757,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_release(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_minus_1_i16_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: lui a2, 16
-; RV32IA-NEXT: addi a2, a2, -1
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: amoor.w.rl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: lui a2, 16
+; RV32IA-WMO-NEXT: addi a2, a2, -1
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: amoor.w.rl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: lui a2, 16
+; RV32IA-TSO-NEXT: addi a2, a2, -1
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_minus_1_i16_release:
; RV64I: # %bb.0:
@@ -7222,16 +7791,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_minus_1_i16_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a2, 16
-; RV64IA-NEXT: addiw a2, a2, -1
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: amoor.w.rl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addiw a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.rl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addiw a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 -1 release
ret i16 %1
}
@@ -7249,16 +7829,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_acq_rel(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: lui a2, 16
-; RV32IA-NEXT: addi a2, a2, -1
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: lui a2, 16
+; RV32IA-WMO-NEXT: addi a2, a2, -1
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: lui a2, 16
+; RV32IA-TSO-NEXT: addi a2, a2, -1
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
; RV64I: # %bb.0:
@@ -7272,16 +7863,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a2, 16
-; RV64IA-NEXT: addiw a2, a2, -1
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addiw a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addiw a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 -1 acq_rel
ret i16 %1
}
@@ -7299,16 +7901,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: lui a2, 16
-; RV32IA-NEXT: addi a2, a2, -1
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: lui a2, 16
+; RV32IA-WMO-NEXT: addi a2, a2, -1
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: lui a2, 16
+; RV32IA-TSO-NEXT: addi a2, a2, -1
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
; RV64I: # %bb.0:
@@ -7322,16 +7935,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a2, 16
-; RV64IA-NEXT: addiw a2, a2, -1
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addiw a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addiw a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 -1 seq_cst
ret i16 %1
}
@@ -8313,20 +8937,35 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_and_i16_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: lui a3, 16
-; RV32IA-NEXT: addi a3, a3, -1
-; RV32IA-NEXT: sll a4, a3, a0
-; RV32IA-NEXT: not a4, a4
-; RV32IA-NEXT: and a1, a1, a3
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: or a1, a4, a1
-; RV32IA-NEXT: amoand.w.aq a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_and_i16_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: lui a3, 16
+; RV32IA-WMO-NEXT: addi a3, a3, -1
+; RV32IA-WMO-NEXT: sll a4, a3, a0
+; RV32IA-WMO-NEXT: not a4, a4
+; RV32IA-WMO-NEXT: and a1, a1, a3
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: or a1, a4, a1
+; RV32IA-WMO-NEXT: amoand.w.aq a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_and_i16_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: lui a3, 16
+; RV32IA-TSO-NEXT: addi a3, a3, -1
+; RV32IA-TSO-NEXT: sll a4, a3, a0
+; RV32IA-TSO-NEXT: not a4, a4
+; RV32IA-TSO-NEXT: and a1, a1, a3
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: or a1, a4, a1
+; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_and_i16_acquire:
; RV64I: # %bb.0:
@@ -8338,20 +8977,35 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i16_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: not a4, a4
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: or a1, a4, a1
-; RV64IA-NEXT: amoand.w.aq a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addiw a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: not a4, a4
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a4, a1
+; RV64IA-WMO-NEXT: amoand.w.aq a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addiw a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: not a4, a4
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a4, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i16 %b acquire
ret i16 %1
}
@@ -8367,20 +9021,35 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_and_i16_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: lui a3, 16
-; RV32IA-NEXT: addi a3, a3, -1
-; RV32IA-NEXT: sll a4, a3, a0
-; RV32IA-NEXT: not a4, a4
-; RV32IA-NEXT: and a1, a1, a3
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: or a1, a4, a1
-; RV32IA-NEXT: amoand.w.rl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_and_i16_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: lui a3, 16
+; RV32IA-WMO-NEXT: addi a3, a3, -1
+; RV32IA-WMO-NEXT: sll a4, a3, a0
+; RV32IA-WMO-NEXT: not a4, a4
+; RV32IA-WMO-NEXT: and a1, a1, a3
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: or a1, a4, a1
+; RV32IA-WMO-NEXT: amoand.w.rl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_and_i16_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: lui a3, 16
+; RV32IA-TSO-NEXT: addi a3, a3, -1
+; RV32IA-TSO-NEXT: sll a4, a3, a0
+; RV32IA-TSO-NEXT: not a4, a4
+; RV32IA-TSO-NEXT: and a1, a1, a3
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: or a1, a4, a1
+; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_and_i16_release:
; RV64I: # %bb.0:
@@ -8392,20 +9061,35 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i16_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: not a4, a4
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: or a1, a4, a1
-; RV64IA-NEXT: amoand.w.rl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addiw a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: not a4, a4
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a4, a1
+; RV64IA-WMO-NEXT: amoand.w.rl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addiw a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: not a4, a4
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a4, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i16 %b release
ret i16 %1
}
@@ -8421,20 +9105,35 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_and_i16_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: lui a3, 16
-; RV32IA-NEXT: addi a3, a3, -1
-; RV32IA-NEXT: sll a4, a3, a0
-; RV32IA-NEXT: not a4, a4
-; RV32IA-NEXT: and a1, a1, a3
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: or a1, a4, a1
-; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_and_i16_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: lui a3, 16
+; RV32IA-WMO-NEXT: addi a3, a3, -1
+; RV32IA-WMO-NEXT: sll a4, a3, a0
+; RV32IA-WMO-NEXT: not a4, a4
+; RV32IA-WMO-NEXT: and a1, a1, a3
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: or a1, a4, a1
+; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_and_i16_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: lui a3, 16
+; RV32IA-TSO-NEXT: addi a3, a3, -1
+; RV32IA-TSO-NEXT: sll a4, a3, a0
+; RV32IA-TSO-NEXT: not a4, a4
+; RV32IA-TSO-NEXT: and a1, a1, a3
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: or a1, a4, a1
+; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_and_i16_acq_rel:
; RV64I: # %bb.0:
@@ -8446,20 +9145,35 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i16_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: not a4, a4
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: or a1, a4, a1
-; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addiw a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: not a4, a4
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a4, a1
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addiw a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: not a4, a4
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a4, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -8475,20 +9189,35 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_and_i16_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: lui a3, 16
-; RV32IA-NEXT: addi a3, a3, -1
-; RV32IA-NEXT: sll a4, a3, a0
-; RV32IA-NEXT: not a4, a4
-; RV32IA-NEXT: and a1, a1, a3
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: or a1, a4, a1
-; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_and_i16_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: lui a3, 16
+; RV32IA-WMO-NEXT: addi a3, a3, -1
+; RV32IA-WMO-NEXT: sll a4, a3, a0
+; RV32IA-WMO-NEXT: not a4, a4
+; RV32IA-WMO-NEXT: and a1, a1, a3
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: or a1, a4, a1
+; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_and_i16_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: lui a3, 16
+; RV32IA-TSO-NEXT: addi a3, a3, -1
+; RV32IA-TSO-NEXT: sll a4, a3, a0
+; RV32IA-TSO-NEXT: not a4, a4
+; RV32IA-TSO-NEXT: and a1, a1, a3
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: or a1, a4, a1
+; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_and_i16_seq_cst:
; RV64I: # %bb.0:
@@ -8500,20 +9229,35 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i16_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: not a4, a4
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: or a1, a4, a1
-; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i16_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addiw a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: not a4, a4
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a4, a1
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i16_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addiw a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: not a4, a4
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a4, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -9047,16 +9791,27 @@ define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_or_i16_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: slli a1, a1, 16
-; RV32IA-NEXT: srli a1, a1, 16
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoor.w.aq a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_or_i16_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: slli a1, a1, 16
+; RV32IA-WMO-NEXT: srli a1, a1, 16
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoor.w.aq a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_or_i16_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: slli a1, a1, 16
+; RV32IA-TSO-NEXT: srli a1, a1, 16
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_or_i16_acquire:
; RV64I: # %bb.0:
@@ -9068,16 +9823,27 @@ define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i16_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: slli a1, a1, 48
-; RV64IA-NEXT: srli a1, a1, 48
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoor.w.aq a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.aq a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i16 %b acquire
ret i16 %1
}
@@ -9093,16 +9859,27 @@ define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_or_i16_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: slli a1, a1, 16
-; RV32IA-NEXT: srli a1, a1, 16
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoor.w.rl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_or_i16_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: slli a1, a1, 16
+; RV32IA-WMO-NEXT: srli a1, a1, 16
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoor.w.rl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_or_i16_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: slli a1, a1, 16
+; RV32IA-TSO-NEXT: srli a1, a1, 16
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_or_i16_release:
; RV64I: # %bb.0:
@@ -9114,16 +9891,27 @@ define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i16_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: slli a1, a1, 48
-; RV64IA-NEXT: srli a1, a1, 48
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoor.w.rl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.rl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i16 %b release
ret i16 %1
}
@@ -9139,16 +9927,27 @@ define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_or_i16_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: slli a1, a1, 16
-; RV32IA-NEXT: srli a1, a1, 16
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_or_i16_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: slli a1, a1, 16
+; RV32IA-WMO-NEXT: srli a1, a1, 16
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_or_i16_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: slli a1, a1, 16
+; RV32IA-TSO-NEXT: srli a1, a1, 16
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_or_i16_acq_rel:
; RV64I: # %bb.0:
@@ -9160,16 +9959,27 @@ define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i16_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: slli a1, a1, 48
-; RV64IA-NEXT: srli a1, a1, 48
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -9185,16 +9995,27 @@ define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_or_i16_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: slli a1, a1, 16
-; RV32IA-NEXT: srli a1, a1, 16
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_or_i16_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: slli a1, a1, 16
+; RV32IA-WMO-NEXT: srli a1, a1, 16
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_or_i16_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: slli a1, a1, 16
+; RV32IA-TSO-NEXT: srli a1, a1, 16
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_or_i16_seq_cst:
; RV64I: # %bb.0:
@@ -9206,16 +10027,27 @@ define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i16_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: slli a1, a1, 48
-; RV64IA-NEXT: srli a1, a1, 48
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i16_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i16_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -9277,16 +10109,27 @@ define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xor_i16_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: slli a1, a1, 16
-; RV32IA-NEXT: srli a1, a1, 16
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xor_i16_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: slli a1, a1, 16
+; RV32IA-WMO-NEXT: srli a1, a1, 16
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoxor.w.aq a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xor_i16_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: slli a1, a1, 16
+; RV32IA-TSO-NEXT: srli a1, a1, 16
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xor_i16_acquire:
; RV64I: # %bb.0:
@@ -9298,16 +10141,27 @@ define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i16_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: slli a1, a1, 48
-; RV64IA-NEXT: srli a1, a1, 48
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.aq a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i16 %b acquire
ret i16 %1
}
@@ -9323,16 +10177,27 @@ define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xor_i16_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: slli a1, a1, 16
-; RV32IA-NEXT: srli a1, a1, 16
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xor_i16_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: slli a1, a1, 16
+; RV32IA-WMO-NEXT: srli a1, a1, 16
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoxor.w.rl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xor_i16_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: slli a1, a1, 16
+; RV32IA-TSO-NEXT: srli a1, a1, 16
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xor_i16_release:
; RV64I: # %bb.0:
@@ -9344,16 +10209,27 @@ define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i16_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: slli a1, a1, 48
-; RV64IA-NEXT: srli a1, a1, 48
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.rl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i16 %b release
ret i16 %1
}
@@ -9369,16 +10245,27 @@ define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xor_i16_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: slli a1, a1, 16
-; RV32IA-NEXT: srli a1, a1, 16
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: slli a1, a1, 16
+; RV32IA-WMO-NEXT: srli a1, a1, 16
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: slli a1, a1, 16
+; RV32IA-TSO-NEXT: srli a1, a1, 16
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xor_i16_acq_rel:
; RV64I: # %bb.0:
@@ -9390,16 +10277,27 @@ define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i16_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: slli a1, a1, 48
-; RV64IA-NEXT: srli a1, a1, 48
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -9415,16 +10313,27 @@ define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xor_i16_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a2, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: slli a1, a1, 16
-; RV32IA-NEXT: srli a1, a1, 16
-; RV32IA-NEXT: sll a1, a1, a0
-; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a2, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: slli a1, a1, 16
+; RV32IA-WMO-NEXT: srli a1, a1, 16
+; RV32IA-WMO-NEXT: sll a1, a1, a0
+; RV32IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a2, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: slli a1, a1, 16
+; RV32IA-TSO-NEXT: srli a1, a1, 16
+; RV32IA-TSO-NEXT: sll a1, a1, a0
+; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xor_i16_seq_cst:
; RV64I: # %bb.0:
@@ -9436,16 +10345,27 @@ define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i16_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: slli a1, a1, 48
-; RV64IA-NEXT: srli a1, a1, 48
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -13087,10 +14007,15 @@ define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_i32_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoswap.w.aq a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_i32_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoswap.w.aq a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_i32_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoswap.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_i32_acquire:
; RV64I: # %bb.0:
@@ -13102,10 +14027,15 @@ define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_i32_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoswap.w.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_i32_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoswap.w.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_i32_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoswap.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i32 %b acquire
ret i32 %1
}
@@ -13121,10 +14051,15 @@ define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_i32_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoswap.w.rl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_i32_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoswap.w.rl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_i32_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoswap.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_i32_release:
; RV64I: # %bb.0:
@@ -13136,10 +14071,15 @@ define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_i32_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoswap.w.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_i32_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoswap.w.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_i32_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoswap.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i32 %b release
ret i32 %1
}
@@ -13155,10 +14095,15 @@ define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_i32_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoswap.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_i32_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoswap.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_i32_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoswap.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_i32_acq_rel:
; RV64I: # %bb.0:
@@ -13170,10 +14115,15 @@ define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_i32_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoswap.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_i32_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoswap.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_i32_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoswap.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i32 %b acq_rel
ret i32 %1
}
@@ -13189,10 +14139,15 @@ define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_i32_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoswap.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_i32_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoswap.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_i32_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoswap.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_i32_seq_cst:
; RV64I: # %bb.0:
@@ -13204,10 +14159,15 @@ define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_i32_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoswap.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_i32_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoswap.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_i32_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoswap.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i32 %b seq_cst
ret i32 %1
}
@@ -13257,10 +14217,15 @@ define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_add_i32_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoadd.w.aq a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_add_i32_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoadd.w.aq a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_add_i32_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_add_i32_acquire:
; RV64I: # %bb.0:
@@ -13272,10 +14237,15 @@ define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_add_i32_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoadd.w.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_add_i32_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoadd.w.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_add_i32_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw add ptr %a, i32 %b acquire
ret i32 %1
}
@@ -13291,10 +14261,15 @@ define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_add_i32_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoadd.w.rl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_add_i32_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoadd.w.rl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_add_i32_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_add_i32_release:
; RV64I: # %bb.0:
@@ -13306,10 +14281,15 @@ define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_add_i32_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoadd.w.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_add_i32_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoadd.w.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_add_i32_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw add ptr %a, i32 %b release
ret i32 %1
}
@@ -13325,10 +14305,15 @@ define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_add_i32_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_add_i32_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_add_i32_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_add_i32_acq_rel:
; RV64I: # %bb.0:
@@ -13340,10 +14325,15 @@ define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_add_i32_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_add_i32_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_add_i32_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw add ptr %a, i32 %b acq_rel
ret i32 %1
}
@@ -13359,10 +14349,15 @@ define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_add_i32_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_add_i32_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_add_i32_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_add_i32_seq_cst:
; RV64I: # %bb.0:
@@ -13374,10 +14369,15 @@ define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_add_i32_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_add_i32_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_add_i32_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw add ptr %a, i32 %b seq_cst
ret i32 %1
}
@@ -13429,11 +14429,17 @@ define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_sub_i32_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: neg a1, a1
-; RV32IA-NEXT: amoadd.w.aq a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_sub_i32_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: neg a1, a1
+; RV32IA-WMO-NEXT: amoadd.w.aq a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_sub_i32_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: neg a1, a1
+; RV32IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_sub_i32_acquire:
; RV64I: # %bb.0:
@@ -13445,11 +14451,17 @@ define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_sub_i32_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: neg a1, a1
-; RV64IA-NEXT: amoadd.w.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_sub_i32_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: neg a1, a1
+; RV64IA-WMO-NEXT: amoadd.w.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_sub_i32_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: neg a1, a1
+; RV64IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw sub ptr %a, i32 %b acquire
ret i32 %1
}
@@ -13465,11 +14477,17 @@ define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_sub_i32_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: neg a1, a1
-; RV32IA-NEXT: amoadd.w.rl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_sub_i32_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: neg a1, a1
+; RV32IA-WMO-NEXT: amoadd.w.rl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_sub_i32_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: neg a1, a1
+; RV32IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_sub_i32_release:
; RV64I: # %bb.0:
@@ -13481,11 +14499,17 @@ define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_sub_i32_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: neg a1, a1
-; RV64IA-NEXT: amoadd.w.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_sub_i32_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: neg a1, a1
+; RV64IA-WMO-NEXT: amoadd.w.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_sub_i32_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: neg a1, a1
+; RV64IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw sub ptr %a, i32 %b release
ret i32 %1
}
@@ -13501,11 +14525,17 @@ define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_sub_i32_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: neg a1, a1
-; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_sub_i32_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: neg a1, a1
+; RV32IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_sub_i32_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: neg a1, a1
+; RV32IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_sub_i32_acq_rel:
; RV64I: # %bb.0:
@@ -13517,11 +14547,17 @@ define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_sub_i32_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: neg a1, a1
-; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_sub_i32_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: neg a1, a1
+; RV64IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_sub_i32_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: neg a1, a1
+; RV64IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw sub ptr %a, i32 %b acq_rel
ret i32 %1
}
@@ -13537,11 +14573,17 @@ define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_sub_i32_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: neg a1, a1
-; RV32IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_sub_i32_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: neg a1, a1
+; RV32IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_sub_i32_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: neg a1, a1
+; RV32IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_sub_i32_seq_cst:
; RV64I: # %bb.0:
@@ -13553,11 +14595,17 @@ define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_sub_i32_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: neg a1, a1
-; RV64IA-NEXT: amoadd.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_sub_i32_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: neg a1, a1
+; RV64IA-WMO-NEXT: amoadd.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_sub_i32_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: neg a1, a1
+; RV64IA-TSO-NEXT: amoadd.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw sub ptr %a, i32 %b seq_cst
ret i32 %1
}
@@ -13607,10 +14655,15 @@ define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_and_i32_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoand.w.aq a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_and_i32_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoand.w.aq a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_and_i32_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoand.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_and_i32_acquire:
; RV64I: # %bb.0:
@@ -13622,10 +14675,15 @@ define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i32_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoand.w.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i32_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoand.w.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i32_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoand.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i32 %b acquire
ret i32 %1
}
@@ -13641,10 +14699,15 @@ define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_and_i32_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoand.w.rl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_and_i32_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoand.w.rl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_and_i32_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoand.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_and_i32_release:
; RV64I: # %bb.0:
@@ -13656,10 +14719,15 @@ define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i32_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoand.w.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i32_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoand.w.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i32_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoand.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i32 %b release
ret i32 %1
}
@@ -13675,10 +14743,15 @@ define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_and_i32_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_and_i32_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoand.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_and_i32_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoand.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_and_i32_acq_rel:
; RV64I: # %bb.0:
@@ -13690,10 +14763,15 @@ define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i32_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i32_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoand.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i32_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoand.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i32 %b acq_rel
ret i32 %1
}
@@ -13709,10 +14787,15 @@ define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_and_i32_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_and_i32_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoand.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_and_i32_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoand.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_and_i32_seq_cst:
; RV64I: # %bb.0:
@@ -13724,10 +14807,15 @@ define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i32_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i32_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoand.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i32_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoand.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i32 %b seq_cst
ret i32 %1
}
@@ -14089,10 +15177,15 @@ define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_or_i32_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoor.w.aq a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_or_i32_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoor.w.aq a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_or_i32_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoor.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_or_i32_acquire:
; RV64I: # %bb.0:
@@ -14104,10 +15197,15 @@ define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i32_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoor.w.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i32_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoor.w.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i32_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoor.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i32 %b acquire
ret i32 %1
}
@@ -14123,10 +15221,15 @@ define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_or_i32_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoor.w.rl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_or_i32_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoor.w.rl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_or_i32_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoor.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_or_i32_release:
; RV64I: # %bb.0:
@@ -14138,10 +15241,15 @@ define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i32_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoor.w.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i32_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoor.w.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i32_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoor.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i32 %b release
ret i32 %1
}
@@ -14157,10 +15265,15 @@ define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_or_i32_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_or_i32_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoor.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_or_i32_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoor.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_or_i32_acq_rel:
; RV64I: # %bb.0:
@@ -14172,10 +15285,15 @@ define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i32_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i32_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoor.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i32_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoor.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i32 %b acq_rel
ret i32 %1
}
@@ -14191,10 +15309,15 @@ define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_or_i32_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_or_i32_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoor.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_or_i32_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoor.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_or_i32_seq_cst:
; RV64I: # %bb.0:
@@ -14206,10 +15329,15 @@ define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i32_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i32_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoor.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i32_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoor.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i32 %b seq_cst
ret i32 %1
}
@@ -14259,10 +15387,15 @@ define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xor_i32_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoxor.w.aq a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xor_i32_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoxor.w.aq a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xor_i32_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoxor.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xor_i32_acquire:
; RV64I: # %bb.0:
@@ -14274,10 +15407,15 @@ define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i32_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoxor.w.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i32_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoxor.w.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i32_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoxor.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i32 %b acquire
ret i32 %1
}
@@ -14293,10 +15431,15 @@ define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xor_i32_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoxor.w.rl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xor_i32_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoxor.w.rl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xor_i32_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoxor.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xor_i32_release:
; RV64I: # %bb.0:
@@ -14308,10 +15451,15 @@ define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i32_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoxor.w.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i32_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoxor.w.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i32_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoxor.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i32 %b release
ret i32 %1
}
@@ -14327,10 +15475,15 @@ define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xor_i32_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xor_i32_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoxor.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xor_i32_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoxor.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xor_i32_acq_rel:
; RV64I: # %bb.0:
@@ -14342,10 +15495,15 @@ define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i32_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i32_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoxor.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i32_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoxor.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i32 %b acq_rel
ret i32 %1
}
@@ -14361,10 +15519,15 @@ define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xor_i32_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xor_i32_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amoxor.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xor_i32_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amoxor.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xor_i32_seq_cst:
; RV64I: # %bb.0:
@@ -14376,10 +15539,15 @@ define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i32_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i32_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoxor.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i32_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoxor.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i32 %b seq_cst
ret i32 %1
}
@@ -14510,10 +15678,15 @@ define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_max_i32_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amomax.w.aq a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_max_i32_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amomax.w.aq a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_max_i32_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amomax.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_max_i32_acquire:
; RV64I: # %bb.0:
@@ -14554,10 +15727,15 @@ define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_max_i32_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomax.w.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_max_i32_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomax.w.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_max_i32_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomax.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw max ptr %a, i32 %b acquire
ret i32 %1
}
@@ -14599,10 +15777,15 @@ define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_max_i32_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amomax.w.rl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_max_i32_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amomax.w.rl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_max_i32_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amomax.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_max_i32_release:
; RV64I: # %bb.0:
@@ -14643,10 +15826,15 @@ define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_max_i32_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomax.w.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_max_i32_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomax.w.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_max_i32_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomax.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw max ptr %a, i32 %b release
ret i32 %1
}
@@ -14688,10 +15876,15 @@ define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_max_i32_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amomax.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_max_i32_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amomax.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_max_i32_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amomax.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_max_i32_acq_rel:
; RV64I: # %bb.0:
@@ -14732,10 +15925,15 @@ define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_max_i32_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomax.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_max_i32_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomax.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_max_i32_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomax.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw max ptr %a, i32 %b acq_rel
ret i32 %1
}
@@ -14777,10 +15975,15 @@ define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_max_i32_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amomax.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_max_i32_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amomax.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_max_i32_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amomax.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_max_i32_seq_cst:
; RV64I: # %bb.0:
@@ -14821,10 +16024,15 @@ define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_max_i32_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomax.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_max_i32_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomax.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_max_i32_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomax.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw max ptr %a, i32 %b seq_cst
ret i32 %1
}
@@ -14955,10 +16163,15 @@ define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_min_i32_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amomin.w.aq a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_min_i32_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amomin.w.aq a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_min_i32_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amomin.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_min_i32_acquire:
; RV64I: # %bb.0:
@@ -14999,10 +16212,15 @@ define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_min_i32_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomin.w.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_min_i32_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomin.w.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_min_i32_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomin.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw min ptr %a, i32 %b acquire
ret i32 %1
}
@@ -15044,10 +16262,15 @@ define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_min_i32_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amomin.w.rl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_min_i32_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amomin.w.rl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_min_i32_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amomin.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_min_i32_release:
; RV64I: # %bb.0:
@@ -15088,10 +16311,15 @@ define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_min_i32_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomin.w.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_min_i32_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomin.w.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_min_i32_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomin.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw min ptr %a, i32 %b release
ret i32 %1
}
@@ -15133,10 +16361,15 @@ define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_min_i32_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amomin.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_min_i32_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amomin.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_min_i32_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amomin.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_min_i32_acq_rel:
; RV64I: # %bb.0:
@@ -15177,10 +16410,15 @@ define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_min_i32_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomin.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_min_i32_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomin.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_min_i32_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomin.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw min ptr %a, i32 %b acq_rel
ret i32 %1
}
@@ -15222,10 +16460,15 @@ define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_min_i32_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amomin.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_min_i32_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amomin.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_min_i32_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amomin.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_min_i32_seq_cst:
; RV64I: # %bb.0:
@@ -15266,10 +16509,15 @@ define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_min_i32_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomin.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_min_i32_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomin.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_min_i32_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomin.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw min ptr %a, i32 %b seq_cst
ret i32 %1
}
@@ -15400,10 +16648,15 @@ define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_umax_i32_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amomaxu.w.aq a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_umax_i32_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amomaxu.w.aq a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_umax_i32_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amomaxu.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_umax_i32_acquire:
; RV64I: # %bb.0:
@@ -15444,10 +16697,15 @@ define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umax_i32_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomaxu.w.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umax_i32_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomaxu.w.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umax_i32_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomaxu.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umax ptr %a, i32 %b acquire
ret i32 %1
}
@@ -15489,10 +16747,15 @@ define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_umax_i32_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amomaxu.w.rl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_umax_i32_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amomaxu.w.rl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_umax_i32_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amomaxu.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_umax_i32_release:
; RV64I: # %bb.0:
@@ -15533,10 +16796,15 @@ define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umax_i32_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomaxu.w.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umax_i32_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomaxu.w.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umax_i32_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomaxu.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umax ptr %a, i32 %b release
ret i32 %1
}
@@ -15578,10 +16846,15 @@ define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_umax_i32_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_umax_i32_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amomaxu.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_umax_i32_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amomaxu.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_umax_i32_acq_rel:
; RV64I: # %bb.0:
@@ -15622,10 +16895,15 @@ define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umax_i32_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umax_i32_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomaxu.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umax_i32_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomaxu.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umax ptr %a, i32 %b acq_rel
ret i32 %1
}
@@ -15667,10 +16945,15 @@ define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_umax_i32_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_umax_i32_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amomaxu.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_umax_i32_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amomaxu.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_umax_i32_seq_cst:
; RV64I: # %bb.0:
@@ -15711,10 +16994,15 @@ define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umax_i32_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umax_i32_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomaxu.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umax_i32_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomaxu.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umax ptr %a, i32 %b seq_cst
ret i32 %1
}
@@ -15845,10 +17133,15 @@ define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_umin_i32_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amominu.w.aq a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_umin_i32_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amominu.w.aq a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_umin_i32_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amominu.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_umin_i32_acquire:
; RV64I: # %bb.0:
@@ -15889,10 +17182,15 @@ define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umin_i32_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amominu.w.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umin_i32_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amominu.w.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umin_i32_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amominu.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umin ptr %a, i32 %b acquire
ret i32 %1
}
@@ -15934,10 +17232,15 @@ define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_umin_i32_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amominu.w.rl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_umin_i32_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amominu.w.rl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_umin_i32_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amominu.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_umin_i32_release:
; RV64I: # %bb.0:
@@ -15978,10 +17281,15 @@ define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umin_i32_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amominu.w.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umin_i32_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amominu.w.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umin_i32_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amominu.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umin ptr %a, i32 %b release
ret i32 %1
}
@@ -16023,10 +17331,15 @@ define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_umin_i32_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amominu.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_umin_i32_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amominu.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_umin_i32_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amominu.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_umin_i32_acq_rel:
; RV64I: # %bb.0:
@@ -16067,10 +17380,15 @@ define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umin_i32_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amominu.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umin_i32_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amominu.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umin_i32_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amominu.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umin ptr %a, i32 %b acq_rel
ret i32 %1
}
@@ -16112,10 +17430,15 @@ define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_umin_i32_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: amominu.w.aqrl a0, a1, (a0)
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_umin_i32_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: amominu.w.aqrl a0, a1, (a0)
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_umin_i32_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: amominu.w a0, a1, (a0)
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_umin_i32_seq_cst:
; RV64I: # %bb.0:
@@ -16156,10 +17479,15 @@ define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umin_i32_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amominu.w.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umin_i32_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amominu.w.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umin_i32_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amominu.w a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umin ptr %a, i32 %b seq_cst
ret i32 %1
}
>From ebc952841964e62787813a005b5441b55806cb5d Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 18 Sep 2023 22:58:26 -0700
Subject: [PATCH 2/2] Fix the same bug for RV64 patterns.
---
llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 27 +-
llvm/test/CodeGen/RISCV/atomic-rmw.ll | 532 ++++++++++++++++-------
2 files changed, 382 insertions(+), 177 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
index 5d4fb31d967b931..c43af14bb7f7005 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
@@ -129,8 +129,9 @@ let Predicates = [HasAtomicLdSt, IsRV64] in {
/// AMOs
-multiclass AMOPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT> {
-let Predicates = [HasStdExtA, NotHasStdExtZtso] in {
+multiclass AMOPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
+ list<Predicate> ExtraPreds = []> {
+let Predicates = !listconcat([HasStdExtA, NotHasStdExtZtso], ExtraPreds) in {
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_monotonic"),
!cast<RVInst>(BaseInst), vt>;
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_acquire"),
@@ -142,7 +143,7 @@ let Predicates = [HasStdExtA, NotHasStdExtZtso] in {
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_seq_cst"),
!cast<RVInst>(BaseInst#"_AQ_RL"), vt>;
}
-let Predicates = [HasStdExtA, HasStdExtZtso] in {
+let Predicates = !listconcat([HasStdExtA, HasStdExtZtso], ExtraPreds) in {
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_monotonic"),
!cast<RVInst>(BaseInst), vt>;
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_acquire"),
@@ -315,17 +316,17 @@ def : Pat<(int_riscv_masked_cmpxchg_i32
} // Predicates = [HasStdExtA]
-let Predicates = [HasStdExtA, IsRV64] in {
+defm : AMOPat<"atomic_swap_64", "AMOSWAP_D", i64, [IsRV64]>;
+defm : AMOPat<"atomic_load_add_64", "AMOADD_D", i64, [IsRV64]>;
+defm : AMOPat<"atomic_load_and_64", "AMOAND_D", i64, [IsRV64]>;
+defm : AMOPat<"atomic_load_or_64", "AMOOR_D", i64, [IsRV64]>;
+defm : AMOPat<"atomic_load_xor_64", "AMOXOR_D", i64, [IsRV64]>;
+defm : AMOPat<"atomic_load_max_64", "AMOMAX_D", i64, [IsRV64]>;
+defm : AMOPat<"atomic_load_min_64", "AMOMIN_D", i64, [IsRV64]>;
+defm : AMOPat<"atomic_load_umax_64", "AMOMAXU_D", i64, [IsRV64]>;
+defm : AMOPat<"atomic_load_umin_64", "AMOMINU_D", i64, [IsRV64]>;
-defm : AMOPat<"atomic_swap_64", "AMOSWAP_D", i64>;
-defm : AMOPat<"atomic_load_add_64", "AMOADD_D", i64>;
-defm : AMOPat<"atomic_load_and_64", "AMOAND_D", i64>;
-defm : AMOPat<"atomic_load_or_64", "AMOOR_D", i64>;
-defm : AMOPat<"atomic_load_xor_64", "AMOXOR_D", i64>;
-defm : AMOPat<"atomic_load_max_64", "AMOMAX_D", i64>;
-defm : AMOPat<"atomic_load_min_64", "AMOMIN_D", i64>;
-defm : AMOPat<"atomic_load_umax_64", "AMOMAXU_D", i64>;
-defm : AMOPat<"atomic_load_umin_64", "AMOMINU_D", i64>;
+let Predicates = [HasStdExtA, IsRV64] in {
/// 64-bit pseudo AMOs
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
index 53702403879c758..c4f224dcba1b21e 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -17562,10 +17562,15 @@ define i64 @atomicrmw_xchg_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_i64_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoswap.d.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_i64_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoswap.d.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_i64_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoswap.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i64 %b acquire
ret i64 %1
}
@@ -17601,10 +17606,15 @@ define i64 @atomicrmw_xchg_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_i64_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoswap.d.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_i64_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoswap.d.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_i64_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoswap.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i64 %b release
ret i64 %1
}
@@ -17640,10 +17650,15 @@ define i64 @atomicrmw_xchg_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_i64_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoswap.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_i64_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoswap.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_i64_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoswap.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i64 %b acq_rel
ret i64 %1
}
@@ -17679,10 +17694,15 @@ define i64 @atomicrmw_xchg_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_i64_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoswap.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_i64_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoswap.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_i64_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoswap.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i64 %b seq_cst
ret i64 %1
}
@@ -17757,10 +17777,15 @@ define i64 @atomicrmw_add_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_add_i64_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoadd.d.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_add_i64_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoadd.d.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_add_i64_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoadd.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw add ptr %a, i64 %b acquire
ret i64 %1
}
@@ -17796,10 +17821,15 @@ define i64 @atomicrmw_add_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_add_i64_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoadd.d.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_add_i64_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoadd.d.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_add_i64_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoadd.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw add ptr %a, i64 %b release
ret i64 %1
}
@@ -17835,10 +17865,15 @@ define i64 @atomicrmw_add_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_add_i64_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_add_i64_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoadd.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_add_i64_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoadd.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw add ptr %a, i64 %b acq_rel
ret i64 %1
}
@@ -17874,10 +17909,15 @@ define i64 @atomicrmw_add_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_add_i64_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_add_i64_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoadd.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_add_i64_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoadd.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw add ptr %a, i64 %b seq_cst
ret i64 %1
}
@@ -17953,11 +17993,17 @@ define i64 @atomicrmw_sub_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_sub_i64_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: neg a1, a1
-; RV64IA-NEXT: amoadd.d.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_sub_i64_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: neg a1, a1
+; RV64IA-WMO-NEXT: amoadd.d.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_sub_i64_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: neg a1, a1
+; RV64IA-TSO-NEXT: amoadd.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw sub ptr %a, i64 %b acquire
ret i64 %1
}
@@ -17993,11 +18039,17 @@ define i64 @atomicrmw_sub_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_sub_i64_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: neg a1, a1
-; RV64IA-NEXT: amoadd.d.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_sub_i64_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: neg a1, a1
+; RV64IA-WMO-NEXT: amoadd.d.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_sub_i64_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: neg a1, a1
+; RV64IA-TSO-NEXT: amoadd.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw sub ptr %a, i64 %b release
ret i64 %1
}
@@ -18033,11 +18085,17 @@ define i64 @atomicrmw_sub_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_sub_i64_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: neg a1, a1
-; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_sub_i64_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: neg a1, a1
+; RV64IA-WMO-NEXT: amoadd.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_sub_i64_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: neg a1, a1
+; RV64IA-TSO-NEXT: amoadd.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw sub ptr %a, i64 %b acq_rel
ret i64 %1
}
@@ -18073,11 +18131,17 @@ define i64 @atomicrmw_sub_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_sub_i64_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: neg a1, a1
-; RV64IA-NEXT: amoadd.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_sub_i64_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: neg a1, a1
+; RV64IA-WMO-NEXT: amoadd.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_sub_i64_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: neg a1, a1
+; RV64IA-TSO-NEXT: amoadd.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw sub ptr %a, i64 %b seq_cst
ret i64 %1
}
@@ -18152,10 +18216,15 @@ define i64 @atomicrmw_and_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i64_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoand.d.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i64_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoand.d.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i64_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoand.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i64 %b acquire
ret i64 %1
}
@@ -18191,10 +18260,15 @@ define i64 @atomicrmw_and_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i64_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoand.d.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i64_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoand.d.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i64_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoand.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i64 %b release
ret i64 %1
}
@@ -18230,10 +18304,15 @@ define i64 @atomicrmw_and_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i64_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoand.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i64_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoand.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i64_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoand.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i64 %b acq_rel
ret i64 %1
}
@@ -18269,10 +18348,15 @@ define i64 @atomicrmw_and_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i64_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoand.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i64_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoand.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_and_i64_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoand.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i64 %b seq_cst
ret i64 %1
}
@@ -18613,10 +18697,15 @@ define i64 @atomicrmw_or_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i64_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoor.d.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i64_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoor.d.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i64_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoor.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i64 %b acquire
ret i64 %1
}
@@ -18652,10 +18741,15 @@ define i64 @atomicrmw_or_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i64_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoor.d.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i64_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoor.d.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i64_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoor.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i64 %b release
ret i64 %1
}
@@ -18691,10 +18785,15 @@ define i64 @atomicrmw_or_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i64_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoor.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i64_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoor.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i64_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoor.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i64 %b acq_rel
ret i64 %1
}
@@ -18730,10 +18829,15 @@ define i64 @atomicrmw_or_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i64_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoor.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i64_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoor.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_or_i64_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoor.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i64 %b seq_cst
ret i64 %1
}
@@ -18808,10 +18912,15 @@ define i64 @atomicrmw_xor_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i64_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoxor.d.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i64_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoxor.d.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i64_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoxor.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i64 %b acquire
ret i64 %1
}
@@ -18847,10 +18956,15 @@ define i64 @atomicrmw_xor_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i64_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoxor.d.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i64_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoxor.d.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i64_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoxor.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i64 %b release
ret i64 %1
}
@@ -18886,10 +19000,15 @@ define i64 @atomicrmw_xor_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i64_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoxor.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i64_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoxor.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i64_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoxor.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i64 %b acq_rel
ret i64 %1
}
@@ -18925,10 +19044,15 @@ define i64 @atomicrmw_xor_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i64_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amoxor.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i64_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amoxor.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xor_i64_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amoxor.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i64 %b seq_cst
ret i64 %1
}
@@ -19231,10 +19355,15 @@ define i64 @atomicrmw_max_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_max_i64_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomax.d.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_max_i64_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomax.d.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_max_i64_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomax.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw max ptr %a, i64 %b acquire
ret i64 %1
}
@@ -19384,10 +19513,15 @@ define i64 @atomicrmw_max_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_max_i64_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomax.d.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_max_i64_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomax.d.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_max_i64_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomax.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw max ptr %a, i64 %b release
ret i64 %1
}
@@ -19537,10 +19671,15 @@ define i64 @atomicrmw_max_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_max_i64_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomax.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_max_i64_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomax.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_max_i64_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomax.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw max ptr %a, i64 %b acq_rel
ret i64 %1
}
@@ -19690,10 +19829,15 @@ define i64 @atomicrmw_max_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_max_i64_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomax.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_max_i64_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomax.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_max_i64_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomax.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw max ptr %a, i64 %b seq_cst
ret i64 %1
}
@@ -19996,10 +20140,15 @@ define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_min_i64_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomin.d.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_min_i64_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomin.d.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_min_i64_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomin.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw min ptr %a, i64 %b acquire
ret i64 %1
}
@@ -20149,10 +20298,15 @@ define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_min_i64_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomin.d.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_min_i64_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomin.d.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_min_i64_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomin.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw min ptr %a, i64 %b release
ret i64 %1
}
@@ -20302,10 +20456,15 @@ define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_min_i64_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomin.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_min_i64_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomin.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_min_i64_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomin.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw min ptr %a, i64 %b acq_rel
ret i64 %1
}
@@ -20455,10 +20614,15 @@ define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_min_i64_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomin.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_min_i64_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomin.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_min_i64_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomin.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw min ptr %a, i64 %b seq_cst
ret i64 %1
}
@@ -20761,10 +20925,15 @@ define i64 @atomicrmw_umax_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umax_i64_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomaxu.d.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umax_i64_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomaxu.d.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umax_i64_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomaxu.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umax ptr %a, i64 %b acquire
ret i64 %1
}
@@ -20914,10 +21083,15 @@ define i64 @atomicrmw_umax_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umax_i64_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomaxu.d.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umax_i64_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomaxu.d.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umax_i64_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomaxu.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umax ptr %a, i64 %b release
ret i64 %1
}
@@ -21067,10 +21241,15 @@ define i64 @atomicrmw_umax_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umax_i64_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomaxu.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umax_i64_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomaxu.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umax_i64_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomaxu.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umax ptr %a, i64 %b acq_rel
ret i64 %1
}
@@ -21220,10 +21399,15 @@ define i64 @atomicrmw_umax_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umax_i64_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amomaxu.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umax_i64_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amomaxu.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umax_i64_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amomaxu.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umax ptr %a, i64 %b seq_cst
ret i64 %1
}
@@ -21526,10 +21710,15 @@ define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umin_i64_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amominu.d.aq a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umin_i64_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amominu.d.aq a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umin_i64_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amominu.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umin ptr %a, i64 %b acquire
ret i64 %1
}
@@ -21679,10 +21868,15 @@ define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umin_i64_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amominu.d.rl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umin_i64_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amominu.d.rl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umin_i64_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amominu.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umin ptr %a, i64 %b release
ret i64 %1
}
@@ -21832,10 +22026,15 @@ define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umin_i64_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amominu.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umin_i64_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amominu.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umin_i64_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amominu.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umin ptr %a, i64 %b acq_rel
ret i64 %1
}
@@ -21985,10 +22184,15 @@ define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umin_i64_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: amominu.d.aqrl a0, a1, (a0)
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umin_i64_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: amominu.d.aqrl a0, a1, (a0)
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_umin_i64_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: amominu.d a0, a1, (a0)
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umin ptr %a, i64 %b seq_cst
ret i64 %1
}
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