[llvm] db47264 - Revert "[AMDGPU]: Allow combining into v_dot4" (#66158)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 12 16:57:21 PDT 2023
Author: Jeffrey Byrnes
Date: 2023-09-12T16:57:17-07:00
New Revision: db47264ab32d2743b17d003c5bd16b99fa06e7e0
URL: https://github.com/llvm/llvm-project/commit/db47264ab32d2743b17d003c5bd16b99fa06e7e0
DIFF: https://github.com/llvm/llvm-project/commit/db47264ab32d2743b17d003c5bd16b99fa06e7e0.diff
LOG: Revert "[AMDGPU]: Allow combining into v_dot4" (#66158)
This reverts commit 7fda1b74be4a173031192d8516869e87e6b7582d.
Added:
Modified:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/test/CodeGen/AMDGPU/idot2.ll
llvm/test/CodeGen/AMDGPU/idot4s.ll
llvm/test/CodeGen/AMDGPU/idot4u.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 2309f392449411c..e87e3dc1393273d 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -12501,193 +12501,6 @@ SDValue SITargetLowering::tryFoldToMad64_32(SDNode *N,
return Accum;
}
-// Collect the ultimate src of each of the mul24 node's operands, and confirm
-// each operand is 8 bytes.
-static std::optional<ByteProvider<SDValue>>
-handleMulOperand(const SDValue &MulOperand) {
- auto Byte0 = calculateByteProvider(MulOperand, 0, 0);
- if (!Byte0 || Byte0->isConstantZero()) {
- return std::nullopt;
- }
- auto Byte1 = calculateByteProvider(MulOperand, 1, 0);
- if (Byte1 && !Byte1->isConstantZero()) {
- return std::nullopt;
- }
- return Byte0;
-}
-
-static unsigned addPermMasks(unsigned First, unsigned Second) {
- unsigned FirstCs = First & 0x0c0c0c0c;
- unsigned SecondCs = Second & 0x0c0c0c0c;
- unsigned FirstNoCs = First & ~0x0c0c0c0c;
- unsigned SecondNoCs = Second & ~0x0c0c0c0c;
-
- assert(FirstCs & 0xFF | SecondCs & 0xFF);
- assert(FirstCs & 0xFF00 | SecondCs & 0xFF00);
- assert(FirstCs & 0xFF0000 | SecondCs & 0xFF0000);
- assert(FirstCs & 0xFF000000 | SecondCs & 0xFF000000);
-
- return (FirstNoCs | SecondNoCs) | (FirstCs & SecondCs);
-}
-
-static void placeSources(ByteProvider<SDValue> &Src0,
- ByteProvider<SDValue> &Src1,
- SmallVectorImpl<std::pair<SDValue, unsigned>> &Src0s,
- SmallVectorImpl<std::pair<SDValue, unsigned>> &Src1s,
- int Step) {
-
- assert(Src0.Src.has_value() && Src1.Src.has_value());
- // Src0s and Src1s are empty, just place arbitrarily
- if (Step == 0) {
- Src0s.push_back({*Src0.Src, (Src0.SrcOffset << 24) + 0x0c0c0c});
- Src1s.push_back({*Src1.Src, (Src1.SrcOffset << 24) + 0x0c0c0c});
- return;
- }
-
- for (int BPI = 0; BPI < 2; BPI++) {
- std::pair<ByteProvider<SDValue>, ByteProvider<SDValue>> BPP = {Src0, Src1};
- if (BPI == 1) {
- BPP = {Src1, Src0};
- }
- unsigned ZeroMask = 0x0c0c0c0c;
- unsigned FMask = 0xFF << (8 * (3 - Step));
-
- unsigned FirstMask =
- BPP.first.SrcOffset << (8 * (3 - Step)) | (ZeroMask & ~FMask);
- unsigned SecondMask =
- BPP.second.SrcOffset << (8 * (3 - Step)) | (ZeroMask & ~FMask);
- // Attempt to find Src vector which contains our SDValue, if so, add our
- // perm mask to the existing one. If we are unable to find a match for the
- // first SDValue, attempt to find match for the second.
- int FirstGroup = -1;
- for (int I = 0; I < 2; I++) {
- SmallVectorImpl<std::pair<SDValue, unsigned>> &Srcs =
- I == 0 ? Src0s : Src1s;
- auto MatchesFirst = [&BPP](std::pair<SDValue, unsigned> IterElt) {
- return IterElt.first == *BPP.first.Src;
- };
-
- auto Match = std::find_if(Srcs.begin(), Srcs.end(), MatchesFirst);
- if (Match != Srcs.end()) {
- Match->second = addPermMasks(FirstMask, Match->second);
- FirstGroup = I;
- break;
- }
- }
- if (FirstGroup != -1) {
- SmallVectorImpl<std::pair<SDValue, unsigned>> &Srcs =
- FirstGroup == 1 ? Src0s : Src1s;
- auto MatchesSecond = [&BPP](std::pair<SDValue, unsigned> IterElt) {
- return IterElt.first == *BPP.second.Src;
- };
- auto Match = std::find_if(Srcs.begin(), Srcs.end(), MatchesSecond);
- if (Match != Srcs.end()) {
- Match->second = addPermMasks(SecondMask, Match->second);
- } else
- Srcs.push_back({*BPP.second.Src, SecondMask});
- return;
- }
- }
-
- // If we have made it here, then we could not find a match in Src0s or Src1s
- // for either Src0 or Src1, so just place them arbitrarily.
-
- unsigned ZeroMask = 0x0c0c0c0c;
- unsigned FMask = 0xFF << (8 * (3 - Step));
-
- Src0s.push_back(
- {*Src0.Src, (Src0.SrcOffset << (8 * (3 - Step)) | (ZeroMask & ~FMask))});
- Src1s.push_back(
- {*Src1.Src, (Src1.SrcOffset << (8 * (3 - Step)) | (ZeroMask & ~FMask))});
-
- return;
-}
-
-static SDValue
-resolveSources(SelectionDAG &DAG, SDLoc SL,
- SmallVectorImpl<std::pair<SDValue, unsigned>> &Srcs,
- bool IsSigned, bool IsAny) {
-
- // If we just have one source, just permute it accordingly.
- if (Srcs.size() == 1) {
- auto Elt = Srcs.begin();
- auto EltVal = DAG.getBitcastedAnyExtOrTrunc(Elt->first, SL, MVT::i32);
-
- // v_perm will produce the original value
- if (Elt->second == 0x3020100)
- return EltVal;
-
- return DAG.getNode(AMDGPUISD::PERM, SL, MVT::i32, EltVal, EltVal,
- DAG.getConstant(Elt->second, SL, MVT::i32));
- }
-
- auto FirstElt = Srcs.begin();
- auto SecondElt = std::next(FirstElt);
-
- SmallVector<SDValue, 2> Perms;
-
- // If we have multiple sources in the chain, combine them via perms (using
- // calculated perm mask) and Ors.
- while (true) {
- auto FirstMask = FirstElt->second;
- auto SecondMask = SecondElt->second;
-
- unsigned FirstCs = FirstMask & 0x0c0c0c0c;
- unsigned FirstPlusFour = FirstMask | 0x04040404;
- // 0x0c + 0x04 = 0x10, so anding with 0x0F will produced 0x00 for any
- // original 0x0C
- FirstMask = (FirstPlusFour & 0x0F0F0F0F) | FirstCs;
-
- auto PermMask = addPermMasks(FirstMask, SecondMask);
- auto FirstVal =
- DAG.getBitcastedAnyExtOrTrunc(FirstElt->first, SL, MVT::i32);
- auto SecondVal =
- DAG.getBitcastedAnyExtOrTrunc(SecondElt->first, SL, MVT::i32);
-
- Perms.push_back(DAG.getNode(AMDGPUISD::PERM, SL, MVT::i32, FirstVal,
- SecondVal,
- DAG.getConstant(PermMask, SL, MVT::i32)));
-
- FirstElt = std::next(SecondElt);
- if (FirstElt == Srcs.end())
- break;
-
- SecondElt = std::next(FirstElt);
- // If we only have a FirstElt, then just combine that into the cumulative
- // source node
- if (SecondElt == Srcs.end()) {
- auto EltVal =
- DAG.getBitcastedAnyExtOrTrunc(FirstElt->first, SL, MVT::i32);
-
- Perms.push_back(
- DAG.getNode(AMDGPUISD::PERM, SL, MVT::i32, EltVal, EltVal,
- DAG.getConstant(FirstElt->second, SL, MVT::i32)));
- break;
- }
- }
-
- assert(Perms.size() == 1 || Perms.size() == 2);
- return Perms.size() == 2
- ? DAG.getNode(ISD::OR, SL, MVT::i32, Perms[0], Perms[1])
- : Perms[0];
-}
-
-static void fixMasks(SmallVectorImpl<std::pair<SDValue, unsigned>> &Srcs,
- unsigned ChainLength) {
- for (auto &[EntryVal, EntryMask] : Srcs) {
- EntryMask = EntryMask >> ((4 - ChainLength) * 8);
- auto ZeroMask = ChainLength == 2 ? 0x0c0c0000 : 0x0c000000;
- EntryMask += ZeroMask;
- }
-}
-
-static bool isMul(const SDValue Op) {
- auto Opcode = Op.getOpcode();
-
- return (Opcode == ISD::MUL || Opcode == AMDGPUISD::MUL_U24 ||
- Opcode == AMDGPUISD::MUL_I24);
-}
-
SDValue SITargetLowering::performAddCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
@@ -12701,140 +12514,14 @@ SDValue SITargetLowering::performAddCombine(SDNode *N,
if (SDValue Folded = tryFoldToMad64_32(N, DCI))
return Folded;
}
+
+ return SDValue();
}
if (SDValue V = reassociateScalarOps(N, DAG)) {
return V;
}
- if ((isMul(LHS) || isMul(RHS)) && Subtarget->hasDot7Insts() &&
- (Subtarget->hasDot1Insts() || Subtarget->hasDot8Insts())) {
- SDValue TempNode(N, 0);
- auto MulIdx = isMul(LHS) ? 0 : 1;
-
- auto MulOpcode = TempNode.getOperand(MulIdx).getOpcode();
- bool IsSigned =
- MulOpcode == AMDGPUISD::MUL_I24 ||
- (MulOpcode == ISD::MUL &&
- TempNode->getOperand(MulIdx)->getFlags().hasNoSignedWrap() &&
- !TempNode->getOperand(MulIdx)->getFlags().hasNoUnsignedWrap());
- SmallVector<std::pair<SDValue, unsigned>, 4> Src0s;
- SmallVector<std::pair<SDValue, unsigned>, 4> Src1s;
- SmallVector<SDValue, 4> Src2s;
-
- // Match the v_dot4 tree, while collecting src nodes.
- int ChainLength = 0;
- for (int I = 0; I < 4; I++) {
- auto MulIdx = isMul(LHS) ? 0 : isMul(RHS) ? 1 : -1;
- if (MulIdx == -1)
- break;
- auto IterIsSigned =
- MulOpcode == AMDGPUISD::MUL_I24 ||
- (MulOpcode == ISD::MUL &&
- TempNode->getOperand(MulIdx)->getFlags().hasNoSignedWrap() &&
- !TempNode->getOperand(MulIdx)->getFlags().hasNoUnsignedWrap());
- if (IterIsSigned != IsSigned) {
- break;
- }
- auto Src0 = handleMulOperand(TempNode->getOperand(MulIdx)->getOperand(0));
- if (!Src0)
- break;
- auto Src1 = handleMulOperand(TempNode->getOperand(MulIdx)->getOperand(1));
- if (!Src1)
- break;
- placeSources(*Src0, *Src1, Src0s, Src1s, I);
- auto AddIdx = 1 - MulIdx;
- // Allow the special case where add (add (mul24, 0), mul24) became ->
- // add (mul24, mul24)
- if (I == 2 && isMul(TempNode->getOperand(AddIdx))) {
- Src2s.push_back(TempNode->getOperand(AddIdx));
- auto Src0 =
- handleMulOperand(TempNode->getOperand(AddIdx)->getOperand(0));
- if (!Src0)
- break;
- auto Src1 =
- handleMulOperand(TempNode->getOperand(AddIdx)->getOperand(1));
- if (!Src1)
- break;
- placeSources(*Src0, *Src1, Src0s, Src1s, I + 1);
- Src2s.push_back(DAG.getConstant(0, SL, MVT::i32));
- ChainLength = I + 2;
- break;
- }
-
- TempNode = TempNode->getOperand(AddIdx);
- Src2s.push_back(TempNode);
- ChainLength = I + 1;
- if (TempNode->getNumOperands() < 2)
- break;
- LHS = TempNode->getOperand(0);
- RHS = TempNode->getOperand(1);
- }
-
- if (ChainLength < 2)
- return SDValue();
-
- // Masks were constructed with assumption that we would find a chain of
- // length 4. If not, then we need to 0 out the MSB bits (via perm mask of
- // 0x0c) so they do not affect dot calculation.
- if (ChainLength < 4) {
- fixMasks(Src0s, ChainLength);
- fixMasks(Src1s, ChainLength);
- }
-
- SDValue Src0, Src1;
-
- // If we are just using a single source for both, and have permuted the
- // bytes consistently, we can just use the sources without permuting
- // (commutation)
- bool UseOriginalSrc = false;
- if (ChainLength == 4 && Src0s.size() == 1 && Src1s.size() == 1 &&
- Src0s.begin()->second == Src1s.begin()->second &&
- Src0s.begin()->first.getValueSizeInBits() == 32 &&
- Src1s.begin()->first.getValueSizeInBits() == 32) {
- SmallVector<unsigned, 4> SrcBytes;
- auto Src0Mask = Src0s.begin()->second;
- SrcBytes.push_back(Src0Mask & 0xFF000000);
- bool UniqueEntries = true;
- for (auto I = 1; I < 4; I++) {
- auto NextByte = Src0Mask & (0xFF << ((3 - I) * 8));
-
- if (is_contained(SrcBytes, NextByte)) {
- UniqueEntries = false;
- break;
- }
- SrcBytes.push_back(NextByte);
- }
-
- if (UniqueEntries) {
- UseOriginalSrc = true;
- // Must be 32 bits to enter above conditional
- assert(Src0s.begin()->first.getValueSizeInBits() == 32);
- assert(Src1s.begin()->first.getValueSizeInBits() == 32);
- Src0 = DAG.getBitcast(MVT::getIntegerVT(32), Src0s.begin()->first);
- Src1 = DAG.getBitcast(MVT::getIntegerVT(32), Src1s.begin()->first);
- }
- }
-
- if (!UseOriginalSrc) {
- Src0 = resolveSources(DAG, SL, Src0s, false, true);
- Src1 = resolveSources(DAG, SL, Src1s, false, true);
- }
-
- SDValue Src2 =
- DAG.getExtOrTrunc(IsSigned, Src2s[ChainLength - 1], SL, MVT::i32);
-
- SDValue IID = DAG.getTargetConstant(IsSigned ? Intrinsic::amdgcn_sdot4
- : Intrinsic::amdgcn_udot4,
- SL, MVT::i64);
-
- assert(!VT.isVector());
- auto Dot = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SL, MVT::i32, IID, Src0,
- Src1, Src2, DAG.getTargetConstant(0, SL, MVT::i1));
-
- return DAG.getExtOrTrunc(IsSigned, Dot, SL, VT);
- }
-
if (VT != MVT::i32 || !DCI.isAfterLegalizeDAG())
return SDValue();
diff --git a/llvm/test/CodeGen/AMDGPU/idot2.ll b/llvm/test/CodeGen/AMDGPU/idot2.ll
index 56f72ac9d9e8c6d..ccde5efce08dc8e 100644
--- a/llvm/test/CodeGen/AMDGPU/idot2.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot2.ll
@@ -2823,18 +2823,18 @@ define amdgpu_kernel void @notsdot2_sext8(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX9-DL-NEXT: s_mov_b32 s1, 0xc0c0001
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: global_load_ushort v1, v0, s[4:5]
; GFX9-DL-NEXT: global_load_ushort v2, v0, s[6:7]
; GFX9-DL-NEXT: s_load_dword s0, s[2:3], 0x0
; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v1, v1, v1, s1
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v2, v2, s1
+; GFX9-DL-NEXT: v_mul_i32_i24_sdwa v3, sext(v2), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-DL-NEXT: v_lshrrev_b16_e32 v1, 8, v1
+; GFX9-DL-NEXT: v_lshrrev_b16_e32 v2, 8, v2
+; GFX9-DL-NEXT: v_mul_i32_i24_sdwa v1, sext(v2), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_i32_i8 v1, v2, v1, s0
+; GFX9-DL-NEXT: v_add3_u32 v1, v1, s0, v3
; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm
;
@@ -2843,20 +2843,21 @@ define amdgpu_kernel void @notsdot2_sext8(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_ushort v1, v0, s[4:5]
; GFX10-DL-NEXT: global_load_ushort v2, v0, s[6:7]
; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc0c0001
+; GFX10-DL-NEXT: v_lshrrev_b16 v0, 8, v1
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v1, v2, v2, 0xc0c0001
+; GFX10-DL-NEXT: v_lshrrev_b16 v3, 8, v2
+; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v1, sext(v2), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v0, sext(v3), sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_mov_b32_e32 v2, s2
-; GFX10-DL-NEXT: v_dot4c_i32_i8_e32 v2, v1, v0
-; GFX10-DL-NEXT: global_store_dword v3, v2, s[0:1]
+; GFX10-DL-NEXT: v_add3_u32 v0, v0, s2, v1
+; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
diff --git a/llvm/test/CodeGen/AMDGPU/idot4s.ll b/llvm/test/CodeGen/AMDGPU/idot4s.ll
index 7edd24f12982ebd..ea22aaee761c8dd 100644
--- a/llvm/test/CodeGen/AMDGPU/idot4s.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot4s.ll
@@ -5,7 +5,6 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9-DL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-DL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-DL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-DL %s
define amdgpu_kernel void @idot4_acc32(ptr addrspace(1) %src1,
; GFX7-LABEL: idot4_acc32:
@@ -118,36 +117,16 @@ define amdgpu_kernel void @idot4_acc32(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
+; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_dot4c_i32_i8_e32 v0, v1, v2
-; GFX10-DL-NEXT: global_store_dword v3, v0, s[0:1]
+; GFX10-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX10-DL-NEXT: v_dot4_i32_i8 v1, v1, v2, s2
+; GFX10-DL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc32:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-DL-NEXT: v_dot4_i32_iu8 v0, v1, v0, s2
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -190,6 +169,8 @@ entry:
ret void
}
+; TODO: Currently, vector elements{0 and 3} get zero_extended from i16 to i32 which should
+; be sign_extended directly to i32; prevents the pattern recognizer to recognize this pattern.
define amdgpu_kernel void @idot4_acc16(ptr addrspace(1) %src1,
; GFX7-LABEL: idot4_acc16:
; GFX7: ; %bb.0: ; %entry
@@ -313,14 +294,33 @@ define amdgpu_kernel void @idot4_acc16(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: v_mov_b32_e32 v1, 0
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v3, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_sshort v4, v1, s[2:3]
+; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
+; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
+; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-DL-NEXT: global_load_ushort v3, v0, s[2:3]
+; GFX9-DL-NEXT: s_waitcnt vmcnt(2)
+; GFX9-DL-NEXT: v_bfe_i32 v6, v1, 0, 8
+; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX9-DL-NEXT: v_bfe_i32 v7, v2, 0, 8
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v8, 8, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v9, 8, v2
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX9-DL-NEXT: v_bfe_i32 v8, v8, 0, 8
+; GFX9-DL-NEXT: v_bfe_i32 v9, v9, 0, 8
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_dot4_i32_i8 v0, v2, v3, v4
-; GFX9-DL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v6, v7, v3
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
+; GFX9-DL-NEXT: v_bfe_i32 v4, v4, 0, 8
+; GFX9-DL-NEXT: v_bfe_i32 v5, v5, 0, 8
+; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v8, v9, v3
+; GFX9-DL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX9-DL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v4, v5, v3
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v1, v2, v3
+; GFX9-DL-NEXT: global_store_short v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm
;
; GFX10-DL-LABEL: idot4_acc16:
@@ -329,34 +329,35 @@ define amdgpu_kernel void @idot4_acc16(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
-; GFX10-DL-NEXT: global_load_sshort v4, v1, s[2:3]
+; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
+; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
+; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-DL-NEXT: global_load_ushort v3, v0, s[2:3]
+; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
+; GFX10-DL-NEXT: v_bfe_i32 v4, v1, 0, 8
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v2
+; GFX10-DL-NEXT: v_bfe_i32 v7, v2, 0, 8
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX10-DL-NEXT: v_bfe_i32 v5, v5, 0, 8
+; GFX10-DL-NEXT: v_bfe_i32 v6, v6, 0, 8
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_dot4c_i32_i8_e32 v4, v2, v3
-; GFX10-DL-NEXT: global_store_short v1, v4, s[2:3]
+; GFX10-DL-NEXT: v_mad_u16 v3, v4, v7, v3
+; GFX10-DL-NEXT: v_bfe_i32 v4, v8, 0, 8
+; GFX10-DL-NEXT: v_bfe_i32 v7, v9, 0, 8
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
+; GFX10-DL-NEXT: v_mad_u16 v3, v5, v6, v3
+; GFX10-DL-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX10-DL-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX10-DL-NEXT: v_mad_u16 v3, v4, v7, v3
+; GFX10-DL-NEXT: v_mad_u16 v1, v1, v2, v3
+; GFX10-DL-NEXT: global_store_short v0, v1, s[2:3]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc16:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v2, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_i16 v3, v1, s[0:1]
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_dot4_i32_iu8 v0, v2, v0, v3
-; GFX11-DL-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -498,14 +499,25 @@ define amdgpu_kernel void @idot4_acc8(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: v_mov_b32_e32 v1, 0
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v3, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
+; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
+; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
+; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-DL-NEXT: global_load_ubyte v3, v0, s[2:3]
+; GFX9-DL-NEXT: s_waitcnt vmcnt(2)
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v1
+; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v2
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v8, 24, v1
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v0, v2, v3, v4
-; GFX9-DL-NEXT: global_store_byte v1, v0, s[2:3]
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v1, v2, v3
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v6, v7, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v9, 24, v2
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v4, v5, v1
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v8, v9, v1
+; GFX9-DL-NEXT: global_store_byte v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm
;
; GFX10-DL-LABEL: idot4_acc8:
@@ -520,28 +532,21 @@ define amdgpu_kernel void @idot4_acc8(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
+; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 8, v2
+; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v2, v3, v4
+; GFX10-DL-NEXT: v_mad_u16 v4, v2, v3, v4
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v4
+; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0
+; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0
; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc8:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v2, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_u8 v3, v1, s[0:1]
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v2, v0, v3
-; GFX11-DL-NEXT: global_store_b8 v1, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -687,9 +692,14 @@ define amdgpu_kernel void @idot4_multiuse_mul1(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: v_bfe_i32 v3, v1, 0, 8
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_bfe_i32 v4, v2, 0, 8
+; GFX9-DL-NEXT: v_mul_i32_i24_sdwa v5, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
+; GFX9-DL-NEXT: v_mul_i32_i24_sdwa v6, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
+; GFX9-DL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
+; GFX9-DL-NEXT: v_mul_i32_i24_e32 v2, v3, v4
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: v_mad_i32_i24 v3, v3, v4, s0
-; GFX9-DL-NEXT: v_dot4_i32_i8 v1, v1, v2, v3
+; GFX9-DL-NEXT: v_add3_u32 v2, v5, v3, v2
+; GFX9-DL-NEXT: v_add3_u32 v1, v2, v6, v1
; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm
;
@@ -707,36 +717,17 @@ define amdgpu_kernel void @idot4_multiuse_mul1(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: v_bfe_i32 v0, v1, 0, 8
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_bfe_i32 v3, v2, 0, 8
+; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v4, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
+; GFX10-DL-NEXT: v_mul_i32_i24_e32 v5, v0, v3
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_mad_i32_i24 v0, v0, v3, s2
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-DL-NEXT: v_dot4c_i32_i8_e32 v0, v1, v2
-; GFX10-DL-NEXT: global_store_dword v3, v0, s[0:1]
+; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v3, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
+; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
+; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-DL-NEXT: v_add3_u32 v0, v4, v0, v5
+; GFX10-DL-NEXT: v_add3_u32 v0, v0, v3, v1
+; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_multiuse_mul1:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_bfe_i32 v2, v1, 0, 8
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_bfe_i32 v3, v0, 0, 8
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-DL-NEXT: v_mad_i32_i24 v2, v2, v3, s2
-; GFX11-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX11-DL-NEXT: v_dot4_i32_iu8 v0, v1, v0, v2
-; GFX11-DL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -781,6 +772,7 @@ entry:
ret void
}
+; TODO: Support this pattern.
define amdgpu_kernel void @idot4_acc32_vecMul(ptr addrspace(1) %src1,
; GFX7-LABEL: idot4_acc32_vecMul:
; GFX7: ; %bb.0: ; %entry
@@ -887,8 +879,17 @@ define amdgpu_kernel void @idot4_acc32_vecMul(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX9-DL-NEXT: s_load_dword s0, s[2:3], 0x0
; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_i32_i8 v1, v1, v2, s0
+; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX9-DL-NEXT: v_lshrrev_b16_e32 v3, 8, v1
+; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
+; GFX9-DL-NEXT: v_lshrrev_b16_e32 v4, 8, v2
+; GFX9-DL-NEXT: v_mul_i32_i24_sdwa v5, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-DL-NEXT: v_mul_i32_i24_sdwa v3, sext(v3), sext(v4) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-DL-NEXT: v_mul_i32_i24_sdwa v6, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
+; GFX9-DL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
+; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-DL-NEXT: v_add3_u32 v2, v5, s0, v3
+; GFX9-DL-NEXT: v_add3_u32 v1, v2, v6, v1
; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm
;
@@ -897,36 +898,25 @@ define amdgpu_kernel void @idot4_acc32_vecMul(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2
+; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX10-DL-NEXT: v_lshrrev_b16 v0, 8, v1
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_dot4c_i32_i8_e32 v0, v1, v2
-; GFX10-DL-NEXT: global_store_dword v3, v0, s[0:1]
+; GFX10-DL-NEXT: v_lshrrev_b16 v3, 8, v2
+; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v4, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v0, sext(v0), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v3, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
+; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
+; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-DL-NEXT: v_add3_u32 v0, v4, s2, v0
+; GFX10-DL-NEXT: v_add3_u32 v0, v0, v3, v1
+; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc32_vecMul:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-DL-NEXT: v_dot4_i32_iu8 v0, v1, v0, s2
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -1147,53 +1137,6 @@ define amdgpu_kernel void @idot4_acc16_vecMul(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v3
; GFX10-DL-NEXT: global_store_short v0, v1, s[0:1]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc16_vecMul:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_u16 v3, v2, s[0:1]
-; GFX11-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX11-DL-NEXT: v_ashrrev_i16 v4, 8, v1
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_ashrrev_i16 v5, 8, v0
-; GFX11-DL-NEXT: v_bfe_i32 v6, v0, 0, 8
-; GFX11-DL-NEXT: v_bfe_i32 v7, v1, 0, 8
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-DL-NEXT: v_perm_b32 v5, v5, v6, 0x5040100
-; GFX11-DL-NEXT: v_perm_b32 v4, v4, v7, 0x5040100
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-DL-NEXT: v_ashrrev_i16 v6, 8, v1
-; GFX11-DL-NEXT: v_ashrrev_i16 v7, 8, v0
-; GFX11-DL-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX11-DL-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX11-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-NEXT: v_perm_b32 v0, v7, v0, 0x5040100
-; GFX11-DL-NEXT: v_perm_b32 v1, v6, v1, 0x5040100
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v4
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_add_nc_u16 v3, v4, v3
-; GFX11-DL-NEXT: v_pk_mul_lo_u16 v0, v1, v0
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-DL-NEXT: v_add_nc_u16 v1, v3, v5
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-NEXT: v_add_nc_u16 v0, v1, v0
-; GFX11-DL-NEXT: v_add_nc_u16 v0, v0, v3
-; GFX11-DL-NEXT: global_store_b16 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -1222,1973 +1165,4 @@ entry:
ret void
}
-define amdgpu_kernel void @idot4_acc32_2ele(ptr addrspace(1) %src1,
-; GFX7-LABEL: idot4_acc32_2ele:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, s3
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5]
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s2, -1
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_bfe_i32 v1, v2, 0, 8
-; GFX7-NEXT: v_bfe_i32 v2, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_i32 v3, v0, 0, 8
-; GFX7-NEXT: v_bfe_i32 v0, v0, 8, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_i32_i24 v1, v1, v3, s4
-; GFX7-NEXT: v_mad_i32_i24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: idot4_acc32_2ele:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_bfe_i32 v1, v3, 0, 8
-; GFX8-NEXT: v_bfe_i32 v3, v3, 8, 8
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_bfe_i32 v2, v0, 0, 8
-; GFX8-NEXT: v_bfe_i32 v0, v0, 8, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_i32_i24 v1, v1, v2, s2
-; GFX8-NEXT: v_mad_i32_i24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: idot4_acc32_2ele:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v3, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_add3_u32 v1, v3, s0, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: idot4_acc32_2ele:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_mov_b32 s1, 0xc0c0100
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v1, v1, v1, s1
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v2, v2, s1
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_i32_i8 v1, v2, v1, s0
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: idot4_acc32_2ele:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc0c0100
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v1, v2, v2, 0xc0c0100
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_mov_b32_e32 v2, s2
-; GFX10-DL-NEXT: v_dot4c_i32_i8_e32 v2, v1, v0
-; GFX10-DL-NEXT: global_store_dword v3, v2, s[0:1]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc32_2ele:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[4:5]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc0c0100
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0xc0c0100
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT: v_dot4_i32_iu8 v0, v0, v1, s2
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = sext i8 %v1e0 to i32
- %v2e0 = extractelement <4 x i8> %vec2, i64 0
- %cv2e0 = sext i8 %v2e0 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = sext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = sext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %add1 = add i32 %mul1, %acc
- %add2 = add i32 %add1, %mul2
- store i32 %add2, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-
-define amdgpu_kernel void @idot4_acc32_3ele(ptr addrspace(1) %src1,
-; GFX7-LABEL: idot4_acc32_3ele:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, s3
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5]
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s2, -1
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_bfe_i32 v1, v2, 0, 8
-; GFX7-NEXT: v_bfe_i32 v3, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_i32 v4, v0, 0, 8
-; GFX7-NEXT: v_bfe_i32 v5, v0, 8, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_i32_i24 v1, v1, v4, s4
-; GFX7-NEXT: v_bfe_i32 v2, v2, 16, 8
-; GFX7-NEXT: v_bfe_i32 v0, v0, 16, 8
-; GFX7-NEXT: v_mad_i32_i24 v1, v3, v5, v1
-; GFX7-NEXT: v_mad_i32_i24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: idot4_acc32_3ele:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_bfe_i32 v1, v3, 0, 8
-; GFX8-NEXT: v_bfe_i32 v4, v3, 8, 8
-; GFX8-NEXT: v_bfe_i32 v3, v3, 16, 8
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_bfe_i32 v2, v0, 0, 8
-; GFX8-NEXT: v_bfe_i32 v5, v0, 8, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_i32_i24 v1, v1, v2, s2
-; GFX8-NEXT: v_bfe_i32 v0, v0, 16, 8
-; GFX8-NEXT: v_mad_i32_i24 v1, v4, v5, v1
-; GFX8-NEXT: v_mad_i32_i24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: idot4_acc32_3ele:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_bfe_i32 v3, v1, 0, 8
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_bfe_i32 v4, v2, 0, 8
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v5, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_mad_i32_i24 v2, v3, v4, s0
-; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v5, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: idot4_acc32_3ele:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_mov_b32 s1, 0xc020100
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v1, v1, v1, s1
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v2, v2, s1
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_i32_i8 v1, v2, v1, s0
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: idot4_acc32_3ele:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc020100
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v1, v2, v2, 0xc020100
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_mov_b32_e32 v2, s2
-; GFX10-DL-NEXT: v_dot4c_i32_i8_e32 v2, v1, v0
-; GFX10-DL-NEXT: global_store_dword v3, v2, s[0:1]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc32_3ele:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[4:5]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc020100
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0xc020100
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT: v_dot4_i32_iu8 v0, v0, v1, s2
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = sext i8 %v1e0 to i32
- %v2e0 = extractelement <4 x i8> %vec2, i64 0
- %cv2e0 = sext i8 %v2e0 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = sext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = sext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v1e2 = extractelement <4 x i8> %vec1, i64 2
- %cv1e2 = sext i8 %v1e2 to i32
- %v2e2 = extractelement <4 x i8> %vec2, i64 2
- %cv2e2 = sext i8 %v2e2 to i32
- %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %add1 = add i32 %mul1, %acc
- %add2 = add i32 %add1, %mul2
- %add3 = add i32 %add2, %mul3
- store i32 %add3, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-
-define amdgpu_kernel void @idot4_acc32_3ele_permuted(ptr addrspace(1) %src1,
-; GFX7-LABEL: idot4_acc32_3ele_permuted:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, s3
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5]
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s2, -1
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_ashrrev_i32_e32 v1, 24, v2
-; GFX7-NEXT: v_bfe_i32 v3, v2, 0, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_ashrrev_i32_e32 v4, 24, v0
-; GFX7-NEXT: v_bfe_i32 v5, v0, 0, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_i32_i24 v1, v1, v4, s4
-; GFX7-NEXT: v_bfe_i32 v2, v2, 16, 8
-; GFX7-NEXT: v_bfe_i32 v0, v0, 16, 8
-; GFX7-NEXT: v_mad_i32_i24 v1, v3, v5, v1
-; GFX7-NEXT: v_mad_i32_i24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: idot4_acc32_3ele_permuted:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_ashrrev_i32_e32 v1, 24, v3
-; GFX8-NEXT: v_bfe_i32 v4, v3, 0, 8
-; GFX8-NEXT: v_bfe_i32 v3, v3, 16, 8
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_ashrrev_i32_e32 v2, 24, v0
-; GFX8-NEXT: v_bfe_i32 v5, v0, 0, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_i32_i24 v1, v1, v2, s2
-; GFX8-NEXT: v_bfe_i32 v0, v0, 16, 8
-; GFX8-NEXT: v_mad_i32_i24 v1, v4, v5, v1
-; GFX8-NEXT: v_mad_i32_i24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: idot4_acc32_3ele_permuted:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_ashrrev_i32_e32 v3, 24, v1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_ashrrev_i32_e32 v4, 24, v2
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v5, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_mad_i32_i24 v2, v3, v4, s0
-; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v5, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: idot4_acc32_3ele_permuted:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_mov_b32 s1, 0xc020003
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v1, v1, v1, s1
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v2, v2, s1
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_i32_i8 v1, v2, v1, s0
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: idot4_acc32_3ele_permuted:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc020003
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v1, v2, v2, 0xc020003
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_mov_b32_e32 v2, s2
-; GFX10-DL-NEXT: v_dot4c_i32_i8_e32 v2, v1, v0
-; GFX10-DL-NEXT: global_store_dword v3, v2, s[0:1]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc32_3ele_permuted:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[4:5]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc020003
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0xc020003
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT: v_dot4_i32_iu8 v0, v0, v1, s2
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 3
- %cv1e0 = sext i8 %v1e0 to i32
- %v2e0 = extractelement <4 x i8> %vec2, i64 3
- %cv2e0 = sext i8 %v2e0 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 0
- %cv1e1 = sext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 0
- %cv2e1 = sext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v1e2 = extractelement <4 x i8> %vec1, i64 2
- %cv1e2 = sext i8 %v1e2 to i32
- %v2e2 = extractelement <4 x i8> %vec2, i64 2
- %cv2e2 = sext i8 %v2e2 to i32
- %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %add1 = add i32 %mul1, %acc
- %add2 = add i32 %add1, %mul2
- %add3 = add i32 %add2, %mul3
- store i32 %add3, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-define amdgpu_kernel void @idot4_acc32_opt(ptr addrspace(1) %src1,
-; GFX7-LABEL: idot4_acc32_opt:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, s3
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5]
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_mov_b32 s2, -1
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_bfe_i32 v3, v2, 8, 8
-; GFX7-NEXT: v_bfe_i32 v1, v2, 0, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_i32 v6, v0, 8, 8
-; GFX7-NEXT: v_bfe_i32 v5, v0, 0, 8
-; GFX7-NEXT: v_mul_i32_i24_e32 v3, v3, v6
-; GFX7-NEXT: v_bfe_i32 v4, v2, 16, 8
-; GFX7-NEXT: v_bfe_i32 v7, v0, 16, 8
-; GFX7-NEXT: v_mad_i32_i24 v1, v1, v5, v3
-; GFX7-NEXT: v_ashrrev_i32_e32 v2, 24, v2
-; GFX7-NEXT: v_ashrrev_i32_e32 v0, 24, v0
-; GFX7-NEXT: v_mad_i32_i24 v1, v4, v7, v1
-; GFX7-NEXT: v_mad_i32_i24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: idot4_acc32_opt:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v2, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_bfe_i32 v4, v3, 0, 8
-; GFX8-NEXT: v_bfe_i32 v7, v3, 16, 8
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_bfe_i32 v5, v2, 0, 8
-; GFX8-NEXT: v_mul_i32_i24_sdwa v6, sext(v3), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX8-NEXT: v_bfe_i32 v8, v2, 16, 8
-; GFX8-NEXT: v_mad_i32_i24 v4, v4, v5, v6
-; GFX8-NEXT: v_ashrrev_i32_e32 v3, 24, v3
-; GFX8-NEXT: v_ashrrev_i32_e32 v2, 24, v2
-; GFX8-NEXT: v_mad_i32_i24 v4, v7, v8, v4
-; GFX8-NEXT: v_mad_i32_i24 v2, v3, v2, v4
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: idot4_acc32_opt:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_bfe_i32 v3, v1, 0, 8
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_bfe_i32 v4, v2, 0, 8
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v5, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v6, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
-; GFX9-NODL-NEXT: v_mad_i32_i24 v2, v3, v4, v5
-; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v6, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: idot4_acc32_opt:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_dot4_i32_i8 v1, v1, v2, 0
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: idot4_acc32_opt:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_dot4c_i32_i8_e32 v0, v1, v2
-; GFX10-DL-NEXT: global_store_dword v3, v0, s[0:1]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc32_opt:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_dot4_i32_iu8 v0, v1, v0, 0
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = sext i8 %v1e0 to i32
- %v2e0 = extractelement <4 x i8> %vec2, i64 0
- %cv2e0 = sext i8 %v2e0 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = sext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = sext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v1e2 = extractelement <4 x i8> %vec1, i64 2
- %cv1e2 = sext i8 %v1e2 to i32
- %v2e2 = extractelement <4 x i8> %vec2, i64 2
- %cv2e2 = sext i8 %v2e2 to i32
- %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2
-
- %v1e3 = extractelement <4 x i8> %vec1, i64 3
- %cv1e3 = sext i8 %v1e3 to i32
- %v2e3 = extractelement <4 x i8> %vec2, i64 3
- %cv2e3 = sext i8 %v2e3 to i32
- %mul4 = mul nuw nsw i32 %cv1e3, %cv2e3
-
- %add2 = add i32 %mul1, %mul2
- %add3 = add i32 %add2, %mul3
- %add4 = add i32 %add3, %mul4
- store i32 %add4, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-define amdgpu_kernel void @idot4_acc32_3src(ptr addrspace(1) %src1,
-; GFX7-LABEL: idot4_acc32_3src:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
-; GFX7-NEXT: s_mov_b32 s11, 0xf000
-; GFX7-NEXT: s_mov_b32 s14, 0
-; GFX7-NEXT: s_mov_b32 s15, s11
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[12:13], s[0:1]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[2:3]
-; GFX7-NEXT: buffer_load_dword v3, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[4:5]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX7-NEXT: s_mov_b32 s10, -1
-; GFX7-NEXT: s_mov_b32 s8, s6
-; GFX7-NEXT: s_mov_b32 s9, s7
-; GFX7-NEXT: s_waitcnt vmcnt(2)
-; GFX7-NEXT: v_bfe_i32 v1, v2, 0, 8
-; GFX7-NEXT: v_bfe_i32 v4, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_bfe_i32 v3, v3, 8, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_i32_i24 v1, v1, v1, s0
-; GFX7-NEXT: v_bfe_i32 v5, v2, 16, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_i32 v6, v0, 16, 8
-; GFX7-NEXT: v_mad_i32_i24 v1, v4, v3, v1
-; GFX7-NEXT: v_ashrrev_i32_e32 v2, 24, v2
-; GFX7-NEXT: v_ashrrev_i32_e32 v0, 24, v0
-; GFX7-NEXT: v_mad_i32_i24 v1, v5, v6, v1
-; GFX7-NEXT: v_mad_i32_i24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[8:11], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: idot4_acc32_3src:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v4, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(2)
-; GFX8-NEXT: v_bfe_i32 v1, v3, 0, 8
-; GFX8-NEXT: v_bfe_i32 v2, v3, 8, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_i32_i24 v1, v1, v1, s0
-; GFX8-NEXT: v_bfe_i32 v5, v3, 16, 8
-; GFX8-NEXT: v_ashrrev_i32_e32 v3, 24, v3
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_bfe_i32 v4, v4, 8, 8
-; GFX8-NEXT: v_mad_i32_i24 v1, v2, v4, v1
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_bfe_i32 v6, v0, 16, 8
-; GFX8-NEXT: v_ashrrev_i32_e32 v0, 24, v0
-; GFX8-NEXT: v_mad_i32_i24 v1, v5, v6, v1
-; GFX8-NEXT: v_mad_i32_i24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: idot4_acc32_3src:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[0:1]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX9-NODL-NEXT: global_load_dword v3, v0, s[4:5]
-; GFX9-NODL-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v4, sext(v1), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v2, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v5, sext(v1), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_add3_u32 v2, v4, s0, v2
-; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v5, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[6:7]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: idot4_acc32_3src:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[2:3]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v3, v0, s[0:1]
-; GFX9-DL-NEXT: s_load_dword s1, s[6:7], 0x0
-; GFX9-DL-NEXT: s_mov_b32 s0, 0x706010c
-; GFX9-DL-NEXT: s_mov_b32 s2, 0xc0c0c00
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v1, v2, v1, s0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v3, v3, s2
-; GFX9-DL-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_i32_i8 v1, v3, v1, s1
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[6:7]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: idot4_acc32_3src:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x2
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[2:3]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v3, v0, s[0:1]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
-; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v0, v2, v1, 0x706010c
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v1, v3, v3, 0xc0c0c00
-; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-DL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_mov_b32_e32 v1, s0
-; GFX10-DL-NEXT: v_dot4c_i32_i8_e32 v1, v3, v0
-; GFX10-DL-NEXT: global_store_dword v2, v1, s[6:7]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc32_3src:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b256 s[0:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x2
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[2:3]
-; GFX11-DL-NEXT: global_load_b32 v2, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[0:1]
-; GFX11-DL-NEXT: s_load_b32 s0, s[6:7], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v1, v2, v1, 0x706010c
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v2, v0, v0, 0xc0c0c00
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-DL-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: v_dot4_i32_iu8 v0, v0, v1, s0
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[6:7]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) %src3,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
- %gep3 = getelementptr <4 x i8>, ptr addrspace(1) %src3, i32 %idx
- %vec3 = load <4 x i8>, ptr addrspace(1) %gep3
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = sext i8 %v1e0 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv1e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = sext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = sext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v1e2 = extractelement <4 x i8> %vec1, i64 2
- %cv1e2 = sext i8 %v1e2 to i32
- %v3e2 = extractelement <4 x i8> %vec3, i64 2
- %cv3e2 = sext i8 %v3e2 to i32
- %mul3 = mul nuw nsw i32 %cv1e2, %cv3e2
-
- %v1e3 = extractelement <4 x i8> %vec1, i64 3
- %cv1e3 = sext i8 %v1e3 to i32
- %v3e3 = extractelement <4 x i8> %vec3, i64 3
- %cv3e3 = sext i8 %v3e3 to i32
- %mul4 = mul nuw nsw i32 %cv1e3, %cv3e3
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %add1 = add i32 %mul1, %acc
- %add2 = add i32 %add1, %mul2
- %add3 = add i32 %add2, %mul3
- %add4 = add i32 %add3, %mul4
- store i32 %add4, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-define amdgpu_kernel void @idot4_acc32_3src_3ele(ptr addrspace(1) %src1,
-; GFX7-LABEL: idot4_acc32_3src_3ele:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
-; GFX7-NEXT: s_mov_b32 s11, 0xf000
-; GFX7-NEXT: s_mov_b32 s14, 0
-; GFX7-NEXT: s_mov_b32 s15, s11
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[12:13], s[0:1]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[2:3]
-; GFX7-NEXT: buffer_load_dword v3, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[4:5]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX7-NEXT: s_mov_b32 s10, -1
-; GFX7-NEXT: s_mov_b32 s8, s6
-; GFX7-NEXT: s_mov_b32 s9, s7
-; GFX7-NEXT: s_waitcnt vmcnt(2)
-; GFX7-NEXT: v_bfe_i32 v1, v2, 0, 8
-; GFX7-NEXT: v_bfe_i32 v4, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_bfe_i32 v3, v3, 8, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_i32_i24 v1, v1, v1, s0
-; GFX7-NEXT: v_bfe_i32 v2, v2, 16, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_i32 v0, v0, 16, 8
-; GFX7-NEXT: v_mad_i32_i24 v1, v4, v3, v1
-; GFX7-NEXT: v_mad_i32_i24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[8:11], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: idot4_acc32_3src_3ele:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v4, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(2)
-; GFX8-NEXT: v_bfe_i32 v1, v3, 0, 8
-; GFX8-NEXT: v_bfe_i32 v2, v3, 8, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_i32_i24 v1, v1, v1, s0
-; GFX8-NEXT: v_bfe_i32 v3, v3, 16, 8
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_bfe_i32 v4, v4, 8, 8
-; GFX8-NEXT: v_mad_i32_i24 v1, v2, v4, v1
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_bfe_i32 v0, v0, 16, 8
-; GFX8-NEXT: v_mad_i32_i24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: idot4_acc32_3src_3ele:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[0:1]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX9-NODL-NEXT: global_load_dword v3, v0, s[4:5]
-; GFX9-NODL-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NODL-NEXT: v_bfe_i32 v4, v1, 0, 8
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v2, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_mad_i32_i24 v3, v4, v4, s0
-; GFX9-NODL-NEXT: v_add3_u32 v1, v3, v2, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[6:7]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: idot4_acc32_3src_3ele:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[2:3]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v3, v0, s[0:1]
-; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0
-; GFX9-DL-NEXT: s_mov_b32 s0, 0xc06010c
-; GFX9-DL-NEXT: s_mov_b32 s1, 0xc0c0c00
-; GFX9-DL-NEXT: s_mov_b32 s2, 0xc020100
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v1, v2, v1, s0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v3, v3, s1
-; GFX9-DL-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX9-DL-NEXT: v_perm_b32 v2, v3, v3, s2
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_i32_i8 v1, v2, v1, s3
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[6:7]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: idot4_acc32_3src_3ele:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x2
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[2:3]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v3, v0, s[0:1]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
-; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v0, v2, v1, 0xc06010c
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v1, v3, v3, 0xc0c0c00
-; GFX10-DL-NEXT: v_perm_b32 v2, v3, v3, 0xc020100
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-DL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_mov_b32_e32 v1, s0
-; GFX10-DL-NEXT: v_dot4c_i32_i8_e32 v1, v2, v0
-; GFX10-DL-NEXT: global_store_dword v3, v1, s[6:7]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc32_3src_3ele:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b256 s[0:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x2
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[2:3]
-; GFX11-DL-NEXT: global_load_b32 v2, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[0:1]
-; GFX11-DL-NEXT: s_load_b32 s0, s[6:7], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v1, v2, v1, 0xc06010c
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v2, v0, v0, 0xc0c0c00
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0xc020100
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-DL-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: v_dot4_i32_iu8 v0, v0, v1, s0
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[6:7]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) %src3,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
- %gep3 = getelementptr <4 x i8>, ptr addrspace(1) %src3, i32 %idx
- %vec3 = load <4 x i8>, ptr addrspace(1) %gep3
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = sext i8 %v1e0 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv1e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = sext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = sext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v1e2 = extractelement <4 x i8> %vec1, i64 2
- %cv1e2 = sext i8 %v1e2 to i32
- %v3e2 = extractelement <4 x i8> %vec3, i64 2
- %cv3e2 = sext i8 %v3e2 to i32
- %mul3 = mul nuw nsw i32 %cv1e2, %cv3e2
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %add1 = add i32 %mul1, %acc
- %add2 = add i32 %add1, %mul2
- %add3 = add i32 %add2, %mul3
- store i32 %add3, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-define amdgpu_kernel void @idot4_bad_source(ptr addrspace(1) %src1,
-; GFX7-LABEL: idot4_bad_source:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX7-NEXT: s_load_dword s12, s[0:1], 0xf
-; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, s3
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5]
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x11
-; GFX7-NEXT: s_sext_i32_i16 s5, s12
-; GFX7-NEXT: s_mov_b32 s2, -1
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v1, s4
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_bfe_i32 v3, v2, 0, 8
-; GFX7-NEXT: v_bfe_i32 v4, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_i32 v5, v0, 8, 8
-; GFX7-NEXT: v_mad_i32_i24 v1, v3, s5, v1
-; GFX7-NEXT: v_bfe_i32 v2, v2, 16, 8
-; GFX7-NEXT: v_bfe_i32 v0, v0, 16, 8
-; GFX7-NEXT: v_mad_i32_i24 v1, v4, v5, v1
-; GFX7-NEXT: v_mad_i32_i24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: idot4_bad_source:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT: s_load_dword s2, s[0:1], 0x3c
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
-; GFX8-NEXT: s_sext_i32_i16 s2, s2
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_bfe_i32 v2, v3, 0, 8
-; GFX8-NEXT: v_bfe_i32 v4, v3, 8, 8
-; GFX8-NEXT: v_mad_i32_i24 v1, v2, s2, v1
-; GFX8-NEXT: v_bfe_i32 v3, v3, 16, 8
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_bfe_i32 v5, v0, 8, 8
-; GFX8-NEXT: v_bfe_i32 v0, v0, 16, 8
-; GFX8-NEXT: v_mad_i32_i24 v1, v4, v5, v1
-; GFX8-NEXT: v_mad_i32_i24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: idot4_bad_source:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: s_load_dword s2, s[0:1], 0x3c
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: s_sext_i32_i16 s2, s2
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_load_dword s3, s[0:1], 0x0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_bfe_i32 v3, v1, 0, 8
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v4, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_mov_b32_e32 v2, s3
-; GFX9-NODL-NEXT: v_mad_i32_i24 v2, v3, s2, v2
-; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v4, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: idot4_bad_source:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-DL-NEXT: s_load_dword s2, s[0:1], 0x3c
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-DL-NEXT: s_mov_b32 s4, 0xc0c0201
-; GFX9-DL-NEXT: s_sext_i32_i16 s2, s2
-; GFX9-DL-NEXT: s_load_dword s3, s[0:1], 0x0
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_mov_b32_e32 v3, s3
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_bfe_i32 v4, v1, 0, 8
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v2, v2, s4
-; GFX9-DL-NEXT: v_mad_i32_i24 v3, v4, s2, v3
-; GFX9-DL-NEXT: v_perm_b32 v1, v1, v1, s4
-; GFX9-DL-NEXT: v_dot4_i32_i8 v1, v1, v2, v3
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: idot4_bad_source:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x3c
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX10-DL-NEXT: s_sext_i32_i16 s2, s2
-; GFX10-DL-NEXT: s_load_dword s3, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_bfe_i32 v0, v1, 0, 8
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v2, v2, v2, 0xc0c0201
-; GFX10-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc0c0201
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_mad_i32_i24 v0, v0, s2, s3
-; GFX10-DL-NEXT: v_dot4c_i32_i8_e32 v0, v1, v2
-; GFX10-DL-NEXT: global_store_dword v3, v0, s[0:1]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_bad_source:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x3c
-; GFX11-DL-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x44
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: s_sext_i32_i16 s2, s2
-; GFX11-DL-NEXT: s_load_b32 s3, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_bfe_i32 v2, v1, 0, 8
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0xc0c0201
-; GFX11-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc0c0201
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: v_mad_i32_i24 v2, v2, s2, s3
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT: v_dot4_i32_iu8 v0, v1, v0, v2
-; GFX11-DL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) %src3,
- i16 %badsource,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
- %gep3 = getelementptr <4 x i8>, ptr addrspace(1) %src3, i32 %idx
- %vec3 = load <4 x i8>, ptr addrspace(1) %gep3
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = sext i8 %v1e0 to i32
- %v2e0 = extractelement <4 x i8> %vec2, i64 0
- %other = sext i16 %badsource to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %other
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = sext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = sext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v2e2 = extractelement <4 x i8> %vec2, i64 2
- %cv2e2 = sext i8 %v2e2 to i32
- %v1e2 = extractelement <4 x i8> %vec1, i64 2
- %cv1e2 = sext i8 %v1e2 to i32
- %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2
-
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %mad1 = add i32 %mul1, %acc
- %mad2 = add i32 %mad1, %mul2
- %mad3 = add i32 %mad2, %mul3
-
- store i32 %mad3, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-
-define amdgpu_kernel void @idot4_commutative(ptr addrspace(1) %src1,
-; GFX7-LABEL: idot4_commutative:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xf
-; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, s3
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5]
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s2, -1
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_bfe_i32 v1, v2, 0, 8
-; GFX7-NEXT: v_bfe_i32 v3, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_i32 v4, v0, 0, 8
-; GFX7-NEXT: v_bfe_i32 v5, v0, 8, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_i32_i24 v1, v1, v4, s4
-; GFX7-NEXT: v_bfe_i32 v0, v0, 16, 8
-; GFX7-NEXT: v_bfe_i32 v2, v2, 16, 8
-; GFX7-NEXT: v_mad_i32_i24 v1, v3, v5, v1
-; GFX7-NEXT: v_mad_i32_i24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: idot4_commutative:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x3c
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_bfe_i32 v1, v3, 0, 8
-; GFX8-NEXT: v_bfe_i32 v4, v3, 8, 8
-; GFX8-NEXT: v_bfe_i32 v3, v3, 16, 8
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_bfe_i32 v2, v0, 0, 8
-; GFX8-NEXT: v_bfe_i32 v5, v0, 8, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_i32_i24 v1, v1, v2, s2
-; GFX8-NEXT: v_bfe_i32 v0, v0, 16, 8
-; GFX8-NEXT: v_mad_i32_i24 v1, v4, v5, v1
-; GFX8-NEXT: v_mad_i32_i24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: idot4_commutative:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x3c
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_bfe_i32 v3, v1, 0, 8
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_bfe_i32 v4, v2, 0, 8
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v5, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_mad_i32_i24 v2, v3, v4, s0
-; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v5, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: idot4_commutative:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x3c
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_mov_b32 s1, 0xc020100
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v1, v1, v1, s1
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v2, v2, s1
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_i32_i8 v1, v2, v1, s0
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: idot4_commutative:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x3c
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc020100
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v1, v2, v2, 0xc020100
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_mov_b32_e32 v2, s2
-; GFX10-DL-NEXT: v_dot4c_i32_i8_e32 v2, v1, v0
-; GFX10-DL-NEXT: global_store_dword v3, v2, s[0:1]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_commutative:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x3c
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[4:5]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc020100
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0xc020100
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT: v_dot4_i32_iu8 v0, v0, v1, s2
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) %src3,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
- %gep3 = getelementptr <4 x i8>, ptr addrspace(1) %src3, i32 %idx
- %vec3 = load <4 x i8>, ptr addrspace(1) %gep3
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = sext i8 %v1e0 to i32
- %v2e0 = extractelement <4 x i8> %vec2, i64 0
- %cv2e0 = sext i8 %v2e0 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = sext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = sext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v2e2 = extractelement <4 x i8> %vec2, i64 2
- %cv2e2 = sext i8 %v2e2 to i32
- %v1e2 = extractelement <4 x i8> %vec1, i64 2
- %cv1e2 = sext i8 %v1e2 to i32
- %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2
-
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %mad1 = add i32 %mul1, %acc
- %mad2 = add i32 %mad1, %mul2
- %mad3 = add i32 %mad2, %mul3
-
- store i32 %mad3, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-define amdgpu_kernel void @idot4_acc32_3src_3ele_src0(ptr addrspace(1) %src1,
-; GFX7-LABEL: idot4_acc32_3src_3ele_src0:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
-; GFX7-NEXT: s_mov_b32 s11, 0xf000
-; GFX7-NEXT: s_mov_b32 s14, 0
-; GFX7-NEXT: s_mov_b32 s15, s11
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[12:13], s[0:1]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[2:3]
-; GFX7-NEXT: buffer_load_dword v3, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[4:5]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX7-NEXT: s_mov_b32 s10, -1
-; GFX7-NEXT: s_mov_b32 s8, s6
-; GFX7-NEXT: s_mov_b32 s9, s7
-; GFX7-NEXT: s_waitcnt vmcnt(2)
-; GFX7-NEXT: v_bfe_i32 v1, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_bfe_i32 v2, v3, 8, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_i32_i24 v4, v2, v2, s0
-; GFX7-NEXT: v_bfe_i32 v3, v3, 16, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_i32 v0, v0, 16, 8
-; GFX7-NEXT: v_mad_i32_i24 v1, v1, v2, v4
-; GFX7-NEXT: v_mad_i32_i24 v0, v3, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[8:11], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: idot4_acc32_3src_3ele_src0:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v4, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(2)
-; GFX8-NEXT: v_bfe_i32 v2, v3, 8, 8
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_bfe_i32 v1, v4, 8, 8
-; GFX8-NEXT: v_bfe_i32 v3, v4, 16, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_i32_i24 v4, v1, v1, s0
-; GFX8-NEXT: v_mad_i32_i24 v1, v2, v1, v4
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_bfe_i32 v0, v0, 16, 8
-; GFX8-NEXT: v_mad_i32_i24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: idot4_acc32_3src_3ele_src0:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[2:3]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v3, v0, s[0:1]
-; GFX9-NODL-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NODL-NEXT: v_bfe_i32 v4, v1, 8, 8
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v2, sext(v3), v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_mad_i32_i24 v3, v4, v4, s0
-; GFX9-NODL-NEXT: v_add3_u32 v1, v3, v2, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[6:7]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: idot4_acc32_3src_3ele_src0:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[0:1]
-; GFX9-DL-NEXT: global_load_dword v3, v0, s[2:3]
-; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0
-; GFX9-DL-NEXT: s_mov_b32 s0, 0xc06010c
-; GFX9-DL-NEXT: s_mov_b32 s1, 0xc0c0c01
-; GFX9-DL-NEXT: s_mov_b32 s2, 0xc020101
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v1, v1, v2, s0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v3, v3, s1
-; GFX9-DL-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX9-DL-NEXT: v_perm_b32 v2, v3, v3, s2
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_i32_i8 v1, v2, v1, s3
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[6:7]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: idot4_acc32_3src_3ele_src0:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x2
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[0:1]
-; GFX10-DL-NEXT: global_load_dword v3, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
-; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v0, v1, v2, 0xc06010c
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v1, v3, v3, 0xc0c0c01
-; GFX10-DL-NEXT: v_perm_b32 v2, v3, v3, 0xc020101
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-DL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_mov_b32_e32 v1, s0
-; GFX10-DL-NEXT: v_dot4c_i32_i8_e32 v1, v2, v0
-; GFX10-DL-NEXT: global_store_dword v3, v1, s[6:7]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc32_3src_3ele_src0:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b256 s[0:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x2
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[2:3]
-; GFX11-DL-NEXT: s_load_b32 s0, s[6:7], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v1, v1, v2, 0xc06010c
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v2, v0, v0, 0xc0c0c01
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0xc020101
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-DL-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: v_dot4_i32_iu8 v0, v0, v1, s0
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[6:7]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) %src3,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
- %gep3 = getelementptr <4 x i8>, ptr addrspace(1) %src3, i32 %idx
- %vec3 = load <4 x i8>, ptr addrspace(1) %gep3
-
- %v2e0 = extractelement <4 x i8> %vec2, i64 1
- %cv2e0 = sext i8 %v2e0 to i32
- %mul1 = mul nuw nsw i32 %cv2e0, %cv2e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = sext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = sext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v3e2 = extractelement <4 x i8> %vec3, i64 2
- %cv3e2 = sext i8 %v3e2 to i32
- %v2e2 = extractelement <4 x i8> %vec2, i64 2
- %cv2e2 = sext i8 %v2e2 to i32
- %mul3 = mul nuw nsw i32 %cv2e2, %cv3e2
-
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %mad1 = add i32 %mul1, %acc
- %mad2 = add i32 %mad1, %mul2
- %mad3 = add i32 %mad2, %mul3
-
- store i32 %mad3, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-define amdgpu_kernel void @idot4_4src(ptr addrspace(1) %src1,
-; GFX7-LABEL: idot4_4src:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x9
-; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: s_mov_b32 s14, 0
-; GFX7-NEXT: s_mov_b32 s15, s3
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[12:13], s[4:5]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[6:7]
-; GFX7-NEXT: buffer_load_dword v3, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[8:9]
-; GFX7-NEXT: buffer_load_dword v4, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[10:11]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x11
-; GFX7-NEXT: s_mov_b32 s2, -1
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
-; GFX7-NEXT: s_waitcnt vmcnt(3)
-; GFX7-NEXT: v_bfe_i32 v1, v2, 0, 8
-; GFX7-NEXT: v_bfe_i32 v2, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(2)
-; GFX7-NEXT: v_bfe_i32 v5, v3, 0, 8
-; GFX7-NEXT: v_bfe_i32 v3, v3, 8, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_i32_i24 v1, v1, v2, s4
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_bfe_i32 v2, v4, 0, 8
-; GFX7-NEXT: v_bfe_i32 v4, v4, 8, 8
-; GFX7-NEXT: v_mad_i32_i24 v1, v5, v3, v1
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_i32 v3, v0, 0, 8
-; GFX7-NEXT: v_bfe_i32 v0, v0, 8, 8
-; GFX7-NEXT: v_mad_i32_i24 v1, v2, v4, v1
-; GFX7-NEXT: v_mad_i32_i24 v0, v3, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: idot4_4src:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v4, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s9
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s8, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v5, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s11
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s10, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(3)
-; GFX8-NEXT: v_bfe_i32 v1, v3, 0, 8
-; GFX8-NEXT: v_bfe_i32 v2, v3, 8, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_i32_i24 v1, v1, v2, s2
-; GFX8-NEXT: s_waitcnt vmcnt(2)
-; GFX8-NEXT: v_bfe_i32 v3, v4, 0, 8
-; GFX8-NEXT: v_bfe_i32 v4, v4, 8, 8
-; GFX8-NEXT: v_mad_i32_i24 v1, v3, v4, v1
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_bfe_i32 v6, v5, 0, 8
-; GFX8-NEXT: v_bfe_i32 v5, v5, 8, 8
-; GFX8-NEXT: v_mad_i32_i24 v1, v6, v5, v1
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_bfe_i32 v7, v0, 0, 8
-; GFX8-NEXT: v_bfe_i32 v0, v0, 8, 8
-; GFX8-NEXT: v_mad_i32_i24 v2, v7, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: idot4_4src:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: global_load_dword v3, v0, s[8:9]
-; GFX9-NODL-NEXT: global_load_dword v4, v0, s[10:11]
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v1, sext(v1), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v2, sext(v2), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v3, sext(v3), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_mul_i32_i24_sdwa v4, sext(v4), sext(v4) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_add3_u32 v1, v1, s2, v2
-; GFX9-NODL-NEXT: v_add3_u32 v1, v1, v3, v4
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: idot4_4src:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX9-DL-NEXT: s_mov_b32 s2, 0xc0c0501
-; GFX9-DL-NEXT: s_mov_b32 s3, 0x5010c0c
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_dword v3, v0, s[8:9]
-; GFX9-DL-NEXT: global_load_dword v4, v0, s[10:11]
-; GFX9-DL-NEXT: s_mov_b32 s4, 0xc0c0400
-; GFX9-DL-NEXT: s_load_dword s6, s[0:1], 0x0
-; GFX9-DL-NEXT: s_mov_b32 s5, 0x4000c0c
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-DL-NEXT: v_perm_b32 v5, v2, v1, s2
-; GFX9-DL-NEXT: v_perm_b32 v1, v2, v1, s4
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v6, v4, v3, s3
-; GFX9-DL-NEXT: v_perm_b32 v2, v4, v3, s5
-; GFX9-DL-NEXT: v_or_b32_e32 v3, v6, v5
-; GFX9-DL-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_i32_i8 v1, v1, v3, s6
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: idot4_4src:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x3
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX10-DL-NEXT: global_load_dword v3, v0, s[8:9]
-; GFX10-DL-NEXT: global_load_dword v4, v0, s[10:11]
-; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX10-DL-NEXT: v_perm_b32 v0, v2, v1, 0xc0c0501
-; GFX10-DL-NEXT: v_perm_b32 v1, v2, v1, 0xc0c0400
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v5, v4, v3, 0x5010c0c
-; GFX10-DL-NEXT: v_perm_b32 v2, v4, v3, 0x4000c0c
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-DL-NEXT: v_or_b32_e32 v0, v5, v0
-; GFX10-DL-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_mov_b32_e32 v2, s2
-; GFX10-DL-NEXT: v_dot4c_i32_i8_e32 v2, v1, v0
-; GFX10-DL-NEXT: global_store_dword v3, v2, s[0:1]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_4src:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b256 s[4:11], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x44
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x3
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v2, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_b32 v3, v0, s[8:9]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[10:11]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX11-DL-NEXT: v_perm_b32 v4, v2, v1, 0xc0c0501
-; GFX11-DL-NEXT: v_perm_b32 v1, v2, v1, 0xc0c0400
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v5, v0, v3, 0x5010c0c
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v3, 0x4000c0c
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-DL-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-DL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-DL-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-DL-NEXT: v_dot4_i32_iu8 v0, v0, v2, s2
-; GFX11-DL-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) %src3,
- ptr addrspace(1) %src4,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
-
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
- %gep3 = getelementptr <4 x i8>, ptr addrspace(1) %src3, i32 %idx
- %vec3 = load <4 x i8>, ptr addrspace(1) %gep3
- %gep4 = getelementptr <4 x i8>, ptr addrspace(1) %src4, i32 %idx
- %vec4 = load <4 x i8>, ptr addrspace(1) %gep4
-
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = sext i8 %v1e0 to i32
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = sext i8 %v1e1 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv1e1
-
- %v2e0 = extractelement <4 x i8> %vec2, i64 0
- %cv2e0 = sext i8 %v2e0 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = sext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv2e0, %cv2e1
-
- %v3e0 = extractelement <4 x i8> %vec3, i64 0
- %cv3e0 = sext i8 %v3e0 to i32
- %v3e1 = extractelement <4 x i8> %vec3, i64 1
- %cv3e1 = sext i8 %v3e1 to i32
- %mul3 = mul nuw nsw i32 %cv3e0, %cv3e1
-
- %v4e0 = extractelement <4 x i8> %vec4, i64 0
- %cv4e0 = sext i8 %v4e0 to i32
- %v4e1 = extractelement <4 x i8> %vec4, i64 1
- %cv4e1 = sext i8 %v4e1 to i32
- %mul4 = mul nuw nsw i32 %cv4e0, %cv4e1
-
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %mad1 = add i32 %mul1, %acc
- %mad2 = add i32 %mad1, %mul2
- %mad3 = add i32 %mad2, %mul3
- %mad4 = add i32 %mad3, %mul4
-
- store i32 %mad4, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-
declare i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/idot4u.ll b/llvm/test/CodeGen/AMDGPU/idot4u.ll
index 7fce369ff9f99da..b7821f8fd6da511 100644
--- a/llvm/test/CodeGen/AMDGPU/idot4u.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot4u.ll
@@ -5,7 +5,6 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9-DL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-DL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-DL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-DL %s
define amdgpu_kernel void @udot4_acc32(ptr addrspace(1) %src1,
; GFX7-LABEL: udot4_acc32:
@@ -128,24 +127,6 @@ define amdgpu_kernel void @udot4_acc32(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, s2
; GFX10-DL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_acc32:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, s2
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -298,14 +279,30 @@ define amdgpu_kernel void @udot4_acc16(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-DL-NEXT: s_movk_i32 s0, 0xff
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v3, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_ushort v4, v1, s[2:3]
+; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
+; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
+; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-DL-NEXT: global_load_ushort v3, v0, s[2:3]
+; GFX9-DL-NEXT: s_waitcnt vmcnt(2)
+; GFX9-DL-NEXT: v_and_b32_e32 v4, 0xff, v1
+; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX9-DL-NEXT: v_and_b32_e32 v5, 0xff, v2
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v2
+; GFX9-DL-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX9-DL-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v0, v2, v3, v4
-; GFX9-DL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v4, v5, v3
+; GFX9-DL-NEXT: v_and_b32_sdwa v8, v1, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-DL-NEXT: v_and_b32_sdwa v9, v2, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v6, v7, v3
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
+; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v8, v9, v3
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v1, v2, v3
+; GFX9-DL-NEXT: global_store_short v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm
;
; GFX10-DL-LABEL: udot4_acc16:
@@ -314,34 +311,32 @@ define amdgpu_kernel void @udot4_acc16(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-DL-NEXT: v_mov_b32_e32 v8, 0xff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
-; GFX10-DL-NEXT: global_load_ushort v4, v1, s[2:3]
+; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
+; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
+; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-DL-NEXT: global_load_ushort v3, v0, s[2:3]
+; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
+; GFX10-DL-NEXT: v_and_b32_e32 v4, 0xff, v1
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v2
+; GFX10-DL-NEXT: v_and_b32_e32 v7, 0xff, v2
+; GFX10-DL-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX10-DL-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v2, v3, v4
-; GFX10-DL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX10-DL-NEXT: v_mad_u16 v3, v4, v7, v3
+; GFX10-DL-NEXT: v_and_b32_sdwa v4, v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-DL-NEXT: v_and_b32_sdwa v7, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
+; GFX10-DL-NEXT: v_mad_u16 v3, v5, v6, v3
+; GFX10-DL-NEXT: v_mad_u16 v3, v4, v7, v3
+; GFX10-DL-NEXT: v_mad_u16 v1, v1, v2, v3
+; GFX10-DL-NEXT: global_store_short v0, v1, s[2:3]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_acc16:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v2, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_u16 v3, v1, s[0:1]
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v2, v0, v3
-; GFX11-DL-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -484,14 +479,25 @@ define amdgpu_kernel void @udot4_acc8(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: v_mov_b32_e32 v1, 0
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v3, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
+; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
+; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
+; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-DL-NEXT: global_load_ubyte v3, v0, s[2:3]
+; GFX9-DL-NEXT: s_waitcnt vmcnt(2)
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v1
+; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v2
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v8, 24, v1
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v0, v2, v3, v4
-; GFX9-DL-NEXT: global_store_byte v1, v0, s[2:3]
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v1, v2, v3
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v6, v7, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v9, 24, v2
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v4, v5, v1
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v8, v9, v1
+; GFX9-DL-NEXT: global_store_byte v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm
;
; GFX10-DL-LABEL: udot4_acc8:
@@ -506,28 +512,21 @@ define amdgpu_kernel void @udot4_acc8(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
+; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 8, v2
+; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v2, v3, v4
+; GFX10-DL-NEXT: v_mad_u16 v4, v2, v3, v4
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v4
+; GFX10-DL-NEXT: v_mad_u16 v0, v6, v7, v0
+; GFX10-DL-NEXT: v_mad_u16 v0, v2, v3, v0
; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_acc8:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v2, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_u8 v3, v1, s[0:1]
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v2, v0, v3
-; GFX11-DL-NEXT: global_store_b8 v1, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -563,6 +562,7 @@ entry:
ret void
}
+; TODO: Generate udot4?
define amdgpu_kernel void @udot2_8(ptr addrspace(1) %src1,
; GFX7-LABEL: udot2_8:
; GFX7: ; %bb.0: ; %entry
@@ -644,19 +644,19 @@ define amdgpu_kernel void @udot2_8(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_mov_b32 s0, 0xc0c0100
+; GFX9-DL-NEXT: v_mov_b32_e32 v1, 0
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: global_load_ubyte v3, v0, s[2:3]
+; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
+; GFX9-DL-NEXT: global_load_dword v3, v0, s[6:7]
+; GFX9-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
; GFX9-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-DL-NEXT: v_perm_b32 v1, v1, v1, s0
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v0, 8, v2
; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v2, v2, v2, s0
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, v3
-; GFX9-DL-NEXT: global_store_byte v0, v1, s[2:3]
+; GFX9-DL-NEXT: v_mad_legacy_u16 v2, v2, v3, v4
+; GFX9-DL-NEXT: v_mad_legacy_u16 v0, v0, v5, v2
+; GFX9-DL-NEXT: global_store_byte v1, v0, s[2:3]
; GFX9-DL-NEXT: s_endpgm
;
; GFX10-DL-LABEL: udot2_8:
@@ -665,44 +665,21 @@ define amdgpu_kernel void @udot2_8(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-DL-NEXT: global_load_ubyte v3, v0, s[2:3]
+; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
+; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
+; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX10-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc0c0100
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 8, v2
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v2, v2, v2, 0xc0c0100
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, v3
-; GFX10-DL-NEXT: global_store_byte v0, v1, s[2:3]
+; GFX10-DL-NEXT: v_mad_u16 v2, v2, v3, v4
+; GFX10-DL-NEXT: v_mad_u16 v0, v0, v5, v2
+; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot2_8:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_u8 v3, v2, s[0:1]
-; GFX11-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX11-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc0c0100
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0xc0c0100
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, v3
-; GFX11-DL-NEXT: global_store_b8 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -826,14 +803,25 @@ define amdgpu_kernel void @udot4_CommutationInsideMAD(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: v_mov_b32_e32 v1, 0
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v3, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
+; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
+; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
+; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-DL-NEXT: global_load_ubyte v3, v0, s[2:3]
+; GFX9-DL-NEXT: s_waitcnt vmcnt(2)
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v1
+; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v2
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v8, 24, v1
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v0, v3, v2, v4
-; GFX9-DL-NEXT: global_store_byte v1, v0, s[2:3]
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v2, v1, v3
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v7, v6, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v9, 24, v2
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v5, v4, v1
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v9, v8, v1
+; GFX9-DL-NEXT: global_store_byte v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm
;
; GFX10-DL-LABEL: udot4_CommutationInsideMAD:
@@ -848,28 +836,21 @@ define amdgpu_kernel void @udot4_CommutationInsideMAD(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
+; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 8, v2
+; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v3, v2, v4
+; GFX10-DL-NEXT: v_mad_u16 v4, v3, v2, v4
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; GFX10-DL-NEXT: v_mad_u16 v0, v5, v0, v4
+; GFX10-DL-NEXT: v_mad_u16 v0, v7, v6, v0
+; GFX10-DL-NEXT: v_mad_u16 v0, v3, v2, v0
; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_CommutationInsideMAD:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v2, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_u8 v3, v1, s[0:1]
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v0, v2, v3
-; GFX11-DL-NEXT: global_store_b8 v1, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -905,6 +886,7 @@ entry:
ret void
}
+; TODO: Support commutation accross the adds.
define amdgpu_kernel void @udot4_CommutationAccrossMADs(ptr addrspace(1) %src1,
; GFX7-LABEL: udot4_CommutationAccrossMADs:
; GFX7: ; %bb.0: ; %entry
@@ -1004,14 +986,25 @@ define amdgpu_kernel void @udot4_CommutationAccrossMADs(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: v_mov_b32_e32 v1, 0
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v3, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
+; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
+; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
+; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-DL-NEXT: global_load_ubyte v3, v0, s[2:3]
+; GFX9-DL-NEXT: s_waitcnt vmcnt(2)
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v1
+; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v2
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v0, v3, v2, v4
-; GFX9-DL-NEXT: global_store_byte v1, v0, s[2:3]
+; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v7, v6, v3
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v8, 24, v1
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v2, v1, v3
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v9, 24, v2
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v5, v4, v1
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v9, v8, v1
+; GFX9-DL-NEXT: global_store_byte v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm
;
; GFX10-DL-LABEL: udot4_CommutationAccrossMADs:
@@ -1026,28 +1019,21 @@ define amdgpu_kernel void @udot4_CommutationAccrossMADs(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
; GFX10-DL-NEXT: global_load_ubyte v4, v1, s[2:3]
+; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 8, v2
+; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v3, v2, v4
+; GFX10-DL-NEXT: v_mad_u16 v0, v5, v0, v4
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v3
+; GFX10-DL-NEXT: v_mad_u16 v0, v3, v2, v0
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; GFX10-DL-NEXT: v_mad_u16 v0, v5, v4, v0
+; GFX10-DL-NEXT: v_mad_u16 v0, v3, v2, v0
; GFX10-DL-NEXT: global_store_byte v1, v0, s[2:3]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_CommutationAccrossMADs:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v2, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_u8 v3, v1, s[0:1]
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v0, v2, v3
-; GFX11-DL-NEXT: global_store_b8 v1, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -1194,9 +1180,14 @@ define amdgpu_kernel void @udot4_multiuse_mul1(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: v_and_b32_e32 v3, 0xff, v1
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_and_b32_e32 v4, 0xff, v2
+; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
+; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v6, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
+; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
+; GFX9-DL-NEXT: v_mul_u32_u24_e32 v2, v3, v4
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-DL-NEXT: v_mad_u32_u24 v3, v3, v4, s0
-; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, v3
+; GFX9-DL-NEXT: v_add3_u32 v2, v5, v3, v2
+; GFX9-DL-NEXT: v_add3_u32 v1, v2, v6, v1
; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm
;
@@ -1214,36 +1205,17 @@ define amdgpu_kernel void @udot4_multiuse_mul1(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: v_and_b32_e32 v0, 0xff, v1
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_and_b32_e32 v3, 0xff, v2
+; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v4, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
+; GFX10-DL-NEXT: v_mul_u32_u24_e32 v5, v0, v3
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_mad_u32_u24 v0, v0, v3, s2
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v1, v2, v0
-; GFX10-DL-NEXT: global_store_dword v3, v0, s[0:1]
+; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
+; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
+; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-DL-NEXT: v_add3_u32 v0, v4, v0, v5
+; GFX10-DL-NEXT: v_add3_u32 v0, v0, v3, v1
+; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_multiuse_mul1:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_and_b32_e32 v2, 0xff, v1
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_and_b32_e32 v3, 0xff, v0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-DL-NEXT: v_mad_u32_u24 v2, v2, v3, s2
-; GFX11-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, v2
-; GFX11-DL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -1397,12 +1369,18 @@ define amdgpu_kernel void @udot4_multiuse_add1(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX9-DL-NEXT: s_load_dword s0, s[2:3], 0x0
; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: s_add_i32 s1, s0, s0
+; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX9-DL-NEXT: v_bfe_u32 v4, v1, 8, 8
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, s0
-; GFX9-DL-NEXT: v_add3_u32 v1, s1, v3, v1
+; GFX9-DL-NEXT: v_bfe_u32 v5, v2, 8, 8
+; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v6, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
+; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
+; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-DL-NEXT: v_mad_u32_u24 v2, v4, v5, s0
+; GFX9-DL-NEXT: v_add_u32_e32 v4, s0, v2
+; GFX9-DL-NEXT: v_add3_u32 v2, v2, v3, v6
+; GFX9-DL-NEXT: v_add3_u32 v1, v2, v1, v4
; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm
;
@@ -1416,41 +1394,21 @@ define amdgpu_kernel void @udot4_multiuse_add1(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
+; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX10-DL-NEXT: v_bfe_u32 v0, v1, 8, 8
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v0, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
+; GFX10-DL-NEXT: v_bfe_u32 v3, v2, 8, 8
+; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v4, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, s2
-; GFX10-DL-NEXT: s_add_i32 s2, s2, s2
-; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-DL-NEXT: v_add3_u32 v0, s2, v0, v1
-; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX10-DL-NEXT: v_mad_u32_u24 v0, v0, v3, s2
+; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
+; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
+; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, s2, v0
+; GFX10-DL-NEXT: v_add3_u32 v0, v0, v4, v3
+; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
+; GFX10-DL-NEXT: v_add3_u32 v0, v0, v1, v2
+; GFX10-DL-NEXT: global_store_dword v3, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_multiuse_add1:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_bfe_u32 v2, v1, 8, 8
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_bfe_u32 v3, v0, 8, 8
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, s2
-; GFX11-DL-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-DL-NEXT: s_add_i32 s2, s2, s2
-; GFX11-DL-NEXT: v_mul_u32_u24_e32 v2, v2, v3
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT: v_add3_u32 v0, s2, v2, v0
-; GFX11-DL-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -1606,14 +1564,30 @@ define amdgpu_kernel void @notdot4_mixedtypes(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-DL-NEXT: s_movk_i32 s0, 0xff
; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v3, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_ushort v4, v1, s[2:3]
+; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
+; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
+; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-DL-NEXT: global_load_ushort v3, v0, s[2:3]
+; GFX9-DL-NEXT: s_waitcnt vmcnt(2)
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v1
+; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v2
+; GFX9-DL-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX9-DL-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX9-DL-NEXT: v_bfe_i32 v4, v1, 0, 8
+; GFX9-DL-NEXT: v_bfe_i32 v5, v2, 0, 8
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v0, v2, v3, v4
-; GFX9-DL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v6, v7, v3
+; GFX9-DL-NEXT: v_and_b32_sdwa v8, v1, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-DL-NEXT: v_and_b32_sdwa v9, v2, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v4, v5, v3
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
+; GFX9-DL-NEXT: v_mad_legacy_u16 v3, v8, v9, v3
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v1, v2, v3
+; GFX9-DL-NEXT: global_store_short v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm
;
; GFX10-DL-LABEL: notdot4_mixedtypes:
@@ -1622,34 +1596,32 @@ define amdgpu_kernel void @notdot4_mixedtypes(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-DL-NEXT: v_mov_b32_e32 v7, 0xff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v3, v0, s[6:7]
-; GFX10-DL-NEXT: global_load_ushort v4, v1, s[2:3]
+; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
+; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
+; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-DL-NEXT: global_load_ushort v3, v0, s[2:3]
+; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v1
+; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v2
+; GFX10-DL-NEXT: v_bfe_i32 v6, v1, 0, 8
+; GFX10-DL-NEXT: v_bfe_i32 v8, v2, 0, 8
+; GFX10-DL-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX10-DL-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v2, v3, v4
-; GFX10-DL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX10-DL-NEXT: v_mad_u16 v3, v4, v5, v3
+; GFX10-DL-NEXT: v_and_b32_sdwa v4, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-DL-NEXT: v_and_b32_sdwa v5, v2, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 24, v2
+; GFX10-DL-NEXT: v_mad_u16 v3, v6, v8, v3
+; GFX10-DL-NEXT: v_mad_u16 v3, v4, v5, v3
+; GFX10-DL-NEXT: v_mad_u16 v1, v1, v2, v3
+; GFX10-DL-NEXT: global_store_short v0, v1, s[2:3]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: notdot4_mixedtypes:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v2, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_u16 v3, v1, s[0:1]
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v2, v0, v3
-; GFX11-DL-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -1693,7 +1665,7 @@ entry:
ret void
}
-; TODO: cleanup s_lshr_b32
+; TODO: cleanup s_lshr_b32 and support this pattern.
define amdgpu_kernel void @udot4_acc32_vecMul(ptr addrspace(1) %src1,
; GFX7-LABEL: udot4_acc32_vecMul:
; GFX7: ; %bb.0: ; %entry
@@ -1795,8 +1767,14 @@ define amdgpu_kernel void @udot4_acc32_vecMul(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
; GFX9-DL-NEXT: s_load_dword s0, s[2:3], 0x0
; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, s0
+; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
+; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v4, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
+; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
+; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
+; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-DL-NEXT: v_add3_u32 v2, v3, s0, v4
+; GFX9-DL-NEXT: v_add3_u32 v1, v2, v5, v1
; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
; GFX9-DL-NEXT: s_endpgm
;
@@ -1809,30 +1787,22 @@ define amdgpu_kernel void @udot4_acc32_vecMul(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0xffff
; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, s2
-; GFX10-DL-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX10-DL-NEXT: v_and_b32_sdwa v3, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
+; GFX10-DL-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v4, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX10-DL-NEXT: v_mul_u32_u24_e32 v0, v3, v0
+; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
+; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
+; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-DL-NEXT: v_add3_u32 v0, v4, s2, v0
+; GFX10-DL-NEXT: v_add3_u32 v0, v0, v3, v1
+; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_acc32_vecMul:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, s2
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -2046,51 +2016,6 @@ define amdgpu_kernel void @udot4_acc16_vecMul(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v3
; GFX10-DL-NEXT: global_store_short v0, v1, s[0:1]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_acc16_vecMul:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v7, 0xff, v1
-; GFX11-DL-NEXT: global_load_u16 v3, v2, s[0:1]
-; GFX11-DL-NEXT: v_lshrrev_b16 v4, 8, v1
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_lshrrev_b16 v5, 8, v0
-; GFX11-DL-NEXT: v_and_b32_e32 v6, 0xff, v0
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-DL-NEXT: v_perm_b32 v4, v4, v7, 0x5040100
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v1, 24, v1
-; GFX11-DL-NEXT: v_perm_b32 v5, v5, v6, 0x5040100
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v0, 24, v0
-; GFX11-DL-NEXT: v_and_b32_e32 v6, 0xff, v9
-; GFX11-DL-NEXT: v_and_b32_e32 v7, 0xff, v8
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v6, 0x5040100
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-NEXT: v_perm_b32 v1, v1, v7, 0x5040100
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v4
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-DL-NEXT: v_pk_mul_lo_u16 v0, v1, v0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_add_nc_u16 v3, v4, v3
-; GFX11-DL-NEXT: v_add_nc_u16 v1, v3, v5
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-DL-NEXT: v_add_nc_u16 v0, v1, v0
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT: v_add_nc_u16 v0, v0, v3
-; GFX11-DL-NEXT: global_store_b16 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -2283,53 +2208,6 @@ define amdgpu_kernel void @udot4_acc8_vecMul(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v2
; GFX10-DL-NEXT: global_store_byte v0, v1, s[0:1]
; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_acc8_vecMul:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_u8 v3, v2, s[0:1]
-; GFX11-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v5, 24, v1
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v6, 24, v0
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-DL-NEXT: v_lshrrev_b16 v8, 8, v1
-; GFX11-DL-NEXT: v_lshrrev_b16 v9, 8, v0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_mad_u16 v0, v1, v0, v3
-; GFX11-DL-NEXT: v_mul_lo_u16 v5, v5, v6
-; GFX11-DL-NEXT: v_mul_lo_u16 v6, v4, v7
-; GFX11-DL-NEXT: v_mul_lo_u16 v8, v8, v9
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-DL-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-NEXT: v_lshlrev_b16 v8, 8, v8
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v1, 8, v5
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-NEXT: v_or_b32_e32 v6, v6, v5
-; GFX11-DL-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-DL-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v6
-; GFX11-DL-NEXT: v_add_nc_u16 v0, v0, v6
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-NEXT: v_mad_u16 v0, v4, v7, v0
-; GFX11-DL-NEXT: v_add_nc_u16 v0, v0, v1
-; GFX11-DL-NEXT: global_store_b8 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
ptr addrspace(1) nocapture %dst) {
entry:
@@ -2355,2229 +2233,4 @@ entry:
ret void
}
-define amdgpu_kernel void @idot4_acc32_2ele(ptr addrspace(1) %src1,
-; GFX7-LABEL: idot4_acc32_2ele:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, s3
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5]
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s2, -1
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-NEXT: v_bfe_u32 v2, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v0
-; GFX7-NEXT: v_bfe_u32 v0, v0, 8, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v1, v1, v3, s4
-; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: idot4_acc32_2ele:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-NEXT: v_bfe_u32 v3, v3, 8, 8
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v0
-; GFX8-NEXT: v_bfe_u32 v0, v0, 8, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v1, v1, v2, s2
-; GFX8-NEXT: v_mad_u32_u24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: idot4_acc32_2ele:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_add3_u32 v1, v3, s0, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: idot4_acc32_2ele:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_mov_b32 s1, 0xc0c0100
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v1, v1, v1, s1
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v2, v2, s1
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v2, v1, s0
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: idot4_acc32_2ele:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc0c0100
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v1, v2, v2, 0xc0c0100
-; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, s2
-; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc32_2ele:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[4:5]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc0c0100
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0xc0c0100
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v0, v1, s2
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = zext i8 %v1e0 to i32
- %v2e0 = extractelement <4 x i8> %vec2, i64 0
- %cv2e0 = zext i8 %v2e0 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = zext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = zext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %add1 = add i32 %mul1, %acc
- %add2 = add i32 %add1, %mul2
- store i32 %add2, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-define amdgpu_kernel void @idot4_acc32_3ele(ptr addrspace(1) %src1,
-; GFX7-LABEL: idot4_acc32_3ele:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, s3
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5]
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s2, -1
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-NEXT: v_bfe_u32 v3, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0
-; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v1, v1, v4, s4
-; GFX7-NEXT: v_bfe_u32 v2, v2, 16, 8
-; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_mad_u32_u24 v1, v3, v5, v1
-; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: idot4_acc32_3ele:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-NEXT: v_bfe_u32 v4, v3, 8, 8
-; GFX8-NEXT: v_bfe_u32 v3, v3, 16, 8
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v0
-; GFX8-NEXT: v_bfe_u32 v5, v0, 8, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v1, v1, v2, s2
-; GFX8-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX8-NEXT: v_mad_u32_u24 v1, v4, v5, v1
-; GFX8-NEXT: v_mad_u32_u24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: idot4_acc32_3ele:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_and_b32_e32 v3, 0xff, v1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_and_b32_e32 v4, 0xff, v2
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_mad_u32_u24 v2, v3, v4, s0
-; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v5, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: idot4_acc32_3ele:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_mov_b32 s1, 0xc020100
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v1, v1, v1, s1
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v2, v2, s1
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v2, v1, s0
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: idot4_acc32_3ele:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc020100
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v1, v2, v2, 0xc020100
-; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, s2
-; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc32_3ele:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[4:5]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc020100
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0xc020100
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v0, v1, s2
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = zext i8 %v1e0 to i32
- %v2e0 = extractelement <4 x i8> %vec2, i64 0
- %cv2e0 = zext i8 %v2e0 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = zext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = zext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v1e2 = extractelement <4 x i8> %vec1, i64 2
- %cv1e2 = zext i8 %v1e2 to i32
- %v2e2 = extractelement <4 x i8> %vec2, i64 2
- %cv2e2 = zext i8 %v2e2 to i32
- %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %add1 = add i32 %mul1, %acc
- %add2 = add i32 %add1, %mul2
- %add3 = add i32 %add2, %mul3
- store i32 %add3, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-define amdgpu_kernel void @idot4_acc32_3ele_permuted(ptr addrspace(1) %src1,
-; GFX7-LABEL: idot4_acc32_3ele_permuted:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, s3
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5]
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s2, -1
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v2
-; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v2
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v0
-; GFX7-NEXT: v_and_b32_e32 v5, 0xff, v0
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v1, v1, v4, s4
-; GFX7-NEXT: v_bfe_u32 v2, v2, 16, 8
-; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_mad_u32_u24 v1, v3, v5, v1
-; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: idot4_acc32_3ele_permuted:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 24, v3
-; GFX8-NEXT: v_and_b32_e32 v4, 0xff, v3
-; GFX8-NEXT: v_bfe_u32 v3, v3, 16, 8
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 24, v0
-; GFX8-NEXT: v_and_b32_e32 v5, 0xff, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v1, v1, v2, s2
-; GFX8-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX8-NEXT: v_mad_u32_u24 v1, v4, v5, v1
-; GFX8-NEXT: v_mad_u32_u24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: idot4_acc32_3ele_permuted:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v3, 24, v1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v4, 24, v2
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_mad_u32_u24 v2, v3, v4, s0
-; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v5, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: idot4_acc32_3ele_permuted:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_mov_b32 s1, 0xc020003
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v1, v1, v1, s1
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v2, v2, s1
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v2, v1, s0
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: idot4_acc32_3ele_permuted:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc020003
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v1, v2, v2, 0xc020003
-; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, s2
-; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc32_3ele_permuted:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[4:5]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc020003
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0xc020003
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v0, v1, s2
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 3
- %cv1e0 = zext i8 %v1e0 to i32
- %v2e0 = extractelement <4 x i8> %vec2, i64 3
- %cv2e0 = zext i8 %v2e0 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 0
- %cv1e1 = zext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 0
- %cv2e1 = zext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v1e2 = extractelement <4 x i8> %vec1, i64 2
- %cv1e2 = zext i8 %v1e2 to i32
- %v2e2 = extractelement <4 x i8> %vec2, i64 2
- %cv2e2 = zext i8 %v2e2 to i32
- %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %add1 = add i32 %mul1, %acc
- %add2 = add i32 %add1, %mul2
- %add3 = add i32 %add2, %mul3
- store i32 %add3, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-
-define amdgpu_kernel void @idot4_acc32_opt(ptr addrspace(1) %src1,
-; GFX7-LABEL: idot4_acc32_opt:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, s3
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5]
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_mov_b32 s2, -1
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_bfe_u32 v3, v2, 8, 8
-; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
-; GFX7-NEXT: v_and_b32_e32 v5, 0xff, v0
-; GFX7-NEXT: v_mul_u32_u24_e32 v3, v3, v6
-; GFX7-NEXT: v_bfe_u32 v4, v2, 16, 8
-; GFX7-NEXT: v_bfe_u32 v7, v0, 16, 8
-; GFX7-NEXT: v_mad_u32_u24 v1, v1, v5, v3
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v2
-; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v0
-; GFX7-NEXT: v_mad_u32_u24 v1, v4, v7, v1
-; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: idot4_acc32_opt:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v2, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v4, 0xff, v3
-; GFX8-NEXT: v_bfe_u32 v7, v3, 16, 8
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v5, 0xff, v2
-; GFX8-NEXT: v_mul_u32_u24_sdwa v6, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX8-NEXT: v_bfe_u32 v8, v2, 16, 8
-; GFX8-NEXT: v_mad_u32_u24 v4, v4, v5, v6
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 24, v3
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 24, v2
-; GFX8-NEXT: v_mad_u32_u24 v4, v7, v8, v4
-; GFX8-NEXT: v_mad_u32_u24 v2, v3, v2, v4
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: idot4_acc32_opt:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_and_b32_e32 v3, 0xff, v1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_and_b32_e32 v4, 0xff, v2
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v6, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
-; GFX9-NODL-NEXT: v_mad_u32_u24 v2, v3, v4, v5
-; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v6, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: idot4_acc32_opt:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, 0
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: idot4_acc32_opt:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, 0
-; GFX10-DL-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: idot4_acc32_opt:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, 0
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = zext i8 %v1e0 to i32
- %v2e0 = extractelement <4 x i8> %vec2, i64 0
- %cv2e0 = zext i8 %v2e0 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = zext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = zext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v1e2 = extractelement <4 x i8> %vec1, i64 2
- %cv1e2 = zext i8 %v1e2 to i32
- %v2e2 = extractelement <4 x i8> %vec2, i64 2
- %cv2e2 = zext i8 %v2e2 to i32
- %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2
-
- %v1e3 = extractelement <4 x i8> %vec1, i64 3
- %cv1e3 = zext i8 %v1e3 to i32
- %v2e3 = extractelement <4 x i8> %vec2, i64 3
- %cv2e3 = zext i8 %v2e3 to i32
- %mul4 = mul nuw nsw i32 %cv1e3, %cv2e3
-
- %add2 = add i32 %mul1, %mul2
- %add3 = add i32 %add2, %mul3
- %add4 = add i32 %add3, %mul4
- store i32 %add4, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-define amdgpu_kernel void @udot4_acc32_3src(ptr addrspace(1) %src1,
-; GFX7-LABEL: udot4_acc32_3src:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
-; GFX7-NEXT: s_mov_b32 s11, 0xf000
-; GFX7-NEXT: s_mov_b32 s14, 0
-; GFX7-NEXT: s_mov_b32 s15, s11
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[12:13], s[0:1]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[2:3]
-; GFX7-NEXT: buffer_load_dword v3, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[4:5]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX7-NEXT: s_mov_b32 s10, -1
-; GFX7-NEXT: s_mov_b32 s8, s6
-; GFX7-NEXT: s_mov_b32 s9, s7
-; GFX7-NEXT: s_waitcnt vmcnt(2)
-; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-NEXT: v_bfe_u32 v4, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_bfe_u32 v3, v3, 8, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v1, v1, v1, s0
-; GFX7-NEXT: v_bfe_u32 v5, v2, 16, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v6, v0, 16, 8
-; GFX7-NEXT: v_mad_u32_u24 v1, v4, v3, v1
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v2
-; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v0
-; GFX7-NEXT: v_mad_u32_u24 v1, v5, v6, v1
-; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[8:11], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: udot4_acc32_3src:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v4, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(2)
-; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-NEXT: v_bfe_u32 v2, v3, 8, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v1, v1, v1, s0
-; GFX8-NEXT: v_bfe_u32 v5, v3, 16, 8
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 24, v3
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_bfe_u32 v4, v4, 8, 8
-; GFX8-NEXT: v_mad_u32_u24 v1, v2, v4, v1
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_bfe_u32 v6, v0, 16, 8
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 24, v0
-; GFX8-NEXT: v_mad_u32_u24 v1, v5, v6, v1
-; GFX8-NEXT: v_mad_u32_u24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: udot4_acc32_3src:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[0:1]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX9-NODL-NEXT: global_load_dword v3, v0, s[4:5]
-; GFX9-NODL-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v4, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v2, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v5, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_add3_u32 v2, v4, s0, v2
-; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v5, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[6:7]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: udot4_acc32_3src:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[2:3]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v3, v0, s[0:1]
-; GFX9-DL-NEXT: s_load_dword s1, s[6:7], 0x0
-; GFX9-DL-NEXT: s_mov_b32 s0, 0x706010c
-; GFX9-DL-NEXT: s_mov_b32 s2, 0xc0c0c00
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v1, v2, v1, s0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v3, v3, s2
-; GFX9-DL-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v3, v1, s1
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[6:7]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: udot4_acc32_3src:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x2
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[2:3]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v3, v0, s[0:1]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
-; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v0, v2, v1, 0x706010c
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v1, v3, v3, 0xc0c0c00
-; GFX10-DL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX10-DL-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v3, v0, s0
-; GFX10-DL-NEXT: global_store_dword v1, v0, s[6:7]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_acc32_3src:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b256 s[0:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x2
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[2:3]
-; GFX11-DL-NEXT: global_load_b32 v2, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[0:1]
-; GFX11-DL-NEXT: s_load_b32 s0, s[6:7], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v1, v2, v1, 0x706010c
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v2, v0, v0, 0xc0c0c00
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-DL-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v0, v1, s0
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[6:7]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) %src3,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
- %gep3 = getelementptr <4 x i8>, ptr addrspace(1) %src3, i32 %idx
- %vec3 = load <4 x i8>, ptr addrspace(1) %gep3
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = zext i8 %v1e0 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv1e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = zext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = zext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v1e2 = extractelement <4 x i8> %vec1, i64 2
- %cv1e2 = zext i8 %v1e2 to i32
- %v3e2 = extractelement <4 x i8> %vec3, i64 2
- %cv3e2 = zext i8 %v3e2 to i32
- %mul3 = mul nuw nsw i32 %cv1e2, %cv3e2
-
- %v1e3 = extractelement <4 x i8> %vec1, i64 3
- %cv1e3 = zext i8 %v1e3 to i32
- %v3e3 = extractelement <4 x i8> %vec3, i64 3
- %cv3e3 = zext i8 %v3e3 to i32
- %mul4 = mul nuw nsw i32 %cv1e3, %cv3e3
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %mad1 = add i32 %mul1, %acc
- %mad2 = add i32 %mad1, %mul2
- %mad3 = add i32 %mad2, %mul3
- %mad4 = add i32 %mad3, %mul4
-
- store i32 %mad4, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-define amdgpu_kernel void @udot4_acc32_3src_3ele(ptr addrspace(1) %src1,
-; GFX7-LABEL: udot4_acc32_3src_3ele:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
-; GFX7-NEXT: s_mov_b32 s11, 0xf000
-; GFX7-NEXT: s_mov_b32 s14, 0
-; GFX7-NEXT: s_mov_b32 s15, s11
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[12:13], s[0:1]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[2:3]
-; GFX7-NEXT: buffer_load_dword v3, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[4:5]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX7-NEXT: s_mov_b32 s10, -1
-; GFX7-NEXT: s_mov_b32 s8, s6
-; GFX7-NEXT: s_mov_b32 s9, s7
-; GFX7-NEXT: s_waitcnt vmcnt(2)
-; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-NEXT: v_bfe_u32 v4, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_bfe_u32 v3, v3, 8, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v1, v1, v1, s0
-; GFX7-NEXT: v_bfe_u32 v2, v2, 16, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_mad_u32_u24 v1, v4, v3, v1
-; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[8:11], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: udot4_acc32_3src_3ele:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v4, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(2)
-; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-NEXT: v_bfe_u32 v2, v3, 8, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v1, v1, v1, s0
-; GFX8-NEXT: v_bfe_u32 v3, v3, 16, 8
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_bfe_u32 v4, v4, 8, 8
-; GFX8-NEXT: v_mad_u32_u24 v1, v2, v4, v1
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX8-NEXT: v_mad_u32_u24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: udot4_acc32_3src_3ele:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[0:1]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX9-NODL-NEXT: global_load_dword v3, v0, s[4:5]
-; GFX9-NODL-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NODL-NEXT: v_and_b32_e32 v4, 0xff, v1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v2, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_mad_u32_u24 v3, v4, v4, s0
-; GFX9-NODL-NEXT: v_add3_u32 v1, v3, v2, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[6:7]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: udot4_acc32_3src_3ele:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[2:3]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v3, v0, s[0:1]
-; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0
-; GFX9-DL-NEXT: s_mov_b32 s0, 0xc06010c
-; GFX9-DL-NEXT: s_mov_b32 s1, 0xc0c0c00
-; GFX9-DL-NEXT: s_mov_b32 s2, 0xc020100
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v1, v2, v1, s0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v3, v3, s1
-; GFX9-DL-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX9-DL-NEXT: v_perm_b32 v2, v3, v3, s2
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v2, v1, s3
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[6:7]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: udot4_acc32_3src_3ele:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x2
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[2:3]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v3, v0, s[0:1]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
-; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v0, v2, v1, 0xc06010c
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v1, v3, v3, 0xc0c0c00
-; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-DL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX10-DL-NEXT: v_perm_b32 v1, v3, v3, 0xc020100
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, s0
-; GFX10-DL-NEXT: global_store_dword v2, v0, s[6:7]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_acc32_3src_3ele:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b256 s[0:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x2
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[2:3]
-; GFX11-DL-NEXT: global_load_b32 v2, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[0:1]
-; GFX11-DL-NEXT: s_load_b32 s0, s[6:7], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v1, v2, v1, 0xc06010c
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v2, v0, v0, 0xc0c0c00
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0xc020100
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-DL-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v0, v1, s0
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[6:7]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) %src3,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
- %gep3 = getelementptr <4 x i8>, ptr addrspace(1) %src3, i32 %idx
- %vec3 = load <4 x i8>, ptr addrspace(1) %gep3
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = zext i8 %v1e0 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv1e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = zext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = zext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v1e2 = extractelement <4 x i8> %vec1, i64 2
- %cv1e2 = zext i8 %v1e2 to i32
- %v3e2 = extractelement <4 x i8> %vec3, i64 2
- %cv3e2 = zext i8 %v3e2 to i32
- %mul3 = mul nuw nsw i32 %cv1e2, %cv3e2
-
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %mad1 = add i32 %mul1, %acc
- %mad2 = add i32 %mad1, %mul2
- %mad3 = add i32 %mad2, %mul3
-
- store i32 %mad3, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-define amdgpu_kernel void @udot4_bad_source(ptr addrspace(1) %src1,
-; GFX7-LABEL: udot4_bad_source:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX7-NEXT: s_load_dword s12, s[0:1], 0xf
-; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, s3
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5]
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x11
-; GFX7-NEXT: s_and_b32 s5, s12, 0xffff
-; GFX7-NEXT: s_mov_b32 s2, -1
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v1, s4
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v2
-; GFX7-NEXT: v_bfe_u32 v4, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8
-; GFX7-NEXT: v_mad_u32_u24 v1, v3, s5, v1
-; GFX7-NEXT: v_bfe_u32 v2, v2, 16, 8
-; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_mad_u32_u24 v1, v4, v5, v1
-; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: udot4_bad_source:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT: s_load_dword s2, s[0:1], 0x3c
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s3, s[0:1], 0x0
-; GFX8-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v3
-; GFX8-NEXT: v_bfe_u32 v4, v3, 8, 8
-; GFX8-NEXT: v_mad_u32_u24 v1, v2, s2, v1
-; GFX8-NEXT: v_bfe_u32 v3, v3, 16, 8
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_bfe_u32 v5, v0, 8, 8
-; GFX8-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX8-NEXT: v_mad_u32_u24 v1, v4, v5, v1
-; GFX8-NEXT: v_mad_u32_u24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: udot4_bad_source:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: s_load_dword s2, s[0:1], 0x3c
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_load_dword s3, s[0:1], 0x0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_and_b32_e32 v3, 0xff, v1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v4, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_mov_b32_e32 v2, s3
-; GFX9-NODL-NEXT: v_mad_u32_u24 v2, v3, s2, v2
-; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v4, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: udot4_bad_source:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-DL-NEXT: s_load_dword s2, s[0:1], 0x3c
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-DL-NEXT: s_mov_b32 s4, 0xc0c0201
-; GFX9-DL-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX9-DL-NEXT: s_load_dword s3, s[0:1], 0x0
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_mov_b32_e32 v3, s3
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_and_b32_e32 v4, 0xff, v1
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v2, v2, s4
-; GFX9-DL-NEXT: v_mad_u32_u24 v3, v4, s2, v3
-; GFX9-DL-NEXT: v_perm_b32 v1, v1, v1, s4
-; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, v3
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: udot4_bad_source:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x3c
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX10-DL-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX10-DL-NEXT: s_load_dword s3, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_and_b32_e32 v0, 0xff, v1
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v2, v2, v2, 0xc0c0201
-; GFX10-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc0c0201
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_mad_u32_u24 v0, v0, s2, s3
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v1, v2, v0
-; GFX10-DL-NEXT: global_store_dword v3, v0, s[0:1]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_bad_source:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x3c
-; GFX11-DL-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x44
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7]
-; GFX11-DL-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX11-DL-NEXT: s_load_b32 s3, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_and_b32_e32 v2, 0xff, v1
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0xc0c0201
-; GFX11-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc0c0201
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: v_mad_u32_u24 v2, v2, s2, s3
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, v2
-; GFX11-DL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) %src3,
- i16 %badsource,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
- %gep3 = getelementptr <4 x i8>, ptr addrspace(1) %src3, i32 %idx
- %vec3 = load <4 x i8>, ptr addrspace(1) %gep3
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = zext i8 %v1e0 to i32
- %v2e0 = extractelement <4 x i8> %vec2, i64 0
- %other = zext i16 %badsource to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %other
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = zext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = zext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v2e2 = extractelement <4 x i8> %vec2, i64 2
- %cv2e2 = zext i8 %v2e2 to i32
- %v1e2 = extractelement <4 x i8> %vec1, i64 2
- %cv1e2 = zext i8 %v1e2 to i32
- %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2
-
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %mad1 = add i32 %mul1, %acc
- %mad2 = add i32 %mad1, %mul2
- %mad3 = add i32 %mad2, %mul3
-
- store i32 %mad3, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-
-define amdgpu_kernel void @udot4_commutative(ptr addrspace(1) %src1,
-; GFX7-LABEL: udot4_commutative:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xf
-; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, s3
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5]
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s2, -1
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-NEXT: v_bfe_u32 v3, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0
-; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v1, v1, v4, s4
-; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_bfe_u32 v2, v2, 16, 8
-; GFX7-NEXT: v_mad_u32_u24 v1, v3, v5, v1
-; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: udot4_commutative:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x3c
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-NEXT: v_bfe_u32 v4, v3, 8, 8
-; GFX8-NEXT: v_bfe_u32 v3, v3, 16, 8
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v0
-; GFX8-NEXT: v_bfe_u32 v5, v0, 8, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v1, v1, v2, s2
-; GFX8-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX8-NEXT: v_mad_u32_u24 v1, v4, v5, v1
-; GFX8-NEXT: v_mad_u32_u24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: udot4_commutative:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x3c
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_and_b32_e32 v3, 0xff, v1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_and_b32_e32 v4, 0xff, v2
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_mad_u32_u24 v2, v3, v4, s0
-; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v5, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: udot4_commutative:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x3c
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_mov_b32 s1, 0xc020100
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-DL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v1, v1, v1, s1
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v2, v2, s1
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v2, v1, s0
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: udot4_commutative:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x3c
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[6:7]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc020100
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v1, v2, v2, 0xc020100
-; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, s2
-; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_commutative:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x3c
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[4:5]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v1, v1, v1, 0xc020100
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0xc020100
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v0, v1, s2
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) %src3,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
- %gep3 = getelementptr <4 x i8>, ptr addrspace(1) %src3, i32 %idx
- %vec3 = load <4 x i8>, ptr addrspace(1) %gep3
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = zext i8 %v1e0 to i32
- %v2e0 = extractelement <4 x i8> %vec2, i64 0
- %cv2e0 = zext i8 %v2e0 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = zext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = zext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v2e2 = extractelement <4 x i8> %vec2, i64 2
- %cv2e2 = zext i8 %v2e2 to i32
- %v1e2 = extractelement <4 x i8> %vec1, i64 2
- %cv1e2 = zext i8 %v1e2 to i32
- %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2
-
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %mad1 = add i32 %mul1, %acc
- %mad2 = add i32 %mad1, %mul2
- %mad3 = add i32 %mad2, %mul3
-
- store i32 %mad3, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-define amdgpu_kernel void @udot4_acc32_3src_3ele_src0(ptr addrspace(1) %src1,
-; GFX7-LABEL: udot4_acc32_3src_3ele_src0:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
-; GFX7-NEXT: s_mov_b32 s11, 0xf000
-; GFX7-NEXT: s_mov_b32 s14, 0
-; GFX7-NEXT: s_mov_b32 s15, s11
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[12:13], s[0:1]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[2:3]
-; GFX7-NEXT: buffer_load_dword v3, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[4:5]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX7-NEXT: s_mov_b32 s10, -1
-; GFX7-NEXT: s_mov_b32 s8, s6
-; GFX7-NEXT: s_mov_b32 s9, s7
-; GFX7-NEXT: s_waitcnt vmcnt(2)
-; GFX7-NEXT: v_bfe_u32 v1, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_bfe_u32 v2, v3, 8, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v4, v2, v2, s0
-; GFX7-NEXT: v_bfe_u32 v3, v3, 16, 8
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX7-NEXT: v_mad_u32_u24 v1, v1, v2, v4
-; GFX7-NEXT: v_mad_u32_u24 v0, v3, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[8:11], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: udot4_acc32_3src_3ele_src0:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v4, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(2)
-; GFX8-NEXT: v_bfe_u32 v2, v3, 8, 8
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_bfe_u32 v1, v4, 8, 8
-; GFX8-NEXT: v_bfe_u32 v3, v4, 16, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v4, v1, v1, s0
-; GFX8-NEXT: v_mad_u32_u24 v1, v2, v1, v4
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX8-NEXT: v_mad_u32_u24 v2, v3, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: udot4_acc32_3src_3ele_src0:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[2:3]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v3, v0, s[0:1]
-; GFX9-NODL-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NODL-NEXT: v_bfe_u32 v4, v1, 8, 8
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v2, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_mad_u32_u24 v3, v4, v4, s0
-; GFX9-NODL-NEXT: v_add3_u32 v1, v3, v2, v1
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[6:7]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: udot4_acc32_3src_3ele_src0:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[0:1]
-; GFX9-DL-NEXT: global_load_dword v3, v0, s[2:3]
-; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0
-; GFX9-DL-NEXT: s_mov_b32 s0, 0xc06010c
-; GFX9-DL-NEXT: s_mov_b32 s1, 0xc0c0c01
-; GFX9-DL-NEXT: s_mov_b32 s2, 0xc020101
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v1, v1, v2, s0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v2, v3, v3, s1
-; GFX9-DL-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX9-DL-NEXT: v_perm_b32 v2, v3, v3, s2
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v2, v1, s3
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[6:7]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: udot4_acc32_3src_3ele_src0:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x2
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[0:1]
-; GFX10-DL-NEXT: global_load_dword v3, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
-; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v0, v1, v2, 0xc06010c
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v1, v3, v3, 0xc0c0c01
-; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-DL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX10-DL-NEXT: v_perm_b32 v1, v3, v3, 0xc020101
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, s0
-; GFX10-DL-NEXT: global_store_dword v2, v0, s[6:7]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_acc32_3src_3ele_src0:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b256 s[0:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x2
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v2, v0, s[0:1]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[2:3]
-; GFX11-DL-NEXT: s_load_b32 s0, s[6:7], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v1, v1, v2, 0xc06010c
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v2, v0, v0, 0xc0c0c01
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0xc020101
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-DL-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v0, v1, s0
-; GFX11-DL-NEXT: global_store_b32 v2, v0, s[6:7]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) %src3,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
- %gep3 = getelementptr <4 x i8>, ptr addrspace(1) %src3, i32 %idx
- %vec3 = load <4 x i8>, ptr addrspace(1) %gep3
-
- %v2e0 = extractelement <4 x i8> %vec2, i64 1
- %cv2e0 = zext i8 %v2e0 to i32
- %mul1 = mul nuw nsw i32 %cv2e0, %cv2e0
-
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = zext i8 %v1e1 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = zext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v3e2 = extractelement <4 x i8> %vec3, i64 2
- %cv3e2 = zext i8 %v3e2 to i32
- %v2e2 = extractelement <4 x i8> %vec2, i64 2
- %cv2e2 = zext i8 %v2e2 to i32
- %mul3 = mul nuw nsw i32 %cv2e2, %cv3e2
-
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %mad1 = add i32 %mul1, %acc
- %mad2 = add i32 %mad1, %mul2
- %mad3 = add i32 %mad2, %mul3
-
- store i32 %mad3, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-define amdgpu_kernel void @udot4_4src(ptr addrspace(1) %src1,
-; GFX7-LABEL: udot4_4src:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x9
-; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: s_mov_b32 s14, 0
-; GFX7-NEXT: s_mov_b32 s15, s3
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[12:13], s[4:5]
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[6:7]
-; GFX7-NEXT: buffer_load_dword v3, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[8:9]
-; GFX7-NEXT: buffer_load_dword v4, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_mov_b64 s[12:13], s[10:11]
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x11
-; GFX7-NEXT: s_mov_b32 s2, -1
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
-; GFX7-NEXT: s_waitcnt vmcnt(3)
-; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-NEXT: v_bfe_u32 v2, v2, 8, 8
-; GFX7-NEXT: s_waitcnt vmcnt(2)
-; GFX7-NEXT: v_and_b32_e32 v5, 0xff, v3
-; GFX7-NEXT: v_bfe_u32 v3, v3, 8, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v1, v1, v2, s4
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX7-NEXT: v_bfe_u32 v4, v4, 8, 8
-; GFX7-NEXT: v_mad_u32_u24 v1, v5, v3, v1
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v0
-; GFX7-NEXT: v_bfe_u32 v0, v0, 8, 8
-; GFX7-NEXT: v_mad_u32_u24 v1, v2, v4, v1
-; GFX7-NEXT: v_mad_u32_u24 v0, v3, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: udot4_4src:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v3, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v4, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s9
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s8, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v5, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v1, s11
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s10, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_dword v0, v[0:1]
-; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(3)
-; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-NEXT: v_bfe_u32 v2, v3, 8, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v1, v1, v2, s2
-; GFX8-NEXT: s_waitcnt vmcnt(2)
-; GFX8-NEXT: v_and_b32_e32 v3, 0xff, v4
-; GFX8-NEXT: v_bfe_u32 v4, v4, 8, 8
-; GFX8-NEXT: v_mad_u32_u24 v1, v3, v4, v1
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v6, 0xff, v5
-; GFX8-NEXT: v_bfe_u32 v5, v5, 8, 8
-; GFX8-NEXT: v_mad_u32_u24 v1, v6, v5, v1
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v7, 0xff, v0
-; GFX8-NEXT: v_bfe_u32 v0, v0, 8, 8
-; GFX8-NEXT: v_mad_u32_u24 v2, v7, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: udot4_4src:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-NODL-NEXT: global_load_dword v3, v0, s[8:9]
-; GFX9-NODL-NEXT: global_load_dword v4, v0, s[10:11]
-; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NODL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v2, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v3, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v4, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_1
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_add3_u32 v1, v1, s2, v2
-; GFX9-NODL-NEXT: v_add3_u32 v1, v1, v3, v4
-; GFX9-NODL-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: udot4_4src:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX9-DL-NEXT: s_mov_b32 s2, 0xc0c0501
-; GFX9-DL-NEXT: s_mov_b32 s3, 0x5010c0c
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX9-DL-NEXT: global_load_dword v3, v0, s[8:9]
-; GFX9-DL-NEXT: global_load_dword v4, v0, s[10:11]
-; GFX9-DL-NEXT: s_mov_b32 s4, 0xc0c0400
-; GFX9-DL-NEXT: s_load_dword s6, s[0:1], 0x0
-; GFX9-DL-NEXT: s_mov_b32 s5, 0x4000c0c
-; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-DL-NEXT: v_perm_b32 v5, v2, v1, s2
-; GFX9-DL-NEXT: v_perm_b32 v1, v2, v1, s4
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v6, v4, v3, s3
-; GFX9-DL-NEXT: v_perm_b32 v2, v4, v3, s5
-; GFX9-DL-NEXT: v_or_b32_e32 v3, v6, v5
-; GFX9-DL-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v1, v3, s6
-; GFX9-DL-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: udot4_4src:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x44
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x3
-; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX10-DL-NEXT: global_load_dword v3, v0, s[8:9]
-; GFX10-DL-NEXT: global_load_dword v4, v0, s[10:11]
-; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX10-DL-NEXT: v_perm_b32 v0, v2, v1, 0xc0c0501
-; GFX10-DL-NEXT: v_perm_b32 v1, v2, v1, 0xc0c0400
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v5, v4, v3, 0x5010c0c
-; GFX10-DL-NEXT: v_perm_b32 v2, v4, v3, 0x4000c0c
-; GFX10-DL-NEXT: v_or_b32_e32 v0, v5, v0
-; GFX10-DL-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, s2
-; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_4src:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b256 s[4:11], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x44
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x3
-; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v2, v0, s[6:7]
-; GFX11-DL-NEXT: global_load_b32 v3, v0, s[8:9]
-; GFX11-DL-NEXT: global_load_b32 v0, v0, s[10:11]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX11-DL-NEXT: v_perm_b32 v4, v2, v1, 0xc0c0501
-; GFX11-DL-NEXT: v_perm_b32 v1, v2, v1, 0xc0c0400
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v5, v0, v3, 0x5010c0c
-; GFX11-DL-NEXT: v_perm_b32 v0, v0, v3, 0x4000c0c
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-DL-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-DL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-DL-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v0, v2, s2
-; GFX11-DL-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) %src3,
- ptr addrspace(1) %src4,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
-
- %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
- %gep3 = getelementptr <4 x i8>, ptr addrspace(1) %src3, i32 %idx
- %vec3 = load <4 x i8>, ptr addrspace(1) %gep3
- %gep4 = getelementptr <4 x i8>, ptr addrspace(1) %src4, i32 %idx
- %vec4 = load <4 x i8>, ptr addrspace(1) %gep4
-
-
- %v1e0 = extractelement <4 x i8> %vec1, i64 0
- %cv1e0 = zext i8 %v1e0 to i32
- %v1e1 = extractelement <4 x i8> %vec1, i64 1
- %cv1e1 = zext i8 %v1e1 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv1e1
-
- %v2e0 = extractelement <4 x i8> %vec2, i64 0
- %cv2e0 = zext i8 %v2e0 to i32
- %v2e1 = extractelement <4 x i8> %vec2, i64 1
- %cv2e1 = zext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv2e0, %cv2e1
-
- %v3e0 = extractelement <4 x i8> %vec3, i64 0
- %cv3e0 = zext i8 %v3e0 to i32
- %v3e1 = extractelement <4 x i8> %vec3, i64 1
- %cv3e1 = zext i8 %v3e1 to i32
- %mul3 = mul nuw nsw i32 %cv3e0, %cv3e1
-
- %v4e0 = extractelement <4 x i8> %vec4, i64 0
- %cv4e0 = zext i8 %v4e0 to i32
- %v4e1 = extractelement <4 x i8> %vec4, i64 1
- %cv4e1 = zext i8 %v4e1 to i32
- %mul4 = mul nuw nsw i32 %cv4e0, %cv4e1
-
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %mad1 = add i32 %mul1, %acc
- %mad2 = add i32 %mad1, %mul2
- %mad3 = add i32 %mad2, %mul3
- %mad4 = add i32 %mad3, %mul4
-
- store i32 %mad4, ptr addrspace(1) %dst, align 4
- ret void
-}
-
-define amdgpu_kernel void @udot4_acc32_multi(ptr addrspace(1) %src1,
-; GFX7-LABEL: udot4_acc32_multi:
-; GFX7: ; %bb.0: ; %entry
-; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GFX7-NEXT: s_mov_b32 s3, 0xf000
-; GFX7-NEXT: s_mov_b32 s10, 0
-; GFX7-NEXT: s_mov_b32 s11, s3
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5]
-; GFX7-NEXT: v_lshlrev_b32_e32 v0, 3, v0
-; GFX7-NEXT: v_mov_b32_e32 v1, 0
-; GFX7-NEXT: s_mov_b64 s[4:5], s[6:7]
-; GFX7-NEXT: s_mov_b64 s[6:7], s[10:11]
-; GFX7-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
-; GFX7-NEXT: s_load_dword s4, s[0:1], 0x0
-; GFX7-NEXT: s_mov_b32 s2, -1
-; GFX7-NEXT: s_waitcnt vmcnt(1)
-; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0
-; GFX7-NEXT: v_bfe_u32 v7, v2, 16, 8
-; GFX7-NEXT: v_bfe_u32 v8, v0, 16, 8
-; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mad_u32_u24 v1, v1, v4, s4
-; GFX7-NEXT: v_and_b32_e32 v9, 0xff, v3
-; GFX7-NEXT: v_mad_u32_u24 v1, v7, v8, v1
-; GFX7-NEXT: v_bfe_u32 v11, v3, 16, 8
-; GFX7-NEXT: v_mad_u32_u24 v1, v9, v4, v1
-; GFX7-NEXT: v_bfe_u32 v5, v2, 8, 8
-; GFX7-NEXT: v_bfe_u32 v6, v0, 8, 8
-; GFX7-NEXT: v_mad_u32_u24 v1, v11, v8, v1
-; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v2
-; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v0
-; GFX7-NEXT: v_mad_u32_u24 v1, v5, v6, v1
-; GFX7-NEXT: v_bfe_u32 v10, v3, 8, 8
-; GFX7-NEXT: v_mad_u32_u24 v1, v2, v0, v1
-; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v3
-; GFX7-NEXT: v_mad_u32_u24 v1, v10, v6, v1
-; GFX7-NEXT: v_mad_u32_u24 v0, v3, v0, v1
-; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GFX7-NEXT: s_endpgm
-;
-; GFX8-LABEL: udot4_acc32_multi:
-; GFX8: ; %bb.0: ; %entry
-; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: v_mov_b32_e32 v3, s7
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, s6, v2
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX8-NEXT: flat_load_dword v2, v[2:3]
-; GFX8-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_and_b32_e32 v3, 0xff, v0
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v4, 0xff, v2
-; GFX8-NEXT: v_bfe_u32 v7, v0, 16, 8
-; GFX8-NEXT: v_bfe_u32 v8, v2, 16, 8
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mad_u32_u24 v3, v3, v4, s2
-; GFX8-NEXT: v_and_b32_e32 v9, 0xff, v1
-; GFX8-NEXT: v_mad_u32_u24 v3, v7, v8, v3
-; GFX8-NEXT: v_bfe_u32 v11, v1, 16, 8
-; GFX8-NEXT: v_mad_u32_u24 v3, v9, v4, v3
-; GFX8-NEXT: v_bfe_u32 v5, v0, 8, 8
-; GFX8-NEXT: v_bfe_u32 v6, v2, 8, 8
-; GFX8-NEXT: v_mad_u32_u24 v3, v11, v8, v3
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 24, v0
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 24, v2
-; GFX8-NEXT: v_mad_u32_u24 v3, v5, v6, v3
-; GFX8-NEXT: v_bfe_u32 v10, v1, 8, 8
-; GFX8-NEXT: v_mad_u32_u24 v0, v0, v2, v3
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 24, v1
-; GFX8-NEXT: v_mad_u32_u24 v0, v10, v6, v0
-; GFX8-NEXT: v_mad_u32_u24 v2, v1, v2, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: flat_store_dword v[0:1], v2
-; GFX8-NEXT: s_endpgm
-;
-; GFX9-NODL-LABEL: udot4_acc32_multi:
-; GFX9-NODL: ; %bb.0: ; %entry
-; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v2, 3, v0
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: global_load_dword v3, v2, s[6:7]
-; GFX9-NODL-NEXT: global_load_dwordx2 v[0:1], v2, s[4:5]
-; GFX9-NODL-NEXT: s_load_dword s0, s[2:3], 0x0
-; GFX9-NODL-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NODL-NEXT: v_and_b32_e32 v4, 0xff, v3
-; GFX9-NODL-NEXT: v_bfe_u32 v6, v3, 16, 8
-; GFX9-NODL-NEXT: v_bfe_u32 v5, v3, 8, 8
-; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v3, 24, v3
-; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v7, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v9, v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v8, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v4, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v5, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v6, v1, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NODL-NEXT: v_add3_u32 v3, v7, s0, v9
-; GFX9-NODL-NEXT: v_add3_u32 v3, v3, v4, v6
-; GFX9-NODL-NEXT: v_add3_u32 v0, v8, v3, v0
-; GFX9-NODL-NEXT: v_add3_u32 v0, v0, v5, v1
-; GFX9-NODL-NEXT: global_store_dword v2, v0, s[2:3]
-; GFX9-NODL-NEXT: s_endpgm
-;
-; GFX9-DL-LABEL: udot4_acc32_multi:
-; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v2, 3, v0
-; GFX9-DL-NEXT: s_mov_b32 s0, 0x6040200
-; GFX9-DL-NEXT: s_mov_b32 s1, 0x2000200
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dwordx2 v[0:1], v2, s[4:5]
-; GFX9-DL-NEXT: global_load_dword v3, v2, s[6:7]
-; GFX9-DL-NEXT: s_load_dword s5, s[2:3], 0x0
-; GFX9-DL-NEXT: s_mov_b32 s4, 0x7050301
-; GFX9-DL-NEXT: s_mov_b32 s6, 0x3010301
-; GFX9-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_perm_b32 v4, v1, v0, s0
-; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX9-DL-NEXT: v_perm_b32 v5, v3, v3, s1
-; GFX9-DL-NEXT: v_perm_b32 v0, v1, v0, s4
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v4, v5, s5
-; GFX9-DL-NEXT: v_perm_b32 v3, v3, v3, s6
-; GFX9-DL-NEXT: v_dot4_u32_u8 v0, v0, v3, v1
-; GFX9-DL-NEXT: global_store_dword v2, v0, s[2:3]
-; GFX9-DL-NEXT: s_endpgm
-;
-; GFX10-DL-LABEL: udot4_acc32_multi:
-; GFX10-DL: ; %bb.0: ; %entry
-; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v2, 3, v0
-; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: s_clause 0x1
-; GFX10-DL-NEXT: global_load_dwordx2 v[0:1], v2, s[4:5]
-; GFX10-DL-NEXT: global_load_dword v3, v2, s[6:7]
-; GFX10-DL-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_perm_b32 v2, v1, v0, 0x6040200
-; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_perm_b32 v4, v3, v3, 0x2000200
-; GFX10-DL-NEXT: v_perm_b32 v0, v1, v0, 0x7050301
-; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-DL-NEXT: v_dot4_u32_u8 v1, v2, v4, s2
-; GFX10-DL-NEXT: v_perm_b32 v2, v3, v3, 0x3010301
-; GFX10-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v0, v2, v1
-; GFX10-DL-NEXT: global_store_dword v3, v0, s[0:1]
-; GFX10-DL-NEXT: s_endpgm
-;
-; GFX11-DL-LABEL: udot4_acc32_multi:
-; GFX11-DL: ; %bb.0: ; %entry
-; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
-; GFX11-DL-NEXT: v_lshlrev_b32_e32 v2, 3, v0
-; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_clause 0x1
-; GFX11-DL-NEXT: global_load_b64 v[0:1], v2, s[4:5]
-; GFX11-DL-NEXT: global_load_b32 v2, v2, s[6:7]
-; GFX11-DL-NEXT: s_load_b32 s2, s[0:1], 0x0
-; GFX11-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT: v_perm_b32 v3, v1, v0, 0x6040200
-; GFX11-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT: v_perm_b32 v4, v2, v2, 0x2000200
-; GFX11-DL-NEXT: v_perm_b32 v0, v1, v0, 0x7050301
-; GFX11-DL-NEXT: v_perm_b32 v2, v2, v2, 0x3010301
-; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-DL-NEXT: v_dot4_u32_u8 v1, v3, v4, s2
-; GFX11-DL-NEXT: v_mov_b32_e32 v3, 0
-; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v0, v2, v1
-; GFX11-DL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GFX11-DL-NEXT: s_nop 0
-; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-DL-NEXT: s_endpgm
- ptr addrspace(1) %src2,
- ptr addrspace(1) nocapture %dst) {
-entry:
- %idx = call i32 @llvm.amdgcn.workitem.id.x()
- %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx
- %vec1 = load <8 x i8>, ptr addrspace(1) %gep1
- %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx
- %vec2 = load <8 x i8>, ptr addrspace(1) %gep2
-
- %v1e0 = extractelement <8 x i8> %vec1, i64 0
- %cv1e0 = zext i8 %v1e0 to i32
- %v2e0 = extractelement <8 x i8> %vec2, i64 0
- %cv2e0 = zext i8 %v2e0 to i32
- %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0
-
- %v1e1 = extractelement <8 x i8> %vec1, i64 1
- %cv1e1 = zext i8 %v1e1 to i32
- %v2e1 = extractelement <8 x i8> %vec2, i64 1
- %cv2e1 = zext i8 %v2e1 to i32
- %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1
-
- %v1e2 = extractelement <8 x i8> %vec1, i64 2
- %cv1e2 = zext i8 %v1e2 to i32
- %v2e2 = extractelement <8 x i8> %vec2, i64 2
- %cv2e2 = zext i8 %v2e2 to i32
- %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2
-
- %v1e3 = extractelement <8 x i8> %vec1, i64 3
- %cv1e3 = zext i8 %v1e3 to i32
- %v2e3 = extractelement <8 x i8> %vec2, i64 3
- %cv2e3 = zext i8 %v2e3 to i32
- %mul4 = mul nuw nsw i32 %cv1e3, %cv2e3
-
- %v1e4 = extractelement <8 x i8> %vec1, i64 4
- %cv1e4 = zext i8 %v1e4 to i32
- %v2e4 = extractelement <8 x i8> %vec2, i64 4
- %cv2e4 = zext i8 %v2e4 to i32
- %mul5 = mul nuw nsw i32 %cv1e4, %cv2e0
-
- %v1e5 = extractelement <8 x i8> %vec1, i64 5
- %cv1e5 = zext i8 %v1e5 to i32
- %v2e5 = extractelement <8 x i8> %vec2, i64 5
- %cv2e5 = zext i8 %v2e5 to i32
- %mul6 = mul nuw nsw i32 %cv1e5, %cv2e1
-
- %v1e6 = extractelement <8 x i8> %vec1, i64 6
- %cv1e6 = zext i8 %v1e6 to i32
- %v2e6 = extractelement <8 x i8> %vec2, i64 6
- %cv2e6 = zext i8 %v2e6 to i32
- %mul7 = mul nuw nsw i32 %cv1e6, %cv2e2
-
- %v1e7 = extractelement <8 x i8> %vec1, i64 7
- %cv1e7 = zext i8 %v1e7 to i32
- %v2e7 = extractelement <8 x i8> %vec2, i64 7
- %cv2e7 = zext i8 %v2e7 to i32
- %mul8 = mul nuw nsw i32 %cv1e7, %cv2e3
-
- %acc = load i32, ptr addrspace(1) %dst, align 4
- %mad11 = add i32 %mul1, %acc
- %mad21 = add i32 %mad11, %mul3
- %mad31 = add i32 %mad21, %mul5
- %mad41 = add i32 %mad31, %mul7
- %mad12 = add i32 %mul2, %mad41
- %mad22 = add i32 %mad12, %mul4
- %mad32 = add i32 %mad22, %mul6
- %mad42 = add i32 %mad32, %mul8
-
- store i32 %mad42, ptr addrspace(1) %dst, align 4
- ret void
-}
-
declare i32 @llvm.amdgcn.workitem.id.x()
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