[llvm] [libc][libm][GPU] Added missing vendor entry points to `libm` for GPUs (PR #66031)
Anton Rydahl via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 11 16:45:20 PDT 2023
Valentin Clement =?utf-8?b?KOODkOODrOODsw=?=,
Valentin Clement =?utf-8?b?KOODkOODrOODsw=?=,MaheshRavishankar
<1663364+MaheshRavishankar at users.noreply.github.com>,Fangrui Song
<i at maskray.me>,Razvan Lupusoru <razvan.lupusoru at gmail.com>,Walter Erquinigo
<a20012251 at gmail.com>,"Yaxun (Sam) Liu" <yaxun.liu at amd.com>,Nico Weber
<thakis at chromium.org>,Stella Laurenzo <stellaraccident at gmail.com>,Lang Hames
<lhames at gmail.com>,Matthias Braun <matze at braunis.de>,Arthur Eubanks
<aeubanks at google.com>,Nico Weber <thakis at chromium.org>,
Valentin Clement =?utf-8?b?KOODkOODrOODsw=?=,Vitaly Buka
<vitalybuka at google.com>,Vitaly Buka <vitalybuka at google.com>,Fangrui Song
<i at maskray.me>,Fangrui Song <i at maskray.me>,Fangrui Song <i at maskray.me>,Fangrui
Song <i at maskray.me>,erichkeane <ekeane at nvidia.com>,Amir Ayupov
<aaupov at fb.com>,Amir Ayupov <aaupov at meta.com>,yinying-lisa-li
<107574043+yinying-lisa-li at users.noreply.github.com>,Christopher Di Bella
<cjdb.ns at gmail.com>,Konstantin Varlamov <varconsteq at gmail.com>,Alexey Bader
<alexey.bader at intel.com>,Vitaly Buka <vitalybuka at google.com>
https://github.com/AntonRydahl created https://github.com/llvm/llvm-project/pull/66031:
There are a number of mathematical functions where no target-agnostic implementations exist, and the compiler built-ins are not correctly lowered on all GPU targets. This patch adds inlined wrappers for those functions to the GPU version of `libm` for AMDGPU and NVPTX targets.
>From f66140b9aa629908012313aa23da3895ddd97df3 Mon Sep 17 00:00:00 2001
From: antonrydahl <rydahl2610 at gmail.com>
Date: Mon, 11 Sep 2023 16:25:39 -0700
Subject: [PATCH 01/35] [libc][libm][GPU] Added missing vendor entrypoints to
`libm` for GPUs
There are a number of mathematical functions where no target agnostic implementations exist and the compiler builtins are not correctly lowered. This patch adds inlined wrappers for those functions to the GPU version of `libm` for AMDGPU and NVPTX targets.
---
libc/config/gpu/entrypoints.txt | 37 ++++-
libc/src/math/CMakeLists.txt | 15 ++
libc/src/math/acos.h | 18 +++
libc/src/math/acosh.h | 18 +++
libc/src/math/asin.h | 18 +++
libc/src/math/asinh.h | 18 +++
libc/src/math/atan.h | 18 +++
libc/src/math/atan2.h | 18 +++
libc/src/math/atan2f.h | 18 +++
libc/src/math/atanh.h | 18 +++
libc/src/math/erf.h | 18 +++
libc/src/math/expm1.h | 18 +++
libc/src/math/gpu/vendor/CMakeLists.txt | 143 ++++++++++++++++++
libc/src/math/gpu/vendor/acos.cpp | 18 +++
libc/src/math/gpu/vendor/acosh.cpp | 18 +++
libc/src/math/gpu/vendor/amdgpu/amdgpu.h | 25 +++
.../src/math/gpu/vendor/amdgpu/declarations.h | 34 ++++-
libc/src/math/gpu/vendor/asin.cpp | 18 +++
libc/src/math/gpu/vendor/asinh.cpp | 18 +++
libc/src/math/gpu/vendor/atan.cpp | 18 +++
libc/src/math/gpu/vendor/atan2.cpp | 20 +++
libc/src/math/gpu/vendor/atan2f.cpp | 21 +++
libc/src/math/gpu/vendor/atanh.cpp | 18 +++
libc/src/math/gpu/vendor/erf.cpp | 18 +++
libc/src/math/gpu/vendor/erff.cpp | 18 +++
libc/src/math/gpu/vendor/exp.cpp | 18 +++
libc/src/math/gpu/vendor/exp10.cpp | 18 +++
libc/src/math/gpu/vendor/exp2.cpp | 18 +++
libc/src/math/gpu/vendor/expm1.cpp | 18 +++
libc/src/math/gpu/vendor/log.cpp | 18 +++
libc/src/math/gpu/vendor/log10.cpp | 18 +++
libc/src/math/gpu/vendor/log10f.cpp | 19 +++
libc/src/math/gpu/vendor/log1p.cpp | 18 +++
libc/src/math/gpu/vendor/log1pf.cpp | 18 +++
libc/src/math/gpu/vendor/log2.cpp | 18 +++
libc/src/math/gpu/vendor/log2f.cpp | 18 +++
libc/src/math/gpu/vendor/logb.cpp | 18 +++
libc/src/math/gpu/vendor/logbf.cpp | 19 +++
libc/src/math/gpu/vendor/logf.cpp | 18 +++
libc/src/math/gpu/vendor/lrint.cpp | 18 +++
libc/src/math/gpu/vendor/lrintf.cpp | 18 +++
libc/src/math/gpu/vendor/lround.cpp | 18 +++
libc/src/math/gpu/vendor/lroundf.cpp | 20 +++
libc/src/math/gpu/vendor/nvptx/declarations.h | 25 +++
libc/src/math/gpu/vendor/nvptx/nvptx.h | 25 +++
libc/src/math/gpu/vendor/tgamma.cpp | 18 +++
libc/src/math/gpu/vendor/tgammaf.cpp | 18 +++
libc/src/math/sincos.h | 18 +++
libc/src/math/tgamma.h | 18 +++
libc/src/math/tgammaf.h | 18 +++
50 files changed, 1081 insertions(+), 6 deletions(-)
create mode 100644 libc/src/math/acos.h
create mode 100644 libc/src/math/acosh.h
create mode 100644 libc/src/math/asin.h
create mode 100644 libc/src/math/asinh.h
create mode 100644 libc/src/math/atan.h
create mode 100644 libc/src/math/atan2.h
create mode 100644 libc/src/math/atan2f.h
create mode 100644 libc/src/math/atanh.h
create mode 100644 libc/src/math/erf.h
create mode 100644 libc/src/math/expm1.h
create mode 100644 libc/src/math/gpu/vendor/acos.cpp
create mode 100644 libc/src/math/gpu/vendor/acosh.cpp
create mode 100644 libc/src/math/gpu/vendor/asin.cpp
create mode 100644 libc/src/math/gpu/vendor/asinh.cpp
create mode 100644 libc/src/math/gpu/vendor/atan.cpp
create mode 100644 libc/src/math/gpu/vendor/atan2.cpp
create mode 100644 libc/src/math/gpu/vendor/atan2f.cpp
create mode 100644 libc/src/math/gpu/vendor/atanh.cpp
create mode 100644 libc/src/math/gpu/vendor/erf.cpp
create mode 100644 libc/src/math/gpu/vendor/erff.cpp
create mode 100644 libc/src/math/gpu/vendor/exp.cpp
create mode 100644 libc/src/math/gpu/vendor/exp10.cpp
create mode 100644 libc/src/math/gpu/vendor/exp2.cpp
create mode 100644 libc/src/math/gpu/vendor/expm1.cpp
create mode 100644 libc/src/math/gpu/vendor/log.cpp
create mode 100644 libc/src/math/gpu/vendor/log10.cpp
create mode 100644 libc/src/math/gpu/vendor/log10f.cpp
create mode 100644 libc/src/math/gpu/vendor/log1p.cpp
create mode 100644 libc/src/math/gpu/vendor/log1pf.cpp
create mode 100644 libc/src/math/gpu/vendor/log2.cpp
create mode 100644 libc/src/math/gpu/vendor/log2f.cpp
create mode 100644 libc/src/math/gpu/vendor/logb.cpp
create mode 100644 libc/src/math/gpu/vendor/logbf.cpp
create mode 100644 libc/src/math/gpu/vendor/logf.cpp
create mode 100644 libc/src/math/gpu/vendor/lrint.cpp
create mode 100644 libc/src/math/gpu/vendor/lrintf.cpp
create mode 100644 libc/src/math/gpu/vendor/lround.cpp
create mode 100644 libc/src/math/gpu/vendor/lroundf.cpp
create mode 100644 libc/src/math/gpu/vendor/tgamma.cpp
create mode 100644 libc/src/math/gpu/vendor/tgammaf.cpp
create mode 100644 libc/src/math/sincos.h
create mode 100644 libc/src/math/tgamma.h
create mode 100644 libc/src/math/tgammaf.h
diff --git a/libc/config/gpu/entrypoints.txt b/libc/config/gpu/entrypoints.txt
index 0e314c60870c6ae..730f76cbd6fbb9c 100644
--- a/libc/config/gpu/entrypoints.txt
+++ b/libc/config/gpu/entrypoints.txt
@@ -113,11 +113,19 @@ set(TARGET_LIBC_ENTRYPOINTS
set(TARGET_LIBM_ENTRYPOINTS
# math.h entrypoints
+ libc.src.math.acos
libc.src.math.acosf
+ libc.src.math.acosh
libc.src.math.acoshf
+ libc.src.math.asin
libc.src.math.asinf
+ libc.src.math.asinh
libc.src.math.asinhf
+ libc.src.math.atan
libc.src.math.atanf
+ libc.src.math.atan2
+ libc.src.math.atan2f
+ libc.src.math.atanh
libc.src.math.atanhf
libc.src.math.ceil
libc.src.math.ceilf
@@ -127,9 +135,15 @@ set(TARGET_LIBM_ENTRYPOINTS
libc.src.math.cosf
libc.src.math.cosh
libc.src.math.coshf
+ libc.src.math.erf
+ libc.src.math.erff
+ libc.src.math.exp10
libc.src.math.exp10f
+ libc.src.math.exp2
libc.src.math.exp2f
+ libc.src.math.exp
libc.src.math.expf
+ libc.src.math.expm1
libc.src.math.expm1f
libc.src.math.fabs
libc.src.math.fabsf
@@ -157,15 +171,26 @@ set(TARGET_LIBM_ENTRYPOINTS
libc.src.math.llrintf
libc.src.math.llround
libc.src.math.llroundf
- libc.src.math.pow
- libc.src.math.powf
- libc.src.math.sin
+ libc.src.math.log10
+ libc.src.math.log10f
+ libc.src.math.log1p
+ libc.src.math.log1pf
+ libc.src.math.log2
+ libc.src.math.log2f
+ libc.src.math.log
+ libc.src.math.logf
+ libc.src.math.lrint
+ libc.src.math.lrintf
+ libc.src.math.lround
+ libc.src.math.lroundf
libc.src.math.modf
libc.src.math.modff
libc.src.math.nearbyint
libc.src.math.nearbyintf
libc.src.math.nextafter
libc.src.math.nextafterf
+ libc.src.math.pow
+ libc.src.math.powf
libc.src.math.remainder
libc.src.math.remainderf
libc.src.math.remquo
@@ -176,6 +201,10 @@ set(TARGET_LIBM_ENTRYPOINTS
libc.src.math.roundf
libc.src.math.scalbn
libc.src.math.scalbnf
+ libc.src.math.sin
+ libc.src.math.sinf
+ libc.src.math.sincos
+ libc.src.math.sincosf
libc.src.math.sinh
libc.src.math.sinhf
libc.src.math.sqrt
@@ -184,6 +213,8 @@ set(TARGET_LIBM_ENTRYPOINTS
libc.src.math.tanf
libc.src.math.tanh
libc.src.math.tanhf
+ libc.src.math.tgamma
+ libc.src.math.tgammaf
libc.src.math.trunc
libc.src.math.truncf
)
diff --git a/libc/src/math/CMakeLists.txt b/libc/src/math/CMakeLists.txt
index 8b2021cac8239fe..f1f72714981a9e5 100644
--- a/libc/src/math/CMakeLists.txt
+++ b/libc/src/math/CMakeLists.txt
@@ -54,14 +54,23 @@ function(add_math_entrypoint_object name)
)
endfunction()
+add_math_entrypoint_object(acos)
add_math_entrypoint_object(acosf)
+add_math_entrypoint_object(acosh)
add_math_entrypoint_object(acoshf)
+add_math_entrypoint_object(asin)
add_math_entrypoint_object(asinf)
+add_math_entrypoint_object(asinh)
add_math_entrypoint_object(asinhf)
+add_math_entrypoint_object(atan)
add_math_entrypoint_object(atanf)
+add_math_entrypoint_object(atan2)
+add_math_entrypoint_object(atan2f)
+
+add_math_entrypoint_object(atanh)
add_math_entrypoint_object(atanhf)
add_math_entrypoint_object(ceil)
@@ -77,6 +86,7 @@ add_math_entrypoint_object(cosf)
add_math_entrypoint_object(cosh)
add_math_entrypoint_object(coshf)
+add_math_entrypoint_object(erf)
add_math_entrypoint_object(erff)
add_math_entrypoint_object(exp)
@@ -88,6 +98,7 @@ add_math_entrypoint_object(exp2f)
add_math_entrypoint_object(exp10)
add_math_entrypoint_object(exp10f)
+add_math_entrypoint_object(expm1)
add_math_entrypoint_object(expm1f)
add_math_entrypoint_object(fabs)
@@ -198,6 +209,7 @@ add_math_entrypoint_object(scalbn)
add_math_entrypoint_object(scalbnf)
add_math_entrypoint_object(scalbnl)
+add_math_entrypoint_object(sincos)
add_math_entrypoint_object(sincosf)
add_math_entrypoint_object(sin)
@@ -216,6 +228,9 @@ add_math_entrypoint_object(tanf)
add_math_entrypoint_object(tanh)
add_math_entrypoint_object(tanhf)
+add_math_entrypoint_object(tgamma)
+add_math_entrypoint_object(tgammaf)
+
add_math_entrypoint_object(trunc)
add_math_entrypoint_object(truncf)
add_math_entrypoint_object(truncl)
diff --git a/libc/src/math/acos.h b/libc/src/math/acos.h
new file mode 100644
index 000000000000000..53b299f1da8902e
--- /dev/null
+++ b/libc/src/math/acos.h
@@ -0,0 +1,18 @@
+//===-- Implementation header for acos --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_MATH_ACOS_H
+#define LLVM_LIBC_SRC_MATH_ACOS_H
+
+namespace __llvm_libc {
+
+double acos(double x);
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_MATH_ACOS_H
diff --git a/libc/src/math/acosh.h b/libc/src/math/acosh.h
new file mode 100644
index 000000000000000..851c619fdb9f799
--- /dev/null
+++ b/libc/src/math/acosh.h
@@ -0,0 +1,18 @@
+//===-- Implementation header for acosh -------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_MATH_ACOSH_H
+#define LLVM_LIBC_SRC_MATH_ACOSH_H
+
+namespace __llvm_libc {
+
+double acosh(double x);
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_MATH_ACOSH_H
diff --git a/libc/src/math/asin.h b/libc/src/math/asin.h
new file mode 100644
index 000000000000000..d8f3f191a357856
--- /dev/null
+++ b/libc/src/math/asin.h
@@ -0,0 +1,18 @@
+//===-- Implementation header for asin --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_MATH_ASIN_H
+#define LLVM_LIBC_SRC_MATH_ASIN_H
+
+namespace __llvm_libc {
+
+double asin(double x);
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_MATH_ASIN_H
diff --git a/libc/src/math/asinh.h b/libc/src/math/asinh.h
new file mode 100644
index 000000000000000..098880f26ecc80c
--- /dev/null
+++ b/libc/src/math/asinh.h
@@ -0,0 +1,18 @@
+//===-- Implementation header for asinh -------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_MATH_ASINH_H
+#define LLVM_LIBC_SRC_MATH_ASINH_H
+
+namespace __llvm_libc {
+
+double asinh(double x);
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_MATH_ASINH_H
diff --git a/libc/src/math/atan.h b/libc/src/math/atan.h
new file mode 100644
index 000000000000000..73d67e526d7d5a5
--- /dev/null
+++ b/libc/src/math/atan.h
@@ -0,0 +1,18 @@
+//===-- Implementation header for atan --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_MATH_ATAN_H
+#define LLVM_LIBC_SRC_MATH_ATAN_H
+
+namespace __llvm_libc {
+
+double atan(double x);
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_MATH_ATAN_H
diff --git a/libc/src/math/atan2.h b/libc/src/math/atan2.h
new file mode 100644
index 000000000000000..cac5b7ddfbb62c1
--- /dev/null
+++ b/libc/src/math/atan2.h
@@ -0,0 +1,18 @@
+//===-- Implementation header for atan2 -------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_MATH_ATAN2_H
+#define LLVM_LIBC_SRC_MATH_ATAN2_H
+
+namespace __llvm_libc {
+
+double atan2(double x, double y);
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_MATH_ATAN2_H
diff --git a/libc/src/math/atan2f.h b/libc/src/math/atan2f.h
new file mode 100644
index 000000000000000..d3e81a2b8d5f2d4
--- /dev/null
+++ b/libc/src/math/atan2f.h
@@ -0,0 +1,18 @@
+//===-- Implementation header for atan2f ------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_MATH_ATAN2F_H
+#define LLVM_LIBC_SRC_MATH_ATAN2F_H
+
+namespace __llvm_libc {
+
+float atan2f(float x, float y);
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_MATH_ATAN2F_H
diff --git a/libc/src/math/atanh.h b/libc/src/math/atanh.h
new file mode 100644
index 000000000000000..de854451e7a281f
--- /dev/null
+++ b/libc/src/math/atanh.h
@@ -0,0 +1,18 @@
+//===-- Implementation header for atanh -------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_MATH_ATANH_H
+#define LLVM_LIBC_SRC_MATH_ATANH_H
+
+namespace __llvm_libc {
+
+double atanh(double x);
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_MATH_ATANH_H
diff --git a/libc/src/math/erf.h b/libc/src/math/erf.h
new file mode 100644
index 000000000000000..86a146182b4f729
--- /dev/null
+++ b/libc/src/math/erf.h
@@ -0,0 +1,18 @@
+//===-- Implementation header for erf ---------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_MATH_ERF_H
+#define LLVM_LIBC_SRC_MATH_ERF_H
+
+namespace __llvm_libc {
+
+double erf(double x);
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_MATH_ERF_H
diff --git a/libc/src/math/expm1.h b/libc/src/math/expm1.h
new file mode 100644
index 000000000000000..7ae354e459feb1f
--- /dev/null
+++ b/libc/src/math/expm1.h
@@ -0,0 +1,18 @@
+//===-- Implementation header for expm1 -------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_MATH_EXPM1_H
+#define LLVM_LIBC_SRC_MATH_EXPM1_H
+
+namespace __llvm_libc {
+
+double expm1(double x);
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_MATH_EXPM1_H
diff --git a/libc/src/math/gpu/vendor/CMakeLists.txt b/libc/src/math/gpu/vendor/CMakeLists.txt
index 2ee74a06a02d461..58910ac517bdc97 100644
--- a/libc/src/math/gpu/vendor/CMakeLists.txt
+++ b/libc/src/math/gpu/vendor/CMakeLists.txt
@@ -29,6 +29,17 @@ endif()
# will link in identity metadata from both libraries. This silences the warning.
list(APPEND bitcode_link_flags "-Wno-linker-warnings")
+add_entrypoint_object(
+ acos
+ SRCS
+ acos.cpp
+ HDRS
+ ../../acos.h
+ COMPILE_OPTIONS
+ ${bitcode_link_flags}
+ -O2
+)
+
add_entrypoint_object(
acosf
SRCS
@@ -40,6 +51,17 @@ add_entrypoint_object(
-O2
)
+add_entrypoint_object(
+ acosh
+ SRCS
+ acosh.cpp
+ HDRS
+ ../../acosh.h
+ COMPILE_OPTIONS
+ ${bitcode_link_flags}
+ -O2
+)
+
add_entrypoint_object(
acoshf
SRCS
@@ -51,6 +73,17 @@ add_entrypoint_object(
-O2
)
+add_entrypoint_object(
+ asin
+ SRCS
+ asin.cpp
+ HDRS
+ ../../asin.h
+ COMPILE_OPTIONS
+ ${bitcode_link_flags}
+ -O2
+)
+
add_entrypoint_object(
asinf
SRCS
@@ -62,6 +95,17 @@ add_entrypoint_object(
-O2
)
+add_entrypoint_object(
+ asinh
+ SRCS
+ asinh.cpp
+ HDRS
+ ../../asinh.h
+ COMPILE_OPTIONS
+ ${bitcode_link_flags}
+ -O2
+)
+
add_entrypoint_object(
asinhf
SRCS
@@ -73,6 +117,17 @@ add_entrypoint_object(
-O2
)
+add_entrypoint_object(
+ atan
+ SRCS
+ atan.cpp
+ HDRS
+ ../../atan.h
+ COMPILE_OPTIONS
+ ${bitcode_link_flags}
+ -O2
+)
+
add_entrypoint_object(
atanf
SRCS
@@ -84,6 +139,39 @@ add_entrypoint_object(
-O2
)
+add_entrypoint_object(
+ atan2
+ SRCS
+ atan2.cpp
+ HDRS
+ ../../atan2.h
+ COMPILE_OPTIONS
+ ${bitcode_link_flags}
+ -O2
+)
+
+add_entrypoint_object(
+ atan2f
+ SRCS
+ atan2f.cpp
+ HDRS
+ ../../atan2f.h
+ COMPILE_OPTIONS
+ ${bitcode_link_flags}
+ -O2
+)
+
+add_entrypoint_object(
+ atanh
+ SRCS
+ atanh.cpp
+ HDRS
+ ../../atanh.h
+ COMPILE_OPTIONS
+ ${bitcode_link_flags}
+ -O2
+)
+
add_entrypoint_object(
atanhf
SRCS
@@ -139,6 +227,28 @@ add_entrypoint_object(
-O2
)
+add_entrypoint_object(
+ erf
+ SRCS
+ erf.cpp
+ HDRS
+ ../../erf.h
+ COMPILE_OPTIONS
+ ${bitcode_link_flags}
+ -O2
+)
+
+add_entrypoint_object(
+ erff
+ SRCS
+ erff.cpp
+ HDRS
+ ../../erff.h
+ COMPILE_OPTIONS
+ ${bitcode_link_flags}
+ -O2
+)
+
add_entrypoint_object(
exp10f
SRCS
@@ -172,6 +282,17 @@ add_entrypoint_object(
-O2
)
+add_entrypoint_object(
+ expm1
+ SRCS
+ expm1.cpp
+ HDRS
+ ../../expm1.h
+ COMPILE_OPTIONS
+ ${bitcode_link_flags}
+ -O2
+)
+
add_entrypoint_object(
expm1f
SRCS
@@ -515,6 +636,28 @@ add_entrypoint_object(
-O2
)
+add_entrypoint_object(
+ tgamma
+ SRCS
+ tgamma.cpp
+ HDRS
+ ../../tgamma.h
+ COMPILE_OPTIONS
+ ${bitcode_link_flags}
+ -O2
+)
+
+add_entrypoint_object(
+ tgammaf
+ SRCS
+ tgammaf.cpp
+ HDRS
+ ../../tgammaf.h
+ COMPILE_OPTIONS
+ ${bitcode_link_flags}
+ -O2
+)
+
add_entrypoint_object(
frexp
SRCS
diff --git a/libc/src/math/gpu/vendor/acos.cpp b/libc/src/math/gpu/vendor/acos.cpp
new file mode 100644
index 000000000000000..7e6d00be3c3e589
--- /dev/null
+++ b/libc/src/math/gpu/vendor/acos.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU acos function ---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/acos.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, acos, (double x)) { return internal::acos(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/acosh.cpp b/libc/src/math/gpu/vendor/acosh.cpp
new file mode 100644
index 000000000000000..2ea150dcf78e03a
--- /dev/null
+++ b/libc/src/math/gpu/vendor/acosh.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU acosh function --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/acosh.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, acosh, (double x)) { return internal::acosh(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/amdgpu/amdgpu.h b/libc/src/math/gpu/vendor/amdgpu/amdgpu.h
index 7755174e445b222..a763f2e3d0f53f1 100644
--- a/libc/src/math/gpu/vendor/amdgpu/amdgpu.h
+++ b/libc/src/math/gpu/vendor/amdgpu/amdgpu.h
@@ -16,19 +16,30 @@
namespace __llvm_libc {
namespace internal {
+LIBC_INLINE double acos(double x) { return __ocml_acos_f64(x); }
LIBC_INLINE float acosf(float x) { return __ocml_acos_f32(x); }
+LIBC_INLINE double acosh(double x) { return __ocml_acosh_f64(x); }
LIBC_INLINE float acoshf(float x) { return __ocml_acosh_f32(x); }
+LIBC_INLINE double asin(double x) { return __ocml_asin_f64(x); }
LIBC_INLINE float asinf(float x) { return __ocml_asin_f32(x); }
+LIBC_INLINE double asinh(double x) { return __ocml_asinh_f64(x); }
LIBC_INLINE float asinhf(float x) { return __ocml_asinh_f32(x); }
+LIBC_INLINE double atan(double x) { return __ocml_atan_f64(x); }
LIBC_INLINE float atanf(float x) { return __ocml_atan_f32(x); }
+LIBC_INLINE double atan2(double x, double y) { return __ocml_atan2_f64(x, y); }
+LIBC_INLINE float atan2f(float x, float y) { return __ocml_atan2_f32(x, y); }
+LIBC_INLINE double atanh(double x) { return __ocml_atanh_f64(x); }
LIBC_INLINE float atanhf(float x) { return __ocml_atanh_f32(x); }
LIBC_INLINE double cos(double x) { return __ocml_cos_f64(x); }
LIBC_INLINE float cosf(float x) { return __ocml_cos_f32(x); }
LIBC_INLINE double cosh(double x) { return __ocml_cosh_f64(x); }
LIBC_INLINE float coshf(float x) { return __ocml_cosh_f32(x); }
+LIBC_INLINE double erf(double x) { return __ocml_erf_f64(x); }
+LIBC_INLINE float erff(float x) { return __ocml_erf_f32(x); }
LIBC_INLINE float expf(float x) { return __builtin_expf(x); }
LIBC_INLINE float exp2f(float x) { return __builtin_exp2f(x); }
LIBC_INLINE float exp10f(float x) { return __ocml_exp10_f32(x); }
+LIBC_INLINE double expm1(double x) { return __ocml_expm1_f64(x); }
LIBC_INLINE float expm1f(float x) { return __ocml_expm1_f32(x); }
LIBC_INLINE double fdim(double x, double y) { return __ocml_fdim_f64(x, y); }
LIBC_INLINE float fdimf(float x, float y) { return __ocml_fdim_f32(x, y); }
@@ -50,6 +61,18 @@ LIBC_INLINE long long llround(double x) {
LIBC_INLINE long long llroundf(float x) {
return static_cast<long long>(__builtin_roundf(x));
}
+LIBC_INLINE double log10(double x) { return __ocml_log10_f64(x); }
+LIBC_INLINE float log10f(float x) { return __ocml_log10_f32(x); }
+LIBC_INLINE double log1p(double x) { return __ocml_log1p_f64(x); }
+LIBC_INLINE float log1pf(float x) { return __ocml_log1p_f32(x); }
+LIBC_INLINE double log2(double x) { return __ocml_log2_f64(x); }
+LIBC_INLINE float log2f(float x) { return __ocml_log2_f32(x); }
+LIBC_INLINE double log(double x) { return __ocml_log_f64(x); }
+LIBC_INLINE float logf(float x) { return __ocml_log_f32(x); }
+LIBC_INLINE long lrint(double x) { return (long)__ocml_rint_f64(x); }
+LIBC_INLINE long lrintf(float x) { return (long)__ocml_rint_f32(x); }
+LIBC_INLINE long lround(double x) { return (long)__ocml_round_f64(x); }
+LIBC_INLINE long lroundf(float x) { return (long)__ocml_round_f32(x); }
LIBC_INLINE double nextafter(double x, double y) {
return __ocml_nextafter_f64(x, y);
}
@@ -96,6 +119,8 @@ LIBC_INLINE float remquof(float x, float y, int *q) {
*q = tmp;
return r;
}
+LIBC_INLINE double tgamma(double x) { return __ocml_tgamma_f64(x); }
+LIBC_INLINE float tgammaf(float x) { return __ocml_tgamma_f32(x); }
} // namespace internal
} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/amdgpu/declarations.h b/libc/src/math/gpu/vendor/amdgpu/declarations.h
index 7219d5a7dfa6d73..84214edb6624bc8 100644
--- a/libc/src/math/gpu/vendor/amdgpu/declarations.h
+++ b/libc/src/math/gpu/vendor/amdgpu/declarations.h
@@ -15,35 +15,61 @@ namespace __llvm_libc {
extern "C" {
float __ocml_acos_f32(float);
+double __ocml_acos_f64(double);
float __ocml_acosh_f32(float);
+double __ocml_acosh_f64(double);
float __ocml_asin_f32(float);
+double __ocml_asin_f64(double);
float __ocml_asinh_f32(float);
+double __ocml_asinh_f64(double);
float __ocml_atan_f32(float);
+double __ocml_atan_f64(double);
+float __ocml_atan2_f32(float, float);
+double __ocml_atan2_f64(double, double);
float __ocml_atanh_f32(float);
+double __ocml_atanh_f64(double);
float __ocml_cos_f32(float);
double __ocml_cos_f64(double);
float __ocml_cosh_f32(float);
double __ocml_cosh_f64(double);
+float __ocml_erf_f32(float);
+double __ocml_erf_f64(double);
float __ocml_exp_f32(float);
+double __ocml_exp_f64(double);
float __ocml_exp2_f32(float);
+double __ocml_exp2_f64(double);
float __ocml_exp10_f32(float);
+double __ocml_exp2_f64(double);
float __ocml_expm1_f32(float);
+double __ocml_expm1_f64(double);
float __ocml_fdim_f32(float, float);
double __ocml_fdim_f64(double, double);
-double __ocml_hypot_f64(double, double);
float __ocml_hypot_f32(float, float);
+double __ocml_hypot_f64(double, double);
int __ocml_ilogb_f64(double);
int __ocml_ilogb_f32(float);
float __ocml_ldexp_f32(float, int);
double __ocml_ldexp_f64(double, int);
+float __ocml_log10_f32(float);
+double __ocml_log10_f64(double);
+float __ocml_log1p_f32(float);
+double __ocml_log1p_f64(double);
+float __ocml_log2_f32(float);
+double __ocml_log2_f64(double);
+float __ocml_log_f32(float);
+double __ocml_log_f64(double);
+long __ocml_lrint_f32(float);
+long __ocml_lrint_f64(double);
+long __ocml_lround_f32(float);
+long __ocml_lround_f64(double);
float __ocml_nextafter_f32(float, float);
double __ocml_nextafter_f64(double, double);
float __ocml_pow_f32(float, float);
double __ocml_pow_f64(double, double);
-double __ocml_rint_f64(double);
float __ocml_rint_f32(float);
-double __ocml_round_f64(double);
+double __ocml_rint_f64(double);
float __ocml_round_f32(float);
+double __ocml_round_f64(double);
float __ocml_sin_f32(float);
double __ocml_sin_f64(double);
float __ocml_sincos_f32(float, float *);
@@ -56,6 +82,8 @@ float __ocml_tanh_f32(float);
double __ocml_tanh_f64(double);
float __ocml_remquo_f32(float, float, gpu::Private<int> *);
double __ocml_remquo_f64(double, double, gpu::Private<int> *);
+double __ocml_tgamma_f64(double);
+float __ocml_tgamma_f32(float);
}
} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/asin.cpp b/libc/src/math/gpu/vendor/asin.cpp
new file mode 100644
index 000000000000000..eaf7253ad1ecaff
--- /dev/null
+++ b/libc/src/math/gpu/vendor/asin.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU asin function ---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/asin.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, asin, (double x)) { return internal::asin(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/asinh.cpp b/libc/src/math/gpu/vendor/asinh.cpp
new file mode 100644
index 000000000000000..ddb33ebae3a590a
--- /dev/null
+++ b/libc/src/math/gpu/vendor/asinh.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU asinh function --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/asinh.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, asinh, (double x)) { return internal::asinh(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/atan.cpp b/libc/src/math/gpu/vendor/atan.cpp
new file mode 100644
index 000000000000000..88452dc60188a59
--- /dev/null
+++ b/libc/src/math/gpu/vendor/atan.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU atan function ---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/atan.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, atan, (double x)) { return internal::atan(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/atan2.cpp b/libc/src/math/gpu/vendor/atan2.cpp
new file mode 100644
index 000000000000000..9f5736f7c30e1f8
--- /dev/null
+++ b/libc/src/math/gpu/vendor/atan2.cpp
@@ -0,0 +1,20 @@
+//===-- Implementation of the GPU atan2 function --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/atan2.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, atan2, (double x, double y)) {
+ return internal::atan2(x, y);
+}
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/atan2f.cpp b/libc/src/math/gpu/vendor/atan2f.cpp
new file mode 100644
index 000000000000000..897bd5d26527763
--- /dev/null
+++ b/libc/src/math/gpu/vendor/atan2f.cpp
@@ -0,0 +1,21 @@
+//===-- Implementation of the GPU atan2f function
+//--------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/atan2f.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(float, atan2f, (float x, float y)) {
+ return internal::atan2f(x, y);
+}
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/atanh.cpp b/libc/src/math/gpu/vendor/atanh.cpp
new file mode 100644
index 000000000000000..97246bf195ff77c
--- /dev/null
+++ b/libc/src/math/gpu/vendor/atanh.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU atanh function --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/atanh.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, atanh, (double x)) { return internal::atanh(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/erf.cpp b/libc/src/math/gpu/vendor/erf.cpp
new file mode 100644
index 000000000000000..f06ab8121ebd669
--- /dev/null
+++ b/libc/src/math/gpu/vendor/erf.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU erf function ----------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/erf.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, erf, (double x)) { return internal::erf(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/erff.cpp b/libc/src/math/gpu/vendor/erff.cpp
new file mode 100644
index 000000000000000..78c31383d86acb1
--- /dev/null
+++ b/libc/src/math/gpu/vendor/erff.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU erff function ---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/erff.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(float, erff, (float x)) { return internal::erff(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/exp.cpp b/libc/src/math/gpu/vendor/exp.cpp
new file mode 100644
index 000000000000000..dc315d9555b422a
--- /dev/null
+++ b/libc/src/math/gpu/vendor/exp.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU exp function ----------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/exp.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, exp, (double x)) { return internal::exp(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/exp10.cpp b/libc/src/math/gpu/vendor/exp10.cpp
new file mode 100644
index 000000000000000..1bb746bfdcac260
--- /dev/null
+++ b/libc/src/math/gpu/vendor/exp10.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU exp10 function --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/exp10.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, exp10, (double x)) { return internal::exp10(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/exp2.cpp b/libc/src/math/gpu/vendor/exp2.cpp
new file mode 100644
index 000000000000000..0dbea3837cbdd0d
--- /dev/null
+++ b/libc/src/math/gpu/vendor/exp2.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU exp2 function ---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/exp2.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, exp2, (double x)) { return internal::exp2(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/expm1.cpp b/libc/src/math/gpu/vendor/expm1.cpp
new file mode 100644
index 000000000000000..528daab22e14cfd
--- /dev/null
+++ b/libc/src/math/gpu/vendor/expm1.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU expm1 function --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/expm1.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, expm1, (double x)) { return internal::expm1(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/log.cpp b/libc/src/math/gpu/vendor/log.cpp
new file mode 100644
index 000000000000000..fe44d78724a4ca2
--- /dev/null
+++ b/libc/src/math/gpu/vendor/log.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU log function ----------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/log.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, log, (double x)) { return internal::log(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/log10.cpp b/libc/src/math/gpu/vendor/log10.cpp
new file mode 100644
index 000000000000000..6666dae827646da
--- /dev/null
+++ b/libc/src/math/gpu/vendor/log10.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU log10 function --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/log10.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, log10, (double x)) { return internal::log10(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/log10f.cpp b/libc/src/math/gpu/vendor/log10f.cpp
new file mode 100644
index 000000000000000..5e938a32895128e
--- /dev/null
+++ b/libc/src/math/gpu/vendor/log10f.cpp
@@ -0,0 +1,19 @@
+//===-- Implementation of the GPU log10f function
+//---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/log10f.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(float, log10f, (float x)) { return internal::log10f(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/log1p.cpp b/libc/src/math/gpu/vendor/log1p.cpp
new file mode 100644
index 000000000000000..e2781bfbab1ceba
--- /dev/null
+++ b/libc/src/math/gpu/vendor/log1p.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU log1p function --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/log1p.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, log1p, (double x)) { return internal::log1p(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/log1pf.cpp b/libc/src/math/gpu/vendor/log1pf.cpp
new file mode 100644
index 000000000000000..3cdde90d94b132f
--- /dev/null
+++ b/libc/src/math/gpu/vendor/log1pf.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU log1pf function -------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/log1pf.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(float, log1pf, (float x)) { return internal::log1pf(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/log2.cpp b/libc/src/math/gpu/vendor/log2.cpp
new file mode 100644
index 000000000000000..45d2200d269009d
--- /dev/null
+++ b/libc/src/math/gpu/vendor/log2.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU log2 function ---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/log2.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, log2, (double x)) { return internal::log2(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/log2f.cpp b/libc/src/math/gpu/vendor/log2f.cpp
new file mode 100644
index 000000000000000..2378bc1bacb47a5
--- /dev/null
+++ b/libc/src/math/gpu/vendor/log2f.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU log2f function --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/log2f.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(float, log2f, (float x)) { return internal::log2f(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/logb.cpp b/libc/src/math/gpu/vendor/logb.cpp
new file mode 100644
index 000000000000000..d7aa9a1d1517e6a
--- /dev/null
+++ b/libc/src/math/gpu/vendor/logb.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU logb function ---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/logb.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, logb, (double x)) { return internal::logb(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/logbf.cpp b/libc/src/math/gpu/vendor/logbf.cpp
new file mode 100644
index 000000000000000..021bed06c69032c
--- /dev/null
+++ b/libc/src/math/gpu/vendor/logbf.cpp
@@ -0,0 +1,19 @@
+//===-- Implementation of the GPU logbf function
+//---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/logbf.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(float, logbf, (float x)) { return internal::logbf(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/logf.cpp b/libc/src/math/gpu/vendor/logf.cpp
new file mode 100644
index 000000000000000..6f0c5d5c144ea96
--- /dev/null
+++ b/libc/src/math/gpu/vendor/logf.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU logf function ---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/logf.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(float, logf, (float x)) { return internal::logf(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/lrint.cpp b/libc/src/math/gpu/vendor/lrint.cpp
new file mode 100644
index 000000000000000..15316f02ebf871e
--- /dev/null
+++ b/libc/src/math/gpu/vendor/lrint.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU lrint function --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/lrint.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(long, lrint, (double x)) { return internal::lrint(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/lrintf.cpp b/libc/src/math/gpu/vendor/lrintf.cpp
new file mode 100644
index 000000000000000..5cbd212e0c999ca
--- /dev/null
+++ b/libc/src/math/gpu/vendor/lrintf.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU lrintf function -------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/lrintf.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(long, lrintf, (float x)) { return internal::lrintf(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/lround.cpp b/libc/src/math/gpu/vendor/lround.cpp
new file mode 100644
index 000000000000000..cb268104d94b99d
--- /dev/null
+++ b/libc/src/math/gpu/vendor/lround.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU lround function -------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/lround.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(long int, lround, (double x)) { return internal::lround(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/lroundf.cpp b/libc/src/math/gpu/vendor/lroundf.cpp
new file mode 100644
index 000000000000000..175c6a2561b27de
--- /dev/null
+++ b/libc/src/math/gpu/vendor/lroundf.cpp
@@ -0,0 +1,20 @@
+//===-- Implementation of the GPU lroundf function ------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/lroundf.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(long int, lroundf, (float x)) {
+ return internal::lroundf(x);
+}
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/nvptx/declarations.h b/libc/src/math/gpu/vendor/nvptx/declarations.h
index 8b6702834a04cf4..b8bb90f3bf585c2 100644
--- a/libc/src/math/gpu/vendor/nvptx/declarations.h
+++ b/libc/src/math/gpu/vendor/nvptx/declarations.h
@@ -12,19 +12,30 @@
namespace __llvm_libc {
extern "C" {
+double __nv_acos(double);
float __nv_acosf(float);
+double __nv_acosh(double);
float __nv_acoshf(float);
+double __nv_asin(double);
float __nv_asinf(float);
+double __nv_asinh(double);
float __nv_asinhf(float);
+double __nv_atan(double);
float __nv_atanf(float);
+double __nv_atan2(double, double);
+float __nv_atan2f(float, float);
+double __nv_atanh(double);
float __nv_atanhf(float);
double __nv_cos(double);
float __nv_cosf(float);
double __nv_cosh(double);
float __nv_coshf(float);
+double __nv_erf(double);
+float __nv_erff(float);
float __nv_expf(float);
float __nv_exp2f(float);
float __nv_exp10f(float);
+double __nv_expm1(double);
float __nv_expm1f(float);
double __nv_fdim(double, double);
float __nv_fdimf(float, float);
@@ -38,6 +49,18 @@ long long __nv_llrint(double);
long long __nv_llrintf(float);
long long __nv_llround(double);
long long __nv_llroundf(float);
+double __nv_log10(double);
+float __nv_log10f(float);
+double __nv_log1p(double);
+float __nv_log1pf(float);
+double __nv_log2(double);
+float __nv_log2f(float);
+double __nv_log(double);
+float __nv_logf(float);
+long __nv_lrint(double);
+long __nv_lrintf(float);
+long __nv_lround(double);
+long __nv_lroundf(float);
double __nv_nextafter(double, double);
float __nv_nextafterf(float, float);
double __nv_pow(double, double);
@@ -58,6 +81,8 @@ double __nv_scalbn(double, int);
float __nv_scalbnf(float, int);
double __nv_remquo(double, double, int *);
float __nv_remquof(float, float, int *);
+double __nv_tgamma(double);
+float __nv_tgammaf(float);
}
} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/nvptx/nvptx.h b/libc/src/math/gpu/vendor/nvptx/nvptx.h
index 6ea1743cf7a6f3e..4a2e8d7ab8debea 100644
--- a/libc/src/math/gpu/vendor/nvptx/nvptx.h
+++ b/libc/src/math/gpu/vendor/nvptx/nvptx.h
@@ -15,19 +15,30 @@
namespace __llvm_libc {
namespace internal {
+LIBC_INLINE double acos(double x) { return __nv_acos(x); }
LIBC_INLINE float acosf(float x) { return __nv_acosf(x); }
+LIBC_INLINE double acosh(double x) { return __nv_acosh(x); }
LIBC_INLINE float acoshf(float x) { return __nv_acoshf(x); }
+LIBC_INLINE double asin(double x) { return __nv_asin(x); }
LIBC_INLINE float asinf(float x) { return __nv_asinf(x); }
+LIBC_INLINE double asinh(double x) { return __nv_asinh(x); }
LIBC_INLINE float asinhf(float x) { return __nv_asinhf(x); }
+LIBC_INLINE double atan2(double x, double y) { return __nv_atan2(x, y); }
+LIBC_INLINE float atan2f(float x, float y) { return __nv_atan2f(x, y); }
+LIBC_INLINE double atan(double x) { return __nv_atan(x); }
LIBC_INLINE float atanf(float x) { return __nv_atanf(x); }
+LIBC_INLINE double atanh(double x) { return __nv_atanh(x); }
LIBC_INLINE float atanhf(float x) { return __nv_atanhf(x); }
LIBC_INLINE double cos(double x) { return __nv_cos(x); }
LIBC_INLINE float cosf(float x) { return __nv_cosf(x); }
LIBC_INLINE double cosh(double x) { return __nv_cosh(x); }
LIBC_INLINE float coshf(float x) { return __nv_coshf(x); }
+LIBC_INLINE double erf(double x) { return __nv_erf(x); }
+LIBC_INLINE float erff(float x) { return __nv_erff(x); }
LIBC_INLINE float expf(float x) { return __nv_expf(x); }
LIBC_INLINE float exp2f(float x) { return __nv_exp2f(x); }
LIBC_INLINE float exp10f(float x) { return __nv_exp10f(x); }
+LIBC_INLINE double expm1(double x) { return __nv_expm1(x); }
LIBC_INLINE float expm1f(float x) { return __nv_expm1f(x); }
LIBC_INLINE double fdim(double x, double y) { return __nv_fdim(x, y); }
LIBC_INLINE float fdimf(float x, float y) { return __nv_fdimf(x, y); }
@@ -41,6 +52,18 @@ LIBC_INLINE long long llrint(double x) { return __nv_llrint(x); }
LIBC_INLINE long long llrintf(float x) { return __nv_llrintf(x); }
LIBC_INLINE long long llround(double x) { return __nv_llround(x); }
LIBC_INLINE long long llroundf(float x) { return __nv_llroundf(x); }
+LIBC_INLINE double log10(double x) { return __nv_log10(x); }
+LIBC_INLINE float log10f(float x) { return __nv_log10f(x); }
+LIBC_INLINE double log1p(double x) { return __nv_log1p(x); }
+LIBC_INLINE float log1pf(float x) { return __nv_log1pf(x); }
+LIBC_INLINE double log2(double x) { return __nv_log2(x); }
+LIBC_INLINE float log2f(float x) { return __nv_log2f(x); }
+LIBC_INLINE double log(double x) { return __nv_log(x); }
+LIBC_INLINE float logf(float x) { return __nv_logf(x); }
+LIBC_INLINE long lrint(double x) { return __nv_lrint(x); }
+LIBC_INLINE long lrintf(float x) { return __nv_lrintf(x); }
+LIBC_INLINE long lround(double x) { return __nv_lround(x); }
+LIBC_INLINE long lroundf(float x) { return __nv_lroundf(x); }
LIBC_INLINE double nextafter(double x, double y) {
return __nv_nextafter(x, y);
}
@@ -71,6 +94,8 @@ LIBC_INLINE double remquo(double x, double y, int *i) {
LIBC_INLINE float remquof(float x, float y, int *i) {
return __nv_remquof(x, y, i);
}
+LIBC_INLINE double tgamma(double x) { return __nv_tgamma(x); }
+LIBC_INLINE float tgammaf(float x) { return __nv_tgammaf(x); }
} // namespace internal
} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/tgamma.cpp b/libc/src/math/gpu/vendor/tgamma.cpp
new file mode 100644
index 000000000000000..9895c4bfcf55926
--- /dev/null
+++ b/libc/src/math/gpu/vendor/tgamma.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU tgamma function -------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/tgamma.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(double, tgamma, (double x)) { return internal::tgamma(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/gpu/vendor/tgammaf.cpp b/libc/src/math/gpu/vendor/tgammaf.cpp
new file mode 100644
index 000000000000000..9e86dacf36083a9
--- /dev/null
+++ b/libc/src/math/gpu/vendor/tgammaf.cpp
@@ -0,0 +1,18 @@
+//===-- Implementation of the GPU tgammaf function ------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/math/tgammaf.h"
+#include "src/__support/common.h"
+
+#include "common.h"
+
+namespace __llvm_libc {
+
+LLVM_LIBC_FUNCTION(float, tgammaf, (float x)) { return internal::tgammaf(x); }
+
+} // namespace __llvm_libc
diff --git a/libc/src/math/sincos.h b/libc/src/math/sincos.h
new file mode 100644
index 000000000000000..2e3d0673935193f
--- /dev/null
+++ b/libc/src/math/sincos.h
@@ -0,0 +1,18 @@
+//===-- Implementation header for sincos ------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_MATH_SINCOS_H
+#define LLVM_LIBC_SRC_MATH_SINCOS_H
+
+namespace __llvm_libc {
+
+void sincos(double x, double *sinx, double *cosx);
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_MATH_SINCOS_H
diff --git a/libc/src/math/tgamma.h b/libc/src/math/tgamma.h
new file mode 100644
index 000000000000000..295070383f3950c
--- /dev/null
+++ b/libc/src/math/tgamma.h
@@ -0,0 +1,18 @@
+//===-- Implementation header for tgamma ------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_MATH_TGAMMA_H
+#define LLVM_LIBC_SRC_MATH_TGAMMA_H
+
+namespace __llvm_libc {
+
+double tgamma(double x);
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_MATH_TGAMMA_H
diff --git a/libc/src/math/tgammaf.h b/libc/src/math/tgammaf.h
new file mode 100644
index 000000000000000..c098dae4b7ec6bd
--- /dev/null
+++ b/libc/src/math/tgammaf.h
@@ -0,0 +1,18 @@
+//===-- Implementation header for tgammaf -----------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIBC_SRC_MATH_TGAMMAF_H
+#define LLVM_LIBC_SRC_MATH_TGAMMAF_H
+
+namespace __llvm_libc {
+
+float tgammaf(float x);
+
+} // namespace __llvm_libc
+
+#endif // LLVM_LIBC_SRC_MATH_TGAMMAF_H
>From 6e4e47f0ef956e282a9addcc756fc0ce72417109 Mon Sep 17 00:00:00 2001
From: walter erquinigo <walter at modular.com>
Date: Mon, 11 Sep 2023 15:05:13 -0400
Subject: [PATCH 02/35] [LLDB][NFC] Add the mojo language to
Language::GetPrimaryLanguage
This doesn't change the current behavior of the function, but the explicit declaration looks cleaner.
---
lldb/source/Target/Language.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/lldb/source/Target/Language.cpp b/lldb/source/Target/Language.cpp
index 78785352676da31..42c3350806d90f5 100644
--- a/lldb/source/Target/Language.cpp
+++ b/lldb/source/Target/Language.cpp
@@ -374,6 +374,7 @@ LanguageType Language::GetPrimaryLanguage(LanguageType language) {
case eLanguageTypeJulia:
case eLanguageTypeDylan:
case eLanguageTypeMipsAssembler:
+ case eLanguageTypeMojo:
case eLanguageTypeUnknown:
default:
return language;
>From 8716a41e80dbb844ea6bd7e6267ce57d984b0ddd Mon Sep 17 00:00:00 2001
From: Philip Reames <preames at rivosinc.com>
Date: Mon, 11 Sep 2023 13:01:14 -0700
Subject: [PATCH 03/35] [RISCV] Add a combine to form masked.load from unit
strided load (#65674)
Add a DAG combine to form a masked.load from a masked_strided_load
intrinsic with stride equal to element size. This covers a couple of
extra test cases, and allows us to simplify and common some existing
code on the concat_vector(load, ...) to strided load transform.
This is the first in a mini-patch series to try and generalize our
strided load and gather matching to handle more cases, and common up
different approaches to the same problems in different places.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 62 +++++++++----------
.../RISCV/rvv/fixed-vectors-masked-gather.ll | 6 +-
.../rvv/strided-load-store-intrinsics.ll | 3 +-
3 files changed, 32 insertions(+), 39 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4ff264635cda248..1158d14002e1d2a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13371,27 +13371,6 @@ static SDValue performCONCAT_VECTORSCombine(SDNode *N, SelectionDAG &DAG,
return SDValue();
}
- // A special case is if the stride is exactly the width of one of the loads,
- // in which case it's contiguous and can be combined into a regular vle
- // without changing the element size
- if (auto *ConstStride = dyn_cast<ConstantSDNode>(Stride);
- ConstStride && !Reversed &&
- ConstStride->getZExtValue() == BaseLdVT.getFixedSizeInBits() / 8) {
- MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
- BaseLd->getPointerInfo(), BaseLd->getMemOperand()->getFlags(),
- VT.getStoreSize(), Align);
- // Can't do the combine if the load isn't naturally aligned with the element
- // type
- if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(),
- DAG.getDataLayout(), VT, *MMO))
- return SDValue();
-
- SDValue WideLoad = DAG.getLoad(VT, DL, BaseLd->getChain(), BasePtr, MMO);
- for (SDValue Ld : N->ops())
- DAG.makeEquivalentMemoryOrdering(cast<LoadSDNode>(Ld), WideLoad);
- return WideLoad;
- }
-
// Get the widened scalar type, e.g. v4i8 -> i64
unsigned WideScalarBitWidth =
BaseLdVT.getScalarSizeInBits() * BaseLdVT.getVectorNumElements();
@@ -13406,20 +13385,22 @@ static SDValue performCONCAT_VECTORSCombine(SDNode *N, SelectionDAG &DAG,
if (!TLI.isLegalStridedLoadStore(WideVecVT, Align))
return SDValue();
- MVT ContainerVT = TLI.getContainerForFixedLengthVector(WideVecVT);
- SDValue VL =
- getDefaultVLOps(WideVecVT, ContainerVT, DL, DAG, Subtarget).second;
- SDVTList VTs = DAG.getVTList({ContainerVT, MVT::Other});
+ SDVTList VTs = DAG.getVTList({WideVecVT, MVT::Other});
SDValue IntID =
- DAG.getTargetConstant(Intrinsic::riscv_vlse, DL, Subtarget.getXLenVT());
+ DAG.getTargetConstant(Intrinsic::riscv_masked_strided_load, DL,
+ Subtarget.getXLenVT());
if (Reversed)
Stride = DAG.getNegative(Stride, DL, Stride->getValueType(0));
+ SDValue AllOneMask =
+ DAG.getSplat(WideVecVT.changeVectorElementType(MVT::i1), DL,
+ DAG.getConstant(1, DL, MVT::i1));
+
SDValue Ops[] = {BaseLd->getChain(),
IntID,
- DAG.getUNDEF(ContainerVT),
+ DAG.getUNDEF(WideVecVT),
BasePtr,
Stride,
- VL};
+ AllOneMask};
uint64_t MemSize;
if (auto *ConstStride = dyn_cast<ConstantSDNode>(Stride);
@@ -13441,11 +13422,7 @@ static SDValue performCONCAT_VECTORSCombine(SDNode *N, SelectionDAG &DAG,
for (SDValue Ld : N->ops())
DAG.makeEquivalentMemoryOrdering(cast<LoadSDNode>(Ld), StridedLoad);
- // Note: Perform the bitcast before the convertFromScalableVector so we have
- // balanced pairs of convertFromScalable/convertToScalable
- SDValue Res = DAG.getBitcast(
- TLI.getContainerForFixedLengthVector(VT.getSimpleVT()), StridedLoad);
- return convertFromScalableVector(VT, Res, DAG, Subtarget);
+ return DAG.getBitcast(VT.getSimpleVT(), StridedLoad);
}
static SDValue combineToVWMACC(SDNode *N, SelectionDAG &DAG,
@@ -14184,6 +14161,25 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
// By default we do not combine any intrinsic.
default:
return SDValue();
+ case Intrinsic::riscv_masked_strided_load: {
+ MVT VT = N->getSimpleValueType(0);
+ auto *Load = cast<MemIntrinsicSDNode>(N);
+ SDValue PassThru = N->getOperand(2);
+ SDValue Base = N->getOperand(3);
+ SDValue Stride = N->getOperand(4);
+ SDValue Mask = N->getOperand(5);
+
+ // If the stride is equal to the element size in bytes, we can use
+ // a masked.load.
+ const unsigned ElementSize = VT.getScalarStoreSize();
+ if (auto *StrideC = dyn_cast<ConstantSDNode>(Stride);
+ StrideC && StrideC->getZExtValue() == ElementSize)
+ return DAG.getMaskedLoad(VT, DL, Load->getChain(), Base,
+ DAG.getUNDEF(XLenVT), Mask, PassThru,
+ Load->getMemoryVT(), Load->getMemOperand(),
+ ISD::UNINDEXED, ISD::NON_EXTLOAD);
+ return SDValue();
+ }
case Intrinsic::riscv_vcpop:
case Intrinsic::riscv_vcpop_mask:
case Intrinsic::riscv_vfirst:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
index f7352b4659e5a9b..f3af177ac0ff27e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
@@ -13010,9 +13010,8 @@ define <4 x i32> @mgather_broadcast_load_masked(ptr %base, <4 x i1> %m) {
define <4 x i32> @mgather_unit_stride_load(ptr %base) {
; RV32-LABEL: mgather_unit_stride_load:
; RV32: # %bb.0:
-; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT: vlse32.v v8, (a0), a1
+; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: ret
;
; RV64V-LABEL: mgather_unit_stride_load:
@@ -13082,9 +13081,8 @@ define <4 x i32> @mgather_unit_stride_load_with_offset(ptr %base) {
; RV32-LABEL: mgather_unit_stride_load_with_offset:
; RV32: # %bb.0:
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT: vlse32.v v8, (a0), a1
+; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: ret
;
; RV64V-LABEL: mgather_unit_stride_load_with_offset:
diff --git a/llvm/test/CodeGen/RISCV/rvv/strided-load-store-intrinsics.ll b/llvm/test/CodeGen/RISCV/rvv/strided-load-store-intrinsics.ll
index c4653954302796e..06af0fc8971a543 100644
--- a/llvm/test/CodeGen/RISCV/rvv/strided-load-store-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/strided-load-store-intrinsics.ll
@@ -55,9 +55,8 @@ define <32 x i8> @strided_load_i8_nostride(ptr %p, <32 x i1> %m) {
; CHECK-LABEL: strided_load_i8_nostride:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32
-; CHECK-NEXT: li a2, 1
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT: vlse8.v v8, (a0), a2, v0.t
+; CHECK-NEXT: vle8.v v8, (a0), v0.t
; CHECK-NEXT: ret
%res = call <32 x i8> @llvm.riscv.masked.strided.load.v32i8.p0.i64(<32 x i8> undef, ptr %p, i64 1, <32 x i1> %m)
ret <32 x i8> %res
>From 9969f958332f86cf3cd63decde4a4242314d0908 Mon Sep 17 00:00:00 2001
From: Vitaly Buka <vitalybuka at google.com>
Date: Mon, 11 Sep 2023 13:18:28 -0700
Subject: [PATCH 04/35] [test][tsan] Disable flaky test on PPC
COMPILER_RT_DEBUG was just added to sanitizer-ppc64le-linux, and this
test is already broken there.
---
compiler-rt/test/tsan/signal_thread2.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/compiler-rt/test/tsan/signal_thread2.cpp b/compiler-rt/test/tsan/signal_thread2.cpp
index a773058b2cf956d..9bde4f70b39d816 100644
--- a/compiler-rt/test/tsan/signal_thread2.cpp
+++ b/compiler-rt/test/tsan/signal_thread2.cpp
@@ -1,6 +1,9 @@
// RUN: %clangxx_tsan %s -o %t && %run %t 2>&1 | FileCheck %s
// UNSUPPORTED: darwin
+// It's very flaky on PPC with COMPILER_RT_DEBUG.
+// UNSUPPORTED: !compiler-rt-optimized && ppc
+
// Test case for https://github.com/google/sanitizers/issues/1540
#include <errno.h>
>From 82f0005eaba417fea7d49be3604e4ca85e792591 Mon Sep 17 00:00:00 2001
From: Mehdi Amini <joker.eph at gmail.com>
Date: Mon, 11 Sep 2023 13:22:35 -0700
Subject: [PATCH 05/35] Lazy initialize diagnostic when handling MLIR
properties (#65868)
Instead of eagerly creating a diagnostic that will be discarded in the
normal case, switch to lazy initialization on error.
---
mlir/include/mlir/IR/ExtensibleDialect.h | 9 +++--
mlir/include/mlir/IR/ODSSupport.h | 17 +++++---
mlir/include/mlir/IR/OpDefinition.h | 7 ++--
mlir/include/mlir/IR/Operation.h | 5 ++-
mlir/include/mlir/IR/OperationSupport.h | 39 +++++++++---------
mlir/include/mlir/IR/Properties.td | 2 +-
mlir/lib/AsmParser/Parser.cpp | 34 +++++++++++-----
mlir/lib/CAPI/IR/IR.cpp | 23 ++++++-----
mlir/lib/IR/MLIRContext.cpp | 2 +-
mlir/lib/IR/ODSSupport.cpp | 41 +++++++++----------
mlir/lib/IR/Operation.cpp | 7 ++--
mlir/lib/IR/OperationSupport.cpp | 7 ++--
mlir/test/lib/Dialect/Test/TestDialect.cpp | 44 ++++++++++-----------
mlir/test/lib/Dialect/Test/TestDialect.h | 6 +--
mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp | 22 +++++------
mlir/unittests/IR/OpPropertiesTest.cpp | 28 +++++++------
16 files changed, 155 insertions(+), 138 deletions(-)
diff --git a/mlir/include/mlir/IR/ExtensibleDialect.h b/mlir/include/mlir/IR/ExtensibleDialect.h
index e4d8d2d6000fc60..37821d3a2a5163f 100644
--- a/mlir/include/mlir/IR/ExtensibleDialect.h
+++ b/mlir/include/mlir/IR/ExtensibleDialect.h
@@ -486,10 +486,11 @@ class DynamicOpDefinition : public OperationName::Impl {
void populateDefaultProperties(OperationName opName,
OpaqueProperties properties) final {}
- LogicalResult setPropertiesFromAttr(OperationName opName,
- OpaqueProperties properties,
- Attribute attr,
- InFlightDiagnostic *diag) final {
+ LogicalResult
+ setPropertiesFromAttr(OperationName opName, OpaqueProperties properties,
+ Attribute attr,
+ function_ref<InFlightDiagnostic &()> getDiag) final {
+ getDiag() << "extensible Dialects don't support properties";
return failure();
}
Attribute getPropertiesAsAttr(Operation *op) final { return {}; }
diff --git a/mlir/include/mlir/IR/ODSSupport.h b/mlir/include/mlir/IR/ODSSupport.h
index 687f764ae95fd99..748bf52a55c557a 100644
--- a/mlir/include/mlir/IR/ODSSupport.h
+++ b/mlir/include/mlir/IR/ODSSupport.h
@@ -14,6 +14,8 @@
#define MLIR_IR_ODSSUPPORT_H
#include "mlir/IR/Attributes.h"
+#include "mlir/IR/MLIRContext.h"
+#include "mlir/Support/LLVM.h"
namespace mlir {
@@ -24,8 +26,9 @@ namespace mlir {
/// Convert an IntegerAttr attribute to an int64_t, or return an error if the
/// attribute isn't an IntegerAttr. If the optional diagnostic is provided an
/// error message is also emitted.
-LogicalResult convertFromAttribute(int64_t &storage, Attribute attr,
- InFlightDiagnostic *diag);
+LogicalResult
+convertFromAttribute(int64_t &storage, Attribute attr,
+ function_ref<InFlightDiagnostic &()> getDiag);
/// Convert the provided int64_t to an IntegerAttr attribute.
Attribute convertToAttribute(MLIRContext *ctx, int64_t storage);
@@ -34,15 +37,17 @@ Attribute convertToAttribute(MLIRContext *ctx, int64_t storage);
/// storage has the same size as the array. An error is returned if the
/// attribute isn't a DenseI64ArrayAttr or it does not have the same size. If
/// the optional diagnostic is provided an error message is also emitted.
-LogicalResult convertFromAttribute(MutableArrayRef<int64_t> storage,
- Attribute attr, InFlightDiagnostic *diag);
+LogicalResult
+convertFromAttribute(MutableArrayRef<int64_t> storage, Attribute attr,
+ function_ref<InFlightDiagnostic &()> getDiag);
/// Convert a DenseI32ArrayAttr to the provided storage. It is expected that the
/// storage has the same size as the array. An error is returned if the
/// attribute isn't a DenseI32ArrayAttr or it does not have the same size. If
/// the optional diagnostic is provided an error message is also emitted.
-LogicalResult convertFromAttribute(MutableArrayRef<int32_t> storage,
- Attribute attr, InFlightDiagnostic *diag);
+LogicalResult
+convertFromAttribute(MutableArrayRef<int32_t> storage, Attribute attr,
+ function_ref<InFlightDiagnostic &()> getDiag);
/// Convert the provided ArrayRef<int64_t> to a DenseI64ArrayAttr attribute.
Attribute convertToAttribute(MLIRContext *ctx, ArrayRef<int64_t> storage);
diff --git a/mlir/include/mlir/IR/OpDefinition.h b/mlir/include/mlir/IR/OpDefinition.h
index 84ba46f4d6f3ec1..895f17dfe1d07c8 100644
--- a/mlir/include/mlir/IR/OpDefinition.h
+++ b/mlir/include/mlir/IR/OpDefinition.h
@@ -1769,9 +1769,10 @@ class Op : public OpState, public Traits<ConcreteType>... {
/// the namespace where the properties are defined. It can also be overridden
/// in the derived ConcreteOp.
template <typename PropertiesTy>
- static LogicalResult setPropertiesFromAttr(PropertiesTy &prop, Attribute attr,
- InFlightDiagnostic *diag) {
- return setPropertiesFromAttribute(prop, attr, diag);
+ static LogicalResult
+ setPropertiesFromAttr(PropertiesTy &prop, Attribute attr,
+ function_ref<InFlightDiagnostic &()> getDiag) {
+ return setPropertiesFromAttribute(prop, attr, getDiag);
}
/// Convert the provided properties to an attribute. This default
/// implementation forwards to a free function `getPropertiesAsAttribute` that
diff --git a/mlir/include/mlir/IR/Operation.h b/mlir/include/mlir/IR/Operation.h
index 361a38e87b6ba32..b815eaf8899d6fc 100644
--- a/mlir/include/mlir/IR/Operation.h
+++ b/mlir/include/mlir/IR/Operation.h
@@ -882,8 +882,9 @@ class alignas(8) Operation final
/// matching the expectations of the properties for this operation. This is
/// mostly useful for unregistered operations or used when parsing the
/// generic format. An optional diagnostic can be passed in for richer errors.
- LogicalResult setPropertiesFromAttribute(Attribute attr,
- InFlightDiagnostic *diagnostic);
+ LogicalResult
+ setPropertiesFromAttribute(Attribute attr,
+ function_ref<InFlightDiagnostic &()> getDiag);
/// Copy properties from an existing other properties object. The two objects
/// must be the same type.
diff --git a/mlir/include/mlir/IR/OperationSupport.h b/mlir/include/mlir/IR/OperationSupport.h
index 670dd289c480a30..19ffddc30904897 100644
--- a/mlir/include/mlir/IR/OperationSupport.h
+++ b/mlir/include/mlir/IR/OperationSupport.h
@@ -136,9 +136,9 @@ class OperationName {
virtual void deleteProperties(OpaqueProperties) = 0;
virtual void populateDefaultProperties(OperationName opName,
OpaqueProperties properties) = 0;
- virtual LogicalResult setPropertiesFromAttr(OperationName, OpaqueProperties,
- Attribute,
- InFlightDiagnostic *) = 0;
+ virtual LogicalResult
+ setPropertiesFromAttr(OperationName, OpaqueProperties, Attribute,
+ function_ref<InFlightDiagnostic &()> getDiag) = 0;
virtual Attribute getPropertiesAsAttr(Operation *) = 0;
virtual void copyProperties(OpaqueProperties, OpaqueProperties) = 0;
virtual llvm::hash_code hashProperties(OpaqueProperties) = 0;
@@ -216,8 +216,9 @@ class OperationName {
void deleteProperties(OpaqueProperties) final;
void populateDefaultProperties(OperationName opName,
OpaqueProperties properties) final;
- LogicalResult setPropertiesFromAttr(OperationName, OpaqueProperties,
- Attribute, InFlightDiagnostic *) final;
+ LogicalResult
+ setPropertiesFromAttr(OperationName, OpaqueProperties, Attribute,
+ function_ref<InFlightDiagnostic &()> getDiag) final;
Attribute getPropertiesAsAttr(Operation *) final;
void copyProperties(OpaqueProperties, OpaqueProperties) final;
llvm::hash_code hashProperties(OpaqueProperties) final;
@@ -434,12 +435,10 @@ class OperationName {
}
/// Define the op properties from the provided Attribute.
- LogicalResult
- setOpPropertiesFromAttribute(OperationName opName,
- OpaqueProperties properties, Attribute attr,
- InFlightDiagnostic *diagnostic) const {
- return getImpl()->setPropertiesFromAttr(opName, properties, attr,
- diagnostic);
+ LogicalResult setOpPropertiesFromAttribute(
+ OperationName opName, OpaqueProperties properties, Attribute attr,
+ function_ref<InFlightDiagnostic &()> getDiag) const {
+ return getImpl()->setPropertiesFromAttr(opName, properties, attr, getDiag);
}
void copyOpProperties(OpaqueProperties lhs, OpaqueProperties rhs) const {
@@ -628,16 +627,15 @@ class RegisteredOperationName : public OperationName {
*properties.as<Properties *>());
}
- LogicalResult setPropertiesFromAttr(OperationName opName,
- OpaqueProperties properties,
- Attribute attr,
- InFlightDiagnostic *diag) final {
+ LogicalResult
+ setPropertiesFromAttr(OperationName opName, OpaqueProperties properties,
+ Attribute attr,
+ function_ref<InFlightDiagnostic &()> getDiag) final {
if constexpr (hasProperties) {
auto p = properties.as<Properties *>();
- return ConcreteOp::setPropertiesFromAttr(*p, attr, diag);
+ return ConcreteOp::setPropertiesFromAttr(*p, attr, getDiag);
}
- if (diag)
- *diag << "This operation does not support properties";
+ getDiag() << "this operation does not support properties";
return failure();
}
Attribute getPropertiesAsAttr(Operation *op) final {
@@ -997,8 +995,9 @@ struct OperationState {
// Set the properties defined on this OpState on the given operation,
// optionally emit diagnostics on error through the provided diagnostic.
- LogicalResult setProperties(Operation *op,
- InFlightDiagnostic *diagnostic) const;
+ LogicalResult
+ setProperties(Operation *op,
+ function_ref<InFlightDiagnostic &()> getDiag) const;
void addOperands(ValueRange newOperands);
diff --git a/mlir/include/mlir/IR/Properties.td b/mlir/include/mlir/IR/Properties.td
index 3d7de7e4f460e51..99da1763524fa94 100644
--- a/mlir/include/mlir/IR/Properties.td
+++ b/mlir/include/mlir/IR/Properties.td
@@ -55,7 +55,7 @@ class Property<string storageTypeParam = "", string desc = ""> {
// Format:
// - `$_storage` is the storage type value.
// - `$_attr` is the attribute.
- // - `$_diag` is an optional Diagnostic pointer to emit error.
+ // - `$_diag` is a callback to get a Diagnostic to emit error.
//
// The expression must return a LogicalResult
code convertFromAttribute = [{
diff --git a/mlir/lib/AsmParser/Parser.cpp b/mlir/lib/AsmParser/Parser.cpp
index 02bf9a418063991..84f44dba806df01 100644
--- a/mlir/lib/AsmParser/Parser.cpp
+++ b/mlir/lib/AsmParser/Parser.cpp
@@ -18,8 +18,10 @@
#include "mlir/IR/AffineMap.h"
#include "mlir/IR/AsmState.h"
#include "mlir/IR/BuiltinOps.h"
+#include "mlir/IR/Diagnostics.h"
#include "mlir/IR/Dialect.h"
#include "mlir/IR/Verifier.h"
+#include "mlir/Support/InterfaceSupport.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/ScopeExit.h"
#include "llvm/ADT/StringSet.h"
@@ -29,6 +31,7 @@
#include "llvm/Support/PrettyStackTrace.h"
#include "llvm/Support/SourceMgr.h"
#include <algorithm>
+#include <memory>
#include <optional>
using namespace mlir;
@@ -1443,12 +1446,17 @@ Operation *OperationParser::parseGenericOperation() {
// Try setting the properties for the operation, using a diagnostic to print
// errors.
if (properties) {
- InFlightDiagnostic diagnostic =
- mlir::emitError(srcLocation, "invalid properties ")
- << properties << " for op " << name << ": ";
- if (failed(op->setPropertiesFromAttribute(properties, &diagnostic)))
+ std::unique_ptr<InFlightDiagnostic> diagnostic;
+ auto getDiag = [&]() -> InFlightDiagnostic & {
+ if (!diagnostic) {
+ diagnostic = std::make_unique<InFlightDiagnostic>(
+ mlir::emitError(srcLocation, "invalid properties ")
+ << properties << " for op " << name << ": ");
+ }
+ return *diagnostic;
+ };
+ if (failed(op->setPropertiesFromAttribute(properties, getDiag)))
return nullptr;
- diagnostic.abandon();
}
return op;
@@ -2001,12 +2009,18 @@ OperationParser::parseCustomOperation(ArrayRef<ResultRecord> resultIDs) {
// Try setting the properties for the operation.
if (properties) {
- InFlightDiagnostic diagnostic =
- mlir::emitError(srcLocation, "invalid properties ")
- << properties << " for op " << op->getName().getStringRef() << ": ";
- if (failed(op->setPropertiesFromAttribute(properties, &diagnostic)))
+ std::unique_ptr<InFlightDiagnostic> diagnostic;
+ auto getDiag = [&]() -> InFlightDiagnostic & {
+ if (!diagnostic) {
+ diagnostic = std::make_unique<InFlightDiagnostic>(
+ mlir::emitError(srcLocation, "invalid properties ")
+ << properties << " for op " << op->getName().getStringRef()
+ << ": ");
+ }
+ return *diagnostic;
+ };
+ if (failed(op->setPropertiesFromAttribute(properties, getDiag)))
return nullptr;
- diagnostic.abandon();
}
return op;
}
diff --git a/mlir/lib/CAPI/IR/IR.cpp b/mlir/lib/CAPI/IR/IR.cpp
index ccdae1424998567..ef234a912490eea 100644
--- a/mlir/lib/CAPI/IR/IR.cpp
+++ b/mlir/lib/CAPI/IR/IR.cpp
@@ -370,16 +370,21 @@ static LogicalResult inferOperationTypes(OperationState &state) {
if (!properties && info->getOpPropertyByteSize() > 0 && !attributes.empty()) {
auto prop = std::make_unique<char[]>(info->getOpPropertyByteSize());
properties = OpaqueProperties(prop.get());
- InFlightDiagnostic diag = emitError(state.location)
- << " failed properties conversion while building "
- << state.name.getStringRef() << " with `"
- << attributes << "`: ";
- if (failed(info->setOpPropertiesFromAttribute(state.name, properties,
- attributes, &diag))) {
- return failure();
+ if (properties) {
+ std::unique_ptr<InFlightDiagnostic> diagnostic;
+ auto getDiag = [&]() -> InFlightDiagnostic & {
+ if (!diagnostic) {
+ diagnostic = std::make_unique<InFlightDiagnostic>(
+ emitError(state.location)
+ << " failed properties conversion while building "
+ << state.name.getStringRef() << " with `" << attributes << "`: ");
+ }
+ return *diagnostic;
+ };
+ if (failed(info->setOpPropertiesFromAttribute(state.name, properties,
+ attributes, getDiag)))
+ return failure();
}
- diag.abandon();
-
if (succeeded(inferInterface->inferReturnTypes(
context, state.location, state.operands, attributes, properties,
state.regions, state.types))) {
diff --git a/mlir/lib/IR/MLIRContext.cpp b/mlir/lib/IR/MLIRContext.cpp
index e19c3d4d54179b3..5f1d036d22b918e 100644
--- a/mlir/lib/IR/MLIRContext.cpp
+++ b/mlir/lib/IR/MLIRContext.cpp
@@ -852,7 +852,7 @@ void OperationName::UnregisteredOpModel::populateDefaultProperties(
OperationName opName, OpaqueProperties properties) {}
LogicalResult OperationName::UnregisteredOpModel::setPropertiesFromAttr(
OperationName opName, OpaqueProperties properties, Attribute attr,
- InFlightDiagnostic *diag) {
+ function_ref<InFlightDiagnostic &()> getDiag) {
*properties.as<Attribute *>() = attr;
return success();
}
diff --git a/mlir/lib/IR/ODSSupport.cpp b/mlir/lib/IR/ODSSupport.cpp
index f67e7dbf38592e2..0601430c4461651 100644
--- a/mlir/lib/IR/ODSSupport.cpp
+++ b/mlir/lib/IR/ODSSupport.cpp
@@ -18,13 +18,12 @@
using namespace mlir;
-LogicalResult mlir::convertFromAttribute(int64_t &storage,
- ::mlir::Attribute attr,
- ::mlir::InFlightDiagnostic *diag) {
+LogicalResult
+mlir::convertFromAttribute(int64_t &storage, Attribute attr,
+ function_ref<InFlightDiagnostic &()> getDiag) {
auto valueAttr = dyn_cast<IntegerAttr>(attr);
if (!valueAttr) {
- if (diag)
- *diag << "expected IntegerAttr for key `value`";
+ getDiag() << "expected IntegerAttr for key `value`";
return failure();
}
storage = valueAttr.getValue().getSExtValue();
@@ -35,35 +34,33 @@ Attribute mlir::convertToAttribute(MLIRContext *ctx, int64_t storage) {
}
template <typename DenseArrayTy, typename T>
-LogicalResult convertDenseArrayFromAttr(MutableArrayRef<T> storage,
- ::mlir::Attribute attr,
- ::mlir::InFlightDiagnostic *diag,
- StringRef denseArrayTyStr) {
+LogicalResult
+convertDenseArrayFromAttr(MutableArrayRef<T> storage, Attribute attr,
+ function_ref<InFlightDiagnostic &()> getDiag,
+ StringRef denseArrayTyStr) {
auto valueAttr = dyn_cast<DenseArrayTy>(attr);
if (!valueAttr) {
- if (diag)
- *diag << "expected " << denseArrayTyStr << " for key `value`";
+ getDiag() << "expected " << denseArrayTyStr << " for key `value`";
return failure();
}
if (valueAttr.size() != static_cast<int64_t>(storage.size())) {
- if (diag)
- *diag << "size mismatch in attribute conversion: " << valueAttr.size()
- << " vs " << storage.size();
+ getDiag() << "size mismatch in attribute conversion: " << valueAttr.size()
+ << " vs " << storage.size();
return failure();
}
llvm::copy(valueAttr.asArrayRef(), storage.begin());
return success();
}
-LogicalResult mlir::convertFromAttribute(MutableArrayRef<int64_t> storage,
- ::mlir::Attribute attr,
- ::mlir::InFlightDiagnostic *diag) {
- return convertDenseArrayFromAttr<DenseI64ArrayAttr>(storage, attr, diag,
+LogicalResult
+mlir::convertFromAttribute(MutableArrayRef<int64_t> storage, Attribute attr,
+ function_ref<InFlightDiagnostic &()> getDiag) {
+ return convertDenseArrayFromAttr<DenseI64ArrayAttr>(storage, attr, getDiag,
"DenseI64ArrayAttr");
}
-LogicalResult mlir::convertFromAttribute(MutableArrayRef<int32_t> storage,
- Attribute attr,
- InFlightDiagnostic *diag) {
- return convertDenseArrayFromAttr<DenseI32ArrayAttr>(storage, attr, diag,
+LogicalResult
+mlir::convertFromAttribute(MutableArrayRef<int32_t> storage, Attribute attr,
+ function_ref<InFlightDiagnostic &()> getDiag) {
+ return convertDenseArrayFromAttr<DenseI32ArrayAttr>(storage, attr, getDiag,
"DenseI32ArrayAttr");
}
diff --git a/mlir/lib/IR/Operation.cpp b/mlir/lib/IR/Operation.cpp
index ef98a89f4bb49b6..aa577aa089c6860 100644
--- a/mlir/lib/IR/Operation.cpp
+++ b/mlir/lib/IR/Operation.cpp
@@ -351,16 +351,15 @@ Attribute Operation::getPropertiesAsAttribute() {
return *getPropertiesStorage().as<Attribute *>();
return info->getOpPropertiesAsAttribute(this);
}
-LogicalResult
-Operation::setPropertiesFromAttribute(Attribute attr,
- InFlightDiagnostic *diagnostic) {
+LogicalResult Operation::setPropertiesFromAttribute(
+ Attribute attr, function_ref<InFlightDiagnostic &()> getDiag) {
std::optional<RegisteredOperationName> info = getRegisteredInfo();
if (LLVM_UNLIKELY(!info)) {
*getPropertiesStorage().as<Attribute *>() = attr;
return success();
}
return info->setOpPropertiesFromAttribute(
- this->getName(), this->getPropertiesStorage(), attr, diagnostic);
+ this->getName(), this->getPropertiesStorage(), attr, getDiag);
}
void Operation::copyProperties(OpaqueProperties rhs) {
diff --git a/mlir/lib/IR/OperationSupport.cpp b/mlir/lib/IR/OperationSupport.cpp
index 79cc38da051ee1d..0cb6a1cd191b161 100644
--- a/mlir/lib/IR/OperationSupport.cpp
+++ b/mlir/lib/IR/OperationSupport.cpp
@@ -198,12 +198,11 @@ OperationState::~OperationState() {
propertiesDeleter(properties);
}
-LogicalResult
-OperationState::setProperties(Operation *op,
- InFlightDiagnostic *diagnostic) const {
+LogicalResult OperationState::setProperties(
+ Operation *op, function_ref<InFlightDiagnostic &()> getDiag) const {
if (LLVM_UNLIKELY(propertiesAttr)) {
assert(!properties);
- return op->setPropertiesFromAttribute(propertiesAttr, diagnostic);
+ return op->setPropertiesFromAttribute(propertiesAttr, getDiag);
}
if (properties)
propertiesSetter(op->getPropertiesStorage(), properties);
diff --git a/mlir/test/lib/Dialect/Test/TestDialect.cpp b/mlir/test/lib/Dialect/Test/TestDialect.cpp
index ae4c9a85605e1c5..55cf4246562e6af 100644
--- a/mlir/test/lib/Dialect/Test/TestDialect.cpp
+++ b/mlir/test/lib/Dialect/Test/TestDialect.cpp
@@ -28,9 +28,11 @@
#include "mlir/Interfaces/CallInterfaces.h"
#include "mlir/Interfaces/FunctionImplementation.h"
#include "mlir/Interfaces/InferIntRangeInterface.h"
+#include "mlir/Support/LLVM.h"
#include "mlir/Support/LogicalResult.h"
#include "mlir/Transforms/FoldUtils.h"
#include "mlir/Transforms/InliningUtils.h"
+#include "llvm/ADT/STLFunctionalExtras.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringSwitch.h"
@@ -50,12 +52,12 @@ using namespace test;
Attribute MyPropStruct::asAttribute(MLIRContext *ctx) const {
return StringAttr::get(ctx, content);
}
-LogicalResult MyPropStruct::setFromAttr(MyPropStruct &prop, Attribute attr,
- InFlightDiagnostic *diag) {
+LogicalResult
+MyPropStruct::setFromAttr(MyPropStruct &prop, Attribute attr,
+ function_ref<InFlightDiagnostic &()> getDiag) {
StringAttr strAttr = dyn_cast<StringAttr>(attr);
if (!strAttr) {
- if (diag)
- *diag << "Expect StringAttr but got " << attr;
+ getDiag() << "Expect StringAttr but got " << attr;
return failure();
}
prop.content = strAttr.getValue();
@@ -103,9 +105,9 @@ static void writeToMlirBytecode(::mlir::DialectBytecodeWriter &writer,
writer.writeVarInt(elt);
}
-static LogicalResult setPropertiesFromAttribute(PropertiesWithCustomPrint &prop,
- Attribute attr,
- InFlightDiagnostic *diagnostic);
+static LogicalResult
+setPropertiesFromAttribute(PropertiesWithCustomPrint &prop, Attribute attr,
+ function_ref<InFlightDiagnostic &()> getDiag);
static DictionaryAttr
getPropertiesAsAttribute(MLIRContext *ctx,
const PropertiesWithCustomPrint &prop);
@@ -114,9 +116,9 @@ static void customPrintProperties(OpAsmPrinter &p,
const PropertiesWithCustomPrint &prop);
static ParseResult customParseProperties(OpAsmParser &parser,
PropertiesWithCustomPrint &prop);
-static LogicalResult setPropertiesFromAttribute(VersionedProperties &prop,
- Attribute attr,
- InFlightDiagnostic *diagnostic);
+static LogicalResult
+setPropertiesFromAttribute(VersionedProperties &prop, Attribute attr,
+ function_ref<InFlightDiagnostic &()> getDiag);
static DictionaryAttr getPropertiesAsAttribute(MLIRContext *ctx,
const VersionedProperties &prop);
static llvm::hash_code computeHash(const VersionedProperties &prop);
@@ -1135,23 +1137,20 @@ OpFoldResult ManualCppOpWithFold::fold(ArrayRef<Attribute> attributes) {
static LogicalResult
setPropertiesFromAttribute(PropertiesWithCustomPrint &prop, Attribute attr,
- InFlightDiagnostic *diagnostic) {
+ function_ref<InFlightDiagnostic &()> getDiag) {
DictionaryAttr dict = dyn_cast<DictionaryAttr>(attr);
if (!dict) {
- if (diagnostic)
- *diagnostic << "expected DictionaryAttr to set TestProperties";
+ getDiag() << "expected DictionaryAttr to set TestProperties";
return failure();
}
auto label = dict.getAs<mlir::StringAttr>("label");
if (!label) {
- if (diagnostic)
- *diagnostic << "expected StringAttr for key `label`";
+ getDiag() << "expected StringAttr for key `label`";
return failure();
}
auto valueAttr = dict.getAs<IntegerAttr>("value");
if (!valueAttr) {
- if (diagnostic)
- *diagnostic << "expected IntegerAttr for key `value`";
+ getDiag() << "expected IntegerAttr for key `value`";
return failure();
}
@@ -1187,23 +1186,20 @@ static ParseResult customParseProperties(OpAsmParser &parser,
}
static LogicalResult
setPropertiesFromAttribute(VersionedProperties &prop, Attribute attr,
- InFlightDiagnostic *diagnostic) {
+ function_ref<InFlightDiagnostic &()> getDiag) {
DictionaryAttr dict = dyn_cast<DictionaryAttr>(attr);
if (!dict) {
- if (diagnostic)
- *diagnostic << "expected DictionaryAttr to set VersionedProperties";
+ getDiag() << "expected DictionaryAttr to set VersionedProperties";
return failure();
}
auto value1Attr = dict.getAs<IntegerAttr>("value1");
if (!value1Attr) {
- if (diagnostic)
- *diagnostic << "expected IntegerAttr for key `value1`";
+ getDiag() << "expected IntegerAttr for key `value1`";
return failure();
}
auto value2Attr = dict.getAs<IntegerAttr>("value2");
if (!value2Attr) {
- if (diagnostic)
- *diagnostic << "expected IntegerAttr for key `value2`";
+ getDiag() << "expected IntegerAttr for key `value2`";
return failure();
}
diff --git a/mlir/test/lib/Dialect/Test/TestDialect.h b/mlir/test/lib/Dialect/Test/TestDialect.h
index 31a29cc7f9f7aa6..0ae0d47615776dd 100644
--- a/mlir/test/lib/Dialect/Test/TestDialect.h
+++ b/mlir/test/lib/Dialect/Test/TestDialect.h
@@ -93,9 +93,9 @@ class MyPropStruct {
// These three methods are invoked through the `MyStructProperty` wrapper
// defined in TestOps.td
mlir::Attribute asAttribute(mlir::MLIRContext *ctx) const;
- static mlir::LogicalResult setFromAttr(MyPropStruct &prop,
- mlir::Attribute attr,
- mlir::InFlightDiagnostic *diag);
+ static mlir::LogicalResult
+ setFromAttr(MyPropStruct &prop, mlir::Attribute attr,
+ llvm::function_ref<mlir::InFlightDiagnostic &()> getDiag);
llvm::hash_code hash() const;
bool operator==(const MyPropStruct &rhs) const {
return content == rhs.content;
diff --git a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
index c0dfce553905a0e..ad4f53c5af3cff4 100644
--- a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
+++ b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
@@ -52,7 +52,7 @@ static const char *const builderOpState = "odsState";
static const char *const propertyStorage = "propStorage";
static const char *const propertyValue = "propValue";
static const char *const propertyAttr = "propAttr";
-static const char *const propertyDiag = "propDiag";
+static const char *const propertyDiag = "getDiag";
/// The names of the implicit attributes that contain variadic operand and
/// result segment sizes.
@@ -1212,7 +1212,9 @@ void OpEmitter::genPropertiesSupport() {
"::mlir::LogicalResult", "setPropertiesFromAttr",
MethodParameter("Properties &", "prop"),
MethodParameter("::mlir::Attribute", "attr"),
- MethodParameter("::mlir::InFlightDiagnostic *", "diag"))
+ MethodParameter(
+ "::llvm::function_ref<::mlir::InFlightDiagnostic &()>",
+ "getDiag"))
->body();
auto &getPropMethod =
opClass
@@ -1264,8 +1266,7 @@ void OpEmitter::genPropertiesSupport() {
setPropMethod << R"decl(
::mlir::DictionaryAttr dict = ::llvm::dyn_cast<::mlir::DictionaryAttr>(attr);
if (!dict) {
- if (diag)
- *diag << "expected DictionaryAttr to set properties";
+ getDiag() << "expected DictionaryAttr to set properties";
return ::mlir::failure();
}
)decl";
@@ -1273,17 +1274,16 @@ void OpEmitter::genPropertiesSupport() {
const char *propFromAttrFmt = R"decl(;
{{
auto setFromAttr = [] (auto &propStorage, ::mlir::Attribute propAttr,
- ::mlir::InFlightDiagnostic *propDiag) {{
+ ::llvm::function_ref<::mlir::InFlightDiagnostic &()> getDiag) {{
{0};
};
{2};
if (!attr) {{
- if (diag)
- *diag << "expected key entry for {1} in DictionaryAttr to set "
+ getDiag() << "expected key entry for {1} in DictionaryAttr to set "
"Properties.";
return ::mlir::failure();
}
- if (::mlir::failed(setFromAttr(prop.{1}, attr, diag)))
+ if (::mlir::failed(setFromAttr(prop.{1}, attr, getDiag)))
return ::mlir::failure();
}
)decl";
@@ -1338,8 +1338,7 @@ void OpEmitter::genPropertiesSupport() {
{2}
if (attr || /*isRequired=*/{1}) {{
if (!attr) {{
- if (diag)
- *diag << "expected key entry for {0} in DictionaryAttr to set "
+ getDiag() << "expected key entry for {0} in DictionaryAttr to set "
"Properties.";
return ::mlir::failure();
}
@@ -1347,8 +1346,7 @@ void OpEmitter::genPropertiesSupport() {
if (convertedAttr) {{
propStorage = convertedAttr;
} else {{
- if (diag)
- *diag << "Invalid attribute `{0}` in property conversion: " << attr;
+ getDiag() << "Invalid attribute `{0}` in property conversion: " << attr;
return ::mlir::failure();
}
}
diff --git a/mlir/unittests/IR/OpPropertiesTest.cpp b/mlir/unittests/IR/OpPropertiesTest.cpp
index 21ea4488e7190f8..2d272dfb558c81c 100644
--- a/mlir/unittests/IR/OpPropertiesTest.cpp
+++ b/mlir/unittests/IR/OpPropertiesTest.cpp
@@ -33,38 +33,33 @@ struct TestProperties {
/// parsing with the generic format.
static LogicalResult
setPropertiesFromAttribute(TestProperties &prop, Attribute attr,
- InFlightDiagnostic *diagnostic) {
+ function_ref<InFlightDiagnostic &()> getDiag) {
DictionaryAttr dict = dyn_cast<DictionaryAttr>(attr);
if (!dict) {
- if (diagnostic)
- *diagnostic << "expected DictionaryAttr to set TestProperties";
+ getDiag() << "expected DictionaryAttr to set TestProperties";
return failure();
}
auto aAttr = dict.getAs<IntegerAttr>("a");
if (!aAttr) {
- if (diagnostic)
- *diagnostic << "expected IntegerAttr for key `a`";
+ getDiag() << "expected IntegerAttr for key `a`";
return failure();
}
auto bAttr = dict.getAs<FloatAttr>("b");
if (!bAttr ||
&bAttr.getValue().getSemantics() != &llvm::APFloatBase::IEEEsingle()) {
- if (diagnostic)
- *diagnostic << "expected FloatAttr for key `b`";
+ getDiag() << "expected FloatAttr for key `b`";
return failure();
}
auto arrayAttr = dict.getAs<DenseI64ArrayAttr>("array");
if (!arrayAttr) {
- if (diagnostic)
- *diagnostic << "expected DenseI64ArrayAttr for key `array`";
+ getDiag() << "expected DenseI64ArrayAttr for key `array`";
return failure();
}
auto label = dict.getAs<mlir::StringAttr>("label");
if (!label) {
- if (diagnostic)
- *diagnostic << "expected StringAttr for key `label`";
+ getDiag() << "expected StringAttr for key `label`";
return failure();
}
@@ -257,8 +252,15 @@ TEST(OpPropertiesTest, FailedProperties) {
attrs.push_back(b.getNamedAttr("a", b.getStringAttr("foo")));
state.propertiesAttr = attrs.getDictionary(&context);
{
- auto diag = op->emitError("setting properties failed: ");
- auto result = state.setProperties(op, &diag);
+ std::unique_ptr<InFlightDiagnostic> diagnostic;
+ auto getDiag = [&]() -> InFlightDiagnostic & {
+ if (!diagnostic) {
+ diagnostic = std::make_unique<InFlightDiagnostic>(
+ op->emitError("setting properties failed: "));
+ }
+ return *diagnostic;
+ };
+ auto result = state.setProperties(op, getDiag);
EXPECT_TRUE(result.failed());
}
EXPECT_STREQ("setting properties failed: expected IntegerAttr for key `a`",
>From 5872841705c0f35879dbcdaad95d06cfcb5b97d3 Mon Sep 17 00:00:00 2001
From: Vitaly Buka <vitalybuka at google.com>
Date: Mon, 11 Sep 2023 13:27:01 -0700
Subject: [PATCH 06/35] [sanitizer] Change return type of
__sanitizer_symbolize_demangle to bool (#65991)
To match other internal symbolizer functions.
This makes harder to distighush small buffer from a different failure,
but we has the same problem for the rest of the lib.
Still we use 16k buffer so it should be enough most of the time.
We can fix all function togerher if future, if needed.
---
.../sanitizer_symbolizer_posix_libcdep.cpp | 29 +++++++------------
.../symbolizer/sanitizer_symbolize.cpp | 6 ++--
2 files changed, 12 insertions(+), 23 deletions(-)
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_posix_libcdep.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_posix_libcdep.cpp
index 1317facec170416..5cba86e39fa2839 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_posix_libcdep.cpp
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_posix_libcdep.cpp
@@ -326,7 +326,7 @@ __sanitizer_symbolize_data(const char *ModuleName, u64 ModuleOffset,
char *Buffer, int MaxLength);
SANITIZER_INTERFACE_ATTRIBUTE SANITIZER_WEAK_ATTRIBUTE void
__sanitizer_symbolize_flush();
-SANITIZER_INTERFACE_ATTRIBUTE SANITIZER_WEAK_ATTRIBUTE int
+SANITIZER_INTERFACE_ATTRIBUTE SANITIZER_WEAK_ATTRIBUTE bool
__sanitizer_symbolize_demangle(const char *Name, char *Buffer, int MaxLength);
SANITIZER_INTERFACE_ATTRIBUTE SANITIZER_WEAK_ATTRIBUTE bool
__sanitizer_symbolize_set_demangle(bool Demangle);
@@ -349,7 +349,7 @@ class InternalSymbolizer final : public SymbolizerTool {
bool SymbolizePC(uptr addr, SymbolizedStack *stack) override {
bool result = __sanitizer_symbolize_code(
- stack->info.module, stack->info.module_offset, buffer_, kBufferSize);
+ stack->info.module, stack->info.module_offset, buffer_, sizeof(buffer_));
if (result)
ParseSymbolizePCOutput(buffer_, stack);
return result;
@@ -357,7 +357,7 @@ class InternalSymbolizer final : public SymbolizerTool {
bool SymbolizeData(uptr addr, DataInfo *info) override {
bool result = __sanitizer_symbolize_data(info->module, info->module_offset,
- buffer_, kBufferSize);
+ buffer_, sizeof(buffer_));
if (result) {
ParseSymbolizeDataOutput(buffer_, info);
info->start += (addr - info->module_offset); // Add the base address.
@@ -371,28 +371,19 @@ class InternalSymbolizer final : public SymbolizerTool {
}
const char *Demangle(const char *name) override {
- if (__sanitizer_symbolize_demangle) {
- for (uptr res_length = 1024;
- res_length <= InternalSizeClassMap::kMaxSize;) {
- char *res_buff = static_cast<char *>(InternalAlloc(res_length));
- uptr req_length =
- __sanitizer_symbolize_demangle(name, res_buff, res_length);
- if (req_length > res_length) {
- res_length = req_length + 1;
- InternalFree(res_buff);
- continue;
- }
- return res_buff;
- }
+ if (&__sanitizer_symbolize_demangle &&
+ __sanitizer_symbolize_demangle(name, buffer_, sizeof(buffer_))) {
+ char *res_buff = nullptr;
+ ExtractToken(buffer_, "", &res_buff);
+ return res_buff;
}
- return name;
+ return nullptr;
}
private:
InternalSymbolizer() {}
- static const int kBufferSize = 16 * 1024;
- char buffer_[kBufferSize];
+ char buffer_[16 * 1024];
};
# else // SANITIZER_SUPPORTS_WEAK_HOOKS
diff --git a/compiler-rt/lib/sanitizer_common/symbolizer/sanitizer_symbolize.cpp b/compiler-rt/lib/sanitizer_common/symbolizer/sanitizer_symbolize.cpp
index 2bc0444050f80e4..6ca4b9835bf3acd 100644
--- a/compiler-rt/lib/sanitizer_common/symbolizer/sanitizer_symbolize.cpp
+++ b/compiler-rt/lib/sanitizer_common/symbolizer/sanitizer_symbolize.cpp
@@ -115,14 +115,12 @@ void __sanitizer_symbolize_flush() {
Symbolizer->flush();
}
-int __sanitizer_symbolize_demangle(const char *Name, char *Buffer,
+bool __sanitizer_symbolize_demangle(const char *Name, char *Buffer,
int MaxLength) {
std::string Result =
llvm::symbolize::LLVMSymbolizer::DemangleName(Name, nullptr);
return __sanitizer::internal_snprintf(Buffer, MaxLength, "%s",
- Result.c_str()) < MaxLength
- ? static_cast<int>(Result.size() + 1)
- : 0;
+ Result.c_str()) < MaxLength;
}
bool __sanitizer_symbolize_set_demangle(bool Value) {
>From 60c243a0b01b1a07d51134a475efa0d537967f80 Mon Sep 17 00:00:00 2001
From: Fabian Mora <fmora.dev at gmail.com>
Date: Mon, 11 Sep 2023 16:32:15 -0400
Subject: [PATCH 07/35] [mlir][gpu] Deprecate gpu::Serialization* passes.
(#65857)
Deprecate the `gpu-to-cubin` & `gpu-to-hsaco` passes in favor of the
`TargetAttr` workflow. This patch removes remaining upstream uses of the
aforementioned passes, including the option to use them in `mlir-opt`. A
future patch will remove these passes entirely.
The passes can be re-enabled in `mlir-opt` by adding the CMake flag: `-DMLIR_ENABLE_DEPRECATED_GPU_SERIALIZATION=1`.
---
mlir/CMakeLists.txt | 1 +
.../mlir/Dialect/GPU/Transforms/Passes.h | 4 +
mlir/include/mlir/InitAllPasses.h | 2 -
.../SparseTensor/Pipelines/CMakeLists.txt | 8 --
.../Pipelines/SparseTensorPipelines.cpp | 10 ++-
mlir/test/Conversion/GPUToCUDA/lit.local.cfg | 2 -
.../GPUToCUDA/lower-nvvm-kernel-to-cubin.mlir | 25 -------
mlir/test/Conversion/GPUToROCm/lit.local.cfg | 2 -
.../lower-rocdl-kernel-to-hsaco.mlir | 25 -------
mlir/test/lib/Dialect/GPU/CMakeLists.txt | 11 ---
.../GPU/TestConvertGPUKernelToCubin.cpp | 73 -------------------
.../GPU/TestConvertGPUKernelToHsaco.cpp | 72 ------------------
mlir/tools/mlir-opt/CMakeLists.txt | 8 ++
mlir/tools/mlir-opt/mlir-opt.cpp | 10 +--
14 files changed, 23 insertions(+), 230 deletions(-)
delete mode 100644 mlir/test/Conversion/GPUToCUDA/lit.local.cfg
delete mode 100644 mlir/test/Conversion/GPUToCUDA/lower-nvvm-kernel-to-cubin.mlir
delete mode 100644 mlir/test/Conversion/GPUToROCm/lit.local.cfg
delete mode 100644 mlir/test/Conversion/GPUToROCm/lower-rocdl-kernel-to-hsaco.mlir
delete mode 100644 mlir/test/lib/Dialect/GPU/TestConvertGPUKernelToCubin.cpp
delete mode 100644 mlir/test/lib/Dialect/GPU/TestConvertGPUKernelToHsaco.cpp
diff --git a/mlir/CMakeLists.txt b/mlir/CMakeLists.txt
index fa4f6e76f985fb5..bbbcb0703f20f42 100644
--- a/mlir/CMakeLists.txt
+++ b/mlir/CMakeLists.txt
@@ -114,6 +114,7 @@ else()
endif()
add_definitions(-DMLIR_ROCM_CONVERSIONS_ENABLED=${MLIR_ENABLE_ROCM_CONVERSIONS})
+set(MLIR_ENABLE_DEPRECATED_GPU_SERIALIZATION 0 CACHE BOOL "Enable deprecated GPU serialization passes")
set(MLIR_ENABLE_CUDA_RUNNER 0 CACHE BOOL "Enable building the mlir CUDA runner")
set(MLIR_ENABLE_ROCM_RUNNER 0 CACHE BOOL "Enable building the mlir ROCm runner")
set(MLIR_ENABLE_SPIRV_CPU_RUNNER 0 CACHE BOOL "Enable building the mlir SPIR-V cpu runner")
diff --git a/mlir/include/mlir/Dialect/GPU/Transforms/Passes.h b/mlir/include/mlir/Dialect/GPU/Transforms/Passes.h
index 033e8755501f967..2a891a7d24f809a 100644
--- a/mlir/include/mlir/Dialect/GPU/Transforms/Passes.h
+++ b/mlir/include/mlir/Dialect/GPU/Transforms/Passes.h
@@ -134,14 +134,17 @@ class SerializeToBlobPass : public OperationPass<gpu::GPUModuleOp> {
/// Register pass to serialize GPU kernel functions to a CUBIN binary
/// annotation.
+LLVM_DEPRECATED("use Target attributes instead", "")
void registerGpuSerializeToCubinPass();
/// Register pass to serialize GPU kernel functions to a HSAco binary
/// annotation.
+LLVM_DEPRECATED("use Target attributes instead", "")
void registerGpuSerializeToHsacoPass();
/// Create an instance of the GPU kernel function to CUBIN binary serialization
/// pass with optLevel (default level 2).
+LLVM_DEPRECATED("use Target attributes instead", "")
std::unique_ptr<Pass> createGpuSerializeToCubinPass(StringRef triple,
StringRef chip,
StringRef features,
@@ -150,6 +153,7 @@ std::unique_ptr<Pass> createGpuSerializeToCubinPass(StringRef triple,
/// Create an instance of the GPU kernel function to HSAco binary serialization
/// pass.
+LLVM_DEPRECATED("use Target attributes instead", "")
std::unique_ptr<Pass> createGpuSerializeToHsacoPass(StringRef triple,
StringRef arch,
StringRef features,
diff --git a/mlir/include/mlir/InitAllPasses.h b/mlir/include/mlir/InitAllPasses.h
index 8f3f92ae43145d1..f7271737c66d1cb 100644
--- a/mlir/include/mlir/InitAllPasses.h
+++ b/mlir/include/mlir/InitAllPasses.h
@@ -65,8 +65,6 @@ inline void registerAllPasses() {
bufferization::registerBufferizationPasses();
func::registerFuncPasses();
registerGPUPasses();
- registerGpuSerializeToCubinPass();
- registerGpuSerializeToHsacoPass();
registerLinalgPasses();
registerNVGPUPasses();
registerSparseTensorPasses();
diff --git a/mlir/lib/Dialect/SparseTensor/Pipelines/CMakeLists.txt b/mlir/lib/Dialect/SparseTensor/Pipelines/CMakeLists.txt
index 3cf530abd744e8e..234a0d82babef67 100644
--- a/mlir/lib/Dialect/SparseTensor/Pipelines/CMakeLists.txt
+++ b/mlir/lib/Dialect/SparseTensor/Pipelines/CMakeLists.txt
@@ -27,11 +27,3 @@ add_mlir_dialect_library(MLIRSparseTensorPipelines
MLIRVectorToLLVM
MLIRVectorTransforms
)
-
-if(MLIR_ENABLE_CUDA_RUNNER)
- # Enable gpu-to-cubin pass.
- target_compile_definitions(obj.MLIRSparseTensorPipelines
- PRIVATE
- MLIR_GPU_TO_CUBIN_PASS_ENABLE=1
- )
-endif()
diff --git a/mlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp b/mlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp
index 24c4c4c43a93dea..37f9e09d34c04e7 100644
--- a/mlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp
+++ b/mlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp
@@ -78,11 +78,13 @@ void mlir::sparse_tensor::buildSparseCompiler(
// Finalize GPU code generation.
if (gpuCodegen) {
-#if MLIR_GPU_TO_CUBIN_PASS_ENABLE
- pm.addNestedPass<gpu::GPUModuleOp>(createGpuSerializeToCubinPass(
- options.gpuTriple, options.gpuChip, options.gpuFeatures));
-#endif
+ GpuNVVMAttachTargetOptions nvvmTargetOptions;
+ nvvmTargetOptions.triple = options.gpuTriple;
+ nvvmTargetOptions.chip = options.gpuChip;
+ nvvmTargetOptions.features = options.gpuFeatures;
+ pm.addPass(createGpuNVVMAttachTarget(nvvmTargetOptions));
pm.addPass(createGpuToLLVMConversionPass());
+ pm.addPass(createGpuModuleToBinaryPass());
}
pm.addPass(createReconcileUnrealizedCastsPass());
diff --git a/mlir/test/Conversion/GPUToCUDA/lit.local.cfg b/mlir/test/Conversion/GPUToCUDA/lit.local.cfg
deleted file mode 100644
index bc470ccc5733a96..000000000000000
--- a/mlir/test/Conversion/GPUToCUDA/lit.local.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-if not config.run_cuda_tests:
- config.unsupported = True
diff --git a/mlir/test/Conversion/GPUToCUDA/lower-nvvm-kernel-to-cubin.mlir b/mlir/test/Conversion/GPUToCUDA/lower-nvvm-kernel-to-cubin.mlir
deleted file mode 100644
index 0a2ac552a7c6db1..000000000000000
--- a/mlir/test/Conversion/GPUToCUDA/lower-nvvm-kernel-to-cubin.mlir
+++ /dev/null
@@ -1,25 +0,0 @@
-// RUN: mlir-opt %s --test-gpu-to-cubin | FileCheck %s
-
-// CHECK: gpu.module @foo attributes {gpu.binary = "CUBIN"}
-gpu.module @foo {
- llvm.func @kernel(%arg0 : f32, %arg1 : !llvm.ptr)
- // CHECK: attributes {gpu.kernel}
- attributes { gpu.kernel } {
- llvm.return
- }
-}
-
-// CHECK: gpu.module @bar attributes {gpu.binary = "CUBIN"}
-gpu.module @bar {
- // CHECK: func @kernel_a
- llvm.func @kernel_a()
- attributes { gpu.kernel } {
- llvm.return
- }
-
- // CHECK: func @kernel_b
- llvm.func @kernel_b()
- attributes { gpu.kernel } {
- llvm.return
- }
-}
diff --git a/mlir/test/Conversion/GPUToROCm/lit.local.cfg b/mlir/test/Conversion/GPUToROCm/lit.local.cfg
deleted file mode 100644
index 2f5cc9f3bad9737..000000000000000
--- a/mlir/test/Conversion/GPUToROCm/lit.local.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-if not config.run_rocm_tests:
- config.unsupported = True
diff --git a/mlir/test/Conversion/GPUToROCm/lower-rocdl-kernel-to-hsaco.mlir b/mlir/test/Conversion/GPUToROCm/lower-rocdl-kernel-to-hsaco.mlir
deleted file mode 100644
index 8e27de4b60de741..000000000000000
--- a/mlir/test/Conversion/GPUToROCm/lower-rocdl-kernel-to-hsaco.mlir
+++ /dev/null
@@ -1,25 +0,0 @@
-// RUN: mlir-opt %s --test-gpu-to-hsaco | FileCheck %s
-
-// CHECK: gpu.module @foo attributes {gpu.binary = "HSACO"}
-gpu.module @foo {
- llvm.func @kernel(%arg0 : f32, %arg1 : !llvm.ptr)
- // CHECK: attributes {gpu.kernel}
- attributes { gpu.kernel } {
- llvm.return
- }
-}
-
-// CHECK: gpu.module @bar attributes {gpu.binary = "HSACO"}
-gpu.module @bar {
- // CHECK: func @kernel_a
- llvm.func @kernel_a()
- attributes { gpu.kernel } {
- llvm.return
- }
-
- // CHECK: func @kernel_b
- llvm.func @kernel_b()
- attributes { gpu.kernel } {
- llvm.return
- }
-}
diff --git a/mlir/test/lib/Dialect/GPU/CMakeLists.txt b/mlir/test/lib/Dialect/GPU/CMakeLists.txt
index ac96229e80a077e..80edd04b691a571 100644
--- a/mlir/test/lib/Dialect/GPU/CMakeLists.txt
+++ b/mlir/test/lib/Dialect/GPU/CMakeLists.txt
@@ -31,8 +31,6 @@ set(LIBS
)
add_mlir_library(MLIRGPUTestPasses
- TestConvertGPUKernelToCubin.cpp
- TestConvertGPUKernelToHsaco.cpp
TestGpuMemoryPromotion.cpp
TestGpuRewrite.cpp
TestLowerToNVVM.cpp
@@ -43,12 +41,3 @@ add_mlir_library(MLIRGPUTestPasses
${LIBS}
)
-# This is how it is defined in mlir/lib/Dialect/GPU/CMakeLists.txt
-# We probably want something better project-wide
-if(MLIR_ENABLE_CUDA_RUNNER)
- # Enable gpu-to-cubin pass.
- target_compile_definitions(MLIRGPUTestPasses
- PRIVATE
- MLIR_GPU_TO_CUBIN_PASS_ENABLE=1
- )
-endif()
diff --git a/mlir/test/lib/Dialect/GPU/TestConvertGPUKernelToCubin.cpp b/mlir/test/lib/Dialect/GPU/TestConvertGPUKernelToCubin.cpp
deleted file mode 100644
index 1c442b0147c8b30..000000000000000
--- a/mlir/test/lib/Dialect/GPU/TestConvertGPUKernelToCubin.cpp
+++ /dev/null
@@ -1,73 +0,0 @@
-//===- TestConvertGPUKernelToCubin.cpp - Test gpu kernel cubin lowering ---===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#include "mlir/Dialect/GPU/Transforms/Passes.h"
-#include "mlir/Pass/Pass.h"
-#include "mlir/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.h"
-#include "mlir/Target/LLVMIR/Export.h"
-#include "llvm/Support/TargetSelect.h"
-
-using namespace mlir;
-
-#if MLIR_CUDA_CONVERSIONS_ENABLED
-namespace {
-class TestSerializeToCubinPass
- : public PassWrapper<TestSerializeToCubinPass, gpu::SerializeToBlobPass> {
-public:
- MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(TestSerializeToCubinPass)
-
- StringRef getArgument() const final { return "test-gpu-to-cubin"; }
- StringRef getDescription() const final {
- return "Lower GPU kernel function to CUBIN binary annotations";
- }
- TestSerializeToCubinPass();
-
-private:
- void getDependentDialects(DialectRegistry ®istry) const override;
-
- // Serializes PTX to CUBIN.
- std::unique_ptr<std::vector<char>>
- serializeISA(const std::string &isa) override;
-};
-} // namespace
-
-TestSerializeToCubinPass::TestSerializeToCubinPass() {
- this->triple = "nvptx64-nvidia-cuda";
- this->chip = "sm_35";
- this->features = "+ptx60";
-}
-
-void TestSerializeToCubinPass::getDependentDialects(
- DialectRegistry ®istry) const {
- registerNVVMDialectTranslation(registry);
- gpu::SerializeToBlobPass::getDependentDialects(registry);
-}
-
-std::unique_ptr<std::vector<char>>
-TestSerializeToCubinPass::serializeISA(const std::string &) {
- std::string data = "CUBIN";
- return std::make_unique<std::vector<char>>(data.begin(), data.end());
-}
-
-namespace mlir {
-namespace test {
-// Register test pass to serialize GPU module to a CUBIN binary annotation.
-void registerTestGpuSerializeToCubinPass() {
- PassRegistration<TestSerializeToCubinPass>([] {
- // Initialize LLVM NVPTX backend.
- LLVMInitializeNVPTXTarget();
- LLVMInitializeNVPTXTargetInfo();
- LLVMInitializeNVPTXTargetMC();
- LLVMInitializeNVPTXAsmPrinter();
-
- return std::make_unique<TestSerializeToCubinPass>();
- });
-}
-} // namespace test
-} // namespace mlir
-#endif // MLIR_CUDA_CONVERSIONS_ENABLED
diff --git a/mlir/test/lib/Dialect/GPU/TestConvertGPUKernelToHsaco.cpp b/mlir/test/lib/Dialect/GPU/TestConvertGPUKernelToHsaco.cpp
deleted file mode 100644
index c204e86632ac920..000000000000000
--- a/mlir/test/lib/Dialect/GPU/TestConvertGPUKernelToHsaco.cpp
+++ /dev/null
@@ -1,72 +0,0 @@
-//===- TestConvertGPUKernelToHsaco.cpp - Test gpu kernel hsaco lowering ---===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#include "mlir/Dialect/GPU/Transforms/Passes.h"
-#include "mlir/Pass/Pass.h"
-#include "mlir/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.h"
-#include "mlir/Target/LLVMIR/Export.h"
-#include "llvm/Support/TargetSelect.h"
-
-using namespace mlir;
-
-#if MLIR_ROCM_CONVERSIONS_ENABLED
-namespace {
-class TestSerializeToHsacoPass
- : public PassWrapper<TestSerializeToHsacoPass, gpu::SerializeToBlobPass> {
-public:
- MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(TestSerializeToHsacoPass)
-
- StringRef getArgument() const final { return "test-gpu-to-hsaco"; }
- StringRef getDescription() const final {
- return "Lower GPU kernel function to HSAco binary annotations";
- }
- TestSerializeToHsacoPass();
-
-private:
- void getDependentDialects(DialectRegistry ®istry) const override;
-
- // Serializes ROCDL IR to HSACO.
- std::unique_ptr<std::vector<char>>
- serializeISA(const std::string &isa) override;
-};
-} // namespace
-
-TestSerializeToHsacoPass::TestSerializeToHsacoPass() {
- this->triple = "amdgcn-amd-amdhsa";
- this->chip = "gfx900";
-}
-
-void TestSerializeToHsacoPass::getDependentDialects(
- DialectRegistry ®istry) const {
- registerROCDLDialectTranslation(registry);
- gpu::SerializeToBlobPass::getDependentDialects(registry);
-}
-
-std::unique_ptr<std::vector<char>>
-TestSerializeToHsacoPass::serializeISA(const std::string &) {
- std::string data = "HSACO";
- return std::make_unique<std::vector<char>>(data.begin(), data.end());
-}
-
-namespace mlir {
-namespace test {
-// Register test pass to serialize GPU module to a HSAco binary annotation.
-void registerTestGpuSerializeToHsacoPass() {
- PassRegistration<TestSerializeToHsacoPass>([] {
- // Initialize LLVM AMDGPU backend.
- LLVMInitializeAMDGPUTarget();
- LLVMInitializeAMDGPUTargetInfo();
- LLVMInitializeAMDGPUTargetMC();
- LLVMInitializeAMDGPUAsmPrinter();
-
- return std::make_unique<TestSerializeToHsacoPass>();
- });
-}
-} // namespace test
-} // namespace mlir
-#endif // MLIR_ROCM_CONVERSIONS_ENABLED
diff --git a/mlir/tools/mlir-opt/CMakeLists.txt b/mlir/tools/mlir-opt/CMakeLists.txt
index df1e9480c754bcc..88a0562cb6e7207 100644
--- a/mlir/tools/mlir-opt/CMakeLists.txt
+++ b/mlir/tools/mlir-opt/CMakeLists.txt
@@ -91,3 +91,11 @@ llvm_update_compile_flags(mlir-opt)
mlir_check_all_link_libraries(mlir-opt)
export_executable_symbols_for_plugins(mlir-opt)
+
+if(MLIR_ENABLE_DEPRECATED_GPU_SERIALIZATION)
+ # Enable deprecated serialization passes.
+ target_compile_definitions(mlir-opt
+ PRIVATE
+ MLIR_DEPRECATED_GPU_SERIALIZATION_ENABLE=1
+ )
+endif()
diff --git a/mlir/tools/mlir-opt/mlir-opt.cpp b/mlir/tools/mlir-opt/mlir-opt.cpp
index a8aeffec1ae72d0..b7647d7de78a10e 100644
--- a/mlir/tools/mlir-opt/mlir-opt.cpp
+++ b/mlir/tools/mlir-opt/mlir-opt.cpp
@@ -80,8 +80,6 @@ void registerTestCallGraphPass();
void registerTestCfAssertPass();
void registerTestConstantFold();
void registerTestControlFlowSink();
-void registerTestGpuSerializeToCubinPass();
-void registerTestGpuSerializeToHsacoPass();
void registerTestDataLayoutPropagation();
void registerTestDataLayoutQuery();
void registerTestDeadCodeAnalysisPass();
@@ -204,11 +202,7 @@ void registerTestPasses() {
mlir::test::registerTestDiagnosticsPass();
mlir::test::registerTestDialectConversionPasses();
#if MLIR_CUDA_CONVERSIONS_ENABLED
- mlir::test::registerTestGpuSerializeToCubinPass();
mlir::test::registerTestLowerToNVVM();
-#endif
-#if MLIR_ROCM_CONVERSIONS_ENABLED
- mlir::test::registerTestGpuSerializeToHsacoPass();
#endif
mlir::test::registerTestDecomposeCallGraphTypes();
mlir::test::registerTestDataLayoutPropagation();
@@ -270,6 +264,10 @@ void registerTestPasses() {
int main(int argc, char **argv) {
registerAllPasses();
+#if MLIR_DEPRECATED_GPU_SERIALIZATION_ENABLE == 1
+ registerGpuSerializeToCubinPass();
+ registerGpuSerializeToHsacoPass();
+#endif
#ifdef MLIR_INCLUDE_TESTS
registerTestPasses();
#endif
>From db1254d79c51db07dd93fbffc155ab2ee624a22e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Valentin=20Clement=20=28=E3=83=90=E3=83=AC=E3=83=B3?=
=?UTF-8?q?=E3=82=BF=E3=82=A4=E3=83=B3=20=E3=82=AF=E3=83=AC=E3=83=A1?=
=?UTF-8?q?=E3=83=B3=29?= <clementval at gmail.com>
Date: Mon, 11 Sep 2023 13:38:03 -0700
Subject: [PATCH 08/35] [mlir][openacc] Model acc cache directive as data entry
operands on acc.loop (#65521)
The `cache` directive may appear at the top of (inside of) a loop. It
specifies array elements or subarrays that should be fetched into the
highest level of the cache for the body of the loop.
The `cache` directive is modeled as a data entry operands attached to
the acc.loop operation.
---
flang/lib/Lower/OpenACC.cpp | 5 +-
mlir/include/mlir/Dialect/OpenACC/OpenACC.h | 3 +-
.../mlir/Dialect/OpenACC/OpenACCOps.td | 53 +++++++++++++------
mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp | 13 +++++
mlir/test/Dialect/OpenACC/ops.mlir | 12 ++++-
5 files changed, 66 insertions(+), 20 deletions(-)
diff --git a/flang/lib/Lower/OpenACC.cpp b/flang/lib/Lower/OpenACC.cpp
index 308ec19d922c7c1..5ead00ef89cbabc 100644
--- a/flang/lib/Lower/OpenACC.cpp
+++ b/flang/lib/Lower/OpenACC.cpp
@@ -1356,8 +1356,8 @@ createLoopOp(Fortran::lower::AbstractConverter &converter,
mlir::Value gangNum;
mlir::Value gangDim;
mlir::Value gangStatic;
- llvm::SmallVector<mlir::Value, 2> tileOperands, privateOperands,
- reductionOperands;
+ llvm::SmallVector<mlir::Value> tileOperands, privateOperands,
+ reductionOperands, cacheOperands;
llvm::SmallVector<mlir::Attribute> privatizations, reductionRecipes;
bool hasGang = false, hasVector = false, hasWorker = false;
@@ -1451,6 +1451,7 @@ createLoopOp(Fortran::lower::AbstractConverter &converter,
addOperands(operands, operandSegments, tileOperands);
addOperands(operands, operandSegments, privateOperands);
addOperands(operands, operandSegments, reductionOperands);
+ addOperands(operands, operandSegments, cacheOperands);
auto loopOp = createRegionOp<mlir::acc::LoopOp, mlir::acc::YieldOp>(
builder, currentLocation, operands, operandSegments);
diff --git a/mlir/include/mlir/Dialect/OpenACC/OpenACC.h b/mlir/include/mlir/Dialect/OpenACC/OpenACC.h
index d75cc1dedc098ae..ca5876fba674599 100644
--- a/mlir/include/mlir/Dialect/OpenACC/OpenACC.h
+++ b/mlir/include/mlir/Dialect/OpenACC/OpenACC.h
@@ -42,7 +42,8 @@
mlir::acc::GetDevicePtrOp, mlir::acc::PrivateOp, \
mlir::acc::FirstprivateOp, mlir::acc::UpdateDeviceOp, \
mlir::acc::UseDeviceOp, mlir::acc::ReductionOp, \
- mlir::acc::DeclareDeviceResidentOp, mlir::acc::DeclareLinkOp
+ mlir::acc::DeclareDeviceResidentOp, mlir::acc::DeclareLinkOp, \
+ mlir::acc::CacheOp
#define ACC_COMPUTE_CONSTRUCT_OPS \
mlir::acc::ParallelOp, mlir::acc::KernelsOp, mlir::acc::SerialOp
#define ACC_DATA_CONSTRUCT_OPS \
diff --git a/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td b/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
index 0032ffa94dede9f..ce1b4e29cd51b9b 100644
--- a/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
+++ b/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
@@ -98,6 +98,8 @@ def OpenACC_UseDevice : I64EnumAttrCase<"acc_use_device", 20>;
def OpenACC_Reduction : I64EnumAttrCase<"acc_reduction", 21>;
def OpenACC_DeclareDeviceResident : I64EnumAttrCase<"acc_declare_device_resident", 22>;
def OpenACC_DeclareLink : I64EnumAttrCase<"acc_declare_link", 23>;
+def OpenACC_Cache : I64EnumAttrCase<"acc_cache", 24>;
+def OpenACC_CacheReadonly : I64EnumAttrCase<"acc_cache_readonly", 25>;
def OpenACC_DataClauseEnum : I64EnumAttr<"DataClause",
"data clauses supported by OpenACC",
@@ -109,6 +111,7 @@ def OpenACC_DataClauseEnum : I64EnumAttr<"DataClause",
OpenACC_IsDevicePtrClause, OpenACC_GetDevicePtrClause, OpenACC_UpdateHost,
OpenACC_UpdateSelf, OpenACC_UpdateDevice, OpenACC_UseDevice,
OpenACC_Reduction, OpenACC_DeclareDeviceResident, OpenACC_DeclareLink,
+ OpenACC_Cache, OpenACC_CacheReadonly,
]> {
let cppNamespace = "::mlir::acc";
let genSpecializedAttr = 0;
@@ -406,6 +409,22 @@ def OpenACC_DeclareLinkOp : OpenACC_DataEntryOp<"declare_link",
let summary = "Represents acc declare link semantics.";
}
+//===----------------------------------------------------------------------===//
+// 2.10 cache directive
+//===----------------------------------------------------------------------===//
+def OpenACC_CacheOp : OpenACC_DataEntryOp<"cache",
+ "mlir::acc::DataClause::acc_cache", ""> {
+ let summary = "Represents the cache directive that is associated with a "
+ "loop.";
+
+ let extraClassDeclaration = [{
+ /// Check if this is a cache with readonly modifier.
+ bool isCacheReadonly() {
+ return getDataClause() == acc::DataClause::acc_cache_readonly;
+ }
+ }];
+}
+
// Data exit operation does not refer to OpenACC spec terminology, but to
// terminology used in this dialect. It refers to data operations that will appear
// after data or compute region. It will be used as the base of acc dialect
@@ -1140,22 +1159,23 @@ def OpenACC_LoopOp : OpenACC_Op<"loop",
}];
let arguments = (ins OptionalAttr<I64Attr>:$collapse,
- Optional<IntOrIndex>:$gangNum,
- Optional<IntOrIndex>:$gangDim,
- Optional<IntOrIndex>:$gangStatic,
- Optional<IntOrIndex>:$workerNum,
- Optional<IntOrIndex>:$vectorLength,
- UnitAttr:$seq,
- UnitAttr:$independent,
- UnitAttr:$auto_,
- UnitAttr:$hasGang,
- UnitAttr:$hasWorker,
- UnitAttr:$hasVector,
- Variadic<IntOrIndex>:$tileOperands,
- Variadic<OpenACC_PointerLikeTypeInterface>:$privateOperands,
- OptionalAttr<SymbolRefArrayAttr>:$privatizations,
- Variadic<AnyType>:$reductionOperands,
- OptionalAttr<SymbolRefArrayAttr>:$reductionRecipes);
+ Optional<IntOrIndex>:$gangNum,
+ Optional<IntOrIndex>:$gangDim,
+ Optional<IntOrIndex>:$gangStatic,
+ Optional<IntOrIndex>:$workerNum,
+ Optional<IntOrIndex>:$vectorLength,
+ UnitAttr:$seq,
+ UnitAttr:$independent,
+ UnitAttr:$auto_,
+ UnitAttr:$hasGang,
+ UnitAttr:$hasWorker,
+ UnitAttr:$hasVector,
+ Variadic<IntOrIndex>:$tileOperands,
+ Variadic<OpenACC_PointerLikeTypeInterface>:$privateOperands,
+ OptionalAttr<SymbolRefArrayAttr>:$privatizations,
+ Variadic<AnyType>:$reductionOperands,
+ OptionalAttr<SymbolRefArrayAttr>:$reductionRecipes,
+ Variadic<OpenACC_PointerLikeTypeInterface>:$cacheOperands);
let results = (outs Variadic<AnyType>:$results);
@@ -1181,6 +1201,7 @@ def OpenACC_LoopOp : OpenACC_Op<"loop",
| `reduction` `(` custom<SymOperandList>(
$reductionOperands, type($reductionOperands), $reductionRecipes)
`)`
+ | `cache` `(` $cacheOperands `:` type($cacheOperands) `)`
)
$region
( `(` type($results)^ `)` )?
diff --git a/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp b/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
index b2480a5186a2e46..b30215663fbcec9 100644
--- a/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
+++ b/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
@@ -299,6 +299,19 @@ LogicalResult acc::UseDeviceOp::verify() {
return success();
}
+//===----------------------------------------------------------------------===//
+// CacheOp
+//===----------------------------------------------------------------------===//
+LogicalResult acc::CacheOp::verify() {
+ // Test for all clauses this operation can be decomposed from:
+ if (getDataClause() != acc::DataClause::acc_cache &&
+ getDataClause() != acc::DataClause::acc_cache_readonly)
+ return emitError(
+ "data clause associated with cache operation must match its intent"
+ " or specify original clause this operation was decomposed from");
+ return success();
+}
+
template <typename StructureOp>
static ParseResult parseRegions(OpAsmParser &parser, OperationState &state,
unsigned nRegions = 1) {
diff --git a/mlir/test/Dialect/OpenACC/ops.mlir b/mlir/test/Dialect/OpenACC/ops.mlir
index 2c296a5087be514..d1950b1fb3f2916 100644
--- a/mlir/test/Dialect/OpenACC/ops.mlir
+++ b/mlir/test/Dialect/OpenACC/ops.mlir
@@ -213,7 +213,7 @@ func.func @compute3(%a: memref<10x10xf32>, %b: memref<10x10xf32>, %c: memref<10x
// -----
-func.func @testloopop() -> () {
+func.func @testloopop(%a : memref<10xf32>) -> () {
%i64Value = arith.constant 1 : i64
%i32Value = arith.constant 128 : i32
%idxValue = arith.constant 8 : index
@@ -282,6 +282,11 @@ func.func @testloopop() -> () {
"test.openacc_dummy_op"() : () -> ()
acc.yield
}
+ %b = acc.cache varPtr(%a : memref<10xf32>) -> memref<10xf32>
+ acc.loop cache(%b : memref<10xf32>) {
+ "test.openacc_dummy_op"() : () -> ()
+ acc.yield
+ }
return
}
@@ -352,6 +357,11 @@ func.func @testloopop() -> () {
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK-NEXT: }
+// CHECK: %{{.*}} = acc.cache varPtr(%{{.*}} : memref<10xf32>) -> memref<10xf32>
+// CHECK-NEXT: acc.loop cache(%{{.*}} : memref<10xf32>) {
+// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
+// CHECK-NEXT: acc.yield
+// CHECK-NEXT: }
// -----
>From 770fcc96e938df2ac0a0aa93019da1b78a232e4e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Valentin=20Clement=20=28=E3=83=90=E3=83=AC=E3=83=B3?=
=?UTF-8?q?=E3=82=BF=E3=82=A4=E3=83=B3=20=E3=82=AF=E3=83=AC=E3=83=A1?=
=?UTF-8?q?=E3=83=B3=29?= <clementval at gmail.com>
Date: Mon, 11 Sep 2023 13:38:21 -0700
Subject: [PATCH 09/35] [flang][openacc] Lower acc cache directive (#65673)
The cache directive is attached directly to the acc.loop operation when
the directive appears in the loop. When it appears before a loop, the
OpenACCCacheConstruct is saved and attached when the acc.loop is
created.
Directive that cannot be attached to a loop are silently discarded.
Depends on #65521
---
flang/lib/Lower/OpenACC.cpp | 38 +++++++++++++++++++++++++--
flang/test/Lower/OpenACC/acc-loop.f90 | 9 +++++++
2 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/flang/lib/Lower/OpenACC.cpp b/flang/lib/Lower/OpenACC.cpp
index 5ead00ef89cbabc..a59a71ff8d8ae68 100644
--- a/flang/lib/Lower/OpenACC.cpp
+++ b/flang/lib/Lower/OpenACC.cpp
@@ -3096,6 +3096,41 @@ void Fortran::lower::finalizeOpenACCRoutineAttachment(
accRoutineInfos.clear();
}
+static void
+genACC(Fortran::lower::AbstractConverter &converter,
+ Fortran::semantics::SemanticsContext &semanticsContext,
+ const Fortran::parser::OpenACCCacheConstruct &cacheConstruct) {
+ fir::FirOpBuilder &builder = converter.getFirOpBuilder();
+ auto loopOp = builder.getRegion().getParentOfType<mlir::acc::LoopOp>();
+ auto crtPos = builder.saveInsertionPoint();
+ if (loopOp) {
+ builder.setInsertionPoint(loopOp);
+ Fortran::lower::StatementContext stmtCtx;
+ llvm::SmallVector<mlir::Value> cacheOperands;
+ const Fortran::parser::AccObjectListWithModifier &listWithModifier =
+ std::get<Fortran::parser::AccObjectListWithModifier>(cacheConstruct.t);
+ const auto &accObjectList =
+ std::get<Fortran::parser::AccObjectList>(listWithModifier.t);
+ const auto &modifier =
+ std::get<std::optional<Fortran::parser::AccDataModifier>>(
+ listWithModifier.t);
+
+ mlir::acc::DataClause dataClause = mlir::acc::DataClause::acc_cache;
+ if (modifier &&
+ (*modifier).v == Fortran::parser::AccDataModifier::Modifier::ReadOnly)
+ dataClause = mlir::acc::DataClause::acc_cache_readonly;
+ genDataOperandOperations<mlir::acc::CacheOp>(
+ accObjectList, converter, semanticsContext, stmtCtx, cacheOperands,
+ dataClause,
+ /*structured=*/true, /*implicit=*/false, /*setDeclareAttr*/ false);
+ loopOp.getCacheOperandsMutable().append(cacheOperands);
+ } else {
+ llvm::report_fatal_error(
+ "could not find loop to attach OpenACC cache information.");
+ }
+ builder.restoreInsertionPoint(crtPos);
+}
+
void Fortran::lower::genOpenACCConstruct(
Fortran::lower::AbstractConverter &converter,
Fortran::semantics::SemanticsContext &semanticsContext,
@@ -3119,8 +3154,7 @@ void Fortran::lower::genOpenACCConstruct(
genACC(converter, semanticsContext, standaloneConstruct);
},
[&](const Fortran::parser::OpenACCCacheConstruct &cacheConstruct) {
- TODO(converter.genLocation(cacheConstruct.source),
- "OpenACC Cache construct not lowered yet!");
+ genACC(converter, semanticsContext, cacheConstruct);
},
[&](const Fortran::parser::OpenACCWaitConstruct &waitConstruct) {
genACC(converter, waitConstruct);
diff --git a/flang/test/Lower/OpenACC/acc-loop.f90 b/flang/test/Lower/OpenACC/acc-loop.f90
index eac4fa41af82a31..17bcb6e509b41ef 100644
--- a/flang/test/Lower/OpenACC/acc-loop.f90
+++ b/flang/test/Lower/OpenACC/acc-loop.f90
@@ -305,4 +305,13 @@ program acc_loop
!CHECK: acc.yield
!CHECK-NEXT: }{{$}}
+ !$acc loop
+ DO i = 1, n
+ !$acc cache(b)
+ a(i) = b(i)
+ END DO
+
+! CHECK: %[[CACHE:.*]] = acc.cache varPtr(%{{.*}} : !fir.ref<!fir.array<10xf32>>) bounds(%{{.*}}) -> !fir.ref<!fir.array<10xf32>> {name = "b"}
+! CHECK: acc.loop cache(%[[CACHE]] : !fir.ref<!fir.array<10xf32>>)
+
end program
>From 66f16456caa07358e5d682691eb80c02a6c6dd64 Mon Sep 17 00:00:00 2001
From: MaheshRavishankar <1663364+MaheshRavishankar at users.noreply.github.com>
Date: Mon, 11 Sep 2023 13:41:38 -0700
Subject: [PATCH 10/35] [mlir][Linalg] Move `linalg.fill` -> `linalg.pack`
pattern into `fill` canonicalization patterns. (#66002)
This pattern fits better with the other canonicalization patterns that
exist for `linalg.fill`.
---
mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp | 63 +++++++++++++++++--
.../Transforms/DataLayoutPropagation.cpp | 60 ------------------
mlir/test/Dialect/Linalg/canonicalize.mlir | 44 +++++++++++++
.../Linalg/data-layout-propagation.mlir | 44 -------------
4 files changed, 101 insertions(+), 110 deletions(-)
diff --git a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
index bcc36d6bd3e95e5..e05a82855c66bd0 100644
--- a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
+++ b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
@@ -737,7 +737,8 @@ struct FoldFillWithTensorExtract : public OpRewritePattern<tensor::ExtractOp> {
LogicalResult matchAndRewrite(tensor::ExtractOp extractOp,
PatternRewriter &rewriter) const override {
- // See if tensor input of tensor.extract op is the result of a linalg.fill op.
+ // See if tensor input of tensor.extract op is the result of a linalg.fill
+ // op.
auto fillOp = extractOp.getTensor().getDefiningOp<linalg::FillOp>();
if (!fillOp)
return failure();
@@ -751,15 +752,65 @@ struct FoldFillWithTensorExtract : public OpRewritePattern<tensor::ExtractOp> {
}
};
+/// Folds pack(fill) into a single fill op if
+/// 1. The pack op does not have padding value, or
+/// 2. The filled value and padding value are the same.
+static FailureOr<FillOp> foldFillPackIntoFillOp(RewriterBase &rewriter,
+ tensor::PackOp packOp) {
+ auto fillOp = packOp.getSource().getDefiningOp<FillOp>();
+ if (!fillOp)
+ return failure();
+
+ if (auto paddingValue = packOp.getPaddingValue())
+ if (!isEqualConstantIntOrValue(paddingValue, fillOp.value()))
+ return failure();
+
+ OpBuilder::InsertionGuard guard(rewriter);
+ rewriter.setInsertionPoint(fillOp);
+
+ Value packOpDest = packOp.getDest();
+ if (!packOpDest.hasOneUse())
+ return failure();
+ if (auto emptyOp = packOpDest.getDefiningOp<tensor::EmptyOp>()) {
+ packOpDest = tensor::PackOp::createDestinationTensor(
+ rewriter, fillOp.getLoc(), fillOp.getDpsInitOperand(0)->get(),
+ packOp.getMixedTiles(), packOp.getInnerDimsPos(),
+ packOp.getOuterDimsPerm());
+ } else {
+ DominanceInfo dom(fillOp);
+ if (!dom.properlyDominates(packOpDest, fillOp))
+ return failure();
+ }
+
+ Value fillDest = packOpDest;
+ return clone(rewriter, fillOp, packOpDest.getType(),
+ {fillOp.value(), fillDest});
+}
+
+/// Wrapper pattern that applies foldFillPackIntoFillOp method.
+struct FoldFillWithPack : public OpRewritePattern<tensor::PackOp> {
+public:
+ FoldFillWithPack(MLIRContext *context)
+ : OpRewritePattern<tensor::PackOp>(context) {}
+
+ LogicalResult matchAndRewrite(tensor::PackOp packOp,
+ PatternRewriter &rewriter) const override {
+ auto fillOp = foldFillPackIntoFillOp(rewriter, packOp);
+ if (failed(fillOp))
+ return failure();
+ rewriter.replaceOp(packOp, fillOp.value().result());
+ return success();
+ }
+};
+
} // namespace
void FillOp::getCanonicalizationPatterns(RewritePatternSet &results,
MLIRContext *context) {
- results
- .add<FoldFillWithTensorExtract,
- FoldFillWithPad, FoldFillWithTensorReshape<tensor::CollapseShapeOp>,
- FoldFillWithTensorReshape<tensor::ExpandShapeOp>,
- FoldInsertPadIntoFill>(context);
+ results.add<FoldFillWithTensorExtract, FoldFillWithPack, FoldFillWithPad,
+ FoldFillWithTensorReshape<tensor::CollapseShapeOp>,
+ FoldFillWithTensorReshape<tensor::ExpandShapeOp>,
+ FoldInsertPadIntoFill>(context);
}
//===----------------------------------------------------------------------===//
diff --git a/mlir/lib/Dialect/Linalg/Transforms/DataLayoutPropagation.cpp b/mlir/lib/Dialect/Linalg/Transforms/DataLayoutPropagation.cpp
index 1ddd8b144c60e85..95a20f2369f9e07 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/DataLayoutPropagation.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/DataLayoutPropagation.cpp
@@ -448,46 +448,6 @@ bubbleUpPackOpThroughGenericOp(RewriterBase &rewriter, tensor::PackOp packOp,
*packInfo);
}
-/// Folds pack(fill) into a single fill op if
-/// 1. The pack op does not have padding value, or
-/// 2. The filled value and padding value are the same.
-static FailureOr<FillOp>
-foldFillPackIntoFillOp(RewriterBase &rewriter, tensor::PackOp packOp,
- ControlPropagationFn controlFn) {
- auto fillOp = packOp.getSource().getDefiningOp<FillOp>();
- if (!fillOp)
- return failure();
-
- // User controlled propagation function.
- if (!controlFn(fillOp))
- return failure();
-
- if (auto paddingValue = packOp.getPaddingValue())
- if (!isEqualConstantIntOrValue(paddingValue, fillOp.value()))
- return failure();
-
- OpBuilder::InsertionGuard guard(rewriter);
- rewriter.setInsertionPoint(fillOp);
-
- Value packOpDest = packOp.getDest();
- if (!packOpDest.hasOneUse())
- return failure();
- if (auto emptyOp = packOpDest.getDefiningOp<tensor::EmptyOp>()) {
- packOpDest = tensor::PackOp::createDestinationTensor(
- rewriter, fillOp.getLoc(), fillOp.getDpsInitOperand(0)->get(),
- packOp.getMixedTiles(), packOp.getInnerDimsPos(),
- packOp.getOuterDimsPerm());
- } else {
- DominanceInfo dom(fillOp);
- if (!dom.properlyDominates(packOpDest, fillOp))
- return failure();
- }
-
- Value fillDest = packOpDest;
- return clone(rewriter, fillOp, packOpDest.getType(),
- {fillOp.value(), fillDest});
-}
-
/// Wrapper pattern that applies bubbleUpPackOpThroughGenericOp method.
struct BubbleUpPackOpThroughGenericOpPattern
: public OpRewritePattern<tensor::PackOp> {
@@ -510,25 +470,6 @@ struct BubbleUpPackOpThroughGenericOpPattern
ControlPropagationFn controlFn;
};
-/// Wrapper pattern that applies foldFillPackIntoFillOp method.
-struct FoldFillPackIntoFillOpPattern : public OpRewritePattern<tensor::PackOp> {
-public:
- FoldFillPackIntoFillOpPattern(MLIRContext *context, ControlPropagationFn fun)
- : OpRewritePattern<tensor::PackOp>(context), controlFn(std::move(fun)) {}
-
- LogicalResult matchAndRewrite(tensor::PackOp packOp,
- PatternRewriter &rewriter) const override {
- auto fillOp = foldFillPackIntoFillOp(rewriter, packOp, controlFn);
- if (failed(fillOp))
- return failure();
- rewriter.replaceOp(packOp, fillOp.value().result());
- return success();
- }
-
-private:
- ControlPropagationFn controlFn;
-};
-
// TODO: Relax this restriction. We should unpack a generic op also
// in the presence of multiple unpack ops as producers.
/// Return the unpacked operand, if present, for the current generic op.
@@ -750,7 +691,6 @@ void mlir::linalg::populateDataLayoutPropagationPatterns(
RewritePatternSet &patterns,
const ControlPropagationFn &controlPackUnPackPropagation) {
patterns.insert<BubbleUpPackOpThroughGenericOpPattern,
- FoldFillPackIntoFillOpPattern,
PushDownUnPackOpThroughGenericOp, PushDownUnPackThroughPadOp>(
patterns.getContext(), controlPackUnPackPropagation);
}
diff --git a/mlir/test/Dialect/Linalg/canonicalize.mlir b/mlir/test/Dialect/Linalg/canonicalize.mlir
index 297b5c4e332c811..7793e435582746c 100644
--- a/mlir/test/Dialect/Linalg/canonicalize.mlir
+++ b/mlir/test/Dialect/Linalg/canonicalize.mlir
@@ -353,6 +353,50 @@ func.func @fold_fill_extract(%arg0 : i1) -> i1 {
// -----
+func.func @fill_pack() -> tensor<24x32x16x16xf32> {
+ %dest = tensor.empty() : tensor<384x512xf32>
+ %cst = arith.constant 0.000000e+00 : f32
+ %0 = tensor.empty() : tensor<24x32x16x16xf32>
+ %1 = linalg.fill ins(%cst : f32) outs(%dest : tensor<384x512xf32>) -> tensor<384x512xf32>
+ %pack = tensor.pack %1 inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %0 : tensor<384x512xf32> -> tensor<24x32x16x16xf32>
+ return %pack : tensor<24x32x16x16xf32>
+}
+// CHECK-LABEL: func.func @fill_pack
+// CHECK: %[[PACKED_EMPTY:.+]] = tensor.empty() : tensor<24x32x16x16xf32>
+// CHECK: %[[FILL:.+]] = linalg.fill ins(%{{.+}}) outs(%[[PACKED_EMPTY]]
+// CHECK: return %[[FILL]]
+
+// -----
+
+#map = affine_map<()[s0] -> (s0 ceildiv 16)>
+func.func @dynamic_fill_pack(%arg0: tensor<?x?xf32>) -> tensor<?x?x16x16xf32> {
+ %cst = arith.constant 0.000000e+00 : f32
+ %c0 = arith.constant 0 : index
+ %c1 = arith.constant 1 : index
+ %0 = linalg.fill ins(%cst : f32) outs(%arg0 : tensor<?x?xf32>) -> tensor<?x?xf32>
+ %dim = tensor.dim %0, %c0 : tensor<?x?xf32>
+ %dim_0 = tensor.dim %0, %c1 : tensor<?x?xf32>
+ %1 = affine.apply #map()[%dim]
+ %2 = affine.apply #map()[%dim_0]
+ %3 = tensor.empty(%1, %2) : tensor<?x?x16x16xf32>
+ %pack = tensor.pack %0 padding_value(%cst : f32) inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %3 : tensor<?x?xf32> -> tensor<?x?x16x16xf32>
+ return %pack : tensor<?x?x16x16xf32>
+}
+// CHECK-DAG: #[[MAP:.+]] = affine_map<()[s0] -> (s0 ceildiv 16)>
+// CHECK: func.func @dynamic_fill_pack
+// CHECK-SAME: %[[DEST:[a-zA-Z0-9]+]]
+// CHECK-DAG: %[[C0:.+]] = arith.constant 0 : index
+// CHECK-DAG: %[[C1:.+]] = arith.constant 1 : index
+// CHECK: %[[D0:.+]] = tensor.dim %[[DEST]], %[[C0]]
+// CHECK: %[[D1:.+]] = tensor.dim %[[DEST]], %[[C1]]
+// CHECK: %[[PACKED_D0:.+]] = affine.apply #[[MAP]]()[%[[D0]]]
+// CHECK: %[[PACKED_D1:.+]] = affine.apply #[[MAP]]()[%[[D1]]]
+// CHECK: %[[PACKED_EMPTY:.+]] = tensor.empty(%[[PACKED_D0]], %[[PACKED_D1]]) : tensor<?x?x16x16xf32>
+// CHECK: %[[FILL:.+]] = linalg.fill ins(%{{.+}}) outs(%[[PACKED_EMPTY]]
+// CHECK: return %[[FILL]]
+
+// -----
+
// CHECK: func @fold_self_copy
func.func @fold_self_copy(%0 : memref<4x16xf32>) {
// CHECK-NEXT: return
diff --git a/mlir/test/Dialect/Linalg/data-layout-propagation.mlir b/mlir/test/Dialect/Linalg/data-layout-propagation.mlir
index 3f98bf06433d2ec..4c59c97aecc2519 100644
--- a/mlir/test/Dialect/Linalg/data-layout-propagation.mlir
+++ b/mlir/test/Dialect/Linalg/data-layout-propagation.mlir
@@ -839,47 +839,3 @@ func.func @unpack_different_destination_shape(%arg0: tensor<1x1x1080x1920x16xi32
// CHECK-SAME: inner_dims_pos = [0] inner_tiles = [16]
// CHECK-SAME: into %[[UNPACK_NEW_DEST]]
// CHECK: return %[[UNPACK]] : tensor<16x540x960xi32>
-
-// -----
-
-func.func @fill_pack() -> tensor<24x32x16x16xf32> {
- %dest = tensor.empty() : tensor<384x512xf32>
- %cst = arith.constant 0.000000e+00 : f32
- %0 = tensor.empty() : tensor<24x32x16x16xf32>
- %1 = linalg.fill ins(%cst : f32) outs(%dest : tensor<384x512xf32>) -> tensor<384x512xf32>
- %pack = tensor.pack %1 inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %0 : tensor<384x512xf32> -> tensor<24x32x16x16xf32>
- return %pack : tensor<24x32x16x16xf32>
-}
-// CHECK-LABEL: func.func @fill_pack
-// CHECK: %[[PACKED_EMPTY:.+]] = tensor.empty() : tensor<24x32x16x16xf32>
-// CHECK: %[[FILL:.+]] = linalg.fill ins(%{{.+}}) outs(%[[PACKED_EMPTY]]
-// CHECK: return %[[FILL]]
-
-// -----
-
-#map = affine_map<()[s0] -> (s0 ceildiv 16)>
-func.func @dynamic_fill_pack(%arg0: tensor<?x?xf32>) -> tensor<?x?x16x16xf32> {
- %cst = arith.constant 0.000000e+00 : f32
- %c0 = arith.constant 0 : index
- %c1 = arith.constant 1 : index
- %0 = linalg.fill ins(%cst : f32) outs(%arg0 : tensor<?x?xf32>) -> tensor<?x?xf32>
- %dim = tensor.dim %0, %c0 : tensor<?x?xf32>
- %dim_0 = tensor.dim %0, %c1 : tensor<?x?xf32>
- %1 = affine.apply #map()[%dim]
- %2 = affine.apply #map()[%dim_0]
- %3 = tensor.empty(%1, %2) : tensor<?x?x16x16xf32>
- %pack = tensor.pack %0 padding_value(%cst : f32) inner_dims_pos = [0, 1] inner_tiles = [16, 16] into %3 : tensor<?x?xf32> -> tensor<?x?x16x16xf32>
- return %pack : tensor<?x?x16x16xf32>
-}
-// CHECK-DAG: #[[MAP:.+]] = affine_map<()[s0] -> (s0 ceildiv 16)>
-// CHECK: func.func @dynamic_fill_pack
-// CHECK-SAME: %[[DEST:[a-zA-Z0-9]+]]
-// CHECK-DAG: %[[C0:.+]] = arith.constant 0 : index
-// CHECK-DAG: %[[C1:.+]] = arith.constant 1 : index
-// CHECK: %[[D0:.+]] = tensor.dim %[[DEST]], %[[C0]]
-// CHECK: %[[D1:.+]] = tensor.dim %[[DEST]], %[[C1]]
-// CHECK: %[[PACKED_D0:.+]] = affine.apply #[[MAP]]()[%[[D0]]]
-// CHECK: %[[PACKED_D1:.+]] = affine.apply #[[MAP]]()[%[[D1]]]
-// CHECK: %[[PACKED_EMPTY:.+]] = tensor.empty(%[[PACKED_D0]], %[[PACKED_D1]]) : tensor<?x?x16x16xf32>
-// CHECK: %[[FILL:.+]] = linalg.fill ins(%{{.+}}) outs(%[[PACKED_EMPTY]]
-// CHECK: return %[[FILL]]
>From 3ed7d3e34b2e4810b9415b5e52f54bff63c4b06b Mon Sep 17 00:00:00 2001
From: Fangrui Song <i at maskray.me>
Date: Mon, 11 Sep 2023 13:51:01 -0700
Subject: [PATCH 11/35] [ELF] Reset two member variables in Ctx::reset
Otherwise they are dangling if lldMain is called more than once.
---
lld/ELF/Driver.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp
index 0b24354b3b8df47..9219314111610d1 100644
--- a/lld/ELF/Driver.cpp
+++ b/lld/ELF/Driver.cpp
@@ -104,7 +104,9 @@ void Ctx::reset() {
nonPrevailingSyms.clear();
whyExtractRecords.clear();
backwardReferences.clear();
+ auxiliaryFiles.clear();
hasSympart.store(false, std::memory_order_relaxed);
+ hasTlsIe.store(false, std::memory_order_relaxed);
needsTlsLd.store(false, std::memory_order_relaxed);
scriptSymOrderCounter = 1;
scriptSymOrder.clear();
>From cc7da52315ef1d5649fcc2e09cb37e32b5e2d60f Mon Sep 17 00:00:00 2001
From: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: Mon, 11 Sep 2023 13:58:10 -0700
Subject: [PATCH 12/35] [flang][openacc] Enable lowering support for OpenACC
atomic operations (#65776)
Since the OpenACC atomics specification is a subset of OpenMP atomics,
the same lowering implementation can be used. This change extracts out
the necessary pieces from the OpenMP lowering and puts them in a shared
spot. The shared spot is a header file so that each implementation can
template specialize directly.
After putting the OpenMP implementation in a common spot, the following
changes were needed to make it work for OpenACC:
* Ensure parsing works correctly by avoiding hardcoded offsets.
* Templatize based on atomic type.
* The checking whether it is OpenMP or OpenACC is done by checking for
OmpAtomicClauseList (OpenACC does not implement this so we just
templatize with void). It was preferable to check this instead of atomic
type because in some cases, like atomic capture, the read/write/update
implementations are called - and we want compile time evaluation of
these conditional parts.
* The memory order and hint are used only for OpenMP.
* Generate acc dialect operations instead of omp dialect operations.
---
flang/lib/Lower/Bridge.cpp | 2 +
flang/lib/Lower/DirectivesCommon.h | 593 ++++++++++++++++++
flang/lib/Lower/OpenACC.cpp | 32 +-
flang/lib/Lower/OpenMP.cpp | 519 +--------------
.../test/Lower/OpenACC/acc-atomic-capture.f90 | 99 +++
flang/test/Lower/OpenACC/acc-atomic-read.f90 | 48 ++
.../Lower/OpenACC/acc-atomic-update-hlfir.f90 | 23 +
.../test/Lower/OpenACC/acc-atomic-update.f90 | 74 +++
flang/test/Lower/OpenACC/acc-atomic-write.f90 | 57 ++
9 files changed, 956 insertions(+), 491 deletions(-)
create mode 100644 flang/lib/Lower/DirectivesCommon.h
create mode 100644 flang/test/Lower/OpenACC/acc-atomic-capture.f90
create mode 100644 flang/test/Lower/OpenACC/acc-atomic-read.f90
create mode 100644 flang/test/Lower/OpenACC/acc-atomic-update-hlfir.f90
create mode 100644 flang/test/Lower/OpenACC/acc-atomic-update.f90
create mode 100644 flang/test/Lower/OpenACC/acc-atomic-write.f90
diff --git a/flang/lib/Lower/Bridge.cpp b/flang/lib/Lower/Bridge.cpp
index 75784f4e5a72be2..cbe108194dd212f 100644
--- a/flang/lib/Lower/Bridge.cpp
+++ b/flang/lib/Lower/Bridge.cpp
@@ -2287,9 +2287,11 @@ class FirConverter : public Fortran::lower::AbstractConverter {
void genFIR(const Fortran::parser::OpenACCConstruct &acc) {
mlir::OpBuilder::InsertPoint insertPt = builder->saveInsertionPoint();
+ localSymbols.pushScope();
genOpenACCConstruct(*this, bridge.getSemanticsContext(), getEval(), acc);
for (Fortran::lower::pft::Evaluation &e : getEval().getNestedEvaluations())
genFIR(e);
+ localSymbols.popScope();
builder->restoreInsertionPoint(insertPt);
}
diff --git a/flang/lib/Lower/DirectivesCommon.h b/flang/lib/Lower/DirectivesCommon.h
new file mode 100644
index 000000000000000..35825a20b4cf93f
--- /dev/null
+++ b/flang/lib/Lower/DirectivesCommon.h
@@ -0,0 +1,593 @@
+//===-- Lower/DirectivesCommon.h --------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Coding style: https://mlir.llvm.org/getting_started/DeveloperGuide/
+//
+//===----------------------------------------------------------------------===//
+///
+/// A location to place directive utilities shared across multiple lowering
+/// files, e.g. utilities shared in OpenMP and OpenACC. The header file can
+/// be used for both declarations and templated/inline implementations.
+//===----------------------------------------------------------------------===//
+
+#ifndef FORTRAN_LOWER_DIRECTIVES_COMMON_H
+#define FORTRAN_LOWER_DIRECTIVES_COMMON_H
+
+#include "flang/Common/idioms.h"
+#include "flang/Lower/Bridge.h"
+#include "flang/Lower/ConvertExpr.h"
+#include "flang/Lower/ConvertVariable.h"
+#include "flang/Lower/OpenACC.h"
+#include "flang/Lower/OpenMP.h"
+#include "flang/Lower/PFTBuilder.h"
+#include "flang/Lower/StatementContext.h"
+#include "flang/Optimizer/Builder/BoxValue.h"
+#include "flang/Optimizer/Builder/FIRBuilder.h"
+#include "flang/Optimizer/Builder/Todo.h"
+#include "flang/Optimizer/HLFIR/HLFIROps.h"
+#include "flang/Parser/parse-tree.h"
+#include "flang/Semantics/openmp-directive-sets.h"
+#include "flang/Semantics/tools.h"
+#include "mlir/Dialect/OpenACC/OpenACC.h"
+#include "mlir/Dialect/OpenMP/OpenMPDialect.h"
+#include "mlir/Dialect/SCF/IR/SCF.h"
+#include "llvm/Frontend/OpenMP/OMPConstants.h"
+#include <type_traits>
+
+namespace Fortran {
+namespace lower {
+
+/// Checks if the assignment statement has a single variable on the RHS.
+static inline bool checkForSingleVariableOnRHS(
+ const Fortran::parser::AssignmentStmt &assignmentStmt) {
+ const Fortran::parser::Expr &expr{
+ std::get<Fortran::parser::Expr>(assignmentStmt.t)};
+ const Fortran::common::Indirection<Fortran::parser::Designator> *designator =
+ std::get_if<Fortran::common::Indirection<Fortran::parser::Designator>>(
+ &expr.u);
+ const Fortran::parser::Name *name =
+ designator
+ ? Fortran::semantics::getDesignatorNameIfDataRef(designator->value())
+ : nullptr;
+ return name != nullptr;
+}
+
+/// Checks if the symbol on the LHS of the assignment statement is present in
+/// the RHS expression.
+static inline bool
+checkForSymbolMatch(const Fortran::parser::AssignmentStmt &assignmentStmt) {
+ const auto &var{std::get<Fortran::parser::Variable>(assignmentStmt.t)};
+ const auto &expr{std::get<Fortran::parser::Expr>(assignmentStmt.t)};
+ const auto *e{Fortran::semantics::GetExpr(expr)};
+ const auto *v{Fortran::semantics::GetExpr(var)};
+ auto varSyms{Fortran::evaluate::GetSymbolVector(*v)};
+ const Fortran::semantics::Symbol &varSymbol{*varSyms.front()};
+ for (const Fortran::semantics::Symbol &symbol :
+ Fortran::evaluate::GetSymbolVector(*e))
+ if (varSymbol == symbol)
+ return true;
+ return false;
+}
+
+/// Populates \p hint and \p memoryOrder with appropriate clause information
+/// if present on atomic construct.
+static inline void genOmpAtomicHintAndMemoryOrderClauses(
+ Fortran::lower::AbstractConverter &converter,
+ const Fortran::parser::OmpAtomicClauseList &clauseList,
+ mlir::IntegerAttr &hint,
+ mlir::omp::ClauseMemoryOrderKindAttr &memoryOrder) {
+ fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder();
+ for (const Fortran::parser::OmpAtomicClause &clause : clauseList.v) {
+ if (const auto *ompClause =
+ std::get_if<Fortran::parser::OmpClause>(&clause.u)) {
+ if (const auto *hintClause =
+ std::get_if<Fortran::parser::OmpClause::Hint>(&ompClause->u)) {
+ const auto *expr = Fortran::semantics::GetExpr(hintClause->v);
+ uint64_t hintExprValue = *Fortran::evaluate::ToInt64(*expr);
+ hint = firOpBuilder.getI64IntegerAttr(hintExprValue);
+ }
+ } else if (const auto *ompMemoryOrderClause =
+ std::get_if<Fortran::parser::OmpMemoryOrderClause>(
+ &clause.u)) {
+ if (std::get_if<Fortran::parser::OmpClause::Acquire>(
+ &ompMemoryOrderClause->v.u)) {
+ memoryOrder = mlir::omp::ClauseMemoryOrderKindAttr::get(
+ firOpBuilder.getContext(),
+ mlir::omp::ClauseMemoryOrderKind::Acquire);
+ } else if (std::get_if<Fortran::parser::OmpClause::Relaxed>(
+ &ompMemoryOrderClause->v.u)) {
+ memoryOrder = mlir::omp::ClauseMemoryOrderKindAttr::get(
+ firOpBuilder.getContext(),
+ mlir::omp::ClauseMemoryOrderKind::Relaxed);
+ } else if (std::get_if<Fortran::parser::OmpClause::SeqCst>(
+ &ompMemoryOrderClause->v.u)) {
+ memoryOrder = mlir::omp::ClauseMemoryOrderKindAttr::get(
+ firOpBuilder.getContext(),
+ mlir::omp::ClauseMemoryOrderKind::Seq_cst);
+ } else if (std::get_if<Fortran::parser::OmpClause::Release>(
+ &ompMemoryOrderClause->v.u)) {
+ memoryOrder = mlir::omp::ClauseMemoryOrderKindAttr::get(
+ firOpBuilder.getContext(),
+ mlir::omp::ClauseMemoryOrderKind::Release);
+ }
+ }
+ }
+}
+
+/// Used to generate atomic.read operation which is created in existing
+/// location set by builder.
+template <typename AtomicListT>
+static inline void genOmpAccAtomicCaptureStatement(
+ Fortran::lower::AbstractConverter &converter, mlir::Value fromAddress,
+ mlir::Value toAddress,
+ [[maybe_unused]] const AtomicListT *leftHandClauseList,
+ [[maybe_unused]] const AtomicListT *rightHandClauseList,
+ mlir::Type elementType) {
+ // Generate `atomic.read` operation for atomic assigment statements
+ fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder();
+ mlir::Location currentLocation = converter.getCurrentLocation();
+
+ if constexpr (std::is_same<AtomicListT,
+ Fortran::parser::OmpAtomicClauseList>()) {
+ // If no hint clause is specified, the effect is as if
+ // hint(omp_sync_hint_none) had been specified.
+ mlir::IntegerAttr hint = nullptr;
+
+ mlir::omp::ClauseMemoryOrderKindAttr memoryOrder = nullptr;
+ if (leftHandClauseList)
+ genOmpAtomicHintAndMemoryOrderClauses(converter, *leftHandClauseList,
+ hint, memoryOrder);
+ if (rightHandClauseList)
+ genOmpAtomicHintAndMemoryOrderClauses(converter, *rightHandClauseList,
+ hint, memoryOrder);
+ firOpBuilder.create<mlir::omp::AtomicReadOp>(
+ currentLocation, fromAddress, toAddress,
+ mlir::TypeAttr::get(elementType), hint, memoryOrder);
+ } else {
+ firOpBuilder.create<mlir::acc::AtomicReadOp>(
+ currentLocation, fromAddress, toAddress,
+ mlir::TypeAttr::get(elementType));
+ }
+}
+
+/// Used to generate atomic.write operation which is created in existing
+/// location set by builder.
+template <typename AtomicListT>
+static inline void genOmpAccAtomicWriteStatement(
+ Fortran::lower::AbstractConverter &converter, mlir::Value lhsAddr,
+ mlir::Value rhsExpr, [[maybe_unused]] const AtomicListT *leftHandClauseList,
+ [[maybe_unused]] const AtomicListT *rightHandClauseList,
+ mlir::Value *evaluatedExprValue = nullptr) {
+ // Generate `atomic.write` operation for atomic assignment statements
+ fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder();
+ mlir::Location currentLocation = converter.getCurrentLocation();
+
+ if constexpr (std::is_same<AtomicListT,
+ Fortran::parser::OmpAtomicClauseList>()) {
+ // If no hint clause is specified, the effect is as if
+ // hint(omp_sync_hint_none) had been specified.
+ mlir::IntegerAttr hint = nullptr;
+ mlir::omp::ClauseMemoryOrderKindAttr memoryOrder = nullptr;
+ if (leftHandClauseList)
+ genOmpAtomicHintAndMemoryOrderClauses(converter, *leftHandClauseList,
+ hint, memoryOrder);
+ if (rightHandClauseList)
+ genOmpAtomicHintAndMemoryOrderClauses(converter, *rightHandClauseList,
+ hint, memoryOrder);
+ firOpBuilder.create<mlir::omp::AtomicWriteOp>(currentLocation, lhsAddr,
+ rhsExpr, hint, memoryOrder);
+ } else {
+ firOpBuilder.create<mlir::acc::AtomicWriteOp>(currentLocation, lhsAddr,
+ rhsExpr);
+ }
+}
+
+/// Used to generate atomic.update operation which is created in existing
+/// location set by builder.
+template <typename AtomicListT>
+static inline void genOmpAccAtomicUpdateStatement(
+ Fortran::lower::AbstractConverter &converter, mlir::Value lhsAddr,
+ mlir::Type varType, const Fortran::parser::Variable &assignmentStmtVariable,
+ const Fortran::parser::Expr &assignmentStmtExpr,
+ [[maybe_unused]] const AtomicListT *leftHandClauseList,
+ [[maybe_unused]] const AtomicListT *rightHandClauseList) {
+ // Generate `omp.atomic.update` operation for atomic assignment statements
+ fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder();
+ mlir::Location currentLocation = converter.getCurrentLocation();
+
+ const auto *varDesignator =
+ std::get_if<Fortran::common::Indirection<Fortran::parser::Designator>>(
+ &assignmentStmtVariable.u);
+ assert(varDesignator && "Variable designator for atomic update assignment "
+ "statement does not exist");
+ const Fortran::parser::Name *name =
+ Fortran::semantics::getDesignatorNameIfDataRef(varDesignator->value());
+ if (!name)
+ TODO(converter.getCurrentLocation(),
+ "Array references as atomic update variable");
+ assert(name && name->symbol &&
+ "No symbol attached to atomic update variable");
+ if (Fortran::semantics::IsAllocatableOrPointer(name->symbol->GetUltimate()))
+ converter.bindSymbol(*name->symbol, lhsAddr);
+
+ // Lowering is in two steps :
+ // subroutine sb
+ // integer :: a, b
+ // !$omp atomic update
+ // a = a + b
+ // end subroutine
+ //
+ // 1. Lower to scf.execute_region_op
+ //
+ // func.func @_QPsb() {
+ // %0 = fir.alloca i32 {bindc_name = "a", uniq_name = "_QFsbEa"}
+ // %1 = fir.alloca i32 {bindc_name = "b", uniq_name = "_QFsbEb"}
+ // %2 = scf.execute_region -> i32 {
+ // %3 = fir.load %0 : !fir.ref<i32>
+ // %4 = fir.load %1 : !fir.ref<i32>
+ // %5 = arith.addi %3, %4 : i32
+ // scf.yield %5 : i32
+ // }
+ // return
+ // }
+ auto tempOp =
+ firOpBuilder.create<mlir::scf::ExecuteRegionOp>(currentLocation, varType);
+ firOpBuilder.createBlock(&tempOp.getRegion());
+ mlir::Block &block = tempOp.getRegion().back();
+ firOpBuilder.setInsertionPointToEnd(&block);
+ Fortran::lower::StatementContext stmtCtx;
+ mlir::Value rhsExpr = fir::getBase(converter.genExprValue(
+ *Fortran::semantics::GetExpr(assignmentStmtExpr), stmtCtx));
+ mlir::Value convertResult =
+ firOpBuilder.createConvert(currentLocation, varType, rhsExpr);
+ // Insert the terminator: YieldOp.
+ firOpBuilder.create<mlir::scf::YieldOp>(currentLocation, convertResult);
+ firOpBuilder.setInsertionPointToStart(&block);
+
+ // 2. Create the omp.atomic.update Operation using the Operations in the
+ // temporary scf.execute_region Operation.
+ //
+ // func.func @_QPsb() {
+ // %0 = fir.alloca i32 {bindc_name = "a", uniq_name = "_QFsbEa"}
+ // %1 = fir.alloca i32 {bindc_name = "b", uniq_name = "_QFsbEb"}
+ // %2 = fir.load %1 : !fir.ref<i32>
+ // omp.atomic.update %0 : !fir.ref<i32> {
+ // ^bb0(%arg0: i32):
+ // %3 = fir.load %1 : !fir.ref<i32>
+ // %4 = arith.addi %arg0, %3 : i32
+ // omp.yield(%3 : i32)
+ // }
+ // return
+ // }
+ mlir::Value updateVar = converter.getSymbolAddress(*name->symbol);
+ if (auto decl = updateVar.getDefiningOp<hlfir::DeclareOp>())
+ updateVar = decl.getBase();
+
+ firOpBuilder.setInsertionPointAfter(tempOp);
+
+ mlir::Operation *atomicUpdateOp = nullptr;
+ if constexpr (std::is_same<AtomicListT,
+ Fortran::parser::OmpAtomicClauseList>()) {
+ // If no hint clause is specified, the effect is as if
+ // hint(omp_sync_hint_none) had been specified.
+ mlir::IntegerAttr hint = nullptr;
+ mlir::omp::ClauseMemoryOrderKindAttr memoryOrder = nullptr;
+ if (leftHandClauseList)
+ genOmpAtomicHintAndMemoryOrderClauses(converter, *leftHandClauseList,
+ hint, memoryOrder);
+ if (rightHandClauseList)
+ genOmpAtomicHintAndMemoryOrderClauses(converter, *rightHandClauseList,
+ hint, memoryOrder);
+ atomicUpdateOp = firOpBuilder.create<mlir::omp::AtomicUpdateOp>(
+ currentLocation, updateVar, hint, memoryOrder);
+ } else {
+ atomicUpdateOp = firOpBuilder.create<mlir::acc::AtomicUpdateOp>(
+ currentLocation, updateVar);
+ }
+
+ llvm::SmallVector<mlir::Type> varTys = {varType};
+ llvm::SmallVector<mlir::Location> locs = {currentLocation};
+ firOpBuilder.createBlock(&atomicUpdateOp->getRegion(0), {}, varTys, locs);
+ mlir::Value val =
+ fir::getBase(atomicUpdateOp->getRegion(0).front().getArgument(0));
+
+ llvm::SmallVector<mlir::Operation *> ops;
+ for (mlir::Operation &op : tempOp.getRegion().getOps())
+ ops.push_back(&op);
+
+ // SCF Yield is converted to OMP Yield. All other operations are copied
+ for (mlir::Operation *op : ops) {
+ if (auto y = mlir::dyn_cast<mlir::scf::YieldOp>(op)) {
+ firOpBuilder.setInsertionPointToEnd(
+ &atomicUpdateOp->getRegion(0).front());
+ if constexpr (std::is_same<AtomicListT,
+ Fortran::parser::OmpAtomicClauseList>()) {
+ firOpBuilder.create<mlir::omp::YieldOp>(currentLocation,
+ y.getResults());
+ } else {
+ firOpBuilder.create<mlir::acc::YieldOp>(currentLocation,
+ y.getResults());
+ }
+ op->erase();
+ } else {
+ op->remove();
+ atomicUpdateOp->getRegion(0).front().push_back(op);
+ }
+ }
+
+ // Remove the load and replace all uses of load with the block argument
+ for (mlir::Operation &op : atomicUpdateOp->getRegion(0).getOps()) {
+ fir::LoadOp y = mlir::dyn_cast<fir::LoadOp>(&op);
+ if (y && y.getMemref() == updateVar)
+ y.getRes().replaceAllUsesWith(val);
+ }
+
+ tempOp.erase();
+}
+
+/// Processes an atomic construct with write clause.
+template <typename AtomicT, typename AtomicListT>
+void genOmpAccAtomicWrite(Fortran::lower::AbstractConverter &converter,
+ const AtomicT &atomicWrite) {
+ const AtomicListT *rightHandClauseList = nullptr;
+ const AtomicListT *leftHandClauseList = nullptr;
+ if constexpr (std::is_same<AtomicListT,
+ Fortran::parser::OmpAtomicClauseList>()) {
+ // Get the address of atomic read operands.
+ rightHandClauseList = &std::get<2>(atomicWrite.t);
+ leftHandClauseList = &std::get<0>(atomicWrite.t);
+ }
+
+ const Fortran::parser::AssignmentStmt &stmt =
+ std::get<Fortran::parser::Statement<Fortran::parser::AssignmentStmt>>(
+ atomicWrite.t)
+ .statement;
+ const Fortran::evaluate::Assignment &assign = *stmt.typedAssignment->v;
+ Fortran::lower::StatementContext stmtCtx;
+ // Get the value and address of atomic write operands.
+ mlir::Value rhsExpr =
+ fir::getBase(converter.genExprValue(assign.rhs, stmtCtx));
+ mlir::Value lhsAddr =
+ fir::getBase(converter.genExprAddr(assign.lhs, stmtCtx));
+ genOmpAccAtomicWriteStatement(converter, lhsAddr, rhsExpr, leftHandClauseList,
+ rightHandClauseList);
+}
+
+/// Processes an atomic construct with read clause.
+template <typename AtomicT, typename AtomicListT>
+void genOmpAccAtomicRead(Fortran::lower::AbstractConverter &converter,
+ const AtomicT &atomicRead) {
+ const AtomicListT *rightHandClauseList = nullptr;
+ const AtomicListT *leftHandClauseList = nullptr;
+ if constexpr (std::is_same<AtomicListT,
+ Fortran::parser::OmpAtomicClauseList>()) {
+ // Get the address of atomic read operands.
+ rightHandClauseList = &std::get<2>(atomicRead.t);
+ leftHandClauseList = &std::get<0>(atomicRead.t);
+ }
+
+ const auto &assignmentStmtExpr = std::get<Fortran::parser::Expr>(
+ std::get<Fortran::parser::Statement<Fortran::parser::AssignmentStmt>>(
+ atomicRead.t)
+ .statement.t);
+ const auto &assignmentStmtVariable = std::get<Fortran::parser::Variable>(
+ std::get<Fortran::parser::Statement<Fortran::parser::AssignmentStmt>>(
+ atomicRead.t)
+ .statement.t);
+
+ Fortran::lower::StatementContext stmtCtx;
+ const Fortran::semantics::SomeExpr &fromExpr =
+ *Fortran::semantics::GetExpr(assignmentStmtExpr);
+ mlir::Type elementType = converter.genType(fromExpr);
+ mlir::Value fromAddress =
+ fir::getBase(converter.genExprAddr(fromExpr, stmtCtx));
+ mlir::Value toAddress = fir::getBase(converter.genExprAddr(
+ *Fortran::semantics::GetExpr(assignmentStmtVariable), stmtCtx));
+ genOmpAccAtomicCaptureStatement(converter, fromAddress, toAddress,
+ leftHandClauseList, rightHandClauseList,
+ elementType);
+}
+
+/// Processes an atomic construct with update clause.
+template <typename AtomicT, typename AtomicListT>
+void genOmpAccAtomicUpdate(Fortran::lower::AbstractConverter &converter,
+ const AtomicT &atomicUpdate) {
+ const AtomicListT *rightHandClauseList = nullptr;
+ const AtomicListT *leftHandClauseList = nullptr;
+ if constexpr (std::is_same<AtomicListT,
+ Fortran::parser::OmpAtomicClauseList>()) {
+ // Get the address of atomic read operands.
+ rightHandClauseList = &std::get<2>(atomicUpdate.t);
+ leftHandClauseList = &std::get<0>(atomicUpdate.t);
+ }
+
+ const auto &assignmentStmtExpr = std::get<Fortran::parser::Expr>(
+ std::get<Fortran::parser::Statement<Fortran::parser::AssignmentStmt>>(
+ atomicUpdate.t)
+ .statement.t);
+ const auto &assignmentStmtVariable = std::get<Fortran::parser::Variable>(
+ std::get<Fortran::parser::Statement<Fortran::parser::AssignmentStmt>>(
+ atomicUpdate.t)
+ .statement.t);
+
+ Fortran::lower::StatementContext stmtCtx;
+ mlir::Value lhsAddr = fir::getBase(converter.genExprAddr(
+ *Fortran::semantics::GetExpr(assignmentStmtVariable), stmtCtx));
+ mlir::Type varType =
+ fir::getBase(
+ converter.genExprValue(
+ *Fortran::semantics::GetExpr(assignmentStmtVariable), stmtCtx))
+ .getType();
+ genOmpAccAtomicUpdateStatement<AtomicListT>(
+ converter, lhsAddr, varType, assignmentStmtVariable, assignmentStmtExpr,
+ leftHandClauseList, rightHandClauseList);
+}
+
+/// Processes an atomic construct with no clause - which implies update clause.
+template <typename AtomicT, typename AtomicListT>
+void genOmpAtomic(Fortran::lower::AbstractConverter &converter,
+ const AtomicT &atomicConstruct) {
+ const AtomicListT &atomicClauseList =
+ std::get<AtomicListT>(atomicConstruct.t);
+ const auto &assignmentStmtExpr = std::get<Fortran::parser::Expr>(
+ std::get<Fortran::parser::Statement<Fortran::parser::AssignmentStmt>>(
+ atomicConstruct.t)
+ .statement.t);
+ const auto &assignmentStmtVariable = std::get<Fortran::parser::Variable>(
+ std::get<Fortran::parser::Statement<Fortran::parser::AssignmentStmt>>(
+ atomicConstruct.t)
+ .statement.t);
+ Fortran::lower::StatementContext stmtCtx;
+ mlir::Value lhsAddr = fir::getBase(converter.genExprAddr(
+ *Fortran::semantics::GetExpr(assignmentStmtVariable), stmtCtx));
+ mlir::Type varType =
+ fir::getBase(
+ converter.genExprValue(
+ *Fortran::semantics::GetExpr(assignmentStmtVariable), stmtCtx))
+ .getType();
+ // If atomic-clause is not present on the construct, the behaviour is as if
+ // the update clause is specified (for both OpenMP and OpenACC).
+ genOmpAccAtomicUpdateStatement<AtomicListT>(
+ converter, lhsAddr, varType, assignmentStmtVariable, assignmentStmtExpr,
+ &atomicClauseList, nullptr);
+}
+
+/// Processes an atomic construct with capture clause.
+template <typename AtomicT, typename AtomicListT>
+void genOmpAccAtomicCapture(Fortran::lower::AbstractConverter &converter,
+ const AtomicT &atomicCapture) {
+ fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder();
+ mlir::Location currentLocation = converter.getCurrentLocation();
+
+ const Fortran::parser::AssignmentStmt &stmt1 =
+ std::get<typename AtomicT::Stmt1>(atomicCapture.t).v.statement;
+ const auto &stmt1Var{std::get<Fortran::parser::Variable>(stmt1.t)};
+ const auto &stmt1Expr{std::get<Fortran::parser::Expr>(stmt1.t)};
+ const Fortran::parser::AssignmentStmt &stmt2 =
+ std::get<typename AtomicT::Stmt2>(atomicCapture.t).v.statement;
+ const auto &stmt2Var{std::get<Fortran::parser::Variable>(stmt2.t)};
+ const auto &stmt2Expr{std::get<Fortran::parser::Expr>(stmt2.t)};
+
+ // Pre-evaluate expressions to be used in the various operations inside
+ // `atomic.capture` since it is not desirable to have anything other than
+ // a `atomic.read`, `atomic.write`, or `atomic.update` operation
+ // inside `atomic.capture`
+ Fortran::lower::StatementContext stmtCtx;
+ mlir::Value stmt1LHSArg, stmt1RHSArg, stmt2LHSArg, stmt2RHSArg;
+ mlir::Type elementType;
+ // LHS evaluations are common to all combinations of `atomic.capture`
+ stmt1LHSArg = fir::getBase(
+ converter.genExprAddr(*Fortran::semantics::GetExpr(stmt1Var), stmtCtx));
+ stmt2LHSArg = fir::getBase(
+ converter.genExprAddr(*Fortran::semantics::GetExpr(stmt2Var), stmtCtx));
+
+ // Operation specific RHS evaluations
+ if (checkForSingleVariableOnRHS(stmt1)) {
+ // Atomic capture construct is of the form [capture-stmt, update-stmt] or
+ // of the form [capture-stmt, write-stmt]
+ stmt1RHSArg = fir::getBase(converter.genExprAddr(
+ *Fortran::semantics::GetExpr(stmt1Expr), stmtCtx));
+ stmt2RHSArg = fir::getBase(converter.genExprValue(
+ *Fortran::semantics::GetExpr(stmt2Expr), stmtCtx));
+
+ } else {
+ // Atomic capture construct is of the form [update-stmt, capture-stmt]
+ stmt1RHSArg = fir::getBase(converter.genExprValue(
+ *Fortran::semantics::GetExpr(stmt1Expr), stmtCtx));
+ stmt2RHSArg = fir::getBase(converter.genExprAddr(
+ *Fortran::semantics::GetExpr(stmt2Expr), stmtCtx));
+ }
+ // Type information used in generation of `atomic.update` operation
+ mlir::Type stmt1VarType =
+ fir::getBase(converter.genExprValue(
+ *Fortran::semantics::GetExpr(stmt1Var), stmtCtx))
+ .getType();
+ mlir::Type stmt2VarType =
+ fir::getBase(converter.genExprValue(
+ *Fortran::semantics::GetExpr(stmt2Var), stmtCtx))
+ .getType();
+
+ mlir::Operation *atomicCaptureOp = nullptr;
+ if constexpr (std::is_same<AtomicListT,
+ Fortran::parser::OmpAtomicClauseList>()) {
+ mlir::IntegerAttr hint = nullptr;
+ mlir::omp::ClauseMemoryOrderKindAttr memoryOrder = nullptr;
+ const AtomicListT &rightHandClauseList = std::get<2>(atomicCapture.t);
+ const AtomicListT &leftHandClauseList = std::get<0>(atomicCapture.t);
+ genOmpAtomicHintAndMemoryOrderClauses(converter, leftHandClauseList, hint,
+ memoryOrder);
+ genOmpAtomicHintAndMemoryOrderClauses(converter, rightHandClauseList, hint,
+ memoryOrder);
+ atomicCaptureOp = firOpBuilder.create<mlir::omp::AtomicCaptureOp>(
+ currentLocation, hint, memoryOrder);
+ } else {
+ atomicCaptureOp =
+ firOpBuilder.create<mlir::acc::AtomicCaptureOp>(currentLocation);
+ }
+
+ firOpBuilder.createBlock(&(atomicCaptureOp->getRegion(0)));
+ mlir::Block &block = atomicCaptureOp->getRegion(0).back();
+ firOpBuilder.setInsertionPointToStart(&block);
+ if (checkForSingleVariableOnRHS(stmt1)) {
+ if (checkForSymbolMatch(stmt2)) {
+ // Atomic capture construct is of the form [capture-stmt, update-stmt]
+ const Fortran::semantics::SomeExpr &fromExpr =
+ *Fortran::semantics::GetExpr(stmt1Expr);
+ elementType = converter.genType(fromExpr);
+ genOmpAccAtomicCaptureStatement<AtomicListT>(
+ converter, stmt1RHSArg, stmt1LHSArg,
+ /*leftHandClauseList=*/nullptr,
+ /*rightHandClauseList=*/nullptr, elementType);
+ genOmpAccAtomicUpdateStatement<AtomicListT>(
+ converter, stmt1RHSArg, stmt2VarType, stmt2Var, stmt2Expr,
+ /*leftHandClauseList=*/nullptr,
+ /*rightHandClauseList=*/nullptr);
+ } else {
+ // Atomic capture construct is of the form [capture-stmt, write-stmt]
+ const Fortran::semantics::SomeExpr &fromExpr =
+ *Fortran::semantics::GetExpr(stmt1Expr);
+ elementType = converter.genType(fromExpr);
+ genOmpAccAtomicCaptureStatement<AtomicListT>(
+ converter, stmt1RHSArg, stmt1LHSArg,
+ /*leftHandClauseList=*/nullptr,
+ /*rightHandClauseList=*/nullptr, elementType);
+ genOmpAccAtomicWriteStatement<AtomicListT>(
+ converter, stmt1RHSArg, stmt2RHSArg,
+ /*leftHandClauseList=*/nullptr,
+ /*rightHandClauseList=*/nullptr);
+ }
+ } else {
+ // Atomic capture construct is of the form [update-stmt, capture-stmt]
+ firOpBuilder.setInsertionPointToEnd(&block);
+ const Fortran::semantics::SomeExpr &fromExpr =
+ *Fortran::semantics::GetExpr(stmt2Expr);
+ elementType = converter.genType(fromExpr);
+ genOmpAccAtomicCaptureStatement<AtomicListT>(
+ converter, stmt1LHSArg, stmt2LHSArg,
+ /*leftHandClauseList=*/nullptr,
+ /*rightHandClauseList=*/nullptr, elementType);
+ firOpBuilder.setInsertionPointToStart(&block);
+ genOmpAccAtomicUpdateStatement<AtomicListT>(
+ converter, stmt1LHSArg, stmt1VarType, stmt1Var, stmt1Expr,
+ /*leftHandClauseList=*/nullptr,
+ /*rightHandClauseList=*/nullptr);
+ }
+ firOpBuilder.setInsertionPointToEnd(&block);
+ if constexpr (std::is_same<AtomicListT,
+ Fortran::parser::OmpAtomicClauseList>()) {
+ firOpBuilder.create<mlir::omp::TerminatorOp>(currentLocation);
+ } else {
+ firOpBuilder.create<mlir::acc::TerminatorOp>(currentLocation);
+ }
+ firOpBuilder.setInsertionPointToStart(&block);
+}
+
+} // namespace lower
+} // namespace Fortran
+
+#endif // FORTRAN_LOWER_DIRECTIVES_COMMON_H
\ No newline at end of file
diff --git a/flang/lib/Lower/OpenACC.cpp b/flang/lib/Lower/OpenACC.cpp
index a59a71ff8d8ae68..732765c4def59cb 100644
--- a/flang/lib/Lower/OpenACC.cpp
+++ b/flang/lib/Lower/OpenACC.cpp
@@ -11,6 +11,7 @@
//===----------------------------------------------------------------------===//
#include "flang/Lower/OpenACC.h"
+#include "DirectivesCommon.h"
#include "flang/Common/idioms.h"
#include "flang/Lower/Bridge.h"
#include "flang/Lower/ConvertType.h"
@@ -3096,6 +3097,34 @@ void Fortran::lower::finalizeOpenACCRoutineAttachment(
accRoutineInfos.clear();
}
+static void
+genACC(Fortran::lower::AbstractConverter &converter,
+ Fortran::lower::pft::Evaluation &eval,
+ const Fortran::parser::OpenACCAtomicConstruct &atomicConstruct) {
+ std::visit(
+ Fortran::common::visitors{
+ [&](const Fortran::parser::AccAtomicRead &atomicRead) {
+ Fortran::lower::genOmpAccAtomicRead<Fortran::parser::AccAtomicRead,
+ void>(converter, atomicRead);
+ },
+ [&](const Fortran::parser::AccAtomicWrite &atomicWrite) {
+ Fortran::lower::genOmpAccAtomicWrite<
+ Fortran::parser::AccAtomicWrite, void>(converter, atomicWrite);
+ },
+ [&](const Fortran::parser::AccAtomicUpdate &atomicUpdate) {
+ Fortran::lower::genOmpAccAtomicUpdate<
+ Fortran::parser::AccAtomicUpdate, void>(converter,
+ atomicUpdate);
+ },
+ [&](const Fortran::parser::AccAtomicCapture &atomicCapture) {
+ Fortran::lower::genOmpAccAtomicCapture<
+ Fortran::parser::AccAtomicCapture, void>(converter,
+ atomicCapture);
+ },
+ },
+ atomicConstruct.u);
+}
+
static void
genACC(Fortran::lower::AbstractConverter &converter,
Fortran::semantics::SemanticsContext &semanticsContext,
@@ -3160,8 +3189,7 @@ void Fortran::lower::genOpenACCConstruct(
genACC(converter, waitConstruct);
},
[&](const Fortran::parser::OpenACCAtomicConstruct &atomicConstruct) {
- TODO(converter.genLocation(atomicConstruct.source),
- "OpenACC Atomic construct not lowered yet!");
+ genACC(converter, eval, atomicConstruct);
},
},
accConstruct.u);
diff --git a/flang/lib/Lower/OpenMP.cpp b/flang/lib/Lower/OpenMP.cpp
index aef9352e70ea32f..e4532c5e9ed8971 100644
--- a/flang/lib/Lower/OpenMP.cpp
+++ b/flang/lib/Lower/OpenMP.cpp
@@ -11,6 +11,7 @@
//===----------------------------------------------------------------------===//
#include "flang/Lower/OpenMP.h"
+#include "DirectivesCommon.h"
#include "flang/Common/idioms.h"
#include "flang/Lower/Bridge.h"
#include "flang/Lower/ConvertExpr.h"
@@ -2952,499 +2953,39 @@ genOMP(Fortran::lower::AbstractConverter &converter,
allocatorOperands, nowaitClauseOperand);
}
-static bool checkForSingleVariableOnRHS(
- const Fortran::parser::AssignmentStmt &assignmentStmt) {
- // Check if the assignment statement has a single variable on the RHS
- const Fortran::parser::Expr &expr{
- std::get<Fortran::parser::Expr>(assignmentStmt.t)};
- const Fortran::common::Indirection<Fortran::parser::Designator> *designator =
- std::get_if<Fortran::common::Indirection<Fortran::parser::Designator>>(
- &expr.u);
- const Fortran::parser::Name *name =
- designator
- ? Fortran::semantics::getDesignatorNameIfDataRef(designator->value())
- : nullptr;
- return name != nullptr;
-}
-
-static bool
-checkForSymbolMatch(const Fortran::parser::AssignmentStmt &assignmentStmt) {
- // Check if the symbol on the LHS of the assignment statement is present in
- // the RHS expression
- const auto &var{std::get<Fortran::parser::Variable>(assignmentStmt.t)};
- const auto &expr{std::get<Fortran::parser::Expr>(assignmentStmt.t)};
- const auto *e{Fortran::semantics::GetExpr(expr)};
- const auto *v{Fortran::semantics::GetExpr(var)};
- auto varSyms{Fortran::evaluate::GetSymbolVector(*v)};
- const Fortran::semantics::Symbol &varSymbol{*varSyms.front()};
- for (const Fortran::semantics::Symbol &symbol :
- Fortran::evaluate::GetSymbolVector(*e))
- if (varSymbol == symbol)
- return true;
- return false;
-}
-
-static void genOmpAtomicHintAndMemoryOrderClauses(
- Fortran::lower::AbstractConverter &converter,
- const Fortran::parser::OmpAtomicClauseList &clauseList,
- mlir::IntegerAttr &hint,
- mlir::omp::ClauseMemoryOrderKindAttr &memoryOrder) {
- fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder();
- for (const Fortran::parser::OmpAtomicClause &clause : clauseList.v) {
- if (const auto *ompClause =
- std::get_if<Fortran::parser::OmpClause>(&clause.u)) {
- if (const auto *hintClause =
- std::get_if<Fortran::parser::OmpClause::Hint>(&ompClause->u)) {
- const auto *expr = Fortran::semantics::GetExpr(hintClause->v);
- uint64_t hintExprValue = *Fortran::evaluate::ToInt64(*expr);
- hint = firOpBuilder.getI64IntegerAttr(hintExprValue);
- }
- } else if (const auto *ompMemoryOrderClause =
- std::get_if<Fortran::parser::OmpMemoryOrderClause>(
- &clause.u)) {
- if (std::get_if<Fortran::parser::OmpClause::Acquire>(
- &ompMemoryOrderClause->v.u)) {
- memoryOrder = mlir::omp::ClauseMemoryOrderKindAttr::get(
- firOpBuilder.getContext(),
- mlir::omp::ClauseMemoryOrderKind::Acquire);
- } else if (std::get_if<Fortran::parser::OmpClause::Relaxed>(
- &ompMemoryOrderClause->v.u)) {
- memoryOrder = mlir::omp::ClauseMemoryOrderKindAttr::get(
- firOpBuilder.getContext(),
- mlir::omp::ClauseMemoryOrderKind::Relaxed);
- } else if (std::get_if<Fortran::parser::OmpClause::SeqCst>(
- &ompMemoryOrderClause->v.u)) {
- memoryOrder = mlir::omp::ClauseMemoryOrderKindAttr::get(
- firOpBuilder.getContext(),
- mlir::omp::ClauseMemoryOrderKind::Seq_cst);
- } else if (std::get_if<Fortran::parser::OmpClause::Release>(
- &ompMemoryOrderClause->v.u)) {
- memoryOrder = mlir::omp::ClauseMemoryOrderKindAttr::get(
- firOpBuilder.getContext(),
- mlir::omp::ClauseMemoryOrderKind::Release);
- }
- }
- }
-}
-
-static void genOmpAtomicCaptureStatement(
- Fortran::lower::AbstractConverter &converter,
- Fortran::lower::pft::Evaluation &eval, mlir::Value fromAddress,
- mlir::Value toAddress,
- const Fortran::parser::OmpAtomicClauseList *leftHandClauseList,
- const Fortran::parser::OmpAtomicClauseList *rightHandClauseList,
- mlir::Type elementType) {
- // Generate `omp.atomic.read` operation for atomic assigment statements
- fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder();
- mlir::Location currentLocation = converter.getCurrentLocation();
-
- // If no hint clause is specified, the effect is as if
- // hint(omp_sync_hint_none) had been specified.
- mlir::IntegerAttr hint = nullptr;
-
- mlir::omp::ClauseMemoryOrderKindAttr memoryOrder = nullptr;
- if (leftHandClauseList)
- genOmpAtomicHintAndMemoryOrderClauses(converter, *leftHandClauseList, hint,
- memoryOrder);
- if (rightHandClauseList)
- genOmpAtomicHintAndMemoryOrderClauses(converter, *rightHandClauseList, hint,
- memoryOrder);
- firOpBuilder.create<mlir::omp::AtomicReadOp>(
- currentLocation, fromAddress, toAddress, mlir::TypeAttr::get(elementType),
- hint, memoryOrder);
-}
-
-static void genOmpAtomicWriteStatement(
- Fortran::lower::AbstractConverter &converter,
- Fortran::lower::pft::Evaluation &eval, mlir::Value lhsAddr,
- mlir::Value rhsExpr,
- const Fortran::parser::OmpAtomicClauseList *leftHandClauseList,
- const Fortran::parser::OmpAtomicClauseList *rightHandClauseList,
- mlir::Value *evaluatedExprValue = nullptr) {
- // Generate `omp.atomic.write` operation for atomic assignment statements
- fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder();
- mlir::Location currentLocation = converter.getCurrentLocation();
- // If no hint clause is specified, the effect is as if
- // hint(omp_sync_hint_none) had been specified.
- mlir::IntegerAttr hint = nullptr;
- mlir::omp::ClauseMemoryOrderKindAttr memoryOrder = nullptr;
- if (leftHandClauseList)
- genOmpAtomicHintAndMemoryOrderClauses(converter, *leftHandClauseList, hint,
- memoryOrder);
- if (rightHandClauseList)
- genOmpAtomicHintAndMemoryOrderClauses(converter, *rightHandClauseList, hint,
- memoryOrder);
- firOpBuilder.create<mlir::omp::AtomicWriteOp>(currentLocation, lhsAddr,
- rhsExpr, hint, memoryOrder);
-}
-
-static void genOmpAtomicUpdateStatement(
- Fortran::lower::AbstractConverter &converter,
- Fortran::lower::pft::Evaluation &eval, mlir::Value lhsAddr,
- mlir::Type varType, const Fortran::parser::Variable &assignmentStmtVariable,
- const Fortran::parser::Expr &assignmentStmtExpr,
- const Fortran::parser::OmpAtomicClauseList *leftHandClauseList,
- const Fortran::parser::OmpAtomicClauseList *rightHandClauseList) {
- // Generate `omp.atomic.update` operation for atomic assignment statements
- fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder();
- mlir::Location currentLocation = converter.getCurrentLocation();
-
- // If no hint clause is specified, the effect is as if
- // hint(omp_sync_hint_none) had been specified.
- mlir::IntegerAttr hint = nullptr;
- mlir::omp::ClauseMemoryOrderKindAttr memoryOrder = nullptr;
- if (leftHandClauseList)
- genOmpAtomicHintAndMemoryOrderClauses(converter, *leftHandClauseList, hint,
- memoryOrder);
- if (rightHandClauseList)
- genOmpAtomicHintAndMemoryOrderClauses(converter, *rightHandClauseList, hint,
- memoryOrder);
- const auto *varDesignator =
- std::get_if<Fortran::common::Indirection<Fortran::parser::Designator>>(
- &assignmentStmtVariable.u);
- assert(varDesignator && "Variable designator for atomic update assignment "
- "statement does not exist");
- const Fortran::parser::Name *name =
- Fortran::semantics::getDesignatorNameIfDataRef(varDesignator->value());
- if (!name)
- TODO(converter.getCurrentLocation(),
- "Array references as atomic update variable");
- assert(name && name->symbol &&
- "No symbol attached to atomic update variable");
- if (Fortran::semantics::IsAllocatableOrPointer(name->symbol->GetUltimate()))
- converter.bindSymbol(*name->symbol, lhsAddr);
-
- // Lowering is in two steps :
- // subroutine sb
- // integer :: a, b
- // !$omp atomic update
- // a = a + b
- // end subroutine
- //
- // 1. Lower to scf.execute_region_op
- //
- // func.func @_QPsb() {
- // %0 = fir.alloca i32 {bindc_name = "a", uniq_name = "_QFsbEa"}
- // %1 = fir.alloca i32 {bindc_name = "b", uniq_name = "_QFsbEb"}
- // %2 = scf.execute_region -> i32 {
- // %3 = fir.load %0 : !fir.ref<i32>
- // %4 = fir.load %1 : !fir.ref<i32>
- // %5 = arith.addi %3, %4 : i32
- // scf.yield %5 : i32
- // }
- // return
- // }
- auto tempOp =
- firOpBuilder.create<mlir::scf::ExecuteRegionOp>(currentLocation, varType);
- firOpBuilder.createBlock(&tempOp.getRegion());
- mlir::Block &block = tempOp.getRegion().back();
- firOpBuilder.setInsertionPointToEnd(&block);
- Fortran::lower::StatementContext stmtCtx;
- mlir::Value rhsExpr = fir::getBase(converter.genExprValue(
- *Fortran::semantics::GetExpr(assignmentStmtExpr), stmtCtx));
- mlir::Value convertResult =
- firOpBuilder.createConvert(currentLocation, varType, rhsExpr);
- // Insert the terminator: YieldOp.
- firOpBuilder.create<mlir::scf::YieldOp>(currentLocation, convertResult);
- firOpBuilder.setInsertionPointToStart(&block);
-
- // 2. Create the omp.atomic.update Operation using the Operations in the
- // temporary scf.execute_region Operation.
- //
- // func.func @_QPsb() {
- // %0 = fir.alloca i32 {bindc_name = "a", uniq_name = "_QFsbEa"}
- // %1 = fir.alloca i32 {bindc_name = "b", uniq_name = "_QFsbEb"}
- // %2 = fir.load %1 : !fir.ref<i32>
- // omp.atomic.update %0 : !fir.ref<i32> {
- // ^bb0(%arg0: i32):
- // %3 = fir.load %1 : !fir.ref<i32>
- // %4 = arith.addi %arg0, %3 : i32
- // omp.yield(%3 : i32)
- // }
- // return
- // }
- mlir::Value updateVar = converter.getSymbolAddress(*name->symbol);
- if (auto decl = updateVar.getDefiningOp<hlfir::DeclareOp>())
- updateVar = decl.getBase();
-
- firOpBuilder.setInsertionPointAfter(tempOp);
- auto atomicUpdateOp = firOpBuilder.create<mlir::omp::AtomicUpdateOp>(
- currentLocation, updateVar, hint, memoryOrder);
-
- llvm::SmallVector<mlir::Type> varTys = {varType};
- llvm::SmallVector<mlir::Location> locs = {currentLocation};
- firOpBuilder.createBlock(&atomicUpdateOp.getRegion(), {}, varTys, locs);
- mlir::Value val =
- fir::getBase(atomicUpdateOp.getRegion().front().getArgument(0));
-
- llvm::SmallVector<mlir::Operation *> ops;
- for (mlir::Operation &op : tempOp.getRegion().getOps())
- ops.push_back(&op);
-
- // SCF Yield is converted to OMP Yield. All other operations are copied
- for (mlir::Operation *op : ops) {
- if (auto y = mlir::dyn_cast<mlir::scf::YieldOp>(op)) {
- firOpBuilder.setInsertionPointToEnd(&atomicUpdateOp.getRegion().front());
- firOpBuilder.create<mlir::omp::YieldOp>(currentLocation, y.getResults());
- op->erase();
- } else {
- op->remove();
- atomicUpdateOp.getRegion().front().push_back(op);
- }
- }
-
- // Remove the load and replace all uses of load with the block argument
- for (mlir::Operation &op : atomicUpdateOp.getRegion().getOps()) {
- fir::LoadOp y = mlir::dyn_cast<fir::LoadOp>(&op);
- if (y && y.getMemref() == updateVar)
- y.getRes().replaceAllUsesWith(val);
- }
-
- tempOp.erase();
-}
-
-static void
-genOmpAtomicWrite(Fortran::lower::AbstractConverter &converter,
- Fortran::lower::pft::Evaluation &eval,
- const Fortran::parser::OmpAtomicWrite &atomicWrite) {
- // Get the value and address of atomic write operands.
- const Fortran::parser::OmpAtomicClauseList &rightHandClauseList =
- std::get<2>(atomicWrite.t);
- const Fortran::parser::OmpAtomicClauseList &leftHandClauseList =
- std::get<0>(atomicWrite.t);
- const Fortran::parser::AssignmentStmt &stmt =
- std::get<3>(atomicWrite.t).statement;
- const Fortran::evaluate::Assignment &assign = *stmt.typedAssignment->v;
- Fortran::lower::StatementContext stmtCtx;
- // Get the value and address of atomic write operands.
- mlir::Value rhsExpr =
- fir::getBase(converter.genExprValue(assign.rhs, stmtCtx));
- mlir::Value lhsAddr =
- fir::getBase(converter.genExprAddr(assign.lhs, stmtCtx));
- genOmpAtomicWriteStatement(converter, eval, lhsAddr, rhsExpr,
- &leftHandClauseList, &rightHandClauseList);
-}
-
-static void genOmpAtomicRead(Fortran::lower::AbstractConverter &converter,
- Fortran::lower::pft::Evaluation &eval,
- const Fortran::parser::OmpAtomicRead &atomicRead) {
- // Get the address of atomic read operands.
- const Fortran::parser::OmpAtomicClauseList &rightHandClauseList =
- std::get<2>(atomicRead.t);
- const Fortran::parser::OmpAtomicClauseList &leftHandClauseList =
- std::get<0>(atomicRead.t);
- const auto &assignmentStmtExpr =
- std::get<Fortran::parser::Expr>(std::get<3>(atomicRead.t).statement.t);
- const auto &assignmentStmtVariable = std::get<Fortran::parser::Variable>(
- std::get<3>(atomicRead.t).statement.t);
-
- Fortran::lower::StatementContext stmtCtx;
- const Fortran::semantics::SomeExpr &fromExpr =
- *Fortran::semantics::GetExpr(assignmentStmtExpr);
- mlir::Type elementType = converter.genType(fromExpr);
- mlir::Value fromAddress =
- fir::getBase(converter.genExprAddr(fromExpr, stmtCtx));
- mlir::Value toAddress = fir::getBase(converter.genExprAddr(
- *Fortran::semantics::GetExpr(assignmentStmtVariable), stmtCtx));
- genOmpAtomicCaptureStatement(converter, eval, fromAddress, toAddress,
- &leftHandClauseList, &rightHandClauseList,
- elementType);
-}
-
-static void
-genOmpAtomicUpdate(Fortran::lower::AbstractConverter &converter,
- Fortran::lower::pft::Evaluation &eval,
- const Fortran::parser::OmpAtomicUpdate &atomicUpdate) {
- const Fortran::parser::OmpAtomicClauseList &rightHandClauseList =
- std::get<2>(atomicUpdate.t);
- const Fortran::parser::OmpAtomicClauseList &leftHandClauseList =
- std::get<0>(atomicUpdate.t);
- const auto &assignmentStmtExpr =
- std::get<Fortran::parser::Expr>(std::get<3>(atomicUpdate.t).statement.t);
- const auto &assignmentStmtVariable = std::get<Fortran::parser::Variable>(
- std::get<3>(atomicUpdate.t).statement.t);
-
- Fortran::lower::StatementContext stmtCtx;
- mlir::Value lhsAddr = fir::getBase(converter.genExprAddr(
- *Fortran::semantics::GetExpr(assignmentStmtVariable), stmtCtx));
- mlir::Type varType =
- fir::getBase(
- converter.genExprValue(
- *Fortran::semantics::GetExpr(assignmentStmtVariable), stmtCtx))
- .getType();
- genOmpAtomicUpdateStatement(converter, eval, lhsAddr, varType,
- assignmentStmtVariable, assignmentStmtExpr,
- &leftHandClauseList, &rightHandClauseList);
-}
-
-static void genOmpAtomic(Fortran::lower::AbstractConverter &converter,
- Fortran::lower::pft::Evaluation &eval,
- const Fortran::parser::OmpAtomic &atomicConstruct) {
- const Fortran::parser::OmpAtomicClauseList &atomicClauseList =
- std::get<Fortran::parser::OmpAtomicClauseList>(atomicConstruct.t);
- const auto &assignmentStmtExpr = std::get<Fortran::parser::Expr>(
- std::get<Fortran::parser::Statement<Fortran::parser::AssignmentStmt>>(
- atomicConstruct.t)
- .statement.t);
- const auto &assignmentStmtVariable = std::get<Fortran::parser::Variable>(
- std::get<Fortran::parser::Statement<Fortran::parser::AssignmentStmt>>(
- atomicConstruct.t)
- .statement.t);
- Fortran::lower::StatementContext stmtCtx;
- mlir::Value lhsAddr = fir::getBase(converter.genExprAddr(
- *Fortran::semantics::GetExpr(assignmentStmtVariable), stmtCtx));
- mlir::Type varType =
- fir::getBase(
- converter.genExprValue(
- *Fortran::semantics::GetExpr(assignmentStmtVariable), stmtCtx))
- .getType();
- // If atomic-clause is not present on the construct, the behaviour is as if
- // the update clause is specified
- genOmpAtomicUpdateStatement(converter, eval, lhsAddr, varType,
- assignmentStmtVariable, assignmentStmtExpr,
- &atomicClauseList, nullptr);
-}
-
-static void
-genOmpAtomicCapture(Fortran::lower::AbstractConverter &converter,
- Fortran::lower::pft::Evaluation &eval,
- const Fortran::parser::OmpAtomicCapture &atomicCapture) {
- fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder();
- mlir::Location currentLocation = converter.getCurrentLocation();
-
- mlir::IntegerAttr hint = nullptr;
- mlir::omp::ClauseMemoryOrderKindAttr memoryOrder = nullptr;
- const Fortran::parser::OmpAtomicClauseList &rightHandClauseList =
- std::get<2>(atomicCapture.t);
- const Fortran::parser::OmpAtomicClauseList &leftHandClauseList =
- std::get<0>(atomicCapture.t);
- genOmpAtomicHintAndMemoryOrderClauses(converter, leftHandClauseList, hint,
- memoryOrder);
- genOmpAtomicHintAndMemoryOrderClauses(converter, rightHandClauseList, hint,
- memoryOrder);
-
- const Fortran::parser::AssignmentStmt &stmt1 =
- std::get<3>(atomicCapture.t).v.statement;
- const auto &stmt1Var{std::get<Fortran::parser::Variable>(stmt1.t)};
- const auto &stmt1Expr{std::get<Fortran::parser::Expr>(stmt1.t)};
- const Fortran::parser::AssignmentStmt &stmt2 =
- std::get<4>(atomicCapture.t).v.statement;
- const auto &stmt2Var{std::get<Fortran::parser::Variable>(stmt2.t)};
- const auto &stmt2Expr{std::get<Fortran::parser::Expr>(stmt2.t)};
-
- // Pre-evaluate expressions to be used in the various operations inside
- // `omp.atomic.capture` since it is not desirable to have anything other than
- // a `omp.atomic.read`, `omp.atomic.write`, or `omp.atomic.update` operation
- // inside `omp.atomic.capture`
- Fortran::lower::StatementContext stmtCtx;
- mlir::Value stmt1LHSArg, stmt1RHSArg, stmt2LHSArg, stmt2RHSArg;
- mlir::Type elementType;
- // LHS evaluations are common to all combinations of `omp.atomic.capture`
- stmt1LHSArg = fir::getBase(
- converter.genExprAddr(*Fortran::semantics::GetExpr(stmt1Var), stmtCtx));
- stmt2LHSArg = fir::getBase(
- converter.genExprAddr(*Fortran::semantics::GetExpr(stmt2Var), stmtCtx));
-
- // Operation specific RHS evaluations
- if (checkForSingleVariableOnRHS(stmt1)) {
- // Atomic capture construct is of the form [capture-stmt, update-stmt] or
- // of the form [capture-stmt, write-stmt]
- stmt1RHSArg = fir::getBase(converter.genExprAddr(
- *Fortran::semantics::GetExpr(stmt1Expr), stmtCtx));
- stmt2RHSArg = fir::getBase(converter.genExprValue(
- *Fortran::semantics::GetExpr(stmt2Expr), stmtCtx));
-
- } else {
- // Atomic capture construct is of the form [update-stmt, capture-stmt]
- stmt1RHSArg = fir::getBase(converter.genExprValue(
- *Fortran::semantics::GetExpr(stmt1Expr), stmtCtx));
- stmt2RHSArg = fir::getBase(converter.genExprAddr(
- *Fortran::semantics::GetExpr(stmt2Expr), stmtCtx));
- }
- // Type information used in generation of `omp.atomic.update` operation
- mlir::Type stmt1VarType =
- fir::getBase(converter.genExprValue(
- *Fortran::semantics::GetExpr(stmt1Var), stmtCtx))
- .getType();
- mlir::Type stmt2VarType =
- fir::getBase(converter.genExprValue(
- *Fortran::semantics::GetExpr(stmt2Var), stmtCtx))
- .getType();
-
- auto atomicCaptureOp = firOpBuilder.create<mlir::omp::AtomicCaptureOp>(
- currentLocation, hint, memoryOrder);
- firOpBuilder.createBlock(&atomicCaptureOp.getRegion());
- mlir::Block &block = atomicCaptureOp.getRegion().back();
- firOpBuilder.setInsertionPointToStart(&block);
- if (checkForSingleVariableOnRHS(stmt1)) {
- if (checkForSymbolMatch(stmt2)) {
- // Atomic capture construct is of the form [capture-stmt, update-stmt]
- const Fortran::semantics::SomeExpr &fromExpr =
- *Fortran::semantics::GetExpr(stmt1Expr);
- elementType = converter.genType(fromExpr);
- genOmpAtomicCaptureStatement(converter, eval, stmt1RHSArg, stmt1LHSArg,
- /*leftHandClauseList=*/nullptr,
- /*rightHandClauseList=*/nullptr,
- elementType);
- genOmpAtomicUpdateStatement(converter, eval, stmt1RHSArg, stmt2VarType,
- stmt2Var, stmt2Expr,
- /*leftHandClauseList=*/nullptr,
- /*rightHandClauseList=*/nullptr);
- } else {
- // Atomic capture construct is of the form [capture-stmt, write-stmt]
- const Fortran::semantics::SomeExpr &fromExpr =
- *Fortran::semantics::GetExpr(stmt1Expr);
- elementType = converter.genType(fromExpr);
- genOmpAtomicCaptureStatement(converter, eval, stmt1RHSArg, stmt1LHSArg,
- /*leftHandClauseList=*/nullptr,
- /*rightHandClauseList=*/nullptr,
- elementType);
- genOmpAtomicWriteStatement(converter, eval, stmt1RHSArg, stmt2RHSArg,
- /*leftHandClauseList=*/nullptr,
- /*rightHandClauseList=*/nullptr);
- }
- } else {
- // Atomic capture construct is of the form [update-stmt, capture-stmt]
- firOpBuilder.setInsertionPointToEnd(&block);
- const Fortran::semantics::SomeExpr &fromExpr =
- *Fortran::semantics::GetExpr(stmt2Expr);
- elementType = converter.genType(fromExpr);
- genOmpAtomicCaptureStatement(converter, eval, stmt1LHSArg, stmt2LHSArg,
- /*leftHandClauseList=*/nullptr,
- /*rightHandClauseList=*/nullptr, elementType);
- firOpBuilder.setInsertionPointToStart(&block);
- genOmpAtomicUpdateStatement(converter, eval, stmt1LHSArg, stmt1VarType,
- stmt1Var, stmt1Expr,
- /*leftHandClauseList=*/nullptr,
- /*rightHandClauseList=*/nullptr);
- }
- firOpBuilder.setInsertionPointToEnd(&block);
- firOpBuilder.create<mlir::omp::TerminatorOp>(currentLocation);
- firOpBuilder.setInsertionPointToStart(&block);
-}
-
static void
genOMP(Fortran::lower::AbstractConverter &converter,
Fortran::lower::pft::Evaluation &eval,
const Fortran::parser::OpenMPAtomicConstruct &atomicConstruct) {
- std::visit(Fortran::common::visitors{
- [&](const Fortran::parser::OmpAtomicRead &atomicRead) {
- genOmpAtomicRead(converter, eval, atomicRead);
- },
- [&](const Fortran::parser::OmpAtomicWrite &atomicWrite) {
- genOmpAtomicWrite(converter, eval, atomicWrite);
- },
- [&](const Fortran::parser::OmpAtomic &atomicConstruct) {
- genOmpAtomic(converter, eval, atomicConstruct);
- },
- [&](const Fortran::parser::OmpAtomicUpdate &atomicUpdate) {
- genOmpAtomicUpdate(converter, eval, atomicUpdate);
- },
- [&](const Fortran::parser::OmpAtomicCapture &atomicCapture) {
- genOmpAtomicCapture(converter, eval, atomicCapture);
- },
- },
- atomicConstruct.u);
+ std::visit(
+ Fortran::common::visitors{
+ [&](const Fortran::parser::OmpAtomicRead &atomicRead) {
+ Fortran::lower::genOmpAccAtomicRead<
+ Fortran::parser::OmpAtomicRead,
+ Fortran::parser::OmpAtomicClauseList>(converter, atomicRead);
+ },
+ [&](const Fortran::parser::OmpAtomicWrite &atomicWrite) {
+ Fortran::lower::genOmpAccAtomicWrite<
+ Fortran::parser::OmpAtomicWrite,
+ Fortran::parser::OmpAtomicClauseList>(converter, atomicWrite);
+ },
+ [&](const Fortran::parser::OmpAtomic &atomicConstruct) {
+ Fortran::lower::genOmpAtomic<Fortran::parser::OmpAtomic,
+ Fortran::parser::OmpAtomicClauseList>(
+ converter, atomicConstruct);
+ },
+ [&](const Fortran::parser::OmpAtomicUpdate &atomicUpdate) {
+ Fortran::lower::genOmpAccAtomicUpdate<
+ Fortran::parser::OmpAtomicUpdate,
+ Fortran::parser::OmpAtomicClauseList>(converter, atomicUpdate);
+ },
+ [&](const Fortran::parser::OmpAtomicCapture &atomicCapture) {
+ Fortran::lower::genOmpAccAtomicCapture<
+ Fortran::parser::OmpAtomicCapture,
+ Fortran::parser::OmpAtomicClauseList>(converter, atomicCapture);
+ },
+ },
+ atomicConstruct.u);
}
static void genOMP(Fortran::lower::AbstractConverter &converter,
diff --git a/flang/test/Lower/OpenACC/acc-atomic-capture.f90 b/flang/test/Lower/OpenACC/acc-atomic-capture.f90
new file mode 100644
index 000000000000000..1a5fe8d57c1533a
--- /dev/null
+++ b/flang/test/Lower/OpenACC/acc-atomic-capture.f90
@@ -0,0 +1,99 @@
+! RUN: %flang_fc1 -emit-fir -fopenacc %s -o - | FileCheck %s
+
+! This test checks the lowering of atomic capture
+
+program acc_atomic_capture_test
+ integer :: x, y
+
+!CHECK: %[[X:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFEx"}
+!CHECK: %[[Y:.*]] = fir.alloca i32 {bindc_name = "y", uniq_name = "_QFEy"}
+!CHECK: acc.atomic.capture {
+!CHECK: acc.atomic.read %[[X]] = %[[Y]] : !fir.ref<i32>
+!CHECK: acc.atomic.update %[[Y]] : !fir.ref<i32> {
+!CHECK: ^bb0(%[[ARG:.*]]: i32):
+!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref<i32>
+!CHECK: %[[result:.*]] = arith.addi %[[temp]], %[[ARG]] : i32
+!CHECK: acc.yield %[[result]] : i32
+!CHECK: }
+!CHECK: }
+
+ !$acc atomic capture
+ x = y
+ y = x + y
+ !$acc end atomic
+
+
+!CHECK: acc.atomic.capture {
+!CHECK: acc.atomic.update %[[Y]] : !fir.ref<i32> {
+!CHECK: ^bb0(%[[ARG:.*]]: i32):
+!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref<i32>
+!CHECK: %[[result:.*]] = arith.muli %[[temp]], %[[ARG]] : i32
+!CHECK: acc.yield %[[result]] : i32
+!CHECK: }
+!CHECK: acc.atomic.read %[[X]] = %[[Y]] : !fir.ref<i32>
+!CHECK: }
+
+ !$acc atomic capture
+ y = x * y
+ x = y
+ !$acc end atomic
+
+!CHECK: %[[constant_20:.*]] = arith.constant 20 : i32
+!CHECK: %[[constant_8:.*]] = arith.constant 8 : i32
+!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref<i32>
+!CHECK: %[[result:.*]] = arith.subi %[[constant_8]], %[[temp]] : i32
+!CHECK: %[[result_noreassoc:.*]] = fir.no_reassoc %[[result]] : i32
+!CHECK: %[[result:.*]] = arith.addi %[[constant_20]], %[[result_noreassoc]] : i32
+!CHECK: acc.atomic.capture {
+!CHECK: acc.atomic.read %[[X]] = %[[Y]] : !fir.ref<i32>
+!CHECK: acc.atomic.write %[[Y]] = %[[result]] : !fir.ref<i32>, i32
+!CHECK: }
+
+ !$acc atomic capture
+ x = y
+ y = 2 * 10 + (8 - x)
+ !$acc end atomic
+end program
+
+
+
+subroutine pointers_in_atomic_capture()
+!CHECK: %[[A:.*]] = fir.alloca !fir.box<!fir.ptr<i32>> {bindc_name = "a", uniq_name = "_QFpointers_in_atomic_captureEa"}
+!CHECK: {{.*}} = fir.zero_bits !fir.ptr<i32>
+!CHECK: {{.*}} = fir.embox {{.*}} : (!fir.ptr<i32>) -> !fir.box<!fir.ptr<i32>>
+!CHECK: fir.store {{.*}} to %[[A]] : !fir.ref<!fir.box<!fir.ptr<i32>>>
+!CHECK: %[[B:.*]] = fir.alloca !fir.box<!fir.ptr<i32>> {bindc_name = "b", uniq_name = "_QFpointers_in_atomic_captureEb"}
+!CHECK: {{.*}} = fir.zero_bits !fir.ptr<i32>
+!CHECK: {{.*}} = fir.embox {{.*}} : (!fir.ptr<i32>) -> !fir.box<!fir.ptr<i32>>
+!CHECK: fir.store {{.*}} to %[[B]] : !fir.ref<!fir.box<!fir.ptr<i32>>>
+!CHECK: %[[C:.*]] = fir.alloca i32 {bindc_name = "c", fir.target, uniq_name = "_QFpointers_in_atomic_captureEc"}
+!CHECK: %[[D:.*]] = fir.alloca i32 {bindc_name = "d", fir.target, uniq_name = "_QFpointers_in_atomic_captureEd"}
+!CHECK: {{.*}} = fir.embox {{.*}} : (!fir.ref<i32>) -> !fir.box<!fir.ptr<i32>>
+!CHECK: fir.store {{.*}} to %[[A]] : !fir.ref<!fir.box<!fir.ptr<i32>>>
+!CHECK: {{.*}} = fir.embox {{.*}} : (!fir.ref<i32>) -> !fir.box<!fir.ptr<i32>>
+!CHECK: fir.store {{.*}} to %[[B]] : !fir.ref<!fir.box<!fir.ptr<i32>>>
+!CHECK: %[[loaded_A:.*]] = fir.load %[[A]] : !fir.ref<!fir.box<!fir.ptr<i32>>>
+!CHECK: %[[loaded_A_addr:.*]] = fir.box_addr %[[loaded_A]] : (!fir.box<!fir.ptr<i32>>) -> !fir.ptr<i32>
+!CHECK: %[[loaded_B:.*]] = fir.load %[[B]] : !fir.ref<!fir.box<!fir.ptr<i32>>>
+!CHECK: %[[loaded_B_addr:.*]] = fir.box_addr %[[loaded_B]] : (!fir.box<!fir.ptr<i32>>) -> !fir.ptr<i32>
+!CHECK: acc.atomic.capture {
+!CHECK: acc.atomic.update %[[loaded_A_addr]] : !fir.ptr<i32> {
+!CHECK: ^bb0(%[[ARG:.*]]: i32):
+!CHECK: %[[PRIVATE_LOADED_B:.*]] = fir.load %[[B]] : !fir.ref<!fir.box<!fir.ptr<i32>>>
+!CHECK: %[[PRIVATE_LOADED_B_addr:.*]] = fir.box_addr %[[PRIVATE_LOADED_B]] : (!fir.box<!fir.ptr<i32>>) -> !fir.ptr<i32>
+!CHECK: %[[loaded_value:.*]] = fir.load %[[PRIVATE_LOADED_B_addr]] : !fir.ptr<i32>
+!CHECK: %[[result:.*]] = arith.addi %[[ARG]], %[[loaded_value]] : i32
+!CHECK: acc.yield %[[result]] : i32
+!CHECK: }
+!CHECK: acc.atomic.read %[[loaded_B_addr]] = %[[loaded_A_addr]] : !fir.ptr<i32>, i32
+!CHECK: }
+ integer, pointer :: a, b
+ integer, target :: c, d
+ a=>c
+ b=>d
+
+ !$acc atomic capture
+ a = a + b
+ b = a
+ !$acc end atomic
+end subroutine
diff --git a/flang/test/Lower/OpenACC/acc-atomic-read.f90 b/flang/test/Lower/OpenACC/acc-atomic-read.f90
new file mode 100644
index 000000000000000..28f0ce44e6f413d
--- /dev/null
+++ b/flang/test/Lower/OpenACC/acc-atomic-read.f90
@@ -0,0 +1,48 @@
+! RUN: bbc --use-desc-for-alloc=false -fopenacc -emit-fir %s -o - | FileCheck %s
+
+! This test checks the lowering of atomic read
+
+!CHECK: func @_QQmain() attributes {fir.bindc_name = "acc_atomic_test"} {
+!CHECK: %[[VAR_G:.*]] = fir.alloca f32 {bindc_name = "g", uniq_name = "_QFEg"}
+!CHECK: %[[VAR_H:.*]] = fir.alloca f32 {bindc_name = "h", uniq_name = "_QFEh"}
+!CHECK: acc.atomic.read %[[VAR_G]] = %[[VAR_H]] : !fir.ref<f32>, f32
+!CHECK: return
+!CHECK: }
+
+program acc_atomic_test
+ real g, h
+ !$acc atomic read
+ g = h
+end program acc_atomic_test
+
+! Test lowering atomic read for pointer variables.
+! Please notice to use %[[VAL_4]] and %[[VAL_1]] for operands of atomic
+! operation, instead of %[[VAL_3]] and %[[VAL_0]].
+
+!CHECK-LABEL: func.func @_QPatomic_read_pointer() {
+!CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box<!fir.ptr<i32>> {bindc_name = "x", uniq_name = "_QFatomic_read_pointerEx"}
+!CHECK: %[[VAL_1:.*]] = fir.alloca !fir.ptr<i32> {uniq_name = "_QFatomic_read_pointerEx.addr"}
+!CHECK: %[[VAL_2:.*]] = fir.zero_bits !fir.ptr<i32>
+!CHECK: fir.store %[[VAL_2]] to %[[VAL_1]] : !fir.ref<!fir.ptr<i32>>
+!CHECK: %[[VAL_3:.*]] = fir.alloca !fir.box<!fir.ptr<i32>> {bindc_name = "y", uniq_name = "_QFatomic_read_pointerEy"}
+!CHECK: %[[VAL_4:.*]] = fir.alloca !fir.ptr<i32> {uniq_name = "_QFatomic_read_pointerEy.addr"}
+!CHECK: %[[VAL_5:.*]] = fir.zero_bits !fir.ptr<i32>
+!CHECK: fir.store %[[VAL_5]] to %[[VAL_4]] : !fir.ref<!fir.ptr<i32>>
+!CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_1]] : !fir.ref<!fir.ptr<i32>>
+!CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_4]] : !fir.ref<!fir.ptr<i32>>
+!CHECK: acc.atomic.read %[[VAL_7]] = %[[VAL_6]] : !fir.ptr<i32>, i32
+!CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_4]] : !fir.ref<!fir.ptr<i32>>
+!CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_8]] : !fir.ptr<i32>
+!CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_1]] : !fir.ref<!fir.ptr<i32>>
+!CHECK: fir.store %[[VAL_9]] to %[[VAL_10]] : !fir.ptr<i32>
+!CHECK: return
+!CHECK: }
+
+subroutine atomic_read_pointer()
+ integer, pointer :: x, y
+
+ !$acc atomic read
+ y = x
+
+ x = y
+end
diff --git a/flang/test/Lower/OpenACC/acc-atomic-update-hlfir.f90 b/flang/test/Lower/OpenACC/acc-atomic-update-hlfir.f90
new file mode 100644
index 000000000000000..24dd0ee5a8999e4
--- /dev/null
+++ b/flang/test/Lower/OpenACC/acc-atomic-update-hlfir.f90
@@ -0,0 +1,23 @@
+! This test checks lowering of atomic and atomic update constructs with HLFIR
+! RUN: bbc -hlfir -fopenacc -emit-hlfir %s -o - | FileCheck %s
+! RUN: %flang_fc1 -flang-experimental-hlfir -emit-hlfir -fopenacc %s -o - | FileCheck %s
+
+subroutine sb
+ integer :: x, y
+
+ !$acc atomic update
+ x = x + y
+end subroutine
+
+!CHECK-LABEL: @_QPsb
+!CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFsbEx"}
+!CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X_REF]] {uniq_name = "_QFsbEx"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i32>)
+!CHECK: %[[Y_REF:.*]] = fir.alloca i32 {bindc_name = "y", uniq_name = "_QFsbEy"}
+!CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[Y_REF]] {uniq_name = "_QFsbEy"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i32>)
+!CHECK: acc.atomic.update %[[X_DECL]]#0 : !fir.ref<i32> {
+!CHECK: ^bb0(%[[ARG_X:.*]]: i32):
+!CHECK: %[[Y_VAL:.*]] = fir.load %[[Y_DECL]]#0 : !fir.ref<i32>
+!CHECK: %[[X_UPDATE_VAL:.*]] = arith.addi %[[ARG_X]], %[[Y_VAL]] : i32
+!CHECK: acc.yield %[[X_UPDATE_VAL]] : i32
+!CHECK: }
+!CHECK: return
diff --git a/flang/test/Lower/OpenACC/acc-atomic-update.f90 b/flang/test/Lower/OpenACC/acc-atomic-update.f90
new file mode 100644
index 000000000000000..546d012982e23ba
--- /dev/null
+++ b/flang/test/Lower/OpenACC/acc-atomic-update.f90
@@ -0,0 +1,74 @@
+! This test checks lowering of atomic and atomic update constructs
+! RUN: bbc --use-desc-for-alloc=false -fopenacc -emit-fir %s -o - | FileCheck %s
+! RUN: %flang_fc1 -mllvm --use-desc-for-alloc=false -emit-fir -fopenacc %s -o - | FileCheck %s
+
+program acc_atomic_update_test
+ integer :: x, y, z
+ integer, pointer :: a, b
+ integer, target :: c, d
+ integer(1) :: i1
+
+ a=>c
+ b=>d
+
+!CHECK: func.func @_QQmain() attributes {fir.bindc_name = "acc_atomic_update_test"} {
+!CHECK: %[[A:.*]] = fir.alloca !fir.box<!fir.ptr<i32>> {bindc_name = "a", uniq_name = "_QFEa"}
+!CHECK: %[[A_ADDR:.*]] = fir.alloca !fir.ptr<i32> {uniq_name = "_QFEa.addr"}
+!CHECK: %{{.*}} = fir.zero_bits !fir.ptr<i32>
+!CHECK: fir.store %{{.*}} to %[[A_ADDR]] : !fir.ref<!fir.ptr<i32>>
+!CHECK: %[[B:.*]] = fir.alloca !fir.box<!fir.ptr<i32>> {bindc_name = "b", uniq_name = "_QFEb"}
+!CHECK: %[[B_ADDR:.*]] = fir.alloca !fir.ptr<i32> {uniq_name = "_QFEb.addr"}
+!CHECK: %{{.*}} = fir.zero_bits !fir.ptr<i32>
+!CHECK: fir.store %{{.*}} to %[[B_ADDR]] : !fir.ref<!fir.ptr<i32>>
+!CHECK: %[[C_ADDR:.*]] = fir.address_of(@_QFEc) : !fir.ref<i32>
+!CHECK: %[[D_ADDR:.*]] = fir.address_of(@_QFEd) : !fir.ref<i32>
+!CHECK: %[[I1:.*]] = fir.alloca i8 {bindc_name = "i1", uniq_name = "_QFEi1"}
+!CHECK: %[[X:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFEx"}
+!CHECK: %[[Y:.*]] = fir.alloca i32 {bindc_name = "y", uniq_name = "_QFEy"}
+!CHECK: %[[Z:.*]] = fir.alloca i32 {bindc_name = "z", uniq_name = "_QFEz"}
+!CHECK: %{{.*}} = fir.convert %[[C_ADDR]] : (!fir.ref<i32>) -> !fir.ptr<i32>
+!CHECK: fir.store %{{.*}} to %[[A_ADDR]] : !fir.ref<!fir.ptr<i32>>
+!CHECK: %{{.*}} = fir.convert %[[D_ADDR]] : (!fir.ref<i32>) -> !fir.ptr<i32>
+!CHECK: fir.store {{.*}} to %[[B_ADDR]] : !fir.ref<!fir.ptr<i32>>
+!CHECK: %[[LOADED_A:.*]] = fir.load %[[A_ADDR]] : !fir.ref<!fir.ptr<i32>>
+!CHECK: acc.atomic.update %[[LOADED_A]] : !fir.ptr<i32> {
+!CHECK: ^bb0(%[[ARG:.*]]: i32):
+!CHECK: %[[LOADED_B:.*]] = fir.load %[[B_ADDR]] : !fir.ref<!fir.ptr<i32>>
+!CHECK: %{{.*}} = fir.load %[[LOADED_B]] : !fir.ptr<i32>
+!CHECK: %[[RESULT:.*]] = arith.addi %[[ARG]], %{{.*}} : i32
+!CHECK: acc.yield %[[RESULT]] : i32
+!CHECK: }
+ !$acc atomic update
+ a = a + b
+
+!CHECK: acc.atomic.update %[[Y]] : !fir.ref<i32> {
+!CHECK: ^bb0(%[[ARG:.*]]: i32):
+!CHECK: {{.*}} = arith.constant 1 : i32
+!CHECK: %[[RESULT:.*]] = arith.addi %[[ARG]], {{.*}} : i32
+!CHECK: acc.yield %[[RESULT]] : i32
+!CHECK: }
+!CHECK: acc.atomic.update %[[Z]] : !fir.ref<i32> {
+!CHECK: ^bb0(%[[ARG:.*]]: i32):
+!CHECK: %[[LOADED_X:.*]] = fir.load %[[X]] : !fir.ref<i32>
+!CHECK: %[[RESULT:.*]] = arith.muli %[[LOADED_X]], %[[ARG]] : i32
+!CHECK: acc.yield %[[RESULT]] : i32
+!CHECK: }
+ !$acc atomic
+ y = y + 1
+ !$acc atomic update
+ z = x * z
+
+!CHECK: acc.atomic.update %[[I1]] : !fir.ref<i8> {
+!CHECK: ^bb0(%[[VAL:.*]]: i8):
+!CHECK: %[[CVT_VAL:.*]] = fir.convert %[[VAL]] : (i8) -> i32
+!CHECK: %[[C1_VAL:.*]] = arith.constant 1 : i32
+!CHECK: %[[ADD_VAL:.*]] = arith.addi %[[CVT_VAL]], %[[C1_VAL]] : i32
+!CHECK: %[[UPDATED_VAL:.*]] = fir.convert %[[ADD_VAL]] : (i32) -> i8
+!CHECK: acc.yield %[[UPDATED_VAL]] : i8
+!CHECK: }
+ !$acc atomic
+ i1 = i1 + 1
+ !$acc end atomic
+!CHECK: return
+!CHECK: }
+end program acc_atomic_update_test
diff --git a/flang/test/Lower/OpenACC/acc-atomic-write.f90 b/flang/test/Lower/OpenACC/acc-atomic-write.f90
new file mode 100644
index 000000000000000..e68aaac3d38581a
--- /dev/null
+++ b/flang/test/Lower/OpenACC/acc-atomic-write.f90
@@ -0,0 +1,57 @@
+! RUN: bbc --use-desc-for-alloc=false -fopenacc -emit-fir %s -o - | FileCheck %s
+
+! This test checks the lowering of atomic write
+
+!CHECK: func @_QQmain() attributes {fir.bindc_name = "acc_atomic_write_test"} {
+!CHECK: %[[VAR_X:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFEx"}
+!CHECK: %[[VAR_Y:.*]] = fir.alloca i32 {bindc_name = "y", uniq_name = "_QFEy"}
+!CHECK: %[[CONST_7:.*]] = arith.constant 7 : i32
+!CHECK: {{.*}} = fir.load %[[VAR_Y]] : !fir.ref<i32>
+!CHECK: %[[VAR_7y:.*]] = arith.muli %[[CONST_7]], {{.*}} : i32
+!CHECK: acc.atomic.write %[[VAR_X]] = %[[VAR_7y]] : !fir.ref<i32>, i32
+!CHECK: return
+!CHECK: }
+
+program acc_atomic_write_test
+ integer :: x, y
+
+ !$acc atomic write
+ x = 7 * y
+
+end program acc_atomic_write_test
+
+! Test lowering atomic read for pointer variables.
+
+!CHECK-LABEL: func.func @_QPatomic_write_pointer() {
+!CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box<!fir.ptr<i32>> {bindc_name = "x", uniq_name = "_QFatomic_write_pointerEx"}
+!CHECK: %[[VAL_1:.*]] = fir.alloca !fir.ptr<i32> {uniq_name = "_QFatomic_write_pointerEx.addr"}
+!CHECK: %[[VAL_2:.*]] = fir.zero_bits !fir.ptr<i32>
+!CHECK: fir.store %[[VAL_2]] to %[[VAL_1]] : !fir.ref<!fir.ptr<i32>>
+!CHECK: %[[VAL_3:.*]] = arith.constant 1 : i32
+!CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_1]] : !fir.ref<!fir.ptr<i32>>
+!CHECK: acc.atomic.write %[[VAL_4]] = %[[VAL_3]] : !fir.ptr<i32>, i32
+!CHECK: %[[VAL_5:.*]] = arith.constant 2 : i32
+!CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_1]] : !fir.ref<!fir.ptr<i32>>
+!CHECK: fir.store %[[VAL_5]] to %[[VAL_6]] : !fir.ptr<i32>
+!CHECK: return
+!CHECK: }
+
+subroutine atomic_write_pointer()
+ integer, pointer :: x
+
+ !$acc atomic write
+ x = 1
+
+ x = 2
+end subroutine
+
+!CHECK-LABEL: func.func @_QPatomic_write_typed_assign
+!CHECK: %[[VAR:.*]] = fir.alloca f32 {bindc_name = "r2", uniq_name = "{{.*}}r2"}
+!CHECK: %[[CST:.*]] = arith.constant 0.000000e+00 : f32
+!CHECK: acc.atomic.write %[[VAR]] = %[[CST]] : !fir.ref<f32>, f32
+
+subroutine atomic_write_typed_assign
+ real :: r2
+ !$acc atomic write
+ r2 = 0
+end subroutine
>From 67d8cd1ca7dfd7653ab0996339970ec6aa15e8ff Mon Sep 17 00:00:00 2001
From: Walter Erquinigo <a20012251 at gmail.com>
Date: Mon, 11 Sep 2023 17:00:01 -0400
Subject: [PATCH 13/35] [lldb-vscode] Make descriptive summaries and raw child
for synthetics configurable (#65687)
"descriptive summaries" should only be used for small to medium binaries
because of the performance penalty the cause when completing types. I'm
defaulting it to false.
Besides that, the "raw child" for synthetics should be optional as well.
I'm defaulting it to false.
Both options can be set via a launch or attach config, following the
pattern of most settings. javascript extension wrappers can set these
settings on their own as well.
---
.../tools/lldb-vscode/lldbvscode_testcase.py | 15 +++-
.../test/tools/lldb-vscode/vscode.py | 6 +-
.../evaluate/TestVSCode_evaluate.py | 24 ++++--
.../variables/TestVSCode_variables.py | 81 +++++++++++++++----
lldb/tools/lldb-vscode/JSONUtils.cpp | 12 ++-
lldb/tools/lldb-vscode/VSCode.cpp | 2 +
lldb/tools/lldb-vscode/VSCode.h | 2 +
lldb/tools/lldb-vscode/lldb-vscode.cpp | 11 ++-
lldb/tools/lldb-vscode/package.json | 20 +++++
9 files changed, 144 insertions(+), 29 deletions(-)
diff --git a/lldb/packages/Python/lldbsuite/test/tools/lldb-vscode/lldbvscode_testcase.py b/lldb/packages/Python/lldbsuite/test/tools/lldb-vscode/lldbvscode_testcase.py
index a6c370ccd2036de..8cd4e8454c89099 100644
--- a/lldb/packages/Python/lldbsuite/test/tools/lldb-vscode/lldbvscode_testcase.py
+++ b/lldb/packages/Python/lldbsuite/test/tools/lldb-vscode/lldbvscode_testcase.py
@@ -1,8 +1,9 @@
-from lldbsuite.test.lldbtest import *
import os
-import vscode
import time
+import vscode
+from lldbsuite.test.lldbtest import *
+
class VSCodeTestCaseBase(TestBase):
NO_DEBUG_INFO_TESTCASE = True
@@ -267,7 +268,7 @@ def disassemble(self, threadId=None, frameIndex=None):
if memoryReference not in self.vscode.disassembled_instructions:
self.vscode.request_disassemble(memoryReference=memoryReference)
-
+
return self.vscode.disassembled_instructions[memoryReference]
def attach(
@@ -348,6 +349,8 @@ def launch(
runInTerminal=False,
expectFailure=False,
postRunCommands=None,
+ enableAutoVariableSummaries=False,
+ enableSyntheticChildDebugging=False,
):
"""Sending launch request to vscode"""
@@ -384,6 +387,8 @@ def cleanup():
sourceMap=sourceMap,
runInTerminal=runInTerminal,
postRunCommands=postRunCommands,
+ enableAutoVariableSummaries=enableAutoVariableSummaries,
+ enableSyntheticChildDebugging=enableSyntheticChildDebugging,
)
if expectFailure:
@@ -418,6 +423,8 @@ def build_and_launch(
disconnectAutomatically=True,
postRunCommands=None,
lldbVSCodeEnv=None,
+ enableAutoVariableSummaries=False,
+ enableSyntheticChildDebugging=False,
):
"""Build the default Makefile target, create the VSCode debug adaptor,
and launch the process.
@@ -446,4 +453,6 @@ def build_and_launch(
runInTerminal=runInTerminal,
disconnectAutomatically=disconnectAutomatically,
postRunCommands=postRunCommands,
+ enableAutoVariableSummaries=enableAutoVariableSummaries,
+ enableSyntheticChildDebugging=enableSyntheticChildDebugging,
)
diff --git a/lldb/packages/Python/lldbsuite/test/tools/lldb-vscode/vscode.py b/lldb/packages/Python/lldbsuite/test/tools/lldb-vscode/vscode.py
index 14f0bf0a2d4ed3d..b30443e2e2acb9e 100644
--- a/lldb/packages/Python/lldbsuite/test/tools/lldb-vscode/vscode.py
+++ b/lldb/packages/Python/lldbsuite/test/tools/lldb-vscode/vscode.py
@@ -648,7 +648,7 @@ def request_disconnect(self, terminateDebuggee=None):
"arguments": args_dict,
}
return self.send_recv(command_dict)
-
+
def request_disassemble(self, memoryReference, offset=-50, instructionCount=200, resolveSymbols=True):
args_dict = {
"memoryReference": memoryReference,
@@ -727,6 +727,8 @@ def request_launch(
sourceMap=None,
runInTerminal=False,
postRunCommands=None,
+ enableAutoVariableSummaries=False,
+ enableSyntheticChildDebugging=False,
):
args_dict = {"program": program}
if args:
@@ -768,6 +770,8 @@ def request_launch(
args_dict["runInTerminal"] = runInTerminal
if postRunCommands:
args_dict["postRunCommands"] = postRunCommands
+ args_dict["enableAutoVariableSummaries"] = enableAutoVariableSummaries
+ args_dict["enableSyntheticChildDebugging"] = enableSyntheticChildDebugging
command_dict = {"command": "launch", "type": "request", "arguments": args_dict}
response = self.send_recv(command_dict)
diff --git a/lldb/test/API/tools/lldb-vscode/evaluate/TestVSCode_evaluate.py b/lldb/test/API/tools/lldb-vscode/evaluate/TestVSCode_evaluate.py
index 85bd23d9abfdef7..d0172ef9160fdd6 100644
--- a/lldb/test/API/tools/lldb-vscode/evaluate/TestVSCode_evaluate.py
+++ b/lldb/test/API/tools/lldb-vscode/evaluate/TestVSCode_evaluate.py
@@ -28,13 +28,17 @@ def assertEvaluateFailure(self, expression):
def isExpressionParsedExpected(self):
return self.context != "hover"
- def run_test_evaluate_expressions(self, context=None):
+ def run_test_evaluate_expressions(
+ self, context=None, enableAutoVariableSummaries=False
+ ):
"""
Tests the evaluate expression request at different breakpoints
"""
self.context = context
program = self.getBuildArtifact("a.out")
- self.build_and_launch(program)
+ self.build_and_launch(
+ program, enableAutoVariableSummaries=enableAutoVariableSummaries
+ )
source = "main.cpp"
self.set_source_breakpoints(
source,
@@ -55,7 +59,9 @@ def run_test_evaluate_expressions(self, context=None):
self.assertEvaluate("var2", "21")
self.assertEvaluate("static_int", "42")
self.assertEvaluate("non_static_int", "43")
- self.assertEvaluate("struct1", "{foo:15}")
+ self.assertEvaluate(
+ "struct1", "{foo:15}" if enableAutoVariableSummaries else "my_struct @ 0x"
+ )
self.assertEvaluate("struct1.foo", "15")
self.assertEvaluate("struct2->foo", "16")
@@ -85,7 +91,9 @@ def run_test_evaluate_expressions(self, context=None):
self.assertEvaluate(
"non_static_int", "10"
) # different variable with the same name
- self.assertEvaluate("struct1", "{foo:15}")
+ self.assertEvaluate(
+ "struct1", "{foo:15}" if enableAutoVariableSummaries else "my_struct @ 0x"
+ )
self.assertEvaluate("struct1.foo", "15")
self.assertEvaluate("struct2->foo", "16")
@@ -146,22 +154,22 @@ def run_test_evaluate_expressions(self, context=None):
@skipIfRemote
def test_generic_evaluate_expressions(self):
# Tests context-less expression evaluations
- self.run_test_evaluate_expressions()
+ self.run_test_evaluate_expressions(enableAutoVariableSummaries=False)
@skipIfWindows
@skipIfRemote
def test_repl_evaluate_expressions(self):
# Tests expression evaluations that are triggered from the Debug Console
- self.run_test_evaluate_expressions("repl")
+ self.run_test_evaluate_expressions("repl", enableAutoVariableSummaries=True)
@skipIfWindows
@skipIfRemote
def test_watch_evaluate_expressions(self):
# Tests expression evaluations that are triggered from a watch expression
- self.run_test_evaluate_expressions("watch")
+ self.run_test_evaluate_expressions("watch", enableAutoVariableSummaries=False)
@skipIfWindows
@skipIfRemote
def test_hover_evaluate_expressions(self):
# Tests expression evaluations that are triggered when hovering on the editor
- self.run_test_evaluate_expressions("hover")
+ self.run_test_evaluate_expressions("hover", enableAutoVariableSummaries=True)
diff --git a/lldb/test/API/tools/lldb-vscode/variables/TestVSCode_variables.py b/lldb/test/API/tools/lldb-vscode/variables/TestVSCode_variables.py
index e9596ac56e0ea95..fc24b3b34e70283 100644
--- a/lldb/test/API/tools/lldb-vscode/variables/TestVSCode_variables.py
+++ b/lldb/test/API/tools/lldb-vscode/variables/TestVSCode_variables.py
@@ -127,15 +127,17 @@ def darwin_dwarf_missing_obj(self, initCommands):
varref_dict = {}
self.verify_variables(verify_locals, locals, varref_dict)
- @skipIfWindows
- @skipIfRemote
- def test_scopes_variables_setVariable_evaluate(self):
+ def do_test_scopes_variables_setVariable_evaluate(
+ self, enableAutoVariableSummaries: bool
+ ):
"""
Tests the "scopes", "variables", "setVariable", and "evaluate"
packets.
"""
program = self.getBuildArtifact("a.out")
- self.build_and_launch(program)
+ self.build_and_launch(
+ program, enableAutoVariableSummaries=enableAutoVariableSummaries
+ )
source = "main.cpp"
breakpoint1_line = line_number(source, "// breakpoint 1")
lines = [breakpoint1_line]
@@ -219,12 +221,20 @@ def test_scopes_variables_setVariable_evaluate(self):
},
"pt": {
"equals": {"type": "PointType"},
- "startswith": {"result": "{x:11, y:22}"},
+ "startswith": {
+ "result": "{x:11, y:22}"
+ if enableAutoVariableSummaries
+ else "PointType @ 0x"
+ },
"hasVariablesReference": True,
},
"pt.buffer": {
"equals": {"type": "int[32]"},
- "startswith": {"result": "{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, ...}"},
+ "startswith": {
+ "result": "{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, ...}"
+ if enableAutoVariableSummaries
+ else "int[32] @ 0x"
+ },
"hasVariablesReference": True,
},
"argv": {
@@ -347,13 +357,27 @@ def test_scopes_variables_setVariable_evaluate(self):
@skipIfWindows
@skipIfRemote
- def test_scopes_and_evaluate_expansion(self):
+ def test_scopes_variables_setVariable_evaluate(self):
+ self.do_test_scopes_variables_setVariable_evaluate(
+ enableAutoVariableSummaries=False
+ )
+
+ @skipIfWindows
+ @skipIfRemote
+ def test_scopes_variables_setVariable_evaluate_with_descriptive_summaries(self):
+ self.do_test_scopes_variables_setVariable_evaluate(
+ enableAutoVariableSummaries=True
+ )
+
+ def do_test_scopes_and_evaluate_expansion(self, enableAutoVariableSummaries: bool):
"""
Tests the evaluated expression expands successfully after "scopes" packets
and permanent expressions persist.
"""
program = self.getBuildArtifact("a.out")
- self.build_and_launch(program)
+ self.build_and_launch(
+ program, enableAutoVariableSummaries=enableAutoVariableSummaries
+ )
source = "main.cpp"
breakpoint1_line = line_number(source, "// breakpoint 1")
lines = [breakpoint1_line]
@@ -410,7 +434,11 @@ def test_scopes_and_evaluate_expansion(self):
"name": "pt",
"response": {
"equals": {"type": "PointType"},
- "startswith": {"result": "{x:11, y:22}"},
+ "startswith": {
+ "result": "{x:11, y:22}"
+ if enableAutoVariableSummaries
+ else "PointType @ 0x"
+ },
"missing": ["indexedVariables"],
"hasVariablesReference": True,
},
@@ -487,14 +515,24 @@ def test_scopes_and_evaluate_expansion(self):
@skipIfWindows
@skipIfRemote
- def test_indexedVariables(self):
+ def test_scopes_and_evaluate_expansion(self):
+ self.do_test_scopes_and_evaluate_expansion(enableAutoVariableSummaries=False)
+
+ @skipIfWindows
+ @skipIfRemote
+ def test_scopes_and_evaluate_expansion_with_descriptive_summaries(self):
+ self.do_test_scopes_and_evaluate_expansion(enableAutoVariableSummaries=True)
+
+ def do_test_indexedVariables(self, enableSyntheticChildDebugging: bool):
"""
Tests that arrays and lldb.SBValue objects that have synthetic child
providers have "indexedVariables" key/value pairs. This helps the IDE
not to fetch too many children all at once.
"""
program = self.getBuildArtifact("a.out")
- self.build_and_launch(program)
+ self.build_and_launch(
+ program, enableSyntheticChildDebugging=enableSyntheticChildDebugging
+ )
source = "main.cpp"
breakpoint1_line = line_number(source, "// breakpoint 4")
lines = [breakpoint1_line]
@@ -507,13 +545,14 @@ def test_indexedVariables(self):
# Verify locals
locals = self.vscode.get_local_variables()
- # The vector variables will have one additional entry from the fake
+ # The vector variables might have one additional entry from the fake
# "[raw]" child.
+ raw_child_count = 1 if enableSyntheticChildDebugging else 0
verify_locals = {
"small_array": {"equals": {"indexedVariables": 5}},
"large_array": {"equals": {"indexedVariables": 200}},
- "small_vector": {"equals": {"indexedVariables": 6}},
- "large_vector": {"equals": {"indexedVariables": 201}},
+ "small_vector": {"equals": {"indexedVariables": 5 + raw_child_count}},
+ "large_vector": {"equals": {"indexedVariables": 200 + raw_child_count}},
"pt": {"missing": ["indexedVariables"]},
}
self.verify_variables(verify_locals, locals)
@@ -526,13 +565,25 @@ def test_indexedVariables(self):
"[2]": {"equals": {"type": "int", "value": "0"}},
"[3]": {"equals": {"type": "int", "value": "0"}},
"[4]": {"equals": {"type": "int", "value": "0"}},
- "[raw]": {"contains": {"type": ["vector"]}},
}
+ if enableSyntheticChildDebugging:
+ verify_children["[raw]"] = ({"contains": {"type": ["vector"]}},)
+
children = self.vscode.request_variables(locals[2]["variablesReference"])[
"body"
]["variables"]
self.verify_variables(verify_children, children)
+ @skipIfWindows
+ @skipIfRemote
+ def test_indexedVariables(self):
+ self.do_test_indexedVariables(enableSyntheticChildDebugging=False)
+
+ @skipIfWindows
+ @skipIfRemote
+ def test_indexedVariables_with_raw_child_for_synthetics(self):
+ self.do_test_indexedVariables(enableSyntheticChildDebugging=True)
+
@skipIfWindows
@skipIfRemote
def test_registers(self):
diff --git a/lldb/tools/lldb-vscode/JSONUtils.cpp b/lldb/tools/lldb-vscode/JSONUtils.cpp
index e34448c9b7f2f85..0d149ff27fd3d3e 100644
--- a/lldb/tools/lldb-vscode/JSONUtils.cpp
+++ b/lldb/tools/lldb-vscode/JSONUtils.cpp
@@ -137,6 +137,12 @@ std::vector<std::string> GetStrings(const llvm::json::Object *obj,
/// glance.
static std::optional<std::string>
GetSyntheticSummaryForContainer(lldb::SBValue &v) {
+ // We gate this feature because it performs GetNumChildren(), which can
+ // cause performance issues because LLDB needs to complete possibly huge
+ // types.
+ if (!g_vsc.enable_auto_variable_summaries)
+ return std::nullopt;
+
if (v.TypeIsPointerType() || !v.MightHaveChildren())
return std::nullopt;
/// As this operation can be potentially slow, we limit the total time spent
@@ -191,6 +197,9 @@ GetSyntheticSummaryForContainer(lldb::SBValue &v) {
/// Return whether we should dereference an SBValue in order to generate a more
/// meaningful summary string.
static bool ShouldBeDereferencedForSummary(lldb::SBValue &v) {
+ if (!g_vsc.enable_auto_variable_summaries)
+ return false;
+
if (!v.GetType().IsPointerType() && !v.GetType().IsReferenceType())
return false;
@@ -1137,7 +1146,8 @@ llvm::json::Value CreateVariable(lldb::SBValue v, int64_t variablesReference,
// We create a "[raw]" fake child for each synthetic type, so we have to
// account for it when returning indexed variables. We don't need to do this
// for non-indexed ones.
- int actual_num_children = num_children + (is_synthetic ? 1 : 0);
+ bool has_raw_child = is_synthetic && g_vsc.enable_synthetic_child_debugging;
+ int actual_num_children = num_children + (has_raw_child ? 1 : 0);
if (is_array) {
object.try_emplace("indexedVariables", actual_num_children);
} else if (num_children > 0) {
diff --git a/lldb/tools/lldb-vscode/VSCode.cpp b/lldb/tools/lldb-vscode/VSCode.cpp
index 85e1f4b4ac06e4e..1384604c48371b7 100644
--- a/lldb/tools/lldb-vscode/VSCode.cpp
+++ b/lldb/tools/lldb-vscode/VSCode.cpp
@@ -41,6 +41,8 @@ VSCode::VSCode()
{"swift_throw", "Swift Throw", lldb::eLanguageTypeSwift}}),
focus_tid(LLDB_INVALID_THREAD_ID), sent_terminated_event(false),
stop_at_entry(false), is_attach(false),
+ enable_auto_variable_summaries(false),
+ enable_synthetic_child_debugging(false),
restarting_process_id(LLDB_INVALID_PROCESS_ID),
configuration_done_sent(false), waiting_for_run_in_terminal(false),
progress_event_reporter(
diff --git a/lldb/tools/lldb-vscode/VSCode.h b/lldb/tools/lldb-vscode/VSCode.h
index 730223046b3c44a..59bb11c71e67203 100644
--- a/lldb/tools/lldb-vscode/VSCode.h
+++ b/lldb/tools/lldb-vscode/VSCode.h
@@ -167,6 +167,8 @@ struct VSCode {
std::atomic<bool> sent_terminated_event;
bool stop_at_entry;
bool is_attach;
+ bool enable_auto_variable_summaries;
+ bool enable_synthetic_child_debugging;
// The process event thread normally responds to process exited events by
// shutting down the entire adapter. When we're restarting, we keep the id of
// the old process here so we can detect this case and keep running.
diff --git a/lldb/tools/lldb-vscode/lldb-vscode.cpp b/lldb/tools/lldb-vscode/lldb-vscode.cpp
index 5480edd74f24f47..3904d430c49b4cd 100644
--- a/lldb/tools/lldb-vscode/lldb-vscode.cpp
+++ b/lldb/tools/lldb-vscode/lldb-vscode.cpp
@@ -647,6 +647,10 @@ void request_attach(const llvm::json::Object &request) {
std::vector<std::string> postRunCommands =
GetStrings(arguments, "postRunCommands");
const llvm::StringRef debuggerRoot = GetString(arguments, "debuggerRoot");
+ g_vsc.enable_auto_variable_summaries =
+ GetBoolean(arguments, "enableAutoVariableSummaries", false);
+ g_vsc.enable_synthetic_child_debugging =
+ GetBoolean(arguments, "enableSyntheticChildDebugging", false);
// This is a hack for loading DWARF in .o files on Mac where the .o files
// in the debug map of the main executable have relative paths which require
@@ -1794,6 +1798,10 @@ void request_launch(const llvm::json::Object &request) {
GetStrings(arguments, "postRunCommands");
g_vsc.stop_at_entry = GetBoolean(arguments, "stopOnEntry", false);
const llvm::StringRef debuggerRoot = GetString(arguments, "debuggerRoot");
+ g_vsc.enable_auto_variable_summaries =
+ GetBoolean(arguments, "enableAutoVariableSummaries", false);
+ g_vsc.enable_synthetic_child_debugging =
+ GetBoolean(arguments, "enableSyntheticChildDebugging", false);
// This is a hack for loading DWARF in .o files on Mac where the .o files
// in the debug map of the main executable have relative paths which require
@@ -3292,7 +3300,8 @@ void request_variables(const llvm::json::Object &request) {
// "[raw]" child that can be used to inspect the raw version of a
// synthetic member. That eliminates the need for the user to go to the
// debug console and type `frame var <variable> to get these values.
- if (variable.IsSynthetic() && i == num_children)
+ if (g_vsc.enable_synthetic_child_debugging && variable.IsSynthetic() &&
+ i == num_children)
addChild(variable.GetNonSyntheticValue(), "[raw]");
}
}
diff --git a/lldb/tools/lldb-vscode/package.json b/lldb/tools/lldb-vscode/package.json
index cc6df03097a70e4..1b3d452f92ab86a 100644
--- a/lldb/tools/lldb-vscode/package.json
+++ b/lldb/tools/lldb-vscode/package.json
@@ -240,6 +240,16 @@
"timeout": {
"type": "string",
"description": "The time in seconds to wait for a program to stop at entry point when launching with \"launchCommands\". Defaults to 30 seconds."
+ },
+ "enableAutoVariableSummaries": {
+ "type": "boolean",
+ "description": "Enable auto generated summaries for variables when no summaries exist for a given type. This feature can cause performance delays in large projects when viewing variables.",
+ "default": false
+ },
+ "enableSyntheticChildDebugging": {
+ "type": "boolean",
+ "description": "If a variable is displayed using a synthetic children, also display the actual contents of the variable at the end under a [raw] entry. This is useful when creating sythetic child plug-ins as it lets you see the actual contents of the variable.",
+ "default": false
}
}
},
@@ -319,6 +329,16 @@
"timeout": {
"type": "string",
"description": "The time in seconds to wait for a program to stop when attaching using \"attachCommands\". Defaults to 30 seconds."
+ },
+ "enableAutoVariableSummaries": {
+ "type": "boolean",
+ "description": "Enable auto generated summaries for variables when no summaries exist for a given type. This feature can cause performance delays in large projects when viewing variables.",
+ "default": false
+ },
+ "enableSyntheticChildDebugging": {
+ "type": "boolean",
+ "description": "If a variable is displayed using a synthetic children, also display the actual contents of the variable at the end under a [raw] entry. This is useful when creating sythetic child plug-ins as it lets you see the actual contents of the variable.",
+ "default": false
}
}
}
>From 212267ce936810370e0ba0b1327d88affaeb7c02 Mon Sep 17 00:00:00 2001
From: "Yaxun (Sam) Liu" <yaxun.liu at amd.com>
Date: Mon, 11 Sep 2023 17:04:55 -0400
Subject: [PATCH 14/35] [CUDA][HIP] Do not mark extern shared var (#65990)
Fixes: https://github.com/llvm/llvm-project/issues/65806
Currently clang put extern shared var ODR-used by host device functions
in global var __clang_gpu_used_external. This behavior was due to
https://reviews.llvm.org/D123441. However, clang should not do that for
extern shared vars since their addresses are per warp, therefore cannot
be accessed by host code.
---
clang/include/clang/AST/ASTContext.h | 3 +++
clang/lib/Sema/SemaExpr.cpp | 1 +
clang/test/CodeGenCUDA/host-used-extern.cu | 20 +++++++++++++++++++-
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/clang/include/clang/AST/ASTContext.h b/clang/include/clang/AST/ASTContext.h
index ec6b579870abbdc..4ee32c76a95d8e3 100644
--- a/clang/include/clang/AST/ASTContext.h
+++ b/clang/include/clang/AST/ASTContext.h
@@ -1141,6 +1141,9 @@ class ASTContext : public RefCountedBase<ASTContext> {
mutable TagDecl *MSGuidTagDecl = nullptr;
/// Keep track of CUDA/HIP device-side variables ODR-used by host code.
+ /// This does not include extern shared variables used by device host
+ /// functions as addresses of shared variables are per warp, therefore
+ /// cannot be accessed by host code.
llvm::DenseSet<const VarDecl *> CUDADeviceVarODRUsedByHost;
/// Keep track of CUDA/HIP external kernels or device variables ODR-used by
diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
index 3e9c3fad03918f0..92496b03ecabe54 100644
--- a/clang/lib/Sema/SemaExpr.cpp
+++ b/clang/lib/Sema/SemaExpr.cpp
@@ -19136,6 +19136,7 @@ MarkVarDeclODRUsed(ValueDecl *V, SourceLocation Loc, Sema &SemaRef,
: diag::note_cuda_host_var);
}
} else if (VarTarget == Sema::CVT_Device &&
+ !Var->hasAttr<CUDASharedAttr>() &&
(UserTarget == Sema::CFT_Host ||
UserTarget == Sema::CFT_HostDevice)) {
// Record a CUDA/HIP device side variable if it is ODR-used
diff --git a/clang/test/CodeGenCUDA/host-used-extern.cu b/clang/test/CodeGenCUDA/host-used-extern.cu
index c7edabf5c582b6f..e8f8e12aad47d1c 100644
--- a/clang/test/CodeGenCUDA/host-used-extern.cu
+++ b/clang/test/CodeGenCUDA/host-used-extern.cu
@@ -9,6 +9,11 @@
// RUN: -std=c++11 -emit-llvm -o - -target-cpu gfx906 \
// RUN: | FileCheck -check-prefixes=NEG,NORDC %s
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -x hip %s \
+// RUN: -fgpu-rdc -std=c++11 -emit-llvm -o - \
+// RUN: | FileCheck -check-prefix=HOST-NEG %s
+
+
#include "Inputs/cuda.h"
// CHECK-LABEL: @__clang_gpu_used_external = internal {{.*}}global
@@ -21,10 +26,13 @@
// NEG-NOT: @__clang_gpu_used_external = {{.*}} @_Z7kernel3v
// NEG-NOT: @__clang_gpu_used_external = {{.*}} @var2
// NEG-NOT: @__clang_gpu_used_external = {{.*}} @var3
+// NEG-NOT: @__clang_gpu_used_external = {{.*}} @ext_shvar
+// NEG-NOT: @__clang_gpu_used_external = {{.*}} @shvar
// NORDC-NOT: @__clang_gpu_used_external = {{.*}} @_Z7kernel1v
// NORDC-NOT: @__clang_gpu_used_external = {{.*}} @_Z7kernel4v
// NORDC-NOT: @__clang_gpu_used_external = {{.*}} @var1
-
+// HOST-NEG-NOT: call void @__hipRegisterVar({{.*}}, ptr @ext_shvar
+// HOST-NEG-NOT: call void @__hipRegisterVar({{.*}}, ptr @shvar
__global__ void kernel1();
// kernel2 is not marked as used since it is a definition.
@@ -49,3 +57,13 @@ void test() {
void *p = (void*)kernel4;
use(&var1);
}
+
+__global__ void test_lambda_using_extern_shared() {
+ extern __shared__ int ext_shvar[];
+ __shared__ int shvar[10];
+ auto lambda = [&]() {
+ ext_shvar[0] = 1;
+ shvar[0] = 2;
+ };
+ lambda();
+}
>From 7206f485f69e2cfdaa248e53ce1da74021bd2952 Mon Sep 17 00:00:00 2001
From: Nico Weber <thakis at chromium.org>
Date: Mon, 11 Sep 2023 13:56:53 -0700
Subject: [PATCH 15/35] Revert "[Driver] Properly report error for unsupported
powerpc darwin/macos triples"
This reverts commit 9f77facfce3ca23213c1de2e3e4c969b5187e29d.
The change unintentionally changed lots of codegen, see
https://github.com/llvm/llvm-project/issues/47698#issuecomment-1714548640
Also revert a follow-up:
This reverts commit b40a5bead2cb95c90ecd8c0fa566722e6133e01c.
---
clang/test/Driver/unsupported-target-arch.c | 4 ----
llvm/lib/TargetParser/Triple.cpp | 6 +++---
llvm/unittests/TargetParser/TripleTest.cpp | 1 -
3 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/clang/test/Driver/unsupported-target-arch.c b/clang/test/Driver/unsupported-target-arch.c
index 8df0ee9fe7d06f1..24174650151f1ce 100644
--- a/clang/test/Driver/unsupported-target-arch.c
+++ b/clang/test/Driver/unsupported-target-arch.c
@@ -59,7 +59,3 @@
// RUN: not %clang --target=thumbeb-none-elf -o %t.o %s 2> %t.err
// RUN: FileCheck --input-file=%t.err --check-prefix=CHECK-THUMBEB-INVALID-ENV %s
// CHECK-THUMBEB-INVALID-ENV: warning: mismatch between architecture and environment in target triple 'thumbeb-none-elf'; did you mean 'thumbeb-none-eabi'? [-Winvalid-command-line-argument]{{$}}
-
-// RUN: not %clang --target=powerpc-apple-darwin -o /dev/null %s 2> %t.err
-// RUN: FileCheck --input-file=%t.err --check-prefix=CHECK-PPCMAC %s
-// CHECK-PPCMAC: error: unknown target triple 'unknown-apple-macosx{{.*}}'
diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp
index 3da145f3b0b8927..260819d4a83d5a2 100644
--- a/llvm/lib/TargetParser/Triple.cpp
+++ b/llvm/lib/TargetParser/Triple.cpp
@@ -787,8 +787,6 @@ static Triple::SubArchType parseSubArch(StringRef SubArchName) {
}
static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
- if (T.isOSDarwin())
- return Triple::MachO;
switch (T.getArch()) {
case Triple::UnknownArch:
case Triple::aarch64:
@@ -797,7 +795,9 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
case Triple::thumb:
case Triple::x86:
case Triple::x86_64:
- if (T.isOSWindows())
+ if (T.isOSDarwin())
+ return Triple::MachO;
+ else if (T.isOSWindows())
return Triple::COFF;
return Triple::ELF;
diff --git a/llvm/unittests/TargetParser/TripleTest.cpp b/llvm/unittests/TargetParser/TripleTest.cpp
index 2b2ec73fcb8a926..dae5a82ff491860 100644
--- a/llvm/unittests/TargetParser/TripleTest.cpp
+++ b/llvm/unittests/TargetParser/TripleTest.cpp
@@ -1937,7 +1937,6 @@ TEST(TripleTest, FileFormat) {
EXPECT_EQ(Triple::MachO, Triple("i686-apple-macosx").getObjectFormat());
EXPECT_EQ(Triple::MachO, Triple("i686-apple-ios").getObjectFormat());
EXPECT_EQ(Triple::MachO, Triple("i686---macho").getObjectFormat());
- EXPECT_EQ(Triple::MachO, Triple("powerpc-apple-macosx").getObjectFormat());
EXPECT_EQ(Triple::COFF, Triple("i686--win32").getObjectFormat());
>From aca7e4e2c5943ae95adf848c4948ef1684731427 Mon Sep 17 00:00:00 2001
From: Stella Laurenzo <stellaraccident at gmail.com>
Date: Mon, 11 Sep 2023 14:10:03 -0700
Subject: [PATCH 16/35] [mlir] Make it possible to build a
DenseResourceElementsAttr from untyped memory. (#66009)
Exposes the existing `get(ShapedType, StringRef, AsmResourceBlob)`
builder publicly (was protected) and adds a CAPI
`mlirUnmanagedDenseBlobResourceElementsAttrGet`.
While such a generic construction interface is a big help when it comes
to interop, it is also necessary for creating resources that don't have
a standard C type (i.e. f16, the f8s, etc).
Previously reviewed/approved as part of https://reviews.llvm.org/D157064
---
mlir/include/mlir-c/BuiltinAttributes.h | 7 +++++++
mlir/include/mlir/IR/BuiltinAttributes.td | 17 ++++++++---------
mlir/lib/CAPI/IR/BuiltinAttributes.cpp | 8 ++++++++
mlir/test/CAPI/ir.c | 15 ++++++++++++---
4 files changed, 35 insertions(+), 12 deletions(-)
diff --git a/mlir/include/mlir-c/BuiltinAttributes.h b/mlir/include/mlir-c/BuiltinAttributes.h
index 63198192453efb8..93c4ed5692ef26d 100644
--- a/mlir/include/mlir-c/BuiltinAttributes.h
+++ b/mlir/include/mlir-c/BuiltinAttributes.h
@@ -600,6 +600,13 @@ mlirUnmanagedDenseDoubleResourceElementsAttrGet(MlirType shapedType,
intptr_t numElements,
const double *elements);
+/// Unlike the typed accessors above, constructs the attribute with a raw
+/// data buffer and no type/alignment checking. Use a more strongly typed
+/// accessor if possible.
+MLIR_CAPI_EXPORTED MlirAttribute mlirUnmanagedDenseBlobResourceElementsAttrGet(
+ MlirType shapedType, MlirStringRef name, const void *data,
+ size_t dataLength);
+
/// Returns the pos-th value (flat contiguous indexing) of a specific type
/// contained by the given dense resource elements attribute.
MLIR_CAPI_EXPORTED bool
diff --git a/mlir/include/mlir/IR/BuiltinAttributes.td b/mlir/include/mlir/IR/BuiltinAttributes.td
index 093303495469c37..390231da662e2d4 100644
--- a/mlir/include/mlir/IR/BuiltinAttributes.td
+++ b/mlir/include/mlir/IR/BuiltinAttributes.td
@@ -466,21 +466,20 @@ def Builtin_DenseResourceElementsAttr : Builtin_Attr<"DenseResourceElements", [
let builders = [
AttrBuilderWithInferredContext<(ins
"ShapedType":$type, "DenseResourceElementsHandle":$handle
- )>
- ];
- let extraClassDeclaration = [{
- protected:
+ )>,
/// A builder that inserts a new resource into the builtin dialect's blob
/// manager using the provided blob. The handle of the inserted blob is used
/// when building the attribute. The provided `blobName` is used as a hint
/// for the key of the new handle for the `blob` resource, but may be
/// changed if necessary to ensure uniqueness during insertion.
- static DenseResourceElementsAttr get(
- ShapedType type, StringRef blobName, AsmResourceBlob blob
- );
+ /// This base class builder does no element type specific size or alignment
+ /// checking. Use the typed subclasses for more safety unless if performing
+ /// generic operations.
+ AttrBuilderWithInferredContext<(ins
+ "ShapedType":$type, "StringRef":$blobName, "AsmResourceBlob":$blob
+ )>
+ ];
- public:
- }];
let skipDefaultBuilders = 1;
}
diff --git a/mlir/lib/CAPI/IR/BuiltinAttributes.cpp b/mlir/lib/CAPI/IR/BuiltinAttributes.cpp
index de221ddbfa7a922..84a958d01d2eb14 100644
--- a/mlir/lib/CAPI/IR/BuiltinAttributes.cpp
+++ b/mlir/lib/CAPI/IR/BuiltinAttributes.cpp
@@ -852,6 +852,14 @@ mlirUnmanagedDenseDoubleResourceElementsAttrGet(MlirType shapedType,
return getDenseResource<DenseF64ResourceElementsAttr>(shapedType, name,
numElements, elements);
}
+MLIR_CAPI_EXPORTED MlirAttribute mlirUnmanagedDenseBlobResourceElementsAttrGet(
+ MlirType shapedType, MlirStringRef name, const void *data,
+ size_t dataLength) {
+ return wrap(DenseResourceElementsAttr::get(
+ llvm::cast<ShapedType>(unwrap(shapedType)), unwrap(name),
+ UnmanagedAsmResourceBlob::allocateInferAlign(
+ llvm::ArrayRef(static_cast<const char *>(data), dataLength))));
+}
template <typename U, typename T>
static T getDenseResourceVal(MlirAttribute attr, intptr_t pos) {
diff --git a/mlir/test/CAPI/ir.c b/mlir/test/CAPI/ir.c
index c3b78fe1762c005..5d78daa296501f4 100644
--- a/mlir/test/CAPI/ir.c
+++ b/mlir/test/CAPI/ir.c
@@ -1118,7 +1118,8 @@ int printBuiltinAttributes(MlirContext ctx) {
const uint8_t *uint8RawData =
(const uint8_t *)mlirDenseElementsAttrGetRawData(uint8Elements);
- const int8_t *int8RawData = (const int8_t *)mlirDenseElementsAttrGetRawData(int8Elements);
+ const int8_t *int8RawData =
+ (const int8_t *)mlirDenseElementsAttrGetRawData(int8Elements);
const uint32_t *uint32RawData =
(const uint32_t *)mlirDenseElementsAttrGetRawData(uint32Elements);
const int32_t *int32RawData =
@@ -1127,7 +1128,8 @@ int printBuiltinAttributes(MlirContext ctx) {
(const uint64_t *)mlirDenseElementsAttrGetRawData(uint64Elements);
const int64_t *int64RawData =
(const int64_t *)mlirDenseElementsAttrGetRawData(int64Elements);
- const float *floatRawData = (const float *)mlirDenseElementsAttrGetRawData(floatElements);
+ const float *floatRawData =
+ (const float *)mlirDenseElementsAttrGetRawData(floatElements);
const double *doubleRawData =
(const double *)mlirDenseElementsAttrGetRawData(doubleElements);
const uint16_t *bf16RawData =
@@ -1268,6 +1270,10 @@ int printBuiltinAttributes(MlirContext ctx) {
MlirAttribute doublesBlob = mlirUnmanagedDenseDoubleResourceElementsAttrGet(
mlirRankedTensorTypeGet(2, shape, mlirF64TypeGet(ctx), encoding),
mlirStringRefCreateFromCString("resource_f64"), 2, doubles);
+ MlirAttribute blobBlob = mlirUnmanagedDenseBlobResourceElementsAttrGet(
+ mlirRankedTensorTypeGet(2, shape, mlirIntegerTypeGet(ctx, 64), encoding),
+ mlirStringRefCreateFromCString("resource_i64_blob"), uints64,
+ sizeof(uints64));
mlirAttributeDump(uint8Blob);
mlirAttributeDump(uint16Blob);
@@ -1279,6 +1285,7 @@ int printBuiltinAttributes(MlirContext ctx) {
mlirAttributeDump(int64Blob);
mlirAttributeDump(floatsBlob);
mlirAttributeDump(doublesBlob);
+ mlirAttributeDump(blobBlob);
// CHECK: dense_resource<resource_ui8> : tensor<1x2xui8>
// CHECK: dense_resource<resource_ui16> : tensor<1x2xui16>
// CHECK: dense_resource<resource_ui32> : tensor<1x2xui32>
@@ -1289,6 +1296,7 @@ int printBuiltinAttributes(MlirContext ctx) {
// CHECK: dense_resource<resource_i64> : tensor<1x2xi64>
// CHECK: dense_resource<resource_f32> : tensor<1x2xf32>
// CHECK: dense_resource<resource_f64> : tensor<1x2xf64>
+ // CHECK: dense_resource<resource_i64_blob> : tensor<1x2xi64>
if (mlirDenseUInt8ResourceElementsAttrGetValue(uint8Blob, 1) != 1 ||
mlirDenseUInt16ResourceElementsAttrGetValue(uint16Blob, 1) != 1 ||
@@ -1302,7 +1310,8 @@ int printBuiltinAttributes(MlirContext ctx) {
fabsf(mlirDenseFloatResourceElementsAttrGetValue(floatsBlob, 1) - 1.0f) >
1e-6 ||
fabs(mlirDenseDoubleResourceElementsAttrGetValue(doublesBlob, 1) - 1.0f) >
- 1e-6)
+ 1e-6 ||
+ mlirDenseUInt64ResourceElementsAttrGetValue(blobBlob, 1) != 1)
return 23;
MlirLocation loc = mlirLocationUnknownGet(ctx);
>From 0b4ef29363b15c4dbef05bedc16f85bec4092cf5 Mon Sep 17 00:00:00 2001
From: Lang Hames <lhames at gmail.com>
Date: Mon, 11 Sep 2023 14:11:26 -0700
Subject: [PATCH 17/35] [ORC] Fix implicit conversion warning due to
5293109774d.
This should fix the warning seen in
https://lab.llvm.org/buildbot/#/builders/13/builds/39980/steps/6/logs/stdio
---
llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h b/llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h
index 239889be91138e7..b8238db5325dafe 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h
@@ -289,7 +289,7 @@ template <typename MachOTraits> class MachOBuilder {
Seg.vmaddr = SegVMAddr;
Seg.fileoff = Offset;
for (auto &Sec : Seg.Sections) {
- Offset = alignTo(Offset, 1 << Sec->align);
+ Offset = alignTo(Offset, size_t{1} << Sec->align);
if (Sec->Content.Size)
Sec->offset = Offset;
Sec->size = Sec->Content.Size;
>From 4caa6bffba3d7344989b974e7283d98c5fcb4178 Mon Sep 17 00:00:00 2001
From: Matthias Braun <matze at braunis.de>
Date: Tue, 22 Aug 2023 14:44:18 -0700
Subject: [PATCH 18/35] LoopUnrollRuntime: Add weights to all branches
Make sure every conditional branch constructed by `LoopUnrollRuntime`
code sets branch weights.
- Add new 1:127 weights for the conditional jumps checking whether the
whole (unrolled) loop should be skipped in the generated prolog or
epilog code.
- Remove `updateLatchBranchWeightsForRemainderLoop` function and just
add weights immediately when constructing the relevant branches. This
leads to simpler code and makes the code more obvious as every call
to `CreateCondBr` now has a `BranchWeights` parameter.
- Rework formula for epilogue latch weights, to assume equal
distribution of remainders and remove `assert` (as I was able to
reach this code when forcing small unroll factors on the commandline).
Differential Revision: https://reviews.llvm.org/D158642
---
.../Transforms/Utils/LoopUnrollRuntime.cpp | 101 +++++++++++-------
.../runtime-exit-phi-scev-invalidation.ll | 8 +-
.../LoopUnroll/runtime-loop-branchweight.ll | 2 +-
.../Transforms/LoopUnroll/runtime-loop.ll | 67 ++++++++----
.../LoopUnroll/unroll-heuristics-pgo.ll | 16 +--
5 files changed, 119 insertions(+), 75 deletions(-)
diff --git a/llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp b/llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
index 831b4876aed6c1e..1c8850048f6ab19 100644
--- a/llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
+++ b/llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
@@ -56,6 +56,17 @@ static cl::opt<bool> UnrollRuntimeOtherExitPredictable(
"unroll-runtime-other-exit-predictable", cl::init(false), cl::Hidden,
cl::desc("Assume the non latch exit block to be predictable"));
+// Probability that the loop trip count is so small that after the prolog
+// we do not enter the unrolled loop at all.
+// It is unlikely that the loop trip count is smaller than the unroll factor;
+// other than that, the choice of constant is not tuned yet.
+static const uint32_t UnrolledLoopHeaderWeights[] = {1, 127};
+// Probability that the loop trip count is so small that we skip the unrolled
+// loop completely and immediately enter the epilogue loop.
+// It is unlikely that the loop trip count is smaller than the unroll factor;
+// other than that, the choice of constant is not tuned yet.
+static const uint32_t EpilogHeaderWeights[] = {1, 127};
+
/// Connect the unrolling prolog code to the original loop.
/// The unrolling prolog code contains code to execute the
/// 'extra' iterations if the run-time trip count modulo the
@@ -169,7 +180,14 @@ static void ConnectProlog(Loop *L, Value *BECount, unsigned Count,
SplitBlockPredecessors(OriginalLoopLatchExit, Preds, ".unr-lcssa", DT, LI,
nullptr, PreserveLCSSA);
// Add the branch to the exit block (around the unrolled loop)
- B.CreateCondBr(BrLoopExit, OriginalLoopLatchExit, NewPreHeader);
+ MDNode *BranchWeights = nullptr;
+ if (hasBranchWeightMD(*Latch->getTerminator())) {
+ // Assume loop is nearly always entered.
+ MDBuilder MDB(B.getContext());
+ BranchWeights = MDB.createBranchWeights(UnrolledLoopHeaderWeights);
+ }
+ B.CreateCondBr(BrLoopExit, OriginalLoopLatchExit, NewPreHeader,
+ BranchWeights);
InsertPt->eraseFromParent();
if (DT) {
auto *NewDom = DT->findNearestCommonDominator(OriginalLoopLatchExit,
@@ -194,8 +212,8 @@ static void ConnectEpilog(Loop *L, Value *ModVal, BasicBlock *NewExit,
BasicBlock *Exit, BasicBlock *PreHeader,
BasicBlock *EpilogPreHeader, BasicBlock *NewPreHeader,
ValueToValueMapTy &VMap, DominatorTree *DT,
- LoopInfo *LI, bool PreserveLCSSA,
- ScalarEvolution &SE) {
+ LoopInfo *LI, bool PreserveLCSSA, ScalarEvolution &SE,
+ unsigned Count) {
BasicBlock *Latch = L->getLoopLatch();
assert(Latch && "Loop must have a latch");
BasicBlock *EpilogLatch = cast<BasicBlock>(VMap[Latch]);
@@ -292,7 +310,13 @@ static void ConnectEpilog(Loop *L, Value *ModVal, BasicBlock *NewExit,
SplitBlockPredecessors(Exit, Preds, ".epilog-lcssa", DT, LI, nullptr,
PreserveLCSSA);
// Add the branch to the exit block (around the unrolling loop)
- B.CreateCondBr(BrLoopExit, EpilogPreHeader, Exit);
+ MDNode *BranchWeights = nullptr;
+ if (hasBranchWeightMD(*Latch->getTerminator())) {
+ // Assume equal distribution in interval [0, Count).
+ MDBuilder MDB(B.getContext());
+ BranchWeights = MDB.createBranchWeights(1, Count - 1);
+ }
+ B.CreateCondBr(BrLoopExit, EpilogPreHeader, Exit, BranchWeights);
InsertPt->eraseFromParent();
if (DT) {
auto *NewDom = DT->findNearestCommonDominator(Exit, NewExit);
@@ -316,8 +340,9 @@ CloneLoopBlocks(Loop *L, Value *NewIter, const bool UseEpilogRemainder,
const bool UnrollRemainder,
BasicBlock *InsertTop,
BasicBlock *InsertBot, BasicBlock *Preheader,
- std::vector<BasicBlock *> &NewBlocks, LoopBlocksDFS &LoopBlocks,
- ValueToValueMapTy &VMap, DominatorTree *DT, LoopInfo *LI) {
+ std::vector<BasicBlock *> &NewBlocks,
+ LoopBlocksDFS &LoopBlocks, ValueToValueMapTy &VMap,
+ DominatorTree *DT, LoopInfo *LI, unsigned Count) {
StringRef suffix = UseEpilogRemainder ? "epil" : "prol";
BasicBlock *Header = L->getHeader();
BasicBlock *Latch = L->getLoopLatch();
@@ -371,7 +396,26 @@ CloneLoopBlocks(Loop *L, Value *NewIter, const bool UseEpilogRemainder,
Value *IdxNext =
Builder.CreateAdd(NewIdx, One, NewIdx->getName() + ".next");
Value *IdxCmp = Builder.CreateICmpNE(IdxNext, NewIter, NewIdx->getName() + ".cmp");
- Builder.CreateCondBr(IdxCmp, FirstLoopBB, InsertBot);
+ MDNode *BranchWeights = nullptr;
+ if (hasBranchWeightMD(*LatchBR)) {
+ uint32_t ExitWeight;
+ uint32_t BackEdgeWeight;
+ if (Count >= 3) {
+ // Note: We do not enter this loop for zero-remainders. The check
+ // is at the end of the loop. We assume equal distribution between
+ // possible remainders in [1, Count).
+ ExitWeight = 1;
+ BackEdgeWeight = (Count - 2) / 2;
+ } else {
+ // Unnecessary backedge, should never be taken. The conditional
+ // jump should be optimized away later.
+ ExitWeight = 1;
+ BackEdgeWeight = 0;
+ }
+ MDBuilder MDB(Builder.getContext());
+ BranchWeights = MDB.createBranchWeights(BackEdgeWeight, ExitWeight);
+ }
+ Builder.CreateCondBr(IdxCmp, FirstLoopBB, InsertBot, BranchWeights);
NewIdx->addIncoming(Zero, InsertTop);
NewIdx->addIncoming(IdxNext, NewBB);
LatchBR->eraseFromParent();
@@ -465,32 +509,6 @@ static bool canProfitablyUnrollMultiExitLoop(
// know of kinds of multiexit loops that would benefit from unrolling.
}
-// Assign the maximum possible trip count as the back edge weight for the
-// remainder loop if the original loop comes with a branch weight.
-static void updateLatchBranchWeightsForRemainderLoop(Loop *OrigLoop,
- Loop *RemainderLoop,
- uint64_t UnrollFactor) {
- uint64_t TrueWeight, FalseWeight;
- BranchInst *LatchBR =
- cast<BranchInst>(OrigLoop->getLoopLatch()->getTerminator());
- if (!extractBranchWeights(*LatchBR, TrueWeight, FalseWeight))
- return;
- uint64_t ExitWeight = LatchBR->getSuccessor(0) == OrigLoop->getHeader()
- ? FalseWeight
- : TrueWeight;
- assert(UnrollFactor > 1);
- uint64_t BackEdgeWeight = (UnrollFactor - 1) * ExitWeight;
- BasicBlock *Header = RemainderLoop->getHeader();
- BasicBlock *Latch = RemainderLoop->getLoopLatch();
- auto *RemainderLatchBR = cast<BranchInst>(Latch->getTerminator());
- unsigned HeaderIdx = (RemainderLatchBR->getSuccessor(0) == Header ? 0 : 1);
- MDBuilder MDB(RemainderLatchBR->getContext());
- MDNode *WeightNode =
- HeaderIdx ? MDB.createBranchWeights(ExitWeight, BackEdgeWeight)
- : MDB.createBranchWeights(BackEdgeWeight, ExitWeight);
- RemainderLatchBR->setMetadata(LLVMContext::MD_prof, WeightNode);
-}
-
/// Calculate ModVal = (BECount + 1) % Count on the abstract integer domain
/// accounting for the possibility of unsigned overflow in the 2s complement
/// domain. Preconditions:
@@ -776,7 +794,13 @@ bool llvm::UnrollRuntimeLoopRemainder(
BasicBlock *RemainderLoop = UseEpilogRemainder ? NewExit : PrologPreHeader;
BasicBlock *UnrollingLoop = UseEpilogRemainder ? NewPreHeader : PrologExit;
// Branch to either remainder (extra iterations) loop or unrolling loop.
- B.CreateCondBr(BranchVal, RemainderLoop, UnrollingLoop);
+ MDNode *BranchWeights = nullptr;
+ if (hasBranchWeightMD(*Latch->getTerminator())) {
+ // Assume loop is nearly always entered.
+ MDBuilder MDB(B.getContext());
+ BranchWeights = MDB.createBranchWeights(EpilogHeaderWeights);
+ }
+ B.CreateCondBr(BranchVal, RemainderLoop, UnrollingLoop, BranchWeights);
PreHeaderBR->eraseFromParent();
if (DT) {
if (UseEpilogRemainder)
@@ -805,12 +829,7 @@ bool llvm::UnrollRuntimeLoopRemainder(
BasicBlock *InsertTop = UseEpilogRemainder ? EpilogPreHeader : PrologPreHeader;
Loop *remainderLoop = CloneLoopBlocks(
L, ModVal, UseEpilogRemainder, UnrollRemainder, InsertTop, InsertBot,
- NewPreHeader, NewBlocks, LoopBlocks, VMap, DT, LI);
-
- // Assign the maximum possible trip count as the back edge weight for the
- // remainder loop if the original loop comes with a branch weight.
- if (remainderLoop && !UnrollRemainder)
- updateLatchBranchWeightsForRemainderLoop(L, remainderLoop, Count);
+ NewPreHeader, NewBlocks, LoopBlocks, VMap, DT, LI, Count);
// Insert the cloned blocks into the function.
F->splice(InsertBot->getIterator(), F, NewBlocks[0]->getIterator(), F->end());
@@ -904,7 +923,7 @@ bool llvm::UnrollRuntimeLoopRemainder(
// Connect the epilog code to the original loop and update the
// PHI functions.
ConnectEpilog(L, ModVal, NewExit, LatchExit, PreHeader, EpilogPreHeader,
- NewPreHeader, VMap, DT, LI, PreserveLCSSA, *SE);
+ NewPreHeader, VMap, DT, LI, PreserveLCSSA, *SE, Count);
// Update counter in loop for unrolling.
// Use an incrementing IV. Pre-incr/post-incr is backedge/trip count.
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll b/llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll
index 82cd5f0d10aec1f..cf875ccdc147ab9 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll
@@ -165,7 +165,7 @@ define void @pr56286(i64 %x, ptr %src, ptr %dst, ptr %ptr.src) !prof !0 {
; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], -1
; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[TMP2]], 7
; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0
-; CHECK-NEXT: br i1 [[LCMP_MOD]], label [[INNER_1_HEADER_PROL_PREHEADER:%.*]], label [[INNER_1_HEADER_PROL_LOOPEXIT:%.*]]
+; CHECK-NEXT: br i1 [[LCMP_MOD]], label [[INNER_1_HEADER_PROL_PREHEADER:%.*]], label [[INNER_1_HEADER_PROL_LOOPEXIT:%.*]], !prof [[PROF3:![0-9]+]]
; CHECK: inner.1.header.prol.preheader:
; CHECK-NEXT: br label [[INNER_1_HEADER_PROL:%.*]]
; CHECK: inner.1.header.prol:
@@ -180,7 +180,7 @@ define void @pr56286(i64 %x, ptr %src, ptr %dst, ptr %ptr.src) !prof !0 {
; CHECK-NEXT: [[CMP_2_PROL:%.*]] = icmp sgt i64 [[INNER_1_IV_PROL]], 0
; CHECK-NEXT: [[PROL_ITER_NEXT]] = add i64 [[PROL_ITER]], 1
; CHECK-NEXT: [[PROL_ITER_CMP:%.*]] = icmp ne i64 [[PROL_ITER_NEXT]], [[XTRAITER]]
-; CHECK-NEXT: br i1 [[PROL_ITER_CMP]], label [[INNER_1_HEADER_PROL]], label [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !prof [[PROF3:![0-9]+]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-NEXT: br i1 [[PROL_ITER_CMP]], label [[INNER_1_HEADER_PROL]], label [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !prof [[PROF4:![0-9]+]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: inner.1.header.prol.loopexit.unr-lcssa:
; CHECK-NEXT: [[L_1_LCSSA_UNR_PH:%.*]] = phi i32 [ [[L_1_PROL]], [[INNER_1_LATCH_PROL]] ]
; CHECK-NEXT: [[INNER_1_IV_UNR_PH:%.*]] = phi i64 [ [[INNER_1_IV_NEXT_PROL]], [[INNER_1_LATCH_PROL]] ]
@@ -189,7 +189,7 @@ define void @pr56286(i64 %x, ptr %src, ptr %dst, ptr %ptr.src) !prof !0 {
; CHECK-NEXT: [[L_1_LCSSA_UNR:%.*]] = phi i32 [ undef, [[OUTER_HEADER]] ], [ [[L_1_LCSSA_UNR_PH]], [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ]
; CHECK-NEXT: [[INNER_1_IV_UNR:%.*]] = phi i64 [ [[X]], [[OUTER_HEADER]] ], [ [[INNER_1_IV_UNR_PH]], [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ]
; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 7
-; CHECK-NEXT: br i1 [[TMP4]], label [[OUTER_MIDDLE:%.*]], label [[OUTER_HEADER_NEW:%.*]]
+; CHECK-NEXT: br i1 [[TMP4]], label [[OUTER_MIDDLE:%.*]], label [[OUTER_HEADER_NEW:%.*]], !prof [[PROF3]]
; CHECK: outer.header.new:
; CHECK-NEXT: br label [[INNER_1_HEADER:%.*]]
; CHECK: inner.1.header:
@@ -233,7 +233,7 @@ define void @pr56286(i64 %x, ptr %src, ptr %dst, ptr %ptr.src) !prof !0 {
; CHECK-NEXT: store i32 [[L_1_7]], ptr [[DST]], align 8
; CHECK-NEXT: [[INNER_1_IV_NEXT_7]] = add i64 [[INNER_1_IV]], 8
; CHECK-NEXT: [[CMP_2_7:%.*]] = icmp sgt i64 [[INNER_1_IV_NEXT_6]], 0
-; CHECK-NEXT: br i1 [[CMP_2_7]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[INNER_1_HEADER]], !prof [[PROF5:![0-9]+]]
+; CHECK-NEXT: br i1 [[CMP_2_7]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[INNER_1_HEADER]], !prof [[PROF6:![0-9]+]]
; CHECK: outer.middle.unr-lcssa:
; CHECK-NEXT: [[L_1_LCSSA_PH:%.*]] = phi i32 [ [[L_1_7]], [[INNER_1_LATCH_7]] ]
; CHECK-NEXT: br label [[OUTER_MIDDLE]]
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-loop-branchweight.ll b/llvm/test/Transforms/LoopUnroll/runtime-loop-branchweight.ll
index 00ddfc82feeb4d6..6e3bbe16167e730 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-loop-branchweight.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-loop-branchweight.ll
@@ -7,7 +7,7 @@
; CHECK-LABEL: for.body.epil:
; CHECK: br i1 [[COND2:%.*]], label %for.body.epil, label %for.end.loopexit.epilog-lcssa, !prof ![[#PROF2:]], !llvm.loop ![[#LOOP2:]]
; CHECK: ![[#PROF]] = !{!"branch_weights", i32 1, i32 2499}
-; CHECK: ![[#PROF2]] = !{!"branch_weights", i32 3, i32 1}
+; CHECK: ![[#PROF2]] = !{!"branch_weights", i32 1, i32 1}
define i3 @test(ptr %a, i3 %n) {
entry:
diff --git a/llvm/test/Transforms/LoopUnroll/runtime-loop.ll b/llvm/test/Transforms/LoopUnroll/runtime-loop.ll
index 15accc8067c8cc8..8acf74a84d2baba 100644
--- a/llvm/test/Transforms/LoopUnroll/runtime-loop.ll
+++ b/llvm/test/Transforms/LoopUnroll/runtime-loop.ll
@@ -18,41 +18,54 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
; COMMON-LABEL: @test(
-; EPILOG: %xtraiter = and i32 %n
-; EPILOG: %lcmp.mod = icmp ne i32 %xtraiter, 0
-; EPILOG: br i1 %lcmp.mod, label %for.body.epil.preheader, label %for.end.loopexit
+; EPILOG: entry:
+; EPILOG: br i1 %cmp1, label %for.end, label %for.body.preheader, !prof [[EPILOG_PROF_0:![0-9]+]]
+; EPILOG: for.body.preheader:
+; EPILOG: %xtraiter = and i32 %n
+; EPILOG: br i1 %1, label %for.end.loopexit.unr-lcssa, label %for.body.preheader.new, !prof [[EPILOG_PROF_1:![0-9]+]]
+
+; EPILOG: for.end.loopexit.unr-lcssa:
+; EPILOG: %lcmp.mod = icmp ne i32 %xtraiter, 0
+; EPILOG: br i1 %lcmp.mod, label %for.body.epil.preheader, label %for.end.loopexit, !prof [[EPILOG_PROF_2:![0-9]+]]
; NOEPILOG-NOT: %xtraiter = and i32 %n
-; PROLOG: %xtraiter = and i32 %n
-; PROLOG: %lcmp.mod = icmp ne i32 %xtraiter, 0
-; PROLOG: br i1 %lcmp.mod, label %for.body.prol.preheader, label %for.body.prol.loopexit
+; PROLOG: entry:
+; PROLOG: br i1 %cmp1, label %for.end, label %for.body.preheader, !prof [[PROLOG_PROF_0:![0-9]+]]
+
+; PROLOG: for.body.preheader:
+; PROLOG: %xtraiter = and i32 %n
+; PROLOG: %lcmp.mod = icmp ne i32 %xtraiter, 0
+; PROLOG: br i1 %lcmp.mod, label %for.body.prol.preheader, label %for.body.prol.loopexit, !prof [[PROLOG_PROF_1:![0-9]+]]
; NOPROLOG-NOT: %xtraiter = and i32 %n
; EPILOG: for.body.epil:
-; EPILOG: %indvars.iv.epil = phi i64 [ %indvars.iv.next.epil, %for.body.epil ], [ %indvars.iv.unr, %for.body.epil.preheader ]
-; EPILOG: %epil.iter.next = add i32 %epil.iter, 1
-; EPILOG: %epil.iter.cmp = icmp ne i32 %epil.iter.next, %xtraiter
-; EPILOG: br i1 %epil.iter.cmp, label %for.body.epil, label %for.end.loopexit.epilog-lcssa, !llvm.loop !0
+; EPILOG: %indvars.iv.epil = phi i64 [ %indvars.iv.next.epil, %for.body.epil ], [ %indvars.iv.unr, %for.body.epil.preheader ]
+; EPILOG: %epil.iter.next = add i32 %epil.iter, 1
+; EPILOG: %epil.iter.cmp = icmp ne i32 %epil.iter.next, %xtraiter
+; EPILOG: br i1 %epil.iter.cmp, label %for.body.epil, label %for.end.loopexit.epilog-lcssa, !prof [[EPILOG_PROF_3:![0-9]+]], !llvm.loop [[EPILOG_LOOP:![0-9]+]]
; NOEPILOG: for.body:
; NOEPILOG-NOT: for.body.epil:
; PROLOG: for.body.prol:
-; PROLOG: %indvars.iv.prol = phi i64 [ %indvars.iv.next.prol, %for.body.prol ], [ 0, %for.body.prol.preheader ]
-; PROLOG: %prol.iter.next = add i32 %prol.iter, 1
-; PROLOG: %prol.iter.cmp = icmp ne i32 %prol.iter.next, %xtraiter
-; PROLOG: br i1 %prol.iter.cmp, label %for.body.prol, label %for.body.prol.loopexit.unr-lcssa, !llvm.loop !0
+; PROLOG: %indvars.iv.prol = phi i64 [ %indvars.iv.next.prol, %for.body.prol ], [ 0, %for.body.prol.preheader ]
+; PROLOG: %prol.iter.next = add i32 %prol.iter, 1
+; PROLOG: %prol.iter.cmp = icmp ne i32 %prol.iter.next, %xtraiter
+; PROLOG: br i1 %prol.iter.cmp, label %for.body.prol, label %for.body.prol.loopexit.unr-lcssa, !prof [[PROLOG_PROF_2:![0-9]+]], !llvm.loop [[PROLOG_LOOP:![0-9]+]]
+
+; PROLOG: for.body.prol.loopexit:
+; PROLOG: br i1 %2, label %for.end.loopexit, label %for.body.preheader.new, !prof [[PROLOG_PROF_1:![0-9]+]]
; NOPROLOG: for.body:
; NOPROLOG-NOT: for.body.prol:
-define i32 @test(ptr nocapture %a, i32 %n) nounwind uwtable readonly {
+define i32 @test(ptr nocapture %a, i32 %n) nounwind uwtable readonly !prof !2 {
entry:
%cmp1 = icmp eq i32 %n, 0
- br i1 %cmp1, label %for.end, label %for.body
+ br i1 %cmp1, label %for.end, label %for.body, !prof !3
for.body: ; preds = %for.body, %entry
%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
@@ -63,7 +76,7 @@ for.body: ; preds = %for.body, %entry
%indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, %n
- br i1 %exitcond, label %for.end, label %for.body
+ br i1 %exitcond, label %for.end, label %for.body, !prof !4
for.end: ; preds = %for.body, %entry
%sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
@@ -274,12 +287,24 @@ exit2.loopexit:
!0 = distinct !{!0, !1}
!1 = !{!"llvm.loop.unroll.runtime.disable"}
+!2 = !{!"function_entry_count", i64 1}
+!3 = !{!"branch_weights", i32 1, i32 11}
+!4 = !{!"branch_weights", i32 1, i32 42}
; need to use LABEL here to separate function IR matching from metadata matching
; COMMON-LABEL: {{^}}!0 =
-; EPILOG-SAME: distinct !{!0, !1}
-; EPILOG: !1 = !{!"llvm.loop.unroll.disable"}
+; EPILOG: [[EPILOG_PROF_0]] = !{!"branch_weights", i32 1, i32 11}
+; EPILOG: [[EPILOG_PROF_1]] = !{!"branch_weights", i32 1, i32 127}
+; EPILOG: [[EPILOG_PROF_2]] = !{!"branch_weights", i32 1, i32 7}
+; EPILOG: [[EPILOG_PROF_3]] = !{!"branch_weights", i32 3, i32 1}
+
+; EPILOG: [[EPILOG_LOOP]] = distinct !{[[EPILOG_LOOP]], [[EPILOG_LOOP_1:![0-9]+]]}
+; EPILOG: [[EPILOG_LOOP_1]] = !{!"llvm.loop.unroll.disable"}
+
+; PROLOG: [[PROLOG_PROF_0]] = !{!"branch_weights", i32 1, i32 11}
+; PROLOG: [[PROLOG_PROF_1]] = !{!"branch_weights", i32 1, i32 127}
+; PROLOG: [[PROLOG_PROF_2]] = !{!"branch_weights", i32 3, i32 1}
-; PROLOG-SAME: distinct !{!0, !1}
-; PROLOG: !1 = !{!"llvm.loop.unroll.disable"}
+; PROLOG: distinct !{[[PROLOG_LOOP]], [[PROLOG_LOOP_1:![0-9]+]]}
+; PROLOG: [[PROLOG_LOOP_1]] = !{!"llvm.loop.unroll.disable"}
diff --git a/llvm/test/Transforms/LoopUnroll/unroll-heuristics-pgo.ll b/llvm/test/Transforms/LoopUnroll/unroll-heuristics-pgo.ll
index 725b4cebe55f5b2..20a247f3e7490d4 100644
--- a/llvm/test/Transforms/LoopUnroll/unroll-heuristics-pgo.ll
+++ b/llvm/test/Transforms/LoopUnroll/unroll-heuristics-pgo.ll
@@ -4,13 +4,13 @@
; CHECK-LABEL: @bar_prof
; CHECK: loop:
-; CHECK: %mul = mul
-; CHECK: %mul.1 = mul
-; CHECK: %mul.2 = mul
-; CHECK: %mul.3 = mul
-; CHECK: br i1 %niter.ncmp.7, label %loop.end.unr-lcssa.loopexit, label %loop, !prof !1
+; CHECK: %mul = mul
+; CHECK: %mul.1 = mul
+; CHECK: %mul.2 = mul
+; CHECK: %mul.3 = mul
+; CHECK: br i1 %niter.ncmp.7, label %loop.end.unr-lcssa.loopexit, label %loop, !prof [[PROF0:![0-9]+]]
; CHECK: loop.epil:
-; CHECK: br i1 %epil.iter.cmp, label %loop.epil, label %loop.end.epilog-lcssa, !prof !2, !llvm.loop !3
+; CHECK: br i1 %epil.iter.cmp, label %loop.epil, label %loop.end.epilog-lcssa, !prof [[PROF1:![0-9]+]], !llvm.loop {{![0-9]+}}
define i32 @bar_prof(ptr noalias nocapture readonly %src, i64 %c) !prof !1 {
entry:
br label %loop
@@ -60,5 +60,5 @@ loop.end:
!1 = !{!"function_entry_count", i64 1}
!2 = !{!"branch_weights", i32 1, i32 1000}
-; CHECK: !1 = !{!"branch_weights", i32 1, i32 124}
-; CHECK: !2 = !{!"branch_weights", i32 7, i32 1}
\ No newline at end of file
+; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 124}
+; CHECK: [[PROF1]] = !{!"branch_weights", i32 3, i32 1}
>From 730f597a250826a07272cd598700eb49248cf2f5 Mon Sep 17 00:00:00 2001
From: Arthur Eubanks <aeubanks at google.com>
Date: Mon, 11 Sep 2023 14:29:37 -0700
Subject: [PATCH 19/35] [test] Add x86-registered-target to
amdgpu_throw_trap.cpp
---
clang/test/OpenMP/amdgpu_throw_trap.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/OpenMP/amdgpu_throw_trap.cpp b/clang/test/OpenMP/amdgpu_throw_trap.cpp
index f1152f78bec1920..82b325275ac3885 100644
--- a/clang/test/OpenMP/amdgpu_throw_trap.cpp
+++ b/clang/test/OpenMP/amdgpu_throw_trap.cpp
@@ -1,4 +1,4 @@
-// REQUIRES: amdgpu-registered-target
+// REQUIRES: amdgpu-registered-target, x86-registered-target
// RUN: %clang_cc1 -fopenmp -triple amdgcn-amd-amdhsa -fopenmp-is-target-device %s -emit-llvm -S -Wno-openmp-target-exception -o - | FileCheck -check-prefix=DEVICE %s
// RUN: %clang_cc1 -fopenmp -triple x86_64-pc-linux-gnu -fopenmp-is-target-device -fcxx-exceptions %s -emit-llvm -S -Wno-openmp-target-exception -o - | FileCheck -check-prefix=HOST %s
>From c82b8978951be7187df330f3e7a6dc27ebcbaef3 Mon Sep 17 00:00:00 2001
From: Nico Weber <thakis at chromium.org>
Date: Mon, 11 Sep 2023 14:30:02 -0700
Subject: [PATCH 20/35] [cfi-verify tests]: Skip two x86-only tests if x86 is
not enabled
With this, check-llvm passes on an arm mac if x86 isn't in
LLVM_TARGETS_TO_BUILD.
This pattern to skip the tests if x86 isn't enabled is used
in every other test in this file.
---
llvm/unittests/tools/llvm-cfi-verify/FileAnalysis.cpp | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/llvm/unittests/tools/llvm-cfi-verify/FileAnalysis.cpp b/llvm/unittests/tools/llvm-cfi-verify/FileAnalysis.cpp
index aca9f393c7ec8c8..e46cbbd3455a4ec 100644
--- a/llvm/unittests/tools/llvm-cfi-verify/FileAnalysis.cpp
+++ b/llvm/unittests/tools/llvm-cfi-verify/FileAnalysis.cpp
@@ -707,6 +707,8 @@ TEST_F(BasicX86FileAnalysisTest, CFIProtectionComplexExample) {
}
TEST_F(BasicX86FileAnalysisTest, UndefSearchLengthOneTest) {
+ if (!SuccessfullyInitialised)
+ GTEST_SKIP();
Analysis.parseSectionContents(
{
0x77, 0x0d, // 0x688118: ja 0x688127 [+12]
@@ -726,6 +728,8 @@ TEST_F(BasicX86FileAnalysisTest, UndefSearchLengthOneTest) {
}
TEST_F(BasicX86FileAnalysisTest, UndefSearchLengthOneTestFarAway) {
+ if (!SuccessfullyInitialised)
+ GTEST_SKIP();
Analysis.parseSectionContents(
{
0x74, 0x73, // 0x7759eb: je 0x775a60
>From a09973e82f693f933224958f7d7d2877cd0e5660 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Valentin=20Clement=20=28=E3=83=90=E3=83=AC=E3=83=B3?=
=?UTF-8?q?=E3=82=BF=E3=82=A4=E3=83=B3=20=E3=82=AF=E3=83=AC=E3=83=A1?=
=?UTF-8?q?=E3=83=B3=29?= <clementval at gmail.com>
Date: Mon, 11 Sep 2023 14:34:21 -0700
Subject: [PATCH 21/35] [flang] Call finalization on empty type (#66010)
According to 7.5.6.3 point 3, finalization occurs when
> A nonpointer, nonallocatable object that is not a dummy argument or
function result is finalized immediately before it would become
undefined due to execution of a RETURN or END statement (19.6.6, item
(3)).
We were not calling the finalization on empty derived-type. There is no
such restriction so this patch updates the code so the finalization is
called for empty type as well.
---
flang/lib/Lower/ConvertVariable.cpp | 2 +-
flang/test/Lower/derived-type-finalization.f90 | 16 ++++++++++++++++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/flang/lib/Lower/ConvertVariable.cpp b/flang/lib/Lower/ConvertVariable.cpp
index 726b8489409ecb4..847ea468f447bc5 100644
--- a/flang/lib/Lower/ConvertVariable.cpp
+++ b/flang/lib/Lower/ConvertVariable.cpp
@@ -88,7 +88,7 @@ static bool hasDefaultInitialization(const Fortran::semantics::Symbol &sym) {
// Does this variable have a finalization?
static bool hasFinalization(const Fortran::semantics::Symbol &sym) {
- if (sym.has<Fortran::semantics::ObjectEntityDetails>() && sym.size())
+ if (sym.has<Fortran::semantics::ObjectEntityDetails>())
if (const Fortran::semantics::DeclTypeSpec *declTypeSpec = sym.GetType())
if (const Fortran::semantics::DerivedTypeSpec *derivedTypeSpec =
declTypeSpec->AsDerived())
diff --git a/flang/test/Lower/derived-type-finalization.f90 b/flang/test/Lower/derived-type-finalization.f90
index 4f223ab7511d19c..2194fd8d96451d0 100644
--- a/flang/test/Lower/derived-type-finalization.f90
+++ b/flang/test/Lower/derived-type-finalization.f90
@@ -23,6 +23,11 @@ module derived_type_finalization
type(t2) :: t
end type
+ type t4
+ contains
+ final :: t4_final
+ end type
+
contains
subroutine t1_final(this)
@@ -227,6 +232,17 @@ subroutine test_avoid_double_free()
! CHECK: %[[RES_CONV:.*]] = fir.convert %[[RES]] : (!fir.ref<!fir.class<!fir.heap<!fir.array<?x!fir.type<_QMderived_type_finalizationTt1{a:i32}>>>>>) -> !fir.box<none>
! CHECK: %{{.*}} = fir.call @_FortranADestroy(%[[RES_CONV]]) {{.*}} : (!fir.box<none>) -> none
+ subroutine t4_final(this)
+ type(t4) :: this
+ end subroutine
+
+ subroutine local_t4()
+ type(t4) :: t
+ end subroutine
+
+! CHECK-LABEL: func.func @_QMderived_type_finalizationPlocal_t4()
+! CHECK: %{{.*}} = fir.call @_FortranADestroy(%2) fastmath<contract> : (!fir.box<none>) -> none
+
end module
program p
>From cd4428b921a219b8559549afde019a941b088657 Mon Sep 17 00:00:00 2001
From: Vitaly Buka <vitalybuka at google.com>
Date: Mon, 11 Sep 2023 14:33:35 -0700
Subject: [PATCH 22/35] [test][hwasan] Disable test failing on x86_64 with no
-lstdc++
---
compiler-rt/test/hwasan/TestCases/sizes.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/compiler-rt/test/hwasan/TestCases/sizes.cpp b/compiler-rt/test/hwasan/TestCases/sizes.cpp
index 2cb70f52147ac18..cdde199d86b91a7 100644
--- a/compiler-rt/test/hwasan/TestCases/sizes.cpp
+++ b/compiler-rt/test/hwasan/TestCases/sizes.cpp
@@ -23,6 +23,9 @@
// allocator can allocate. Tests that an integer overflow in the parameters of
// calloc is caught.
+// FIXME: Fails on some bots.
+// UNSUPPORTED: target=x86_64{{.*}}
+
#include <assert.h>
#include <malloc.h>
#include <stdlib.h>
>From 45d89b5dfdc82cc997f32f5dc495aa0c719ed572 Mon Sep 17 00:00:00 2001
From: Vitaly Buka <vitalybuka at google.com>
Date: Mon, 11 Sep 2023 14:40:40 -0700
Subject: [PATCH 23/35] [test][hwasan] Relax test condition
The test is flaky after Kernel upgrade from 6.0 to 6.5.
---
compiler-rt/test/hwasan/TestCases/Linux/release-shadow.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/compiler-rt/test/hwasan/TestCases/Linux/release-shadow.c b/compiler-rt/test/hwasan/TestCases/Linux/release-shadow.c
index 3271ab58ba26e55..0572a9217b67d99 100644
--- a/compiler-rt/test/hwasan/TestCases/Linux/release-shadow.c
+++ b/compiler-rt/test/hwasan/TestCases/Linux/release-shadow.c
@@ -54,7 +54,7 @@ void test_rss_difference(void *p) {
size_t diff = rss_before - rss_after;
fprintf(stderr, "diff %zu\n", diff);
// Check that the difference is at least close to kNumShadowPages.
- assert(diff > kNumShadowPages / 4 * 3);
+ assert(diff > kNumShadowPages / 2);
}
int main() {
>From 8ebecf8bc8c1b45d3d2a88316b0de73d1fc32a10 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i at maskray.me>
Date: Mon, 11 Sep 2023 14:42:37 -0700
Subject: [PATCH 24/35] [test] Change llc -march= to -mtriple=
The issue is uncovered by #47698: for IR files without a target triple,
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense, e.g. riscv64-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead
of rejecting it outrightly.
---
.../AMDGPU/GlobalISel/combine-short-clamp.ll | 4 +-
.../AMDGPU/GlobalISel/inst-select-freeze.mir | 4 +-
...llvm.amdgcn.global.atomic.fadd-with-ret.ll | 2 +-
....amdgcn.raw.buffer.atomic.fadd-with-ret.ll | 2 +-
...gcn.raw.ptr.buffer.atomic.fadd-with-ret.ll | 2 +-
...dgcn.struct.buffer.atomic.fadd-with-ret.ll | 2 +-
....struct.ptr.buffer.atomic.fadd-with-ret.ll | 2 +-
.../GlobalISel/llvm.amdgcn.workitem.id.ll | 4 +-
.../GlobalISel/regbankselect-freeze.mir | 2 +-
llvm/test/CodeGen/AMDGPU/addrspacecast.ll | 4 +-
.../CodeGen/AMDGPU/amdgcn.private-memory.ll | 8 +-
.../test/CodeGen/AMDGPU/amdgpu-reloc-const.ll | 4 +-
.../CodeGen/AMDGPU/amdgpu.private-memory.ll | 10 +-
llvm/test/CodeGen/AMDGPU/bf16.ll | 10 +-
llvm/test/CodeGen/AMDGPU/branch-relaxation.ll | 4 +-
llvm/test/CodeGen/AMDGPU/build_vector.ll | 4 +-
.../CodeGen/AMDGPU/call-argument-types.ll | 8 +-
.../CodeGen/AMDGPU/calling-conventions.ll | 6 +-
llvm/test/CodeGen/AMDGPU/coalescer_remat.ll | 2 +-
.../AMDGPU/control-flow-fastregalloc.ll | 4 +-
.../CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll | 2 +-
llvm/test/CodeGen/AMDGPU/debug.ll | 4 +-
llvm/test/CodeGen/AMDGPU/ds_write2st64.ll | 2 +-
.../test/CodeGen/AMDGPU/dynamic_stackalloc.ll | 4 +-
.../CodeGen/AMDGPU/elf-header-flags-mach.ll | 152 +++++++++---------
.../AMDGPU/elf-header-flags-sramecc.ll | 20 +--
.../CodeGen/AMDGPU/elf-header-flags-xnack.ll | 8 +-
llvm/test/CodeGen/AMDGPU/elf-header-osabi.ll | 2 +-
llvm/test/CodeGen/AMDGPU/elf.ll | 12 +-
llvm/test/CodeGen/AMDGPU/elf.metadata.ll | 2 +-
llvm/test/CodeGen/AMDGPU/elf.r600.ll | 4 +-
llvm/test/CodeGen/AMDGPU/extload-align.ll | 2 +-
llvm/test/CodeGen/AMDGPU/extload.ll | 4 +-
llvm/test/CodeGen/AMDGPU/extract-lowbits.ll | 4 +-
.../CodeGen/AMDGPU/extract-subvector-16bit.ll | 6 +-
.../AMDGPU/extract-subvector-equal-length.ll | 2 +-
llvm/test/CodeGen/AMDGPU/extract-subvector.ll | 2 +-
.../CodeGen/AMDGPU/extract_vector_elt-f16.ll | 6 +-
.../CodeGen/AMDGPU/extract_vector_elt-f64.ll | 4 +-
.../CodeGen/AMDGPU/extract_vector_elt-i16.ll | 6 +-
.../CodeGen/AMDGPU/extract_vector_elt-i64.ll | 4 +-
llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll | 2 +-
.../CodeGen/AMDGPU/flat-scratch-i8-i16.ll | 4 +-
llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll | 34 ++--
llvm/test/CodeGen/AMDGPU/flat-scratch.ll | 8 +-
llvm/test/CodeGen/AMDGPU/fneg.f16.ll | 8 +-
llvm/test/CodeGen/AMDGPU/function-returns.ll | 8 +-
.../CodeGen/AMDGPU/gfx902-without-xnack.ll | 2 +-
.../global-atomics-fp-wrong-subtarget.ll | 4 +-
.../test/CodeGen/AMDGPU/hsa-default-device.ll | 2 +-
llvm/test/CodeGen/AMDGPU/imm16.ll | 2 +-
.../CodeGen/AMDGPU/insert-delay-alu-bug.ll | 2 +-
llvm/test/CodeGen/AMDGPU/kernel-args.ll | 4 +-
.../CodeGen/AMDGPU/large-alloca-compute.ll | 14 +-
llvm/test/CodeGen/AMDGPU/lds-alignment.ll | 2 +-
.../AMDGPU/llvm.amdgcn.groupstaticsize.ll | 4 +-
.../CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll | 4 +-
.../CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll | 4 +-
.../AMDGPU/llvm.amdgcn.workgroup.id.ll | 8 +-
.../CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll | 12 +-
llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll | 4 +-
llvm/test/CodeGen/AMDGPU/load-constant-f64.ll | 4 +-
llvm/test/CodeGen/AMDGPU/load-constant-i1.ll | 4 +-
llvm/test/CodeGen/AMDGPU/load-constant-i16.ll | 4 +-
llvm/test/CodeGen/AMDGPU/load-constant-i32.ll | 4 +-
llvm/test/CodeGen/AMDGPU/load-constant-i64.ll | 4 +-
llvm/test/CodeGen/AMDGPU/load-constant-i8.ll | 4 +-
llvm/test/CodeGen/AMDGPU/load-global-f32.ll | 4 +-
llvm/test/CodeGen/AMDGPU/load-global-f64.ll | 4 +-
llvm/test/CodeGen/AMDGPU/load-global-i1.ll | 4 +-
llvm/test/CodeGen/AMDGPU/load-global-i16.ll | 4 +-
llvm/test/CodeGen/AMDGPU/load-global-i32.ll | 4 +-
llvm/test/CodeGen/AMDGPU/load-global-i64.ll | 4 +-
llvm/test/CodeGen/AMDGPU/load-global-i8.ll | 4 +-
llvm/test/CodeGen/AMDGPU/load-local-f64.ll | 10 +-
llvm/test/CodeGen/AMDGPU/load-local-i1.ll | 6 +-
llvm/test/CodeGen/AMDGPU/load-local-i64.ll | 10 +-
llvm/test/CodeGen/AMDGPU/load-local-i8.ll | 10 +-
llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll | 4 +-
llvm/test/CodeGen/AMDGPU/loop-prefetch.ll | 6 +-
.../lower-range-metadata-intrinsic-call.ll | 4 +-
.../AMDGPU/module-lds-false-sharing.ll | 8 +-
.../move-addr64-rsrc-dead-subreg-writes.ll | 2 +-
.../CodeGen/AMDGPU/no-hsa-graphics-shaders.ll | 2 +-
.../AMDGPU/nullptr-long-address-spaces.ll | 2 +-
llvm/test/CodeGen/AMDGPU/nullptr.ll | 2 +-
llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll | 4 +-
.../CodeGen/AMDGPU/private-element-size.ll | 6 +-
.../promote-alloca-invariant-markers.ll | 2 +-
.../CodeGen/AMDGPU/promote-alloca-no-opts.ll | 4 +-
.../CodeGen/AMDGPU/register-count-comments.ll | 4 +-
llvm/test/CodeGen/AMDGPU/salu-to-valu.ll | 4 +-
llvm/test/CodeGen/AMDGPU/scratch-simple.ll | 24 +--
llvm/test/CodeGen/AMDGPU/setcc.ll | 2 +-
llvm/test/CodeGen/AMDGPU/sext-in-reg.ll | 6 +-
llvm/test/CodeGen/AMDGPU/shl.ll | 4 +-
llvm/test/CodeGen/AMDGPU/sra.ll | 4 +-
llvm/test/CodeGen/AMDGPU/store-global.ll | 6 +-
llvm/test/CodeGen/AMDGPU/store-local.ll | 6 +-
.../test/CodeGen/AMDGPU/tex-clause-antidep.ll | 2 +-
llvm/test/CodeGen/AMDGPU/trap-abis.ll | 6 +-
llvm/test/CodeGen/AMDGPU/trap.ll | 4 +-
llvm/test/CodeGen/AMDGPU/udiv.ll | 4 +-
llvm/test/CodeGen/AMDGPU/unknown-processor.ll | 2 +-
llvm/test/CodeGen/AMDGPU/unsupported-calls.ll | 4 +-
.../CodeGen/AMDGPU/vector-alloca-bitcast.ll | 4 +-
llvm/test/CodeGen/AMDGPU/vector-alloca.ll | 8 +-
...vgpr-spill-emergency-stack-slot-compute.ll | 10 +-
.../AMDGPU/vgpr-spill-emergency-stack-slot.ll | 6 +-
llvm/test/CodeGen/AVR/ctors.ll | 2 +-
llvm/test/CodeGen/AVR/jmp-long.ll | 2 +-
llvm/test/CodeGen/AVR/rust-trait-object.ll | 4 +-
llvm/test/CodeGen/AVR/sections.ll | 8 +-
llvm/test/CodeGen/BPF/BTF/align.ll | 4 +-
llvm/test/CodeGen/BPF/BTF/binary-format.ll | 4 +-
.../CodeGen/BPF/elf-symbol-information.ll | 2 +-
llvm/test/CodeGen/BPF/objdump_atomics.ll | 2 +-
llvm/test/CodeGen/BPF/objdump_cond_op.ll | 2 +-
llvm/test/CodeGen/BPF/objdump_cond_op_2.ll | 2 +-
llvm/test/CodeGen/BPF/objdump_dis_all.ll | 2 +-
llvm/test/CodeGen/BPF/objdump_fi_ri.ll | 2 +-
llvm/test/CodeGen/BPF/objdump_imm_hex.ll | 4 +-
llvm/test/CodeGen/BPF/objdump_intrinsics.ll | 4 +-
llvm/test/CodeGen/BPF/objdump_nop.ll | 2 +-
llvm/test/CodeGen/BPF/objdump_static_var.ll | 4 +-
llvm/test/CodeGen/BPF/objdump_trivial.ll | 2 +-
llvm/test/CodeGen/BPF/objdump_two_funcs.ll | 4 +-
llvm/test/CodeGen/BPF/reloc-2.ll | 4 +-
llvm/test/CodeGen/BPF/reloc-3.ll | 4 +-
llvm/test/CodeGen/BPF/reloc-btf-2.ll | 4 +-
llvm/test/CodeGen/BPF/reloc-btf.ll | 2 +-
llvm/test/CodeGen/BPF/reloc.ll | 2 +-
llvm/test/CodeGen/Hexagon/S3_2op.ll | 2 +-
llvm/test/CodeGen/Hexagon/cmp.ll | 2 +-
llvm/test/CodeGen/Hexagon/compound.ll | 2 +-
llvm/test/CodeGen/Hexagon/dualstore.ll | 2 +-
llvm/test/CodeGen/Hexagon/duplex.ll | 2 +-
llvm/test/CodeGen/Hexagon/extlow.ll | 2 +-
llvm/test/CodeGen/Hexagon/relax.ll | 2 +-
llvm/test/CodeGen/Hexagon/simple_addend.ll | 2 +-
llvm/test/CodeGen/Hexagon/tc_duplex_asm.ll | 2 +-
llvm/test/CodeGen/Hexagon/vect-regpairs.ll | 4 +-
llvm/test/CodeGen/Hexagon/vrcmpys.ll | 2 +-
llvm/test/CodeGen/Mips/2008-07-22-Cstpool.ll | 2 +-
llvm/test/CodeGen/Mips/Fast-ISel/shift.ll | 2 +-
.../CodeGen/Mips/cconv/callee-saved-float.ll | 34 ++--
.../Mips/compactbranches/no-beqzc-bnezc.ll | 8 +-
llvm/test/CodeGen/Mips/dsp-spill-reload.ll | 4 +-
.../Mips/inlineasm-constraint-bad-l1.ll | 2 +-
llvm/test/CodeGen/Mips/mature-mc-support.ll | 16 +-
llvm/test/CodeGen/Mips/micromips-atomic1.ll | 2 +-
llvm/test/CodeGen/Mips/micromips-b-range.ll | 2 +-
llvm/test/CodeGen/Mips/micromips-eva.mir | 2 +-
.../CodeGen/Mips/unaligned-memops-mapping.mir | 2 +-
.../RISCV/rvv/debug-info-rvv-dbg-value.mir | 4 +-
llvm/test/CodeGen/SPARC/mature-mc-support.ll | 8 +-
llvm/test/CodeGen/SPARC/missing-sret.ll | 2 +-
llvm/test/CodeGen/XCore/codemodel.ll | 12 +-
llvm/test/CodeGen/XCore/epilogue_prologue.ll | 4 +-
llvm/test/CodeGen/XCore/scavenging.ll | 2 +-
160 files changed, 460 insertions(+), 460 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
index d907560ff445187..ed525fb83c6de82 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
@@ -1,7 +1,7 @@
; RUN: llc -global-isel -mcpu=tahiti -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX678,GFX6789 %s
; RUN: llc -global-isel -mcpu=gfx900 -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9,GFX6789 %s
-; RUN: llc -global-isel -mcpu=gfx1010 -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10 %s
-; RUN: llc -global-isel -mcpu=gfx1100 -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10 %s
+; RUN: llc -global-isel -mcpu=gfx1010 -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10 %s
+; RUN: llc -global-isel -mcpu=gfx1100 -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10 %s
declare i64 @llvm.smax.i64(i64, i64)
declare i64 @llvm.smin.i64(i64, i64)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
index d20fd4ed067e18d..7afc2b9015c3c59 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GFX6 %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GFX6 %s
-# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GFX10 %s
-# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GFX10 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GFX10 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GFX10 %s
---
name: test_freeze_s1_vgpr_to_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd-with-ret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd-with-ret.ll
index ba9d5378c276733..9a66fe10ccdf34a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd-with-ret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd-with-ret.ll
@@ -1,5 +1,5 @@
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX90A %s
-; RUN: not --crash llc -global-isel < %s -march=amdgcn -mcpu=gfx908 -verify-machineinstrs 2>&1 | FileCheck %s -check-prefix=GFX908
+; RUN: not --crash llc -global-isel < %s -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs 2>&1 | FileCheck %s -check-prefix=GFX908
declare float @llvm.amdgcn.global.atomic.fadd.f32.p1.f32(ptr addrspace(1) nocapture, float)
declare <2 x half> @llvm.amdgcn.global.atomic.fadd.f32.p1.v2f16(ptr addrspace(1) nocapture, <2 x half>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
index 14e76bd39fc282d..d59c5a6a2609ce8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
@@ -1,5 +1,5 @@
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX90A %s
-; RUN: not --crash llc -global-isel < %s -march=amdgcn -mcpu=gfx908 -verify-machineinstrs 2>&1 | FileCheck %s -check-prefix=GFX908
+; RUN: not --crash llc -global-isel < %s -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs 2>&1 | FileCheck %s -check-prefix=GFX908
declare float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i32 immarg)
declare <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i32>, i32, i32, i32 immarg)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
index b535c683b7d6208..798a3ee1d75fd1e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
@@ -1,5 +1,5 @@
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX90A %s
-; RUN: not --crash llc -global-isel < %s -march=amdgcn -mcpu=gfx908 -verify-machineinstrs 2>&1 | FileCheck %s -check-prefix=GFX908
+; RUN: not --crash llc -global-isel < %s -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs 2>&1 | FileCheck %s -check-prefix=GFX908
declare float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float, ptr addrspace(8), i32, i32, i32 immarg)
declare <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half>, ptr addrspace(8), i32, i32, i32 immarg)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
index a85e82d74c8aec1..89daf3ae88cbc5a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
@@ -1,5 +1,5 @@
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX90A %s
-; RUN: not --crash llc -global-isel < %s -march=amdgcn -mcpu=gfx908 -verify-machineinstrs 2>&1 | FileCheck %s -check-prefix=GFX908
+; RUN: not --crash llc -global-isel < %s -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs 2>&1 | FileCheck %s -check-prefix=GFX908
; GFX908: LLVM ERROR: cannot select: %{{[0-9]+}}:vgpr_32(s32) = G_AMDGPU_BUFFER_ATOMIC_FADD %{{[0-9]+}}:vgpr, %{{[0-9]+}}:sgpr(<4 x s32>), %{{[0-9]+}}:vgpr(s32), %{{[0-9]+}}:vgpr, %{{[0-9]+}}:sgpr, 0, 0, -1 :: (volatile dereferenceable load store (s32), align 1, addrspace 8) (in function: buffer_atomic_add_f32_rtn)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
index daf1ca1599f768e..5b0b91f983fe643 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
@@ -1,5 +1,5 @@
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX90A %s
-; RUN: not --crash llc -global-isel < %s -march=amdgcn -mcpu=gfx908 -verify-machineinstrs 2>&1 | FileCheck %s -check-prefix=GFX908
+; RUN: not --crash llc -global-isel < %s -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs 2>&1 | FileCheck %s -check-prefix=GFX908
; GFX908: LLVM ERROR: cannot select: %{{[0-9]+}}:vgpr_32(s32) = G_AMDGPU_BUFFER_ATOMIC_FADD %{{[0-9]+}}:vgpr, %{{[0-9]+}}:sgpr(<4 x s32>), %{{[0-9]+}}:vgpr(s32), %{{[0-9]+}}:vgpr, %{{[0-9]+}}:sgpr, 0, 0, -1 :: (volatile dereferenceable load store (s32) on %ir.rsrc.load, align 1, addrspace 8) (in function: buffer_atomic_add_f32_rtn)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
index eeefae7318ad436..e60b391abd60cf1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
@@ -4,8 +4,8 @@
; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -global-isel -mtriple=amdgcn-- -mcpu=tonga -mattr=+flat-for-global -verify-machineinstrs | FileCheck --check-prefixes=ALL,MESA,UNPACKED %s
; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=+flat-for-global -mcpu=hawaii -verify-machineinstrs | FileCheck -check-prefixes=ALL,CO-V2,UNPACKED %s
; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=ALL,CO-V2,UNPACKED %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -global-isel -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a -verify-machineinstrs | FileCheck -check-prefixes=ALL,PACKED-TID %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -global-isel -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-vopd=0 | FileCheck -check-prefixes=ALL,PACKED-TID %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -global-isel -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a -verify-machineinstrs | FileCheck -check-prefixes=ALL,PACKED-TID %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -global-isel -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-vopd=0 | FileCheck -check-prefixes=ALL,PACKED-TID %s
declare i32 @llvm.amdgcn.workitem.id.x() #0
declare i32 @llvm.amdgcn.workitem.id.y() #0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
index 6ccfe95431cab82..d87bc1f01bdb85b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-regbankselect %s -o - | FileCheck %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=amdgpu-regbankselect %s -o - | FileCheck %s
-# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbankselect %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbankselect %s -o - | FileCheck %s
---
name: test_freeze_s1_vgpr_to_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
index 42fea4cd5a61c26..97f9c24fce4583a 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s
; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast:
; HSA: enable_sgpr_private_segment_buffer = 1
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
index c3ce12201dec0cd..a3f27ebddf9d6ff 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
@@ -1,9 +1,9 @@
-; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck --check-prefixes=GCN,GCN-PROMOTE %s
+; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -mtriple=amdgcn < %s | FileCheck --check-prefixes=GCN,GCN-PROMOTE %s
; RUN: llc -mattr=+promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck --check-prefixes=GCN,GCN-PROMOTE %s
-; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck --check-prefixes=GCN,GCN-ALLOCA %s
+; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -mtriple=amdgcn < %s | FileCheck --check-prefixes=GCN,GCN-ALLOCA %s
; RUN: llc -mattr=-promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri < %s | FileCheck --check-prefixes=GCN,GCN-ALLOCA %s
-; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCN,GCN-PROMOTE %s
-; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCN,GCN-ALLOCA %s
+; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCN,GCN-PROMOTE %s
+; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCN,GCN-ALLOCA %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll
index 365e1dbcdbb4aed..2feeb83e6f1467b 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -filetype=obj -o %t.o < %s && llvm-readobj -r %t.o | FileCheck --check-prefix=ELF %s
-; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel -mtriple=amdgcn--amdpal -mcpu=gfx900 -filetype=obj -o %t.o < %s && llvm-readobj -r %t.o | FileCheck --check-prefix=ELF %s
; GCN-LABEL: {{^}}ps_main:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll b/llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
index 452459a41fcff58..dd8eacb060e72dc 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
@@ -1,10 +1,10 @@
-; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -show-mc-encoding -mattr=+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -march=amdgcn | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s
+; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -show-mc-encoding -mattr=+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s
; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -show-mc-encoding -mattr=+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-PROMOTE %s
-; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -march=amdgcn | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC
+; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC
; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-ALLOCA %s
-; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -show-mc-encoding -mattr=+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s
-; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -show-mc-encoding -mattr=+promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE-VECT -check-prefix=SI -check-prefix=FUNC %s
-; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s
+; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -show-mc-encoding -mattr=+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -mtriple=amdgcn -mcpu=tonga -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s
+; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -show-mc-encoding -mattr=+promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -mtriple=amdgcn -mcpu=tonga -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE-VECT -check-prefix=SI -check-prefix=FUNC %s
+; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -mtriple=amdgcn -mcpu=tonga -mattr=-unaligned-access-mode | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s
; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | opt -S -mtriple=amdgcn-unknown-amdhsa -data-layout=A5 -mcpu=kaveri -passes=amdgpu-promote-alloca -disable-promote-alloca-to-vector | FileCheck -enable-var-scope -check-prefix=HSAOPT -check-prefix=OPT %s
; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | opt -S -mtriple=amdgcn-unknown-unknown -data-layout=A5 -mcpu=kaveri -passes=amdgpu-promote-alloca -disable-promote-alloca-to-vector | FileCheck -enable-var-scope -check-prefix=NOHSAOPT -check-prefix=OPT %s
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index 423274ace8bb6d8..0a81e98005b1adf 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s -check-prefixes=GCN
-; RUN: llc < %s -march=amdgcn -mcpu=hawaii -verify-machineinstrs | FileCheck %s -check-prefixes=GFX7
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefixes=GFX8
-; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck %s -check-prefixes=GFX9
-; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s -check-prefixes=GFX10
+; RUN: llc < %s -mtriple=amdgcn -verify-machineinstrs | FileCheck %s -check-prefixes=GCN
+; RUN: llc < %s -mtriple=amdgcn -mcpu=hawaii -verify-machineinstrs | FileCheck %s -check-prefixes=GFX7
+; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefixes=GFX8
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck %s -check-prefixes=GFX9
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s -check-prefixes=GFX10
; We only have storage-only BF16 support. We can load/store those values as we treat them as u16, but
; we don't support operations on them. As such, codegen is expected to fail for any operation other
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll b/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
index 5c7ece9015b9acc..f980707f4cbfc2e 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
+++ b/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 -simplifycfg-require-and-preserve-domtree=1 -amdgpu-long-branch-factor=0 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 -simplifycfg-require-and-preserve-domtree=1 -amdgpu-long-branch-factor=0 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; FIXME: We should use llvm-mc for this, but we can't even parse our own output.
; See PR33579.
-; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=4 -amdgpu-long-branch-factor=0 -o %t.o -filetype=obj -simplifycfg-require-and-preserve-domtree=1 %s
+; RUN: llc -mtriple=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=4 -amdgpu-long-branch-factor=0 -o %t.o -filetype=obj -simplifycfg-require-and-preserve-domtree=1 %s
; RUN: llvm-readobj -r %t.o | FileCheck --check-prefix=OBJ %s
; OBJ: Relocations [
diff --git a/llvm/test/CodeGen/AMDGPU/build_vector.ll b/llvm/test/CodeGen/AMDGPU/build_vector.ll
index 49bb75a7e990dce..f2283f6ae404190 100644
--- a/llvm/test/CodeGen/AMDGPU/build_vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/build_vector.ll
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefixes=R600,ALL
-; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefixes=GFX6,GFX678,ALL
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=GFX8,GFX678,ALL
+; RUN: llc < %s -mtriple=amdgcn -verify-machineinstrs | FileCheck %s --check-prefixes=GFX6,GFX678,ALL
+; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=GFX8,GFX678,ALL
; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX10,GFX1011,ALL
; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX11,GFX1011,ALL
diff --git a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
index 43d3c58aeb1d074..4e2b83af7f5e20b 100644
--- a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI %s
-; RUN: llc -march=amdgcn -mcpu=hawaii -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CI %s
-; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
-; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI %s
+; RUN: llc -mtriple=amdgcn -mcpu=hawaii -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=HSA %s
declare hidden void @external_void_func_i1(i1) #0
diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
index 14a81a2b24b8e14..c2c639b91db5c5e 100644
--- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
-; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11 %s
+; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11 %s
; Make sure we don't crash or assert on spir_kernel calling convention.
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll b/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
index 37f36547bc17c86..bc199a8e4d69000 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
+++ b/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs -mtriple=amdgcn-- -o - %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -verify-machineinstrs -mtriple=amdgcn-- -o - %s | FileCheck %s
declare float @llvm.fma.f32(float, float, float)
diff --git a/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll b/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
index d261c8849701dd3..7d808470ab583ff 100644
--- a/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
+++ b/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O0 -mtriple=amdgcn--amdhsa -march=amdgcn -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VMEM -check-prefix=GCN %s
-; RUN: llc -O0 -mtriple=amdgcn--amdhsa -march=amdgcn -amdgpu-spill-sgpr-to-vgpr=1 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VGPR -check-prefix=GCN %s
+; RUN: llc -O0 -mtriple=amdgcn--amdhsa -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VMEM -check-prefix=GCN %s
+; RUN: llc -O0 -mtriple=amdgcn--amdhsa -amdgpu-spill-sgpr-to-vgpr=1 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VGPR -check-prefix=GCN %s
; Verify registers used for tracking exec mask changes when all
; registers are spilled at the end of the block. The SGPR spill
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
index 62fdfdea6ad1b1d..79c4fa29dc3302d 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -stop-after=amdgpu-isel -verify-machineinstrs -O0 < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -stop-after=amdgpu-isel -verify-machineinstrs -O0 < %s | FileCheck -check-prefix=GCN %s
define i32 @divergent_lshr_and_cmp(i32 %x) {
; GCN-LABEL: name: divergent_lshr_and_cmp
diff --git a/llvm/test/CodeGen/AMDGPU/debug.ll b/llvm/test/CodeGen/AMDGPU/debug.ll
index 5620c70d44f1638..783b3ced30d7860 100644
--- a/llvm/test/CodeGen/AMDGPU/debug.ll
+++ b/llvm/test/CodeGen/AMDGPU/debug.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=verde -verify-machineinstrs -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI %s
; Test for a crash in the custom assembly dump code.
diff --git a/llvm/test/CodeGen/AMDGPU/ds_write2st64.ll b/llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
index ab2d4a9db603aef..26ccc32e1bf678d 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
+; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
@lds = addrspace(3) global [512 x float] undef, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
index 54b4e83e75a44c1..4c0d8ea243e7dc6 100644
--- a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
+++ b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
@@ -1,5 +1,5 @@
-; RUN: not llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tahiti -mattr=+promote-alloca -verify-machineinstrs < %s 2>&1 | FileCheck %s
-; RUN: not llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tahiti -mattr=-promote-alloca -verify-machineinstrs < %s 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tahiti -mattr=+promote-alloca -verify-machineinstrs < %s 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tahiti -mattr=-promote-alloca -verify-machineinstrs < %s 2>&1 | FileCheck %s
; RUN: not llc -march=r600 -mtriple=r600-- -mcpu=cypress < %s 2>&1 | FileCheck %s
target datalayout = "A5"
diff --git a/llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll b/llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
index c135e218a37d8e7..64f4ad5c72990d4 100644
--- a/llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
+++ b/llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
@@ -1,79 +1,79 @@
-; RUN: llc -filetype=obj -march=r600 -mcpu=r600 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,R600 %s
-; RUN: llc -filetype=obj -march=r600 -mcpu=r630 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,R630 %s
-; RUN: llc -filetype=obj -march=r600 -mcpu=rs880 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,RS880 %s
-; RUN: llc -filetype=obj -march=r600 -mcpu=rv670 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,RV670 %s
-; RUN: llc -filetype=obj -march=r600 -mcpu=rv710 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,RV710 %s
-; RUN: llc -filetype=obj -march=r600 -mcpu=rv730 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,RV730 %s
-; RUN: llc -filetype=obj -march=r600 -mcpu=rv770 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,RV770 %s
-; RUN: llc -filetype=obj -march=r600 -mcpu=cedar < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,CEDAR %s
-; RUN: llc -filetype=obj -march=r600 -mcpu=cypress < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,CYPRESS %s
-; RUN: llc -filetype=obj -march=r600 -mcpu=juniper < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,JUNIPER %s
-; RUN: llc -filetype=obj -march=r600 -mcpu=redwood < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,REDWOOD %s
-; RUN: llc -filetype=obj -march=r600 -mcpu=sumo < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,SUMO %s
-; RUN: llc -filetype=obj -march=r600 -mcpu=barts < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,BARTS %s
-; RUN: llc -filetype=obj -march=r600 -mcpu=caicos < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,CAICOS %s
-; RUN: llc -filetype=obj -march=r600 -mcpu=cayman < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,CAYMAN %s
-; RUN: llc -filetype=obj -march=r600 -mcpu=turks < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,TURKS %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx600 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX600 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=tahiti < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX600 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx601 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX601 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=pitcairn < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX601 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=verde < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX601 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx602 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX602 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=hainan < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX602 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=oland < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX602 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx700 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX700 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=kaveri < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX700 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx701 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX701 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=hawaii < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX701 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx702 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX702 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx703 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX703 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=kabini < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX703 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=mullins < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX703 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx704 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX704 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=bonaire < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX704 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx705 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX705 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx801 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX801 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=carrizo < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX801 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx802 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX802 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=iceland < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX802 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=tonga < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX802 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx803 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX803 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=fiji < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX803 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=polaris10 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX803 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=polaris11 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX803 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx805 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX805 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=tongapro < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX805 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx810 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX810 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=stoney < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX810 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx900 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX900 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx902 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX902 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx904 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX904 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX906 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx908 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX908 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx909 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX909 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx90a < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX90A %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx90c < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX90C %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx940 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX940 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx941 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX941 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx942 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX942 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1010 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1010 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1011 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1011 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1012 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1012 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1013 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1013 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1030 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1030 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1031 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1031 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1032 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1032 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1033 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1033 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1034 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1034 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1035 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1035 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1036 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1036 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1100 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1100 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1101 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1101 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1102 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1102 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1103 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1103 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1150 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1150 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1151 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1151 %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=r600 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,R600 %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=r630 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,R630 %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=rs880 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,RS880 %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=rv670 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,RV670 %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=rv710 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,RV710 %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=rv730 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,RV730 %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=rv770 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,RV770 %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=cedar < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,CEDAR %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=cypress < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,CYPRESS %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=juniper < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,JUNIPER %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=redwood < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,REDWOOD %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=sumo < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,SUMO %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=barts < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,BARTS %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=caicos < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,CAICOS %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=cayman < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,CAYMAN %s
+; RUN: llc -filetype=obj -mtriple=r600 -mcpu=turks < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-R600,TURKS %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx600 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX600 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=tahiti < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX600 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx601 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX601 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=pitcairn < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX601 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=verde < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX601 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx602 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX602 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=hainan < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX602 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=oland < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX602 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx700 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX700 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=kaveri < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX700 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx701 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX701 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=hawaii < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX701 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx702 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX702 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx703 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX703 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=kabini < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX703 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=mullins < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX703 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx704 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX704 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=bonaire < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX704 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx705 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX705 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx801 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX801 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=carrizo < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX801 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx802 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX802 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=iceland < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX802 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=tonga < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX802 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx803 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX803 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=fiji < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX803 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=polaris10 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX803 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=polaris11 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX803 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx805 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX805 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=tongapro < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX805 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx810 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX810 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=stoney < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX810 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx900 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX900 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx902 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX902 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx904 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX904 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx906 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX906 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx908 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX908 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx909 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX909 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx90a < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX90A %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx90c < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX90C %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx940 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX940 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx941 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX941 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx942 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX942 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1010 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1010 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1011 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1011 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1012 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1012 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1013 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1013 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1030 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1030 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1031 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1031 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1032 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1032 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1033 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1033 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1034 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1034 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1035 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1035 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1036 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1036 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1100 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1100 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1101 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1101 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1102 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1102 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1103 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1103 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1150 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1150 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1151 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1151 %s
; FIXME: With the default attributes the eflags are not accurate for
; xnack and sramecc. Subsequent Target-ID patches will address this.
diff --git a/llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll b/llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
index 62a08cf7ad19bd4..961b89ab28f6237 100644
--- a/llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
+++ b/llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
@@ -1,16 +1,16 @@
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=SRAM-ECC-GFX906 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 -mattr=-sramecc < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NO-SRAM-ECC-GFX906 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 -mattr=+sramecc < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=SRAM-ECC-GFX906 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 -mattr=+sramecc,+xnack < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=SRAM-ECC-XNACK-GFX906 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx906 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=SRAM-ECC-GFX906 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx906 -mattr=-sramecc < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NO-SRAM-ECC-GFX906 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx906 -mattr=+sramecc < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=SRAM-ECC-GFX906 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx906 -mattr=+sramecc,+xnack < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=SRAM-ECC-XNACK-GFX906 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx908 < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX908 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx908 -mattr=+sramecc < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX908 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx908 < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX908 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx908 -mattr=+sramecc < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX908 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx90a < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX90A %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx90a < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX90A %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx90a < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX90A %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx90a < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX90A %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx940 < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX940 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx940 -mattr=+sramecc < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX940 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx940 < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX940 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx940 -mattr=+sramecc < %s | llvm-readobj --file-header - | FileCheck --check-prefix=SRAM-ECC-GFX940 %s
; NO-SRAM-ECC-GFX906: Flags [
; NO-SRAM-ECC-GFX906-NEXT: EF_AMDGPU_FEATURE_XNACK_V3 (0x100)
diff --git a/llvm/test/CodeGen/AMDGPU/elf-header-flags-xnack.ll b/llvm/test/CodeGen/AMDGPU/elf-header-flags-xnack.ll
index 22dcaf971c48375..98aae6d603edacd 100644
--- a/llvm/test/CodeGen/AMDGPU/elf-header-flags-xnack.ll
+++ b/llvm/test/CodeGen/AMDGPU/elf-header-flags-xnack.ll
@@ -1,7 +1,7 @@
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=XNACK-GFX801 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx801 -mattr=+xnack < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=XNACK-GFX801 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx802 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NO-XNACK-GFX802 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx802 -mattr=-xnack < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NO-XNACK-GFX802 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=XNACK-GFX801 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx801 -mattr=+xnack < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=XNACK-GFX801 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx802 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NO-XNACK-GFX802 %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx802 -mattr=-xnack < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NO-XNACK-GFX802 %s
; XNACK-GFX801: Flags [
; XNACK-GFX801-NEXT: EF_AMDGPU_FEATURE_XNACK_V3 (0x100)
diff --git a/llvm/test/CodeGen/AMDGPU/elf-header-osabi.ll b/llvm/test/CodeGen/AMDGPU/elf-header-osabi.ll
index 1cbde24c96a8b66..e5de7859dab6f94 100644
--- a/llvm/test/CodeGen/AMDGPU/elf-header-osabi.ll
+++ b/llvm/test/CodeGen/AMDGPU/elf-header-osabi.ll
@@ -1,4 +1,4 @@
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NONE %s
+; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NONE %s
; RUN: llc -filetype=obj -mtriple=amdgcn-amd- -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NONE %s
; RUN: llc -filetype=obj -mtriple=amdgcn-amd-unknown -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NONE %s
; RUN: llc -filetype=obj -mtriple=amdgcn--amdhsa -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=HSA %s
diff --git a/llvm/test/CodeGen/AMDGPU/elf.ll b/llvm/test/CodeGen/AMDGPU/elf.ll
index be49e273ad9fbe3..f51d9fc5125ba68 100644
--- a/llvm/test/CodeGen/AMDGPU/elf.ll
+++ b/llvm/test/CodeGen/AMDGPU/elf.ll
@@ -1,9 +1,9 @@
-; RUN: llc < %s -march=amdgcn -verify-machineinstrs -filetype=obj | llvm-readobj -S --symbols --file-headers - | FileCheck --check-prefix=ELF %s
-; RUN: llc < %s -march=amdgcn -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -filetype=obj | llvm-readobj -S --symbols --file-headers - | FileCheck --check-prefix=ELF %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TONGA %s
-; RUN: llc < %s -march=amdgcn -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs -filetype=obj | llvm-readobj -S --symbols --file-headers - | FileCheck --check-prefix=ELF %s
-; RUN: llc < %s -march=amdgcn -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s
+; RUN: llc < %s -mtriple=amdgcn -verify-machineinstrs -filetype=obj | llvm-readobj -S --symbols --file-headers - | FileCheck --check-prefix=ELF %s
+; RUN: llc < %s -mtriple=amdgcn -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -filetype=obj | llvm-readobj -S --symbols --file-headers - | FileCheck --check-prefix=ELF %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TONGA %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs -filetype=obj | llvm-readobj -S --symbols --file-headers - | FileCheck --check-prefix=ELF %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG --check-prefix=TYPICAL %s
; Test that we don't try to produce a COFF file on windows
; RUN: llc < %s -mtriple=amdgcn-pc-mingw -verify-machineinstrs -filetype=obj | llvm-readobj -S --symbols --file-headers - | FileCheck --check-prefix=ELF %s
diff --git a/llvm/test/CodeGen/AMDGPU/elf.metadata.ll b/llvm/test/CodeGen/AMDGPU/elf.metadata.ll
index ff082c1419573c0..4a5d597c58838a9 100644
--- a/llvm/test/CodeGen/AMDGPU/elf.metadata.ll
+++ b/llvm/test/CodeGen/AMDGPU/elf.metadata.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=amdgcn -mcpu=fiji -filetype=obj | llvm-readobj --symbols -S --sd - | FileCheck %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=fiji -filetype=obj | llvm-readobj --symbols -S --sd - | FileCheck %s
; CHECK: Section {
; CHECK: Name: .AMDGPU.comment.info_1
diff --git a/llvm/test/CodeGen/AMDGPU/elf.r600.ll b/llvm/test/CodeGen/AMDGPU/elf.r600.ll
index 503d518d1ef82d3..8da573170f3834e 100644
--- a/llvm/test/CodeGen/AMDGPU/elf.r600.ll
+++ b/llvm/test/CodeGen/AMDGPU/elf.r600.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood -filetype=obj | llvm-readobj -S - | FileCheck --check-prefix=ELF %s
-; RUN: llc < %s -march=r600 -mcpu=redwood -o - | FileCheck --check-prefix=CONFIG %s
+; RUN: llc < %s -mtriple=r600 -mcpu=redwood -filetype=obj | llvm-readobj -S - | FileCheck --check-prefix=ELF %s
+; RUN: llc < %s -mtriple=r600 -mcpu=redwood -o - | FileCheck --check-prefix=CONFIG %s
; ELF: Format: elf32-amdgpu
; ELF: Name: .AMDGPU.config
diff --git a/llvm/test/CodeGen/AMDGPU/extload-align.ll b/llvm/test/CodeGen/AMDGPU/extload-align.ll
index 2777bdcd2cc4c5d..d0bdfa8c8f8c70d 100644
--- a/llvm/test/CodeGen/AMDGPU/extload-align.ll
+++ b/llvm/test/CodeGen/AMDGPU/extload-align.ll
@@ -1,4 +1,4 @@
-; RUN: llc -debug-only=machine-scheduler -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs %s -o - 2>&1| FileCheck -check-prefix=DEBUG %s
+; RUN: llc -debug-only=machine-scheduler -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs %s -o - 2>&1| FileCheck -check-prefix=DEBUG %s
target datalayout = "A5"
; REQUIRES: asserts
diff --git a/llvm/test/CodeGen/AMDGPU/extload.ll b/llvm/test/CodeGen/AMDGPU/extload.ll
index 79de37db22a3f5d..34764bda2e1313d 100644
--- a/llvm/test/CodeGen/AMDGPU/extload.ll
+++ b/llvm/test/CodeGen/AMDGPU/extload.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
+; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=EG,FUNC %s
; FIXME: This seems to not ever actually become an extload
diff --git a/llvm/test/CodeGen/AMDGPU/extract-lowbits.ll b/llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
index 930216a95135602..8d28d2df6a6b7e2 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; Loosely based on test/CodeGen/{X86,AArch64}/extract-lowbits.ll,
; but with all 64-bit tests, and tests with loads dropped.
diff --git a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
index 7c469c9f4ccae45..db5fd5efb04442e 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs -o - %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx1100 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs -o - %s | FileCheck -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx1100 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX11 %s
define <4 x i16> @vec_8xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1) %p1) {
; SI-LABEL: vec_8xi16_extract_4xi16:
diff --git a/llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll b/llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
index 23c96373dcb052a..23cd7d4d02d879d 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck %s
; Test for ICE in SelectionDAG::computeKnownBits when visiting EXTRACT_SUBVECTOR
; with DemandedElts already as wide as the source vector.
diff --git a/llvm/test/CodeGen/AMDGPU/extract-subvector.ll b/llvm/test/CodeGen/AMDGPU/extract-subvector.ll
index 3a1c9f1f00687d6..ee9a8902cac3a47 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-subvector.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-subvector.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: extract_2xi16
; GCN: buffer_load_ushort
diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
index 16496336f7bcfd8..b60fc2bb2da3a0d 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
define amdgpu_kernel void @extract_vector_elt_v2f16(ptr addrspace(1) %out, ptr addrspace(4) %vec.ptr) #0 {
; SI-LABEL: extract_vector_elt_v2f16:
diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll
index 5002929ec6d13d3..a3e7b06ea117e52 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; GCN-LABEL: {{^}}extract_vector_elt_v3f64_2:
; GCN: buffer_load_dwordx4
diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
index 2d520825b4d1a6d..747e8ca5114f0a1 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,SIVI %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX89,SIVI %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX89 %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,SIVI %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX89,SIVI %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX89 %s
; GCN-LABEL: {{^}}extract_vector_elt_v2i16:
; GCN: s_load_dword [[VEC:s[0-9]+]]
diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll
index 564b57544092fd0..d41ab264495ad14 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; How the replacement of i64 stores with v2i32 stores resulted in
; breaking other users of the bitcast if they already existed
diff --git a/llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll b/llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
index 0e9d05440e8eafd..b09b08cde6c3516 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
+++ b/llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn--amdpal -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn--amdpal -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; NOTE: llvm.amdgcn.wwm is deprecated, use llvm.amdgcn.strict.wwm instead.
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
index 7a2bed327db0574..e29183568134455 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -march=amdgcn -mcpu=gfx1010 -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10 %s
-; RUN: llc -mtriple=amdgcn -march=amdgcn -mcpu=gfx1100 -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn -mcpu=gfx1010 -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10 %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn -mcpu=gfx1100 -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11 %s
; vgpr offset
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
index be4b1277b360f63..6ce8d6f0c53475d 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
@@ -1,26 +1,26 @@
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs | FileCheck -check-prefix=CI -check-prefix=GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mcpu=fiji -mattr=-xnack -verify-machineinstrs | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mcpu=kaveri -verify-machineinstrs | FileCheck -check-prefix=CI -check-prefix=GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mcpu=fiji -mattr=-xnack -verify-machineinstrs | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mcpu=carrizo -mattr=-xnack -verify-machineinstrs | FileCheck -check-prefixes=VI-NOXNACK,GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mcpu=stoney -mattr=-xnack -verify-machineinstrs | FileCheck -check-prefixes=VI-NOXNACK,GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mcpu=carrizo -mattr=-xnack -verify-machineinstrs | FileCheck -check-prefixes=VI-NOXNACK,GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mcpu=stoney -mattr=-xnack -verify-machineinstrs | FileCheck -check-prefixes=VI-NOXNACK,GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mcpu=carrizo -mattr=+xnack -verify-machineinstrs | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mcpu=stoney -mattr=+xnack -verify-machineinstrs | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mcpu=carrizo -mattr=+xnack -verify-machineinstrs | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mcpu=stoney -mattr=+xnack -verify-machineinstrs | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs | FileCheck -check-prefixes=CI,HSA-CI-V2,GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=+xnack -verify-machineinstrs | FileCheck -check-prefixes=VI-XNACK,HSA-VI-XNACK-V2,GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs | FileCheck -check-prefixes=CI,HSA-CI-V2,GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=+xnack -verify-machineinstrs | FileCheck -check-prefixes=VI-XNACK,HSA-VI-XNACK-V2,GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs | FileCheck -check-prefixes=GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-xnack -verify-machineinstrs | FileCheck -check-prefixes=VI-NOXNACK,HSA-VI-NOXNACK,GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=+xnack -verify-machineinstrs | FileCheck -check-prefixes=VI-XNACK,HSA-VI-XNACK,GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs | FileCheck -check-prefixes=GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-xnack -verify-machineinstrs | FileCheck -check-prefixes=VI-NOXNACK,HSA-VI-NOXNACK,GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=+xnack -verify-machineinstrs | FileCheck -check-prefixes=VI-XNACK,HSA-VI-XNACK,GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=+architected-flat-scratch -verify-machineinstrs | FileCheck -check-prefixes=GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=+architected-flat-scratch,-xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-NOXNACK,GFX9-ARCH-FLAT,GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=+architected-flat-scratch,+xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-XNACK,GFX9-ARCH-FLAT,GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=+architected-flat-scratch -verify-machineinstrs | FileCheck -check-prefixes=GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=+architected-flat-scratch,-xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-NOXNACK,GFX9-ARCH-FLAT,GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=+architected-flat-scratch,+xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-XNACK,GFX9-ARCH-FLAT,GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+architected-flat-scratch -verify-machineinstrs | FileCheck -check-prefixes=GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+architected-flat-scratch,-xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-NOXNACK,GFX10-ARCH-FLAT,GCN %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+architected-flat-scratch,+xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-XNACK,GFX10-ARCH-FLAT,GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+architected-flat-scratch -verify-machineinstrs | FileCheck -check-prefixes=GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+architected-flat-scratch,-xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-NOXNACK,GFX10-ARCH-FLAT,GCN %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+architected-flat-scratch,+xnack -verify-machineinstrs | FileCheck -check-prefixes=HSA-VI-XNACK,GFX10-ARCH-FLAT,GCN %s
; GCN-LABEL: {{^}}no_vcc_no_flat:
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
index 1592936f2c4f43e..07b3df2a8520aae 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9 %s
-; RUN: llc -march=amdgcn -mcpu=gfx1030 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
-; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX11 %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9-PAL %s
-; RUN: llc -march=amdgcn -mcpu=gfx940 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX940 %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-PAL,GFX1010-PAL %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1030 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-PAL,GFX1030-PAL %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1100 -mattr=-promote-alloca -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11-PAL %s
diff --git a/llvm/test/CodeGen/AMDGPU/fneg.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg.f16.ll
index bfb79424fc4d49f..2a5a1c1913362bb 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg.f16.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=kaveri -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIVI,CI %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIVI,GFX8 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1100 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=kaveri -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIVI,CI %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIVI,GFX8 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
; FIXME: Should be able to do scalar op
define amdgpu_kernel void @s_fneg_f16(ptr addrspace(1) %out, half %in) #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/function-returns.ll b/llvm/test/CodeGen/AMDGPU/function-returns.ll
index c8406914259a159..0f0ee0fcba0e499 100644
--- a/llvm/test/CodeGen/AMDGPU/function-returns.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-returns.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX789,CI %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX789,GFX89,GFX8 %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX789,GFX89,GFX9 %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX789,CI %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX789,GFX89,GFX8 %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX789,GFX89,GFX9 %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
define i1 @i1_func_void() #0 {
; GFX789-LABEL: i1_func_void:
diff --git a/llvm/test/CodeGen/AMDGPU/gfx902-without-xnack.ll b/llvm/test/CodeGen/AMDGPU/gfx902-without-xnack.ll
index 64f2efe02005833..3e0faef71feb6fb 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx902-without-xnack.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx902-without-xnack.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx902 -mattr=-xnack < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx902 -mattr=-xnack < %s | FileCheck %s
; CHECK: .hsa_code_object_isa 9,0,2,"AMD","AMDGPU"
define amdgpu_kernel void @test_kernel(ptr addrspace(1) %out0, ptr addrspace(1) %out1) nounwind {
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll b/llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
index 3be1282fb91eebf..53fcc078b5a4a22 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=amdgcn -mcpu=gfx803 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
-; RUN: llc -march=amdgcn -mcpu=gfx803 -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx803 -d - | FileCheck -check-prefix=DISASSEMBLY-VI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx803 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx803 -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx803 -d - | FileCheck -check-prefix=DISASSEMBLY-VI %s
; Make sure we can encode and don't fail on functions which have
; instructions not actually supported by the subtarget.
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-default-device.ll b/llvm/test/CodeGen/AMDGPU/hsa-default-device.ll
index 46375714fb9ab58..198033ea458811d 100644
--- a/llvm/test/CodeGen/AMDGPU/hsa-default-device.ll
+++ b/llvm/test/CodeGen/AMDGPU/hsa-default-device.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
; Make sure that with an HSA triple, we don't default to an
; unsupported device.
diff --git a/llvm/test/CodeGen/AMDGPU/imm16.ll b/llvm/test/CodeGen/AMDGPU/imm16.ll
index be39feb30bc1ba9..dcc615232e56bed 100644
--- a/llvm/test/CodeGen/AMDGPU/imm16.ll
+++ b/llvm/test/CodeGen/AMDGPU/imm16.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-flat-for-global -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -mattr=-flat-for-global -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX11 %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -mattr=-flat-for-global -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI %s
-; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; FIXME: Merge into imm.ll
diff --git a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
index 760601d3c70e683..3cdf238ddd4b57f 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GFX11
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GFX11
declare i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/kernel-args.ll b/llvm/test/CodeGen/AMDGPU/kernel-args.ll
index 812a1c2486872d1..d37819ac69412c5 100644
--- a/llvm/test/CodeGen/AMDGPU/kernel-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/kernel-args.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck -check-prefixes=SI %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=VI %s
+; RUN: llc < %s -mtriple=amdgcn -verify-machineinstrs | FileCheck -check-prefixes=SI %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=VI %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=GFX9 %s
; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck -check-prefixes=EGCM,EG %s
; RUN: llc < %s -march=r600 -mcpu=cayman -verify-machineinstrs | FileCheck -check-prefixes=EGCM,CM %s
diff --git a/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll b/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
index 65c2ecbfa946299..a14e996156237d9 100644
--- a/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
+++ b/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
@@ -1,10 +1,10 @@
-; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck --check-prefixes=GCN,CI,ALL %s
-; RUN: llc -march=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck --check-prefixes=GCN,VI,ALL %s
-; RUN: llc -march=amdgcn -mcpu=gfx900 --show-mc-encoding < %s | FileCheck --check-prefixes=GCN,GFX9,ALL %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCNHSA,ALL %s
-; RUN: llc -march=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCNHSA,ALL %s
-; RUN: llc -march=amdgcn -mcpu=gfx1010 -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCNHSA,ALL %s
-; RUN: llc -march=amdgcn -mcpu=gfx1100 -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global,-architected-flat-scratch,-user-sgpr-init16-bug < %s | FileCheck --check-prefixes=GCNHSA,ALL %s
+; RUN: llc -mtriple=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck --check-prefixes=GCN,CI,ALL %s
+; RUN: llc -mtriple=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck --check-prefixes=GCN,VI,ALL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 --show-mc-encoding < %s | FileCheck --check-prefixes=GCN,GFX9,ALL %s
+; RUN: llc -mtriple=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCNHSA,ALL %s
+; RUN: llc -mtriple=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCNHSA,ALL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCNHSA,ALL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global,-architected-flat-scratch,-user-sgpr-init16-bug < %s | FileCheck --check-prefixes=GCNHSA,ALL %s
; FIXME: align on alloca seems to be ignored for private_segment_alignment
diff --git a/llvm/test/CodeGen/AMDGPU/lds-alignment.ll b/llvm/test/CodeGen/AMDGPU/lds-alignment.ll
index f29ccd0e1be5a8b..dde15c15882c56d 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-alignment.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-alignment.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefix=HSA %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefix=HSA %s
@lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
@lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
index 63c2a117f668bca..da4950f7b612c7e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,NOHSA %s
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,NOHSA %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,HSA %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,HSA %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,NOHSA %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,NOHSA %s
; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,HSA %s
; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,HSA %s
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll
index def43948cbc9001..52bdfbd62680f3f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
index bafafa33016fac0..6e2bb00925f7145 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march amdgcn %s -filetype=obj -o /dev/null
-; RUN: llc -march amdgcn <%s | FileCheck %s
+; RUN: llc -mtriple=amdgcn %s -filetype=obj -o /dev/null
+; RUN: llc -mtriple=amdgcn < %s | FileCheck %s
define amdgpu_kernel void @f() {
; CHECK: ; divergent unreachable
call void @llvm.amdgcn.unreachable()
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
index 70bb18e4d6e31d2..eaa24fea63e63df 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
@@ -1,7 +1,7 @@
-; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -verify-machineinstrs | FileCheck --check-prefixes=ALL,CO-V2 %s
-; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=carrizo -verify-machineinstrs | FileCheck --check-prefixes=ALL,CO-V2 %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck --check-prefixes=ALL,UNKNOWN-OS %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefixes=ALL,UNKNOWN-OS %s
+; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -verify-machineinstrs | FileCheck --check-prefixes=ALL,CO-V2 %s
+; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=carrizo -verify-machineinstrs | FileCheck --check-prefixes=ALL,CO-V2 %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck --check-prefixes=ALL,UNKNOWN-OS %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefixes=ALL,UNKNOWN-OS %s
; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn-unknown-mesa3d -mcpu=tahiti -verify-machineinstrs | FileCheck -check-prefixes=ALL,CO-V2 %s
; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn-unknown-mesa3d -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=ALL,CO-V2 %s
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
index 28251e4b66e1b41..3fa7e35cd11f0ef 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
@@ -1,11 +1,11 @@
-; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -verify-machineinstrs | FileCheck --check-prefixes=ALL,CO-V2,UNPACKED %s
-; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefixes=ALL,CO-V2,UNPACKED %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs | FileCheck --check-prefixes=ALL,MESA,UNPACKED %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefixes=ALL,MESA,UNPACKED %s
+; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -verify-machineinstrs | FileCheck --check-prefixes=ALL,CO-V2,UNPACKED %s
+; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefixes=ALL,CO-V2,UNPACKED %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mcpu=hawaii -verify-machineinstrs | FileCheck --check-prefixes=ALL,MESA,UNPACKED %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck --check-prefixes=ALL,MESA,UNPACKED %s
; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn-unknown-mesa3d -mcpu=hawaii -verify-machineinstrs | FileCheck -check-prefixes=ALL,CO-V2,UNPACKED %s
; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn-unknown-mesa3d -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck -check-prefixes=ALL,CO-V2,UNPACKED %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a -verify-machineinstrs | FileCheck -check-prefixes=ALL,PACKED-TID %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-vopd=0 | FileCheck -check-prefixes=ALL,PACKED-TID %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a -verify-machineinstrs | FileCheck -check-prefixes=ALL,PACKED-TID %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-vopd=0 | FileCheck -check-prefixes=ALL,PACKED-TID %s
declare i32 @llvm.amdgcn.workitem.id.x() #0
declare i32 @llvm.amdgcn.workitem.id.y() #0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
index e6747c6dd35032e..955e3fb0f39fc99 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOOPT %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,OPT %s
+; RUN: llc -O0 -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOOPT %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,OPT %s
; GCN-LABEL: {{^}}test_debug_value:
; NOOPT: .loc 1 1 42 prologue_end ; /tmp/test_debug_value.cl:1:42
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-f64.ll b/llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
index 9382f1eb4f15aba..09ef53f33030800 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6-NOHSA %s
+; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6-NOHSA %s
; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GFX7-HSA %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8-NOHSA %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8-NOHSA %s
; FUNC-LABEL: {{^}}constant_load_f64:
define amdgpu_kernel void @constant_load_f64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
index 7f946e1d592c4e9..9af908d74c7d4c0 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6 %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
define amdgpu_kernel void @constant_load_i1(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
index ab80e45162ffff2..7d9845970491800 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-NOHSA-SI %s
+; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-NOHSA-SI %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-HSA %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-NOHSA-VI %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-NOHSA-VI %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck --check-prefix=EG %s
define amdgpu_kernel void @constant_load_i16(ptr addrspace(1) %out, ptr addrspace(4) %in) {
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
index 6de7af87c5cc622..d2ea7a95473e03a 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6-NOHSA %s
+; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6-NOHSA %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GFX7-HSA %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8-NOHSA %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8-NOHSA %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9-HSA %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9-HSA %s
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i64.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
index 1a1e8c7f77fbc01..17061e41b5bb674 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=GFX6 %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck --check-prefix=GFX7 %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG %s
define amdgpu_kernel void @constant_load_i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
index 6ecb070eebe28ef..7c3a5db46a8d8bf 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6-NOHSA %s
+; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6-NOHSA %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GFX7-HSA %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8-NOHSA %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8-NOHSA %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s
; TODO: NOT AND
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-f32.ll b/llvm/test/CodeGen/AMDGPU/load-global-f32.ll
index 35b4059952527c9..01800b3cbcf6c01 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-f32.ll
@@ -1,6 +1,6 @@
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-NOHSA,FUNC,SI-NOHSA %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-NOHSA,FUNC,SI-NOHSA %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-HSA,FUNC,GCNX3-HSA %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-NOHSA,FUNC,GCNX3-NOHSA %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-NOHSA,FUNC,GCNX3-NOHSA %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=R600,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cayman < %s | FileCheck --check-prefixes=R600,FUNC %s
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-f64.ll b/llvm/test/CodeGen/AMDGPU/load-global-f64.ll
index 55646206622f147..ed3618dfd64745e 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-f64.ll
@@ -1,6 +1,6 @@
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-NOHSA,FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-NOHSA,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-HSA,FUNC %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-NOHSA,FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-NOHSA,FUNC %s
; FUNC-LABEL: {{^}}global_load_f64:
; GCN-NOHSA: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i1.ll b/llvm/test/CodeGen/AMDGPU/load-global-i1.ll
index f36d55ec3fdc249..3aa159c8d484383 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i1.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}global_load_i1:
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
index f957e0368c426a4..11c8fb2422ed08d 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=GCN-NOHSA-SI %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=GCN-NOHSA-SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=GCN-HSA %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=GCN-NOHSA-VI %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=GCN-NOHSA-VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=EG %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=CM %s
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i32.ll b/llvm/test/CodeGen/AMDGPU/load-global-i32.ll
index f99bd4cb15c6436..c4d9b4b2bb5ebbb 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i32.ll
@@ -1,6 +1,6 @@
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=SI-NOHSA -check-prefix=FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=SI-NOHSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=GCNX3-HSA -check-prefix=FUNC %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=GCNX3-NOHSA -check-prefix=FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=GCNX3-NOHSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i64.ll b/llvm/test/CodeGen/AMDGPU/load-global-i64.ll
index 87ac70639370a93..1305d5106e93eed 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i64.ll
@@ -1,6 +1,6 @@
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-NOHSA,FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-NOHSA,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-HSA,FUNC %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-NOHSA,FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN-NOHSA,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=EG,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cayman < %s | FileCheck --check-prefixes=EG,FUNC %s
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
index 1013168ca450fe6..9efa8b5e8ce8aa3 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
@@ -1,6 +1,6 @@
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GCN-NOHSA,SI,FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GCN-NOHSA,SI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GCN-HSA,SI,FUNC %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GCN-NOHSA,VI,FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GCN-NOHSA,VI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s
diff --git a/llvm/test/CodeGen/AMDGPU/load-local-f64.ll b/llvm/test/CodeGen/AMDGPU/load-local-f64.ll
index 136289ea74e3390..2ad372b6714c51c 100644
--- a/llvm/test/CodeGen/AMDGPU/load-local-f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-local-f64.ll
@@ -1,12 +1,12 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
+; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefixes=EG,FUNC %s
; Testing for ds_read_b128
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
; FUNC-LABEL: {{^}}local_load_f64:
; SICIV: s_mov_b32 m0
diff --git a/llvm/test/CodeGen/AMDGPU/load-local-i1.ll b/llvm/test/CodeGen/AMDGPU/load-local-i1.ll
index 31cf71a44b5cc00..0d7b60f1d085bde 100644
--- a/llvm/test/CodeGen/AMDGPU/load-local-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-local-i1.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefixes=EG,FUNC %s
; FUNC-LABEL: {{^}}local_load_i1:
diff --git a/llvm/test/CodeGen/AMDGPU/load-local-i64.ll b/llvm/test/CodeGen/AMDGPU/load-local-i64.ll
index e6d5ba9de63989f..d7d03da549b34a1 100644
--- a/llvm/test/CodeGen/AMDGPU/load-local-i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-local-i64.ll
@@ -1,12 +1,12 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
+; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefixes=EG,FUNC %s
; Testing for ds_read/write_b128
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
; FUNC-LABEL: {{^}}local_load_i64:
; SICIVI: s_mov_b32 m0
diff --git a/llvm/test/CodeGen/AMDGPU/load-local-i8.ll b/llvm/test/CodeGen/AMDGPU/load-local-i8.ll
index 54fef9184fe7098..3eaffa8facdf5ac 100644
--- a/llvm/test/CodeGen/AMDGPU/load-local-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-local-i8.ll
@@ -1,11 +1,11 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,SI,SICIVI,FUNC %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,VI,SICIVI,FUNC %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GFX9,FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,SI,SICIVI,FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,VI,SICIVI,FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GFX9,FUNC %s
; RUN: llc -march=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s
; Testing for ds_read/write_b128
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+enable-ds128 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=CIVI,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+enable-ds128 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=CIVI,FUNC %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=+enable-ds128 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=CIVI,FUNC %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+enable-ds128 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=CIVI,FUNC %s
; FUNC-LABEL: {{^}}local_load_i8:
; GCN-NOT: s_wqm_b64
diff --git a/llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll b/llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll
index df31ab06d277e6c..1d9ddc58a44768b 100644
--- a/llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll
@@ -1,6 +1,6 @@
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=SI-NOHSA,SI,FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=SI-NOHSA,SI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck --check-prefixes=FUNC,CI-HSA,SI %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=SI-NOHSA,SI,FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=SI-NOHSA,SI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=FUNC %s
diff --git a/llvm/test/CodeGen/AMDGPU/loop-prefetch.ll b/llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
index 1227f83baabe73c..028758b99ca7f4a 100644
--- a/llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
+++ b/llvm/test/CodeGen/AMDGPU/loop-prefetch.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs -asm-verbose=0 < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10-ASM %s
-; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s -filetype=obj | llvm-objdump -d --arch-name=amdgcn --mcpu=gfx1030 --symbolize-operands - | FileCheck --check-prefixes=GCN,GFX10,GFX10-DIS %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs -asm-verbose=0 < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10-ASM %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s -filetype=obj | llvm-objdump -d --arch-name=amdgcn --mcpu=gfx1030 --symbolize-operands - | FileCheck --check-prefixes=GCN,GFX10,GFX10-DIS %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s
; GFX8-NOT: s_inst_prefetch
; GFX8-NOT: .palign 6
diff --git a/llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll b/llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll
index 727899eb5387d0e..b7919fe30021ddf 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-unknown < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-unknown-unknown < %s | FileCheck %s
; and can be eliminated
; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range:
diff --git a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
index e023e1b7a0bee20..e557e0ce9b1be5e 100644
--- a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
+++ b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,GFX9 %s
-; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,GFX10 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX9 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX10 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,GFX9 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX10 %s
; Test case looks at the allocated offset of @used_by_both. It's at zero when
; allocated by itself, but at 8 when allocated in combination with the double.
diff --git a/llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll b/llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
index e1cd951cfb5cb6a..ac58a13f476b429 100644
--- a/llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=amdgcn -mcpu=kaveri -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mcpu=kaveri -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s
; Check that when mubuf addr64 instruction is handled in moveToVALU
; from the pointer, dead register writes are not emitted.
diff --git a/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll b/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
index a50de61963fda05..8a72c966f6b3410 100644
--- a/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
+++ b/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
@@ -1,4 +1,4 @@
-; RUN: not llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s 2>&1 | FileCheck %s
; CHECK: in function pixel_s{{.*}}: unsupported non-compute shaders with HSA
define amdgpu_ps void @pixel_shader() #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll b/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
index f8958cfa5f48e24..2b7c51a7d198e0a 100644
--- a/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
+++ b/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
@@ -1,5 +1,5 @@
; XFAIL: *
-; RUN: llc < %s -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs | FileCheck -check-prefixes=CHECK,GCN %s
+; RUN: llc < %s -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs | FileCheck -check-prefixes=CHECK,GCN %s
; RUN: llc < %s -march=r600 -mtriple=r600-- -verify-machineinstrs | FileCheck -check-prefixes=CHECK,R600 %s
; This is a temporary xfail, as the assembly printer is broken when dealing with
diff --git a/llvm/test/CodeGen/AMDGPU/nullptr.ll b/llvm/test/CodeGen/AMDGPU/nullptr.ll
index 6bbfdc6363be969..3d1096c86b3b78b 100644
--- a/llvm/test/CodeGen/AMDGPU/nullptr.ll
+++ b/llvm/test/CodeGen/AMDGPU/nullptr.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs | FileCheck -check-prefixes=CHECK,GCN %s
+;RUN: llc < %s -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs | FileCheck -check-prefixes=CHECK,GCN %s
;RUN: llc < %s -march=r600 -mtriple=r600-- -verify-machineinstrs | FileCheck -check-prefixes=CHECK,R600 %s
%struct.S = type { ptr addrspace(5), ptr addrspace(1), ptr addrspace(4), ptr addrspace(3), ptr, ptr addrspace(2)}
diff --git a/llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll b/llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
index ee09680c1fdbb1d..031a46271f2c0ed 100644
--- a/llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
+++ b/llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=amdgcn -mcpu=gfx1030 -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx1030 -d - | FileCheck -check-prefix=OBJ %s
-; RUN: llc -march=amdgcn -mcpu=gfx1030 -show-mc-encoding < %s | FileCheck -check-prefix=ASM %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -filetype=obj < %s | llvm-objdump --triple=amdgcn--amdhsa --mcpu=gfx1030 -d - | FileCheck -check-prefix=OBJ %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -show-mc-encoding < %s | FileCheck -check-prefix=ASM %s
declare i32 @llvm.amdgcn.permlane16(i32, i32, i32, i32, i1, i1)
diff --git a/llvm/test/CodeGen/AMDGPU/private-element-size.ll b/llvm/test/CodeGen/AMDGPU/private-element-size.ll
index fa83ed9df705e5c..9cb7f1b4b8fc8a4 100644
--- a/llvm/test/CodeGen/AMDGPU/private-element-size.ll
+++ b/llvm/test/CodeGen/AMDGPU/private-element-size.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefixes=HSA-ELT16,ALL %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-8 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefixes=HSA-ELT8,ALL,HSA-ELTGE8 %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefixes=HSA-ELT4,ALL %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefixes=HSA-ELT16,ALL %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-8 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefixes=HSA-ELT8,ALL,HSA-ELTGE8 %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefixes=HSA-ELT4,ALL %s
; ALL-LABEL: {{^}}private_elt_size_v4i32:
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll
index 3071562c85ca273..d202606d524f811 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll
@@ -1,4 +1,4 @@
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn-- -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mtriple=amdgcn-- -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
target datalayout = "A5"
declare ptr @llvm.invariant.start.p5(i64, ptr addrspace(5) nocapture) #0
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll
index 03535620412f2d2..d7d6d3761a7a67d 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=+promote-alloca < %s | FileCheck -check-prefix=NOOPTS -check-prefix=ALL %s
-; RUN: llc -O1 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=+promote-alloca < %s | FileCheck -check-prefix=OPTS -check-prefix=ALL %s
+; RUN: llc -O0 -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=+promote-alloca < %s | FileCheck -check-prefix=NOOPTS -check-prefix=ALL %s
+; RUN: llc -O1 -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=+promote-alloca < %s | FileCheck -check-prefix=OPTS -check-prefix=ALL %s
; ALL-LABEL: {{^}}promote_alloca_i32_array_array:
; NOOPTS: workgroup_group_segment_byte_size = 0{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/register-count-comments.ll b/llvm/test/CodeGen/AMDGPU/register-count-comments.ll
index 35149d354f2a80a..049ed2cf488f214 100644
--- a/llvm/test/CodeGen/AMDGPU/register-count-comments.ll
+++ b/llvm/test/CodeGen/AMDGPU/register-count-comments.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs -asm-verbose < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs -asm-verbose -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn -verify-machineinstrs -asm-verbose < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs -asm-verbose -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s
declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0
diff --git a/llvm/test/CodeGen/AMDGPU/salu-to-valu.ll b/llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
index 3307b837d393371..7027521d7e2dcea 100644
--- a/llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
+++ b/llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
@@ -1,5 +1,5 @@
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=SI %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=CI -check-prefix=CI-NOHSA %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=SI %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=CI -check-prefix=CI-NOHSA %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI --check-prefix=GCN-HSA %s
declare i32 @llvm.amdgcn.workitem.id.x() #0
diff --git a/llvm/test/CodeGen/AMDGPU/scratch-simple.ll b/llvm/test/CodeGen/AMDGPU/scratch-simple.ll
index a5bd362d3b2e5eb..c3cbdaf2dbe1914 100644
--- a/llvm/test/CodeGen/AMDGPU/scratch-simple.ll
+++ b/llvm/test/CodeGen/AMDGPU/scratch-simple.ll
@@ -1,15 +1,15 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,SI,SIVI,MUBUF %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx803 -mattr=-flat-for-global -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,VI,SIVI,MUBUF %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,MUBUF,GFX9-MUBUF,GFX9_10-MUBUF %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -filetype=obj -amdgpu-use-divergent-register-indexing < %s | llvm-readobj -r - | FileCheck --check-prefix=RELS %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx1010 -mattr=-flat-for-global -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,MUBUF,GFX10_W32-MUBUF,GFX9_10-MUBUF %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx1010 -mattr=-flat-for-global,+wavefrontsize64 -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,MUBUF,GFX10_W64-MUBUF,GFX9_10-MUBUF %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global,+enable-flat-scratch -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,FLATSCR,GFX9-FLATSCR %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx1030 -mattr=-flat-for-global,+enable-flat-scratch -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,FLATSCR,GFX10-FLATSCR %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn--amdpal -mcpu=gfx900 -mattr=-flat-for-global,+enable-flat-scratch -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,FLATSCR,GFX9-FLATSCR-PAL %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn--amdpal -mcpu=gfx1030 -mattr=-flat-for-global,+enable-flat-scratch -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,FLATSCR,GFX10-FLATSCR-PAL %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-flat-for-global,+enable-flat-scratch -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,GFX11-FLATSCR %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn--amdpal -mcpu=gfx1100 -mattr=-flat-for-global,+enable-flat-scratch -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,GFX11-FLATSCR %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=verde -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,SI,SIVI,MUBUF %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx803 -mattr=-flat-for-global -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,VI,SIVI,MUBUF %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,MUBUF,GFX9-MUBUF,GFX9_10-MUBUF %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -filetype=obj -amdgpu-use-divergent-register-indexing < %s | llvm-readobj -r - | FileCheck --check-prefix=RELS %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx1010 -mattr=-flat-for-global -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,MUBUF,GFX10_W32-MUBUF,GFX9_10-MUBUF %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx1010 -mattr=-flat-for-global,+wavefrontsize64 -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,MUBUF,GFX10_W64-MUBUF,GFX9_10-MUBUF %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global,+enable-flat-scratch -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,FLATSCR,GFX9-FLATSCR %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx1030 -mattr=-flat-for-global,+enable-flat-scratch -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,FLATSCR,GFX10-FLATSCR %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn--amdpal -mcpu=gfx900 -mattr=-flat-for-global,+enable-flat-scratch -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,FLATSCR,GFX9-FLATSCR-PAL %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn--amdpal -mcpu=gfx1030 -mattr=-flat-for-global,+enable-flat-scratch -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,FLATSCR,GFX10-FLATSCR-PAL %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-flat-for-global,+enable-flat-scratch -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,GFX11-FLATSCR %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn--amdpal -mcpu=gfx1100 -mattr=-flat-for-global,+enable-flat-scratch -amdgpu-use-divergent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9PLUS,GFX11-FLATSCR %s
; RELS: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0
; RELS: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD1
diff --git a/llvm/test/CodeGen/AMDGPU/setcc.ll b/llvm/test/CodeGen/AMDGPU/setcc.ll
index b250c915473eeb1..8758a40f8d6e8c0 100644
--- a/llvm/test/CodeGen/AMDGPU/setcc.ll
+++ b/llvm/test/CodeGen/AMDGPU/setcc.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=R600 -check-prefix=FUNC %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
diff --git a/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll b/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
index 637683315b73d0e..88ff4a44c18c383 100644
--- a/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
+++ b/llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
@@ -1,6 +1,6 @@
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,SI,FUNC %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX89,FUNC %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX9,GFX89,FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,SI,FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX89,FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX9,GFX89,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600-- -mcpu=cypress < %s | FileCheck -enable-var-scope --check-prefixes=EG,FUNC %s
; FIXME: i16 promotion pass ruins the scalar cases when legal.
diff --git a/llvm/test/CodeGen/AMDGPU/shl.ll b/llvm/test/CodeGen/AMDGPU/shl.ll
index 4f94d2180d30ae9..195043299786c83 100644
--- a/llvm/test/CodeGen/AMDGPU/shl.ll
+++ b/llvm/test/CodeGen/AMDGPU/shl.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs | FileCheck %s --check-prefixes=SI
-; RUN: llc < %s -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=VI
+; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs | FileCheck %s --check-prefixes=SI
+; RUN: llc < %s -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=VI
; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs | FileCheck %s --check-prefixes=EG
declare i32 @llvm.amdgcn.workitem.id.x() #0
diff --git a/llvm/test/CodeGen/AMDGPU/sra.ll b/llvm/test/CodeGen/AMDGPU/sra.ll
index f0f498dd264cc62..b26148b071ee228 100644
--- a/llvm/test/CodeGen/AMDGPU/sra.ll
+++ b/llvm/test/CodeGen/AMDGPU/sra.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SI
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=VI
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SI
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=VI
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck %s -check-prefixes=EG
declare i32 @llvm.amdgcn.workitem.id.x() #0
diff --git a/llvm/test/CodeGen/AMDGPU/store-global.ll b/llvm/test/CodeGen/AMDGPU/store-global.ll
index 1d4fd51cc166fa3..1329d9285aec0e2 100644
--- a/llvm/test/CodeGen/AMDGPU/store-global.ll
+++ b/llvm/test/CodeGen/AMDGPU/store-global.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=VI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=VI -check-prefix=FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=FUNC %s
; RUN: llc -march=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
diff --git a/llvm/test/CodeGen/AMDGPU/store-local.ll b/llvm/test/CodeGen/AMDGPU/store-local.ll
index f3c0eed491d5b9c..89ac7554adfb6e4 100644
--- a/llvm/test/CodeGen/AMDGPU/store-local.ll
+++ b/llvm/test/CodeGen/AMDGPU/store-local.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,VI,FUNC %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,VI,FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
; RUN: llc -march=r600 -mtriple=r600-- -mcpu=redwood < %s | FileCheck -check-prefixes=EG,FUNC %s
; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cayman < %s | FileCheck -check-prefixes=CM,FUNC %s
diff --git a/llvm/test/CodeGen/AMDGPU/tex-clause-antidep.ll b/llvm/test/CodeGen/AMDGPU/tex-clause-antidep.ll
index 2420286f766edc4..6e906446ccc6237 100644
--- a/llvm/test/CodeGen/AMDGPU/tex-clause-antidep.ll
+++ b/llvm/test/CodeGen/AMDGPU/tex-clause-antidep.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s
;CHECK: TEX
;CHECK-NEXT: ALU
diff --git a/llvm/test/CodeGen/AMDGPU/trap-abis.ll b/llvm/test/CodeGen/AMDGPU/trap-abis.ll
index c9987ac7831a420..de970c115c5347d 100644
--- a/llvm/test/CodeGen/AMDGPU/trap-abis.ll
+++ b/llvm/test/CodeGen/AMDGPU/trap-abis.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck --check-prefix=NOHSA-TRAP-GFX900-V2 %s
-; RUN: sed 's/CODE_OBJECT_VERSION/300/g' %s | llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck --check-prefix=NOHSA-TRAP-GFX900-V3 %s
-; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck --check-prefix=NOHSA-TRAP-GFX900-V4 %s
+; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck --check-prefix=NOHSA-TRAP-GFX900-V2 %s
+; RUN: sed 's/CODE_OBJECT_VERSION/300/g' %s | llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck --check-prefix=NOHSA-TRAP-GFX900-V3 %s
+; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck --check-prefix=NOHSA-TRAP-GFX900-V4 %s
; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs | FileCheck --check-prefix=HSA-TRAP-GFX803-V2 %s
; RUN: sed 's/CODE_OBJECT_VERSION/300/g' %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs | FileCheck --check-prefix=HSA-TRAP-GFX803-V3 %s
; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs | FileCheck --check-prefix=HSA-TRAP-GFX803-V4 %s
diff --git a/llvm/test/CodeGen/AMDGPU/trap.ll b/llvm/test/CodeGen/AMDGPU/trap.ll
index 7b7a223579fb7cc..9e0ec026a920104 100644
--- a/llvm/test/CodeGen/AMDGPU/trap.ll
+++ b/llvm/test/CodeGen/AMDGPU/trap.ll
@@ -20,8 +20,8 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s
-; RUN: llc -global-isel=0 -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
-; RUN: llc -global-isel=1 -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
; GCN-WARNING: warning: <unknown>:0:0: in function hsa_debugtrap void (ptr addrspace(1)): debugtrap handler not supported
diff --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll
index 647db3c35c158bb..88a49cfc6e6696c 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SI
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -denormal-fp-math-f32=preserve-sign < %s | FileCheck %s -check-prefixes=VI
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SI
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -denormal-fp-math-f32=preserve-sign < %s | FileCheck %s -check-prefixes=VI
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=fiji -denormal-fp-math-f32=ieee < %s | FileCheck %s -check-prefixes=GCN
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=gfx1030 -denormal-fp-math-f32=ieee < %s | FileCheck %s -check-prefixes=GFX1030
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefixes=EG
diff --git a/llvm/test/CodeGen/AMDGPU/unknown-processor.ll b/llvm/test/CodeGen/AMDGPU/unknown-processor.ll
index 8a9408711890148..25ade6e8c3f8d4b 100644
--- a/llvm/test/CodeGen/AMDGPU/unknown-processor.ll
+++ b/llvm/test/CodeGen/AMDGPU/unknown-processor.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=GCN %s
; RUN: llc -march=r600 -mtriple=r600-- -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=R600 %s
target datalayout = "A5"
diff --git a/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll b/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
index 81b53252f45e8ae..4e20629c6941d42 100644
--- a/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
+++ b/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
@@ -1,5 +1,5 @@
-; RUN: not llc -march=amdgcn -mtriple=amdgcn-mesa-mesa3d -tailcallopt < %s 2>&1 | FileCheck --check-prefix=GCN %s
-; RUN: not llc -march=amdgcn -mtriple=amdgcn--amdpal -tailcallopt < %s 2>&1 | FileCheck --check-prefix=GCN %s
+; RUN: not llc -mtriple=amdgcn -mtriple=amdgcn-mesa-mesa3d -tailcallopt < %s 2>&1 | FileCheck --check-prefix=GCN %s
+; RUN: not llc -mtriple=amdgcn -mtriple=amdgcn--amdpal -tailcallopt < %s 2>&1 | FileCheck --check-prefix=GCN %s
; RUN: not llc -march=r600 -mtriple=r600-- -mcpu=cypress -tailcallopt < %s 2>&1 | FileCheck -check-prefix=R600 %s
declare i32 @external_function(i32) nounwind
diff --git a/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll b/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
index 500c33acf3e21bb..dff077cc85c4bc2 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
@@ -1,6 +1,6 @@
; RUN: opt -S -mtriple=amdgcn- -passes=sroa %s -o %t.sroa.ll
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %t.sroa.ll | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-ALLOCA %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %t.sroa.ll | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-PROMOTE %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %t.sroa.ll | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-ALLOCA %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %t.sroa.ll | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-PROMOTE %s
; RUN: opt -S -mtriple=amdgcn-- -passes='sroa,amdgpu-promote-alloca,instcombine' < %s | FileCheck -check-prefix=OPT %s
target datalayout = "A5"
diff --git a/llvm/test/CodeGen/AMDGPU/vector-alloca.ll b/llvm/test/CodeGen/AMDGPU/vector-alloca.ll
index cff7b2d38ebfb9e..fa2a6c58446e6fb 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-alloca.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-alloca.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=verde -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=verde -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
; RUN: llc -march=r600 -mtriple=r600-- -mcpu=redwood < %s | FileCheck --check-prefixes=EG,FUNC %s
; RUN: opt -S -mtriple=amdgcn-- -passes='amdgpu-promote-alloca,sroa,instcombine' < %s | FileCheck -check-prefix=OPT %s
target datalayout = "A5"
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll b/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
index 8dffaca003e2304..f4b5ffa4de5bf04 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
@@ -1,9 +1,9 @@
; XFAIL: *
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=SIMESA %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=VIMESA %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=GFX9MESA %s
-; RUN: llc -march=amdgcn -mcpu=hawaii -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CIHSA -check-prefix=HSA %s
-; RUN: llc -march=amdgcn -mcpu=fiji -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VIHSA -check-prefix=HSA %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=SIMESA %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=VIMESA %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=GFX9MESA %s
+; RUN: llc -mtriple=amdgcn -mcpu=hawaii -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CIHSA -check-prefix=HSA %s
+; RUN: llc -mtriple=amdgcn -mcpu=fiji -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VIHSA -check-prefix=HSA %s
; This ends up using all 256 registers and requires register
; scavenging which will fail to find an unsued register.
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll b/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
index b4529a787178ed9..ba606d4a72019ae 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+; RUN: llc -mtriple=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
; This ends up using all 255 registers and requires register
; scavenging which will fail to find an unsued register.
diff --git a/llvm/test/CodeGen/AVR/ctors.ll b/llvm/test/CodeGen/AVR/ctors.ll
index 33fe088bdde25ba..728f188e553e3ba 100644
--- a/llvm/test/CodeGen/AVR/ctors.ll
+++ b/llvm/test/CodeGen/AVR/ctors.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
define void @do_nothing() addrspace(1) #0 {
; CHECK-LABEL: do_nothing:
diff --git a/llvm/test/CodeGen/AVR/jmp-long.ll b/llvm/test/CodeGen/AVR/jmp-long.ll
index 9878fda1028a017..52143a2675c1b99 100644
--- a/llvm/test/CodeGen/AVR/jmp-long.ll
+++ b/llvm/test/CodeGen/AVR/jmp-long.ll
@@ -1,4 +1,4 @@
-; RUN: llc -filetype=obj -march avr -mattr=jmpcall < %s | llvm-objdump -dr --mattr=jmpcall - | FileCheck %s
+; RUN: llc -filetype=obj -mtriple=avr -mattr=jmpcall < %s | llvm-objdump -dr --mattr=jmpcall - | FileCheck %s
; Test the fix in https://reviews.llvm.org/D78459.
; Long branches (that use jmp instead of rjmp) were broken: the jump was to a
diff --git a/llvm/test/CodeGen/AVR/rust-trait-object.ll b/llvm/test/CodeGen/AVR/rust-trait-object.ll
index fde89a3b817887f..87142cb11d84175 100644
--- a/llvm/test/CodeGen/AVR/rust-trait-object.ll
+++ b/llvm/test/CodeGen/AVR/rust-trait-object.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=avr -filetype=asm | FileCheck %s -check-prefix=CHECK-ASM
-; RUN: llc < %s -march=avr -filetype=obj | llvm-objdump -Dr - \
+; RUN: llc < %s -mtriple=avr -filetype=asm | FileCheck %s -check-prefix=CHECK-ASM
+; RUN: llc < %s -mtriple=avr -filetype=obj | llvm-objdump -Dr - \
; RUN: | FileCheck %s -check-prefix=CHECK-OBJ
; Somewhat pruned test case from rustc using trait objects
diff --git a/llvm/test/CodeGen/AVR/sections.ll b/llvm/test/CodeGen/AVR/sections.ll
index eff725817be8dcd..4fd9eb142bef64e 100644
--- a/llvm/test/CodeGen/AVR/sections.ll
+++ b/llvm/test/CodeGen/AVR/sections.ll
@@ -1,10 +1,10 @@
-; RUN: llc < %s -march=avr --mcpu=atxmega384d3 \
+; RUN: llc < %s -mtriple=avr --mcpu=atxmega384d3 \
; RUN: | FileCheck --check-prefixes=CHECK,NOSECTIONS %s
-; RUN: llc -function-sections -data-sections < %s -march=avr --mcpu=atxmega384d3 \
+; RUN: llc -function-sections -data-sections < %s -mtriple=avr --mcpu=atxmega384d3 \
; RUN: | FileCheck --check-prefixes=CHECK,SECTIONS %s
-; RUN: not llc -function-sections -data-sections < %s -march=avr --mcpu=at90s8515 2>&1 \
+; RUN: not llc -function-sections -data-sections < %s -mtriple=avr --mcpu=at90s8515 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-8515 %s
-; RUN: not llc -function-sections -data-sections < %s -march=avr --mcpu=attiny40 2>&1 \
+; RUN: not llc -function-sections -data-sections < %s -mtriple=avr --mcpu=attiny40 2>&1 \
; RUN: | FileCheck --check-prefixes=CHECK-tiny40 %s
; Test that functions (in address space 1) are not considered .progmem data.
diff --git a/llvm/test/CodeGen/BPF/BTF/align.ll b/llvm/test/CodeGen/BPF/BTF/align.ll
index d842b17ca88deab..9803a82a80e0c73 100644
--- a/llvm/test/CodeGen/BPF/BTF/align.ll
+++ b/llvm/test/CodeGen/BPF/BTF/align.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=bpfel -filetype=obj < %s | llvm-readelf -S - | FileCheck %s
-; RUN: llc -march=bpfeb -filetype=obj < %s | llvm-readelf -S - | FileCheck %s
+; RUN: llc -mtriple=bpfel -filetype=obj < %s | llvm-readelf -S - | FileCheck %s
+; RUN: llc -mtriple=bpfeb -filetype=obj < %s | llvm-readelf -S - | FileCheck %s
; Source:
; int foo() { return 0; }
; Compilation flags:
diff --git a/llvm/test/CodeGen/BPF/BTF/binary-format.ll b/llvm/test/CodeGen/BPF/BTF/binary-format.ll
index d5b4b4786c16cb6..3b1be1af43ec586 100644
--- a/llvm/test/CodeGen/BPF/BTF/binary-format.ll
+++ b/llvm/test/CodeGen/BPF/BTF/binary-format.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-readelf -x ".BTF" -x ".BTF.ext" - | FileCheck -check-prefixes=CHECK,CHECK-EL %s
-; RUN: llc -march=bpfeb -filetype=obj -o - %s | llvm-readelf -x ".BTF" -x ".BTF.ext" - | FileCheck -check-prefixes=CHECK,CHECK-EB %s
+; RUN: llc -mtriple=bpfel -filetype=obj -o - %s | llvm-readelf -x ".BTF" -x ".BTF.ext" - | FileCheck -check-prefixes=CHECK,CHECK-EL %s
+; RUN: llc -mtriple=bpfeb -filetype=obj -o - %s | llvm-readelf -x ".BTF" -x ".BTF.ext" - | FileCheck -check-prefixes=CHECK,CHECK-EB %s
; Source code:
; int f(int a) { return a; }
diff --git a/llvm/test/CodeGen/BPF/elf-symbol-information.ll b/llvm/test/CodeGen/BPF/elf-symbol-information.ll
index 5e400dab32e016a..6a588b1d406f5d9 100644
--- a/llvm/test/CodeGen/BPF/elf-symbol-information.ll
+++ b/llvm/test/CodeGen/BPF/elf-symbol-information.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-readelf --symbols - | FileCheck %s
+; RUN: llc -mtriple=bpfel -filetype=obj -o - %s | llvm-readelf --symbols - | FileCheck %s
; CHECK: 0 FILE LOCAL DEFAULT ABS elf-symbol-information.ll
; CHECK: 8 FUNC GLOBAL DEFAULT 2 test_func
diff --git a/llvm/test/CodeGen/BPF/objdump_atomics.ll b/llvm/test/CodeGen/BPF/objdump_atomics.ll
index 57dad3ad137916a..14a6dfdab11c490 100644
--- a/llvm/test/CodeGen/BPF/objdump_atomics.ll
+++ b/llvm/test/CodeGen/BPF/objdump_atomics.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+; RUN: llc -mtriple=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
; CHECK-LABEL: test_load_add_32
; CHECK: c3 21
diff --git a/llvm/test/CodeGen/BPF/objdump_cond_op.ll b/llvm/test/CodeGen/BPF/objdump_cond_op.ll
index d6d7ebc64b83056..4a4fa84376cc80a 100644
--- a/llvm/test/CodeGen/BPF/objdump_cond_op.ll
+++ b/llvm/test/CodeGen/BPF/objdump_cond_op.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+; RUN: llc -mtriple=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
; Source Code:
; int gbl;
diff --git a/llvm/test/CodeGen/BPF/objdump_cond_op_2.ll b/llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
index a1f8fdb28b2030e..4edd52a463ea9d7 100644
--- a/llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
+++ b/llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+; RUN: llc -mtriple=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
; Source Code:
; int test(int a, int b) {
diff --git a/llvm/test/CodeGen/BPF/objdump_dis_all.ll b/llvm/test/CodeGen/BPF/objdump_dis_all.ll
index c0faecfddb4361a..ea9323a42887d5c 100644
--- a/llvm/test/CodeGen/BPF/objdump_dis_all.ll
+++ b/llvm/test/CodeGen/BPF/objdump_dis_all.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -D - | FileCheck %s
+; RUN: llc -mtriple=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -D - | FileCheck %s
;
; Source:
; /* *(u64 *)(r10 - 16) = r1 */
diff --git a/llvm/test/CodeGen/BPF/objdump_fi_ri.ll b/llvm/test/CodeGen/BPF/objdump_fi_ri.ll
index f82a2346a84a2e5..942f1281ed822f6 100644
--- a/llvm/test/CodeGen/BPF/objdump_fi_ri.ll
+++ b/llvm/test/CodeGen/BPF/objdump_fi_ri.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=bpfel -filetype=obj -o - %s \
+; RUN: llc -mtriple=bpfel -filetype=obj -o - %s \
; RUN: | llvm-objdump --no-print-imm-hex --arch=bpfel --section=foo -d - \
; RUN: | FileCheck %s
diff --git a/llvm/test/CodeGen/BPF/objdump_imm_hex.ll b/llvm/test/CodeGen/BPF/objdump_imm_hex.ll
index 1b0e9456faab1c7..1760bb6b6c52180 100644
--- a/llvm/test/CodeGen/BPF/objdump_imm_hex.ll
+++ b/llvm/test/CodeGen/BPF/objdump_imm_hex.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck --check-prefix=CHECK-DEC %s
-; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump -d --print-imm-hex - | FileCheck --check-prefix=CHECK-HEX %s
+; RUN: llc -mtriple=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck --check-prefix=CHECK-DEC %s
+; RUN: llc -mtriple=bpfel -filetype=obj -o - %s | llvm-objdump -d --print-imm-hex - | FileCheck --check-prefix=CHECK-HEX %s
; Source Code:
; int gbl;
diff --git a/llvm/test/CodeGen/BPF/objdump_intrinsics.ll b/llvm/test/CodeGen/BPF/objdump_intrinsics.ll
index 952171ede59288c..92db0882398b641 100644
--- a/llvm/test/CodeGen/BPF/objdump_intrinsics.ll
+++ b/llvm/test/CodeGen/BPF/objdump_intrinsics.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck --check-prefix=CHECK-EL %s
-; RUN: llc -march=bpfeb -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck --check-prefix=CHECK-EB %s
+; RUN: llc -mtriple=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck --check-prefix=CHECK-EL %s
+; RUN: llc -mtriple=bpfeb -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck --check-prefix=CHECK-EB %s
; Function Attrs: nounwind uwtable
define i32 @ld_b(i64 %foo, ptr nocapture %bar, ptr %ctx, ptr %ctx2) #0 {
diff --git a/llvm/test/CodeGen/BPF/objdump_nop.ll b/llvm/test/CodeGen/BPF/objdump_nop.ll
index 6df2699f2e74ffd..219b51bcb1decba 100644
--- a/llvm/test/CodeGen/BPF/objdump_nop.ll
+++ b/llvm/test/CodeGen/BPF/objdump_nop.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
+; RUN: llc -mtriple=bpfel -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
;
; Source:
; int test() {
diff --git a/llvm/test/CodeGen/BPF/objdump_static_var.ll b/llvm/test/CodeGen/BPF/objdump_static_var.ll
index 8763dfeca827ade..a91074ebddd4678 100644
--- a/llvm/test/CodeGen/BPF/objdump_static_var.ll
+++ b/llvm/test/CodeGen/BPF/objdump_static_var.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck --check-prefix=CHECK %s
-; RUN: llc -march=bpfeb -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck --check-prefix=CHECK %s
+; RUN: llc -mtriple=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck --check-prefix=CHECK %s
+; RUN: llc -mtriple=bpfeb -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck --check-prefix=CHECK %s
; src:
; static volatile long a = 2;
diff --git a/llvm/test/CodeGen/BPF/objdump_trivial.ll b/llvm/test/CodeGen/BPF/objdump_trivial.ll
index b7c8b7a8c63d72e..47a01fd45a76412 100644
--- a/llvm/test/CodeGen/BPF/objdump_trivial.ll
+++ b/llvm/test/CodeGen/BPF/objdump_trivial.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+; RUN: llc -mtriple=bpfel -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
; CHECK: if r2 s> r1 goto
; CHECK: call 1
diff --git a/llvm/test/CodeGen/BPF/objdump_two_funcs.ll b/llvm/test/CodeGen/BPF/objdump_two_funcs.ll
index a05a54c192ba483..fb1043ce4cdf208 100644
--- a/llvm/test/CodeGen/BPF/objdump_two_funcs.ll
+++ b/llvm/test/CodeGen/BPF/objdump_two_funcs.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump -S - | FileCheck %s
-; RUN: llc -march=bpfeb -filetype=obj -o - %s | llvm-objdump -S - | FileCheck %s
+; RUN: llc -mtriple=bpfel -filetype=obj -o - %s | llvm-objdump -S - | FileCheck %s
+; RUN: llc -mtriple=bpfeb -filetype=obj -o - %s | llvm-objdump -S - | FileCheck %s
;
; Source code:
; __attribute__((section("s1")))
diff --git a/llvm/test/CodeGen/BPF/reloc-2.ll b/llvm/test/CodeGen/BPF/reloc-2.ll
index 762ae755b77fb51..50baef7faf22cbc 100644
--- a/llvm/test/CodeGen/BPF/reloc-2.ll
+++ b/llvm/test/CodeGen/BPF/reloc-2.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=bpfel -filetype=obj -o %t.el < %s
+; RUN: llc -mtriple=bpfel -filetype=obj -o %t.el < %s
; RUN: llvm-objdump -r %t.el | FileCheck --check-prefix=RELOC %s
; RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn %t.el | FileCheck --check-prefix=DUMP %s
-; RUN: llc -march=bpfeb -filetype=obj -o %t.eb < %s
+; RUN: llc -mtriple=bpfeb -filetype=obj -o %t.eb < %s
; RUN: llvm-objdump -r %t.eb | FileCheck --check-prefix=RELOC %s
; RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn %t.eb | FileCheck --check-prefix=DUMP %s
diff --git a/llvm/test/CodeGen/BPF/reloc-3.ll b/llvm/test/CodeGen/BPF/reloc-3.ll
index 58076d7cacdde61..e4bb18c5c286c09 100644
--- a/llvm/test/CodeGen/BPF/reloc-3.ll
+++ b/llvm/test/CodeGen/BPF/reloc-3.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=bpfel -filetype=obj -o %t.el < %s
+; RUN: llc -mtriple=bpfel -filetype=obj -o %t.el < %s
; RUN: llvm-readelf -r %t.el | FileCheck %s
-; RUN: llc -march=bpfeb -filetype=obj -o %t.eb < %s
+; RUN: llc -mtriple=bpfeb -filetype=obj -o %t.eb < %s
; RUN: llvm-readelf -r %t.eb | FileCheck %s
; source code:
diff --git a/llvm/test/CodeGen/BPF/reloc-btf-2.ll b/llvm/test/CodeGen/BPF/reloc-btf-2.ll
index 3f1c4da46351967..7398257e43a91ab 100644
--- a/llvm/test/CodeGen/BPF/reloc-btf-2.ll
+++ b/llvm/test/CodeGen/BPF/reloc-btf-2.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=bpfel -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
-; RUN: llc -march=bpfeb -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
+; RUN: llc -mtriple=bpfel -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
+; RUN: llc -mtriple=bpfeb -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
; source code:
; int g __attribute__((section("ids"))) = 4;
diff --git a/llvm/test/CodeGen/BPF/reloc-btf.ll b/llvm/test/CodeGen/BPF/reloc-btf.ll
index aa929257e039998..b9f6e3af6d72cfc 100644
--- a/llvm/test/CodeGen/BPF/reloc-btf.ll
+++ b/llvm/test/CodeGen/BPF/reloc-btf.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=bpfel -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
+; RUN: llc -mtriple=bpfel -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
; Function Attrs: norecurse nounwind readnone
define dso_local i32 @test() local_unnamed_addr #0 !dbg !7 {
diff --git a/llvm/test/CodeGen/BPF/reloc.ll b/llvm/test/CodeGen/BPF/reloc.ll
index 123de4851746536..be4855069177155 100644
--- a/llvm/test/CodeGen/BPF/reloc.ll
+++ b/llvm/test/CodeGen/BPF/reloc.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=bpfel -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
+; RUN: llc -mtriple=bpfel -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
%struct.bpf_context = type { i64, i64, i64, i64, i64, i64, i64 }
%struct.sk_buff = type { i64, i64, i64, i64, i64, i64, i64 }
diff --git a/llvm/test/CodeGen/Hexagon/S3_2op.ll b/llvm/test/CodeGen/Hexagon/S3_2op.ll
index b4cf8c9b735bb4a..1424169230da126 100644
--- a/llvm/test/CodeGen/Hexagon/S3_2op.ll
+++ b/llvm/test/CodeGen/Hexagon/S3_2op.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -filetype=obj < %s -o - | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+; RUN: llc -mtriple=hexagon -filetype=obj < %s -o - | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
; CHECK-LABEL: <f0>:
; CHECK: r{{[1-9]}}:{{[0-9]}} = abs(r{{[1-9]}}:{{[0-9]}})
diff --git a/llvm/test/CodeGen/Hexagon/cmp.ll b/llvm/test/CodeGen/Hexagon/cmp.ll
index ce5361ecb525a77..0060b3eac71a8e9 100644
--- a/llvm/test/CodeGen/Hexagon/cmp.ll
+++ b/llvm/test/CodeGen/Hexagon/cmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon --filetype=obj < %s -o - | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+; RUN: llc -mtriple=hexagon --filetype=obj < %s -o - | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
; Function Attrs: nounwind
define i32 @cmpeq(i32 %i) #0 {
diff --git a/llvm/test/CodeGen/Hexagon/compound.ll b/llvm/test/CodeGen/Hexagon/compound.ll
index 84fbeda7ead47e0..3ede372799d7214 100644
--- a/llvm/test/CodeGen/Hexagon/compound.ll
+++ b/llvm/test/CodeGen/Hexagon/compound.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -filetype=obj -ifcvt-limit=0 -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+; RUN: llc -mtriple=hexagon -filetype=obj -ifcvt-limit=0 -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
; CHECK: p0 = cmp.gt(r0,#-1); if (!p0.new) jump:nt
diff --git a/llvm/test/CodeGen/Hexagon/dualstore.ll b/llvm/test/CodeGen/Hexagon/dualstore.ll
index 7318fe54ba1d6de..acf38525a257b52 100644
--- a/llvm/test/CodeGen/Hexagon/dualstore.ll
+++ b/llvm/test/CodeGen/Hexagon/dualstore.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -filetype=obj %s -o - | llvm-objdump -d - | FileCheck %s
+; RUN: llc -mtriple=hexagon -filetype=obj %s -o - | llvm-objdump -d - | FileCheck %s
; Check that we generate dual stores in one packet in V4
; CHECK: 00 40 9f 52 529f4000
diff --git a/llvm/test/CodeGen/Hexagon/duplex.ll b/llvm/test/CodeGen/Hexagon/duplex.ll
index 9f25726cf597dc9..2f28e0bad9bb731 100644
--- a/llvm/test/CodeGen/Hexagon/duplex.ll
+++ b/llvm/test/CodeGen/Hexagon/duplex.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
+; RUN: llc -mtriple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
; CHECK: c0 3f 00 48 48003fc0
diff --git a/llvm/test/CodeGen/Hexagon/extlow.ll b/llvm/test/CodeGen/Hexagon/extlow.ll
index f3925d89ab98870..af34c61c234b3e9 100644
--- a/llvm/test/CodeGen/Hexagon/extlow.ll
+++ b/llvm/test/CodeGen/Hexagon/extlow.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -O0 %s -o - | llvm-mc -arch=hexagon -filetype=obj | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+; RUN: llc -mtriple=hexagon -O0 %s -o - | llvm-mc -triple=hexagon -filetype=obj | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
; CHECK: immext(#16777216)
; CHECK-NEXT: r0 = add(r0,##16777279)
diff --git a/llvm/test/CodeGen/Hexagon/relax.ll b/llvm/test/CodeGen/Hexagon/relax.ll
index e027bb63e1a575c..e2422316fa8de47 100644
--- a/llvm/test/CodeGen/Hexagon/relax.ll
+++ b/llvm/test/CodeGen/Hexagon/relax.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -filetype=obj < %s | llvm-objdump --no-print-imm-hex -d -r - | FileCheck %s
+; RUN: llc -mtriple=hexagon -filetype=obj < %s | llvm-objdump --no-print-imm-hex -d -r - | FileCheck %s
declare void @bar()
diff --git a/llvm/test/CodeGen/Hexagon/simple_addend.ll b/llvm/test/CodeGen/Hexagon/simple_addend.ll
index 4a6f0323bcbc7a7..909a43f6eac841b 100644
--- a/llvm/test/CodeGen/Hexagon/simple_addend.ll
+++ b/llvm/test/CodeGen/Hexagon/simple_addend.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -filetype=obj -o - < %s | llvm-readobj -r - | FileCheck %s
+; RUN: llc -mtriple=hexagon -filetype=obj -o - < %s | llvm-readobj -r - | FileCheck %s
declare void @bar(i32);
diff --git a/llvm/test/CodeGen/Hexagon/tc_duplex_asm.ll b/llvm/test/CodeGen/Hexagon/tc_duplex_asm.ll
index 3f97f98aefc3b4a..afdce3a6e5636d7 100644
--- a/llvm/test/CodeGen/Hexagon/tc_duplex_asm.ll
+++ b/llvm/test/CodeGen/Hexagon/tc_duplex_asm.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -mattr=+duplex -mcpu=hexagonv67t -filetype=obj < %s \
+; RUN: llc -mtriple=hexagon -mattr=+duplex -mcpu=hexagonv67t -filetype=obj < %s \
; RUN: -o - | llvm-objdump -d - | FileCheck %s
; Check that we generate two memory operations in tiny core if duplexes
diff --git a/llvm/test/CodeGen/Hexagon/vect-regpairs.ll b/llvm/test/CodeGen/Hexagon/vect-regpairs.ll
index d26c5f74f84de55..f21290c0fbcb0c0 100644
--- a/llvm/test/CodeGen/Hexagon/vect-regpairs.ll
+++ b/llvm/test/CodeGen/Hexagon/vect-regpairs.ll
@@ -1,5 +1,5 @@
-;RUN: llc -march=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj < %s -o - | llvm-objdump --mcpu=hexagonv66 --mattr=+hvx -d - | FileCheck --check-prefix=CHECK-V66 %s
-;RUN: llc -march=hexagon -mcpu=hexagonv67 -mhvx -filetype=obj < %s -o - | llvm-objdump --mcpu=hexagonv67 --mattr=+hvx -d - | FileCheck --check-prefix=CHECK-V67 %s
+;RUN: llc -mtriple=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj < %s -o - | llvm-objdump --mcpu=hexagonv66 --mattr=+hvx -d - | FileCheck --check-prefix=CHECK-V66 %s
+;RUN: llc -mtriple=hexagon -mcpu=hexagonv67 -mhvx -filetype=obj < %s -o - | llvm-objdump --mcpu=hexagonv67 --mattr=+hvx -d - | FileCheck --check-prefix=CHECK-V67 %s
; Should not attempt to use v<even>:<odd> 'reverse' vector regpairs
; on old or new arches (should not crash).
diff --git a/llvm/test/CodeGen/Hexagon/vrcmpys.ll b/llvm/test/CodeGen/Hexagon/vrcmpys.ll
index 36fa6e6ef7eba40..366cb0148493a1a 100644
--- a/llvm/test/CodeGen/Hexagon/vrcmpys.ll
+++ b/llvm/test/CodeGen/Hexagon/vrcmpys.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon --filetype=obj < %s -o - | llvm-objdump -d - | FileCheck %s
+; RUN: llc -mtriple=hexagon --filetype=obj < %s -o - | llvm-objdump -d - | FileCheck %s
@g0 = common global double 0.000000e+00, align 8
@g1 = common global double 0.000000e+00, align 8
diff --git a/llvm/test/CodeGen/Mips/2008-07-22-Cstpool.ll b/llvm/test/CodeGen/Mips/2008-07-22-Cstpool.ll
index a8e54707ddb214c..032d608d60fad3d 100644
--- a/llvm/test/CodeGen/Mips/2008-07-22-Cstpool.ll
+++ b/llvm/test/CodeGen/Mips/2008-07-22-Cstpool.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips < %s | FileCheck %s
+; RUN: llc -mtriple=mips < %s | FileCheck %s
define float @F(float %a) nounwind {
; CHECK: .rodata.cst4,"aM", at progbits
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/shift.ll b/llvm/test/CodeGen/Mips/Fast-ISel/shift.ll
index e3edf245e981665..cf1278214fee739 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/shift.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/shift.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 -fast-isel=true -filetype=obj %s -o - \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -O0 -fast-isel=true -filetype=obj %s -o - \
; RUN: | llvm-objdump -d - | FileCheck %s
; This test checks that encoding for srl is correct when fast-isel for mips32r2 is used.
diff --git a/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll b/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll
index fdfaf3f7ee040ee..14d781dc57df8eb 100644
--- a/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll
+++ b/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll
@@ -1,24 +1,24 @@
-; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32-INV %s
-; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32-INV %s
+; RUN: llc -mtriple=mips < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -mtriple=mips < %s | FileCheck --check-prefixes=ALL,O32-INV %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck --check-prefixes=ALL,O32-INV %s
-; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-INV %s
-; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-INV %s
+; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-INV %s
+; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-INV %s
-; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
-; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
-; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N32-INV %s
-; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N32-INV %s
+; RUN: llc -mtriple=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
+; RUN: llc -mtriple=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
+; RUN: llc -mtriple=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N32-INV %s
+; RUN: llc -mtriple=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N32-INV %s
-; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
-; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
-; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s
-; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s
+; RUN: llc -mtriple=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
+; RUN: llc -mtriple=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
+; RUN: llc -mtriple=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s
+; RUN: llc -mtriple=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -filetype=obj < %s -o - | llvm-objdump --no-show-raw-insn --arch=mips --mcpu=mips32r6 --mattr=micromips -d - | FileCheck --check-prefix=MM32R6 %s
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -filetype=obj < %s -o - | llvm-objdump --no-show-raw-insn --arch=mips --mcpu=mips32r6 --mattr=micromips -d - | FileCheck --check-prefix=MM32R6 %s
; Test the callee-saved registers are callee-saved as specified by section
; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec.
diff --git a/llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll b/llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
index 5e607c2639f3b4e..204fac56a933147 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
+++ b/llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=mipsel -mcpu=mips32r6 -disable-mips-delay-filler < %s | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips32r6 -disable-mips-delay-filler < %s -filetype=obj \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -disable-mips-delay-filler < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -disable-mips-delay-filler < %s -filetype=obj \
; RUN: -o - | llvm-objdump -d - | FileCheck %s --check-prefix=ENCODING
-; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s -filetype=obj \
+; RUN: llc -mtriple=mipsel -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s -filetype=obj \
; RUN: -o - | llvm-objdump -d - | FileCheck %s --check-prefix=ENCODING
; bnezc and beqzc have restriction that $rt != 0
diff --git a/llvm/test/CodeGen/Mips/dsp-spill-reload.ll b/llvm/test/CodeGen/Mips/dsp-spill-reload.ll
index 85d94d46ffc3990..f18f58b8042658c 100644
--- a/llvm/test/CodeGen/Mips/dsp-spill-reload.ll
+++ b/llvm/test/CodeGen/Mips/dsp-spill-reload.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mips -mattr=+dsp < %s -asm-show-inst -O0 | FileCheck %s \
+; RUN: llc -mtriple=mips -mattr=+dsp < %s -asm-show-inst -O0 | FileCheck %s \
; RUN: --check-prefixes=ASM,ALL
-; RUN: llc -march=mips -mattr=+dsp,+micromips < %s -O0 -filetype=obj | \
+; RUN: llc -mtriple=mips -mattr=+dsp,+micromips < %s -O0 -filetype=obj | \
; RUN: llvm-objdump --no-print-imm-hex -d - | FileCheck %s --check-prefixes=MM-OBJ,ALL
; Test that spill and reloads use the dsp "variant" instructions. We use -O0
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-l1.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-l1.ll
index 1cd86d617a24ff9..a2d180739e8e201 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-l1.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-l1.ll
@@ -1,7 +1,7 @@
; Negative test. The constraint 'l' represents the register 'lo'.
; Check error message in case of invalid usage.
;
-; RUN: not llc -march=mips -filetype=obj < %s 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=mips -filetype=obj < %s 2>&1 | FileCheck %s
define void @constraint_l() nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/mature-mc-support.ll b/llvm/test/CodeGen/Mips/mature-mc-support.ll
index 9c93e96a376b8f2..67e21958cb72533 100644
--- a/llvm/test/CodeGen/Mips/mature-mc-support.ll
+++ b/llvm/test/CodeGen/Mips/mature-mc-support.ll
@@ -3,28 +3,28 @@
; FIXME: Mips doesn't use the integrated assembler by default so we only test
; that -filetype=obj tries to parse the assembly.
-; SKIP: not llc -march=mips < %s > /dev/null 2> %t1
+; SKIP: not llc -mtriple=mips < %s > /dev/null 2> %t1
; SKIP: FileCheck %s < %t1
-; RUN: not llc -march=mips -filetype=obj < %s > /dev/null 2> %t2
+; RUN: not llc -mtriple=mips -filetype=obj < %s > /dev/null 2> %t2
; RUN: FileCheck %s < %t2
-; SKIP: not llc -march=mipsel < %s > /dev/null 2> %t3
+; SKIP: not llc -mtriple=mipsel < %s > /dev/null 2> %t3
; SKIP: FileCheck %s < %t3
-; RUN: not llc -march=mipsel -filetype=obj < %s > /dev/null 2> %t4
+; RUN: not llc -mtriple=mipsel -filetype=obj < %s > /dev/null 2> %t4
; RUN: FileCheck %s < %t4
-; SKIP: not llc -march=mips64 < %s > /dev/null 2> %t5
+; SKIP: not llc -mtriple=mips64 < %s > /dev/null 2> %t5
; SKIP: FileCheck %s < %t5
-; RUN: not llc -march=mips64 -filetype=obj < %s > /dev/null 2> %t6
+; RUN: not llc -mtriple=mips64 -filetype=obj < %s > /dev/null 2> %t6
; RUN: FileCheck %s < %t6
-; SKIP: not llc -march=mips64el < %s > /dev/null 2> %t7
+; SKIP: not llc -mtriple=mips64el < %s > /dev/null 2> %t7
; SKIP: FileCheck %s < %t7
-; RUN: not llc -march=mips64el -filetype=obj < %s > /dev/null 2> %t8
+; RUN: not llc -mtriple=mips64el -filetype=obj < %s > /dev/null 2> %t8
; RUN: FileCheck %s < %t8
module asm " .this_directive_is_very_unlikely_to_exist"
diff --git a/llvm/test/CodeGen/Mips/micromips-atomic1.ll b/llvm/test/CodeGen/Mips/micromips-atomic1.ll
index 74e4f626620174b..296ea390d27e9e0 100644
--- a/llvm/test/CodeGen/Mips/micromips-atomic1.ll
+++ b/llvm/test/CodeGen/Mips/micromips-atomic1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -filetype=obj --disable-machine-licm -mattr=micromips < %s -o - \
+; RUN: llc -mtriple=mipsel -filetype=obj --disable-machine-licm -mattr=micromips < %s -o - \
; RUN: | llvm-objdump --no-print-imm-hex --no-show-raw-insn -d - | FileCheck %s --check-prefix=MICROMIPS
; Use llvm-objdump to check wheter the encodings of microMIPS atomic instructions are correct.
diff --git a/llvm/test/CodeGen/Mips/micromips-b-range.ll b/llvm/test/CodeGen/Mips/micromips-b-range.ll
index 81d1c04208ccf2a..26f8cfd31ceba62 100644
--- a/llvm/test/CodeGen/Mips/micromips-b-range.ll
+++ b/llvm/test/CodeGen/Mips/micromips-b-range.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -relocation-model=pic -mattr=+micromips \
+; RUN: llc -mtriple=mips -relocation-model=pic -mattr=+micromips \
; RUN: -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
; CHECK-LABEL: <foo>:
diff --git a/llvm/test/CodeGen/Mips/micromips-eva.mir b/llvm/test/CodeGen/Mips/micromips-eva.mir
index f45118d7fb7b2d5..3851a6961e03f37 100644
--- a/llvm/test/CodeGen/Mips/micromips-eva.mir
+++ b/llvm/test/CodeGen/Mips/micromips-eva.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=finalize-isel \
+# RUN: llc -O0 -mtriple=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=finalize-isel \
# RUN: -filetype obj %s -o - | llvm-objdump --no-print-imm-hex --mattr=+eva -d - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir b/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
index 662b9bc4b66d054..df5ef982a19f757 100644
--- a/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
+++ b/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=finalize-isel \
+# RUN: llc -O0 -mtriple=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=finalize-isel \
# RUN: -filetype obj %s -o - | llvm-objdump --no-print-imm-hex --mattr=+eva -d - | FileCheck %s
# Test that MIPS unaligned load/store instructions can be mapped to their
diff --git a/llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir b/llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
index 67865ce5f433fc7..5221fa73525cc0d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
@@ -1,6 +1,6 @@
-# RUN: llc -march=riscv64 -mattr=+v -o %t0 -filetype=obj \
+# RUN: llc -mtriple=riscv64 -mattr=+v -o %t0 -filetype=obj \
# RUN: -start-before=prologepilog %s
-# RUN: llc -march=riscv64 -mattr=+v -o %t1 -filetype=obj \
+# RUN: llc -mtriple=riscv64 -mattr=+v -o %t1 -filetype=obj \
# RUN: -frame-pointer=all -start-before=prologepilog %s
# RUN: llvm-dwarfdump --name="value0" %t0 | FileCheck %s --check-prefix=CHECK0-PLUS
# RUN: llvm-dwarfdump --name="value1" %t0 | FileCheck %s --check-prefix=CHECK1-PLUS
diff --git a/llvm/test/CodeGen/SPARC/mature-mc-support.ll b/llvm/test/CodeGen/SPARC/mature-mc-support.ll
index 3951ddd604c48be..653ffd038286807 100644
--- a/llvm/test/CodeGen/SPARC/mature-mc-support.ll
+++ b/llvm/test/CodeGen/SPARC/mature-mc-support.ll
@@ -3,16 +3,16 @@
; FIXME: SPARC doesn't use the integrated assembler by default in all cases
; so we only test that -filetype=obj tries to parse the assembly.
-; SKIP: not llc -march=sparc < %s > /dev/null 2> %t1
+; SKIP: not llc -mtriple=sparc < %s > /dev/null 2> %t1
; SKIP: FileCheck %s < %t1
-; RUN: not llc -march=sparc -filetype=obj < %s > /dev/null 2> %t2
+; RUN: not llc -mtriple=sparc -filetype=obj < %s > /dev/null 2> %t2
; RUN: FileCheck %s < %t2
-; SKIP: not llc -march=sparcv9 < %s > /dev/null 2> %t3
+; SKIP: not llc -mtriple=sparcv9 < %s > /dev/null 2> %t3
; SKIP: FileCheck %s < %t3
-; RUN: not llc -march=sparcv9 -filetype=obj < %s > /dev/null 2> %t4
+; RUN: not llc -mtriple=sparcv9 -filetype=obj < %s > /dev/null 2> %t4
; RUN: FileCheck %s < %t4
module asm " .this_directive_is_very_unlikely_to_exist"
diff --git a/llvm/test/CodeGen/SPARC/missing-sret.ll b/llvm/test/CodeGen/SPARC/missing-sret.ll
index c7435766aebc771..a030096c329cec1 100644
--- a/llvm/test/CodeGen/SPARC/missing-sret.ll
+++ b/llvm/test/CodeGen/SPARC/missing-sret.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=sparc -filetype=obj < %s > /dev/null 2> %t2
+; RUN: llc -mtriple=sparc -filetype=obj < %s > /dev/null 2> %t2
define void @mul_double_cc({ double, double }* noalias sret({ double, double }) %agg.result, double %a, double %b, double %c, double %d) {
entry:
diff --git a/llvm/test/CodeGen/XCore/codemodel.ll b/llvm/test/CodeGen/XCore/codemodel.ll
index ff58dca6c00a913..4335f98c1999707 100644
--- a/llvm/test/CodeGen/XCore/codemodel.ll
+++ b/llvm/test/CodeGen/XCore/codemodel.ll
@@ -1,13 +1,13 @@
-; RUN: not --crash llc < %s -march=xcore -code-model=medium 2>&1 | FileCheck %s -check-prefix=BAD_CM
-; RUN: not --crash llc < %s -march=xcore -code-model=kernel 2>&1 | FileCheck %s -check-prefix=BAD_CM
-; RUN: not --crash llc < %s -march=xcore -code-model=tiny 2>&1 | FileCheck %s -check-prefix=BAD_CM
+; RUN: not --crash llc < %s -mtriple=xcore -code-model=medium 2>&1 | FileCheck %s -check-prefix=BAD_CM
+; RUN: not --crash llc < %s -mtriple=xcore -code-model=kernel 2>&1 | FileCheck %s -check-prefix=BAD_CM
+; RUN: not --crash llc < %s -mtriple=xcore -code-model=tiny 2>&1 | FileCheck %s -check-prefix=BAD_CM
; BAD_CM: Target only supports CodeModel Small or Large
-; RUN: llc < %s -march=xcore | FileCheck %s
-; RUN: llc < %s -march=xcore -code-model=small | FileCheck %s
-; RUN: llc < %s -march=xcore -code-model=large | FileCheck %s -check-prefix=LARGE
+; RUN: llc < %s -mtriple=xcore | FileCheck %s
+; RUN: llc < %s -mtriple=xcore -code-model=small | FileCheck %s
+; RUN: llc < %s -mtriple=xcore -code-model=large | FileCheck %s -check-prefix=LARGE
; CHECK-LABEL: test:
diff --git a/llvm/test/CodeGen/XCore/epilogue_prologue.ll b/llvm/test/CodeGen/XCore/epilogue_prologue.ll
index 7b38cb8d622e787..8130ced2bd6e2c8 100644
--- a/llvm/test/CodeGen/XCore/epilogue_prologue.ll
+++ b/llvm/test/CodeGen/XCore/epilogue_prologue.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=xcore | FileCheck %s
-; RUN: llc < %s -march=xcore -frame-pointer=all | FileCheck %s -check-prefix=CHECKFP
+; RUN: llc < %s -mtriple=xcore | FileCheck %s
+; RUN: llc < %s -mtriple=xcore -frame-pointer=all | FileCheck %s -check-prefix=CHECKFP
; When using SP for small frames, we don't need any scratch registers (SR).
; When using SP for large frames, we may need two scratch registers.
diff --git a/llvm/test/CodeGen/XCore/scavenging.ll b/llvm/test/CodeGen/XCore/scavenging.ll
index db9b6221a7285bc..1315e9a572bec08 100644
--- a/llvm/test/CodeGen/XCore/scavenging.ll
+++ b/llvm/test/CodeGen/XCore/scavenging.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=xcore | FileCheck %s
+; RUN: llc < %s -mtriple=xcore | FileCheck %s
@size = global i32 0 ; <ptr> [#uses=1]
@g0 = external global i32 ; <ptr> [#uses=2]
>From e78d3cdbfc6425d0cfeb106b58f16ceede0ce5ab Mon Sep 17 00:00:00 2001
From: Fangrui Song <i at maskray.me>
Date: Mon, 11 Sep 2023 14:51:50 -0700
Subject: [PATCH 25/35] [test] Change llvm-mc -arch= to -triple=
The issue is uncovered by #47698: for assembly files, -triple= specifies the
full target triple while -arch= merely sets the architecture part of the default
target triple, leaving a target triple which may not make sense, e.g.
riscv64-apple-darwin.
Therefore, -arch= is error-prone and not recommended for tests. The issue has
been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it
outrightly.
Due to the nature of the issue, we don't see the issue in tests using
architectures that any of Mach-O/COFF/XCOFF supports.
---
llvm/test/MC/AMDGPU/accvgpr-altnames.s | 2 +-
llvm/test/MC/AMDGPU/add-sub-no-carry.s | 6 ++--
llvm/test/MC/AMDGPU/atomic-fadd-insts.s | 4 +--
llvm/test/MC/AMDGPU/branch-comment.s | 2 +-
llvm/test/MC/AMDGPU/buf-fmt-d16-packed.s | 6 ++--
llvm/test/MC/AMDGPU/buf-fmt-d16-unpacked.s | 6 ++--
llvm/test/MC/AMDGPU/buffer_wbinv1l_vol_vi.s | 2 +-
llvm/test/MC/AMDGPU/cpol-err.s | 2 +-
llvm/test/MC/AMDGPU/dl-insts-err.s | 10 +++---
llvm/test/MC/AMDGPU/dl-insts.s | 4 +--
llvm/test/MC/AMDGPU/dpp-err.s | 12 +++----
llvm/test/MC/AMDGPU/dpp64.s | 4 +--
llvm/test/MC/AMDGPU/ds-err.s | 4 +--
llvm/test/MC/AMDGPU/ds-gfx9.s | 4 +--
llvm/test/MC/AMDGPU/ds.s | 16 +++++-----
llvm/test/MC/AMDGPU/elf-notes-verify-amdgcn.s | 2 +-
llvm/test/MC/AMDGPU/elf-notes-verify-r600.s | 2 +-
llvm/test/MC/AMDGPU/exp-err.s | 6 ++--
llvm/test/MC/AMDGPU/exp-gfx10.s | 8 ++---
llvm/test/MC/AMDGPU/exp-pregfx11.s | 8 ++---
llvm/test/MC/AMDGPU/exp.s | 10 +++---
llvm/test/MC/AMDGPU/expressions-gfx10.s | 4 +--
llvm/test/MC/AMDGPU/expressions-gfx9.s | 4 +--
llvm/test/MC/AMDGPU/expressions.s | 4 +--
llvm/test/MC/AMDGPU/flat-gfx10.s | 4 +--
llvm/test/MC/AMDGPU/flat-gfx9.s | 8 ++---
llvm/test/MC/AMDGPU/flat-global.s | 10 +++---
llvm/test/MC/AMDGPU/flat-scratch-gfx940.s | 2 +-
.../MC/AMDGPU/flat-scratch-instructions.s | 10 +++---
llvm/test/MC/AMDGPU/flat-scratch-st-mode.s | 8 ++---
llvm/test/MC/AMDGPU/flat-scratch.s | 10 +++---
llvm/test/MC/AMDGPU/flat.s | 10 +++---
llvm/test/MC/AMDGPU/fma-mix.s | 6 ++--
llvm/test/MC/AMDGPU/gfx10-constant-bus.s | 8 ++---
llvm/test/MC/AMDGPU/gfx10-vop2be-literal.s | 2 +-
llvm/test/MC/AMDGPU/gfx1011_dlops.s | 18 +++++------
llvm/test/MC/AMDGPU/gfx1011_err.s | 4 +--
llvm/test/MC/AMDGPU/gfx1013.s | 2 +-
llvm/test/MC/AMDGPU/gfx1030_err.s | 14 ++++----
llvm/test/MC/AMDGPU/gfx1030_new.s | 14 ++++----
llvm/test/MC/AMDGPU/gfx1030_unsupported.s | 4 +--
llvm/test/MC/AMDGPU/gfx10_asm_dpp16.s | 8 ++---
llvm/test/MC/AMDGPU/gfx10_asm_dpp8.s | 8 ++---
llvm/test/MC/AMDGPU/gfx10_asm_ds.s | 4 +--
llvm/test/MC/AMDGPU/gfx10_asm_err.s | 12 +++----
llvm/test/MC/AMDGPU/gfx10_asm_flat.s | 4 +--
llvm/test/MC/AMDGPU/gfx10_asm_mimg.s | 2 +-
llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s | 2 +-
llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s | 4 +--
llvm/test/MC/AMDGPU/gfx10_asm_smem.s | 4 +--
llvm/test/MC/AMDGPU/gfx10_asm_sop.s | 4 +--
llvm/test/MC/AMDGPU/gfx10_asm_vop1.s | 8 ++---
llvm/test/MC/AMDGPU/gfx10_asm_vop2.s | 8 ++---
llvm/test/MC/AMDGPU/gfx10_asm_vop3.s | 8 ++---
llvm/test/MC/AMDGPU/gfx10_asm_vopc.s | 8 ++---
llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s | 8 ++---
llvm/test/MC/AMDGPU/gfx10_asm_vopc_sdwa.s | 8 ++---
llvm/test/MC/AMDGPU/gfx10_asm_vopcx.s | 4 +--
llvm/test/MC/AMDGPU/gfx10_err_pos.s | 2 +-
llvm/test/MC/AMDGPU/gfx10_unsupported.s | 6 ++--
llvm/test/MC/AMDGPU/gfx10_unsupported_dpp.s | 6 ++--
llvm/test/MC/AMDGPU/gfx10_unsupported_e32.s | 6 ++--
llvm/test/MC/AMDGPU/gfx10_unsupported_e64.s | 6 ++--
.../MC/AMDGPU/gfx10_unsupported_e64_dpp.s | 6 ++--
llvm/test/MC/AMDGPU/gfx10_unsupported_sdwa.s | 6 ++--
llvm/test/MC/AMDGPU/gfx11-promotions.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_ds.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_err.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_exp.s | 6 ++--
llvm/test/MC/AMDGPU/gfx11_asm_flat.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_flat_errs.s | 10 +++---
llvm/test/MC/AMDGPU/gfx11_asm_ldsdir.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_ldsdir_err.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_mimg.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_mimg_err.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_mimg_features.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_mtbuf.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_mtbuf_alias.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_mubuf.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_mubuf_alias.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_operands.s | 6 ++--
llvm/test/MC/AMDGPU/gfx11_asm_smem.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_smem_alias.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_sop1.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_sop2.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_sopc.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_sopk.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_sopk_err.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_sopp.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_vinterp.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_vinterp_err.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_vop1.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s | 4 +--
.../MC/AMDGPU/gfx11_asm_vop1_t16_promote.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_vop2.s | 8 ++---
llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s | 8 ++---
llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s | 8 ++---
llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s | 4 +--
.../MC/AMDGPU/gfx11_asm_vop2_t16_promote.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_vop3.s | 8 ++---
llvm/test/MC/AMDGPU/gfx11_asm_vop3_alias.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s | 8 ++---
.../AMDGPU/gfx11_asm_vop3_dpp16_from_vop1.s | 2 +-
.../AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s | 8 ++---
.../AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s | 8 ++---
.../AMDGPU/gfx11_asm_vop3_dpp16_from_vopcx.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s | 8 ++---
.../MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop1.s | 2 +-
.../MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s | 8 ++---
.../MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s | 8 ++---
.../AMDGPU/gfx11_asm_vop3_dpp8_from_vopcx.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s | 4 +--
.../test/MC/AMDGPU/gfx11_asm_vop3_from_vop1.s | 2 +-
.../test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s | 8 ++---
.../test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s | 8 ++---
.../MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_vop3p.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp16.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp8.s | 4 +--
.../test/MC/AMDGPU/gfx11_asm_vop3p_features.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_vopc.s | 8 ++---
llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s | 8 ++---
llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s | 8 ++---
llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s | 2 +-
.../MC/AMDGPU/gfx11_asm_vopc_t16_promote.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_vopcx.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp16.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp8.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s | 2 +-
.../MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_vopd.s | 6 ++--
llvm/test/MC/AMDGPU/gfx11_asm_vopd_err.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_vopd_features.s | 2 +-
llvm/test/MC/AMDGPU/gfx11_asm_wmma.s | 8 ++---
llvm/test/MC/AMDGPU/gfx11_unsupported.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_unsupported_dpp.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_unsupported_e32.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_unsupported_e64.s | 4 +--
llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa.s | 4 +--
llvm/test/MC/AMDGPU/gfx7_asm_ds.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_exp.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_flat.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_mimg.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_mtbuf.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_smrd.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_sop1.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_sop2.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_sopc.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_sopk.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_sopp.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_vintrp.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_vop1.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_vop2.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_vop3.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_vop3_e64.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_asm_vopc.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_err_pos.s | 2 +-
llvm/test/MC/AMDGPU/gfx7_unsupported.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_ds.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_exp.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_flat.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_mimg.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_mtbuf.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_smem.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_sop1.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_sop2.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_sopc.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_sopk.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_sopp.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_vintrp.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_vop1.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_vop2.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_vop3.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_vop3_e64.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_asm_vopc.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_err_pos.s | 2 +-
llvm/test/MC/AMDGPU/gfx8_unsupported.s | 2 +-
llvm/test/MC/AMDGPU/gfx9-asm-err.s | 2 +-
llvm/test/MC/AMDGPU/gfx9-vop2be-literal.s | 2 +-
llvm/test/MC/AMDGPU/gfx908_err_pos.s | 2 +-
llvm/test/MC/AMDGPU/gfx90a_asm_features.s | 6 ++--
llvm/test/MC/AMDGPU/gfx90a_err.s | 2 +-
llvm/test/MC/AMDGPU/gfx90a_err_pos.s | 2 +-
llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s | 4 +--
llvm/test/MC/AMDGPU/gfx940_asm_features.s | 6 ++--
llvm/test/MC/AMDGPU/gfx940_err.s | 2 +-
llvm/test/MC/AMDGPU/gfx940_err_pos.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_ds.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_exp.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_flat.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_mimg.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_mtbuf.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_smem.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_sop1.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_sop2.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_sopc.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_sopk.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_sopp.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_vintrp.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_vop1.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_vop2.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_vop3.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_vop3p.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_asm_vopc.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_err_pos.s | 2 +-
llvm/test/MC/AMDGPU/gfx9_unsupported.s | 2 +-
llvm/test/MC/AMDGPU/hsa_isa_version_attrs.s | 4 +--
llvm/test/MC/AMDGPU/inline-imm-inv2pi.s | 4 +--
llvm/test/MC/AMDGPU/labels-branch-err.s | 2 +-
llvm/test/MC/AMDGPU/labels-branch-gfx9.s | 4 +--
llvm/test/MC/AMDGPU/labels-branch.s | 4 +--
llvm/test/MC/AMDGPU/lds_direct-ci.s | 2 +-
llvm/test/MC/AMDGPU/lds_direct-err.s | 2 +-
llvm/test/MC/AMDGPU/lds_direct-gfx10.s | 4 +--
llvm/test/MC/AMDGPU/lds_direct.s | 2 +-
llvm/test/MC/AMDGPU/literal16-err.s | 2 +-
llvm/test/MC/AMDGPU/literal16.s | 2 +-
llvm/test/MC/AMDGPU/literals.s | 22 ++++++-------
llvm/test/MC/AMDGPU/literalv216-err.s | 4 +--
llvm/test/MC/AMDGPU/literalv216.s | 8 ++---
llvm/test/MC/AMDGPU/macro-examples.s | 2 +-
llvm/test/MC/AMDGPU/mad-mix.s | 6 ++--
llvm/test/MC/AMDGPU/mai-err-gfx940.s | 2 +-
llvm/test/MC/AMDGPU/mai-err.s | 4 +--
llvm/test/MC/AMDGPU/mai-gfx90a.s | 2 +-
llvm/test/MC/AMDGPU/mai-gfx940.s | 4 +--
llvm/test/MC/AMDGPU/mai.s | 4 +--
llvm/test/MC/AMDGPU/max-branch-distance.s | 2 +-
llvm/test/MC/AMDGPU/mimg-err-gfx940.s | 2 +-
llvm/test/MC/AMDGPU/mimg-err.s | 10 +++---
llvm/test/MC/AMDGPU/mimg-gfx90a.s | 2 +-
llvm/test/MC/AMDGPU/mimg.s | 26 +++++++--------
.../MC/AMDGPU/misaligned-vgpr-tuples-err.s | 2 +-
llvm/test/MC/AMDGPU/mtbuf-gfx10.s | 4 +--
llvm/test/MC/AMDGPU/mtbuf.s | 12 +++----
llvm/test/MC/AMDGPU/mubuf-gfx10.s | 2 +-
llvm/test/MC/AMDGPU/mubuf-gfx9.s | 4 +--
llvm/test/MC/AMDGPU/mubuf.s | 12 +++----
llvm/test/MC/AMDGPU/offset-expr.s | 2 +-
llvm/test/MC/AMDGPU/offsetbug_once.s | 4 +--
llvm/test/MC/AMDGPU/offsetbug_one_and_one.s | 4 +--
llvm/test/MC/AMDGPU/offsetbug_twice.s | 4 +--
llvm/test/MC/AMDGPU/out-of-range-registers.s | 18 +++++------
llvm/test/MC/AMDGPU/reg-syntax-err.s | 2 +-
llvm/test/MC/AMDGPU/reg-syntax-extra.s | 16 +++++-----
llvm/test/MC/AMDGPU/regression/bug28165.s | 8 ++---
llvm/test/MC/AMDGPU/regression/bug28168.s | 4 +--
llvm/test/MC/AMDGPU/regression/bug28413.s | 8 ++---
llvm/test/MC/AMDGPU/regression/bug28538.s | 8 ++---
llvm/test/MC/AMDGPU/s_endpgm.s | 6 ++--
llvm/test/MC/AMDGPU/smem-err.s | 2 +-
llvm/test/MC/AMDGPU/smem.s | 28 ++++++++--------
llvm/test/MC/AMDGPU/smrd-err.s | 4 +--
llvm/test/MC/AMDGPU/smrd.s | 16 +++++-----
llvm/test/MC/AMDGPU/sop1-err.s | 6 ++--
llvm/test/MC/AMDGPU/sop1.s | 18 +++++------
llvm/test/MC/AMDGPU/sop2-err.s | 2 +-
llvm/test/MC/AMDGPU/sop2.s | 26 +++++++--------
llvm/test/MC/AMDGPU/sopc-err.s | 2 +-
llvm/test/MC/AMDGPU/sopc.s | 8 ++---
llvm/test/MC/AMDGPU/sopk-err.s | 26 +++++++--------
llvm/test/MC/AMDGPU/sopk.s | 26 +++++++--------
llvm/test/MC/AMDGPU/sopp-err.s | 10 +++---
llvm/test/MC/AMDGPU/sopp-gfx10.s | 2 +-
llvm/test/MC/AMDGPU/sopp-gfx9.s | 2 +-
llvm/test/MC/AMDGPU/sopp.s | 6 ++--
llvm/test/MC/AMDGPU/sym_kernel_scope.s | 2 +-
llvm/test/MC/AMDGPU/sym_kernel_scope_agpr.s | 4 +--
llvm/test/MC/AMDGPU/sym_option.s | 18 +++++------
llvm/test/MC/AMDGPU/trap.s | 18 +++++------
llvm/test/MC/AMDGPU/v_illegal-atomics.s | 4 +--
llvm/test/MC/AMDGPU/vcmpx-gfx10.s | 2 +-
llvm/test/MC/AMDGPU/vintrp-e64-err.s | 6 ++--
llvm/test/MC/AMDGPU/vintrp-err.s | 4 +--
llvm/test/MC/AMDGPU/vintrp.s | 4 +--
llvm/test/MC/AMDGPU/vop-err.s | 4 +--
llvm/test/MC/AMDGPU/vop1-gfx9-err.s | 6 ++--
llvm/test/MC/AMDGPU/vop1-gfx9.s | 8 ++---
llvm/test/MC/AMDGPU/vop1.s | 18 +++++------
llvm/test/MC/AMDGPU/vop2-err.s | 4 +--
llvm/test/MC/AMDGPU/vop2.s | 18 +++++------
llvm/test/MC/AMDGPU/vop3-convert.s | 18 +++++------
llvm/test/MC/AMDGPU/vop3-errs.s | 8 ++---
llvm/test/MC/AMDGPU/vop3-gfx10.s | 2 +-
llvm/test/MC/AMDGPU/vop3-gfx9.s | 16 +++++-----
llvm/test/MC/AMDGPU/vop3-literal.s | 8 ++---
llvm/test/MC/AMDGPU/vop3-modifiers-err.s | 2 +-
llvm/test/MC/AMDGPU/vop3-modifiers.s | 2 +-
llvm/test/MC/AMDGPU/vop3-vop1-nosrc.s | 4 +--
llvm/test/MC/AMDGPU/vop3.s | 16 +++++-----
llvm/test/MC/AMDGPU/vop3p-err.s | 2 +-
llvm/test/MC/AMDGPU/vop3p.s | 2 +-
llvm/test/MC/AMDGPU/vop_dpp.s | 16 +++++-----
llvm/test/MC/AMDGPU/vop_dpp_expr.s | 4 +--
llvm/test/MC/AMDGPU/vop_sdwa.s | 16 +++++-----
llvm/test/MC/AMDGPU/vopc-errs.s | 6 ++--
llvm/test/MC/AMDGPU/vopc-vi.s | 6 ++--
llvm/test/MC/AMDGPU/vopc.s | 6 ++--
llvm/test/MC/AMDGPU/wave32.s | 8 ++---
llvm/test/MC/AMDGPU/wave_any.s | 2 +-
llvm/test/MC/AMDGPU/xdl-insts-err.s | 4 +--
.../MC/AMDGPU/xdl-insts-gfx1011-gfx1012.s | 4 +--
llvm/test/MC/AMDGPU/xdl-insts-gfx908.s | 6 ++--
llvm/test/MC/AMDGPU/xnack-mask.s | 12 +++----
.../AMDGPU/buf_fmt_packed_d16.txt | 4 +--
.../AMDGPU/buf_fmt_unpacked_d16.txt | 2 +-
.../MC/Disassembler/AMDGPU/decode-err.txt | 6 ++--
.../MC/Disassembler/AMDGPU/gfx10-null-reg.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx10-sgpr-max.txt | 2 +-
.../AMDGPU/gfx10-vop2be-literal.txt | 2 +-
.../AMDGPU/gfx10-vop3-literal.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx10-wave32.txt | 4 +--
.../Disassembler/AMDGPU/gfx1011-xdl-insts.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx1011_dlops.txt | 18 +++++------
.../MC/Disassembler/AMDGPU/gfx1030_new.txt | 14 ++++----
llvm/test/MC/Disassembler/AMDGPU/gfx10_ds.txt | 4 +--
.../test/MC/Disassembler/AMDGPU/gfx10_exp.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx10_flat.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx10_mimg.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx10_mtbuf.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx10_mubuf.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx10_smem.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx10_sop1.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx10_sop2.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx10_sopc.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx10_sopk.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx10_sopp.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx10_vop1.txt | 4 +--
.../Disassembler/AMDGPU/gfx10_vop1_dpp16.txt | 4 +--
.../Disassembler/AMDGPU/gfx10_vop1_dpp8.txt | 4 +--
.../Disassembler/AMDGPU/gfx10_vop1_sdwa.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx10_vop2.txt | 4 +--
.../Disassembler/AMDGPU/gfx10_vop2_dpp16.txt | 4 +--
.../Disassembler/AMDGPU/gfx10_vop2_dpp8.txt | 4 +--
.../Disassembler/AMDGPU/gfx10_vop2_sdwa.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx10_vop3.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx10_vop3c.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx10_vop3cx.txt | 4 +--
.../AMDGPU/gfx10_vop3p_literalv216.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx10_vopc.txt | 4 +--
.../Disassembler/AMDGPU/gfx10_vopc_sdwa.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx10_vopcx.txt | 4 +--
.../Disassembler/AMDGPU/gfx10_vopcx_sdwa.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx11_dasm_ds.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx11_dasm_exp.txt | 2 +-
.../Disassembler/AMDGPU/gfx11_dasm_flat.txt | 2 +-
.../Disassembler/AMDGPU/gfx11_dasm_ldsdir.txt | 4 +--
.../Disassembler/AMDGPU/gfx11_dasm_mimg.txt | 2 +-
.../AMDGPU/gfx11_dasm_mimg_features.txt | 2 +-
.../Disassembler/AMDGPU/gfx11_dasm_mtbuf.txt | 2 +-
.../Disassembler/AMDGPU/gfx11_dasm_mubuf.txt | 2 +-
.../Disassembler/AMDGPU/gfx11_dasm_smem.txt | 4 +--
.../Disassembler/AMDGPU/gfx11_dasm_sop1.txt | 4 +--
.../Disassembler/AMDGPU/gfx11_dasm_sop2.txt | 4 +--
.../Disassembler/AMDGPU/gfx11_dasm_sopc.txt | 4 +--
.../Disassembler/AMDGPU/gfx11_dasm_sopk.txt | 4 +--
.../Disassembler/AMDGPU/gfx11_dasm_sopp.txt | 4 +--
.../AMDGPU/gfx11_dasm_vinterp.txt | 2 +-
.../Disassembler/AMDGPU/gfx11_dasm_vop1.txt | 4 +--
.../AMDGPU/gfx11_dasm_vop1_dpp16.txt | 4 +--
.../AMDGPU/gfx11_dasm_vop1_dpp8.txt | 4 +--
.../Disassembler/AMDGPU/gfx11_dasm_vop2.txt | 4 +--
.../AMDGPU/gfx11_dasm_vop2_dpp16.txt | 4 +--
.../AMDGPU/gfx11_dasm_vop2_dpp8.txt | 4 +--
.../Disassembler/AMDGPU/gfx11_dasm_vop3.txt | 4 +--
.../AMDGPU/gfx11_dasm_vop3_dpp16.txt | 4 +--
.../gfx11_dasm_vop3_dpp16_from_vop1.txt | 2 +-
.../gfx11_dasm_vop3_dpp16_from_vop2.txt | 4 +--
.../gfx11_dasm_vop3_dpp16_from_vopc.txt | 4 +--
.../gfx11_dasm_vop3_dpp16_from_vopcx.txt | 4 +--
.../AMDGPU/gfx11_dasm_vop3_dpp8.txt | 4 +--
.../AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt | 2 +-
.../AMDGPU/gfx11_dasm_vop3_dpp8_from_vop2.txt | 4 +--
.../AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt | 4 +--
.../gfx11_dasm_vop3_dpp8_from_vopcx.txt | 4 +--
.../AMDGPU/gfx11_dasm_vop3_from_vop1.txt | 2 +-
.../AMDGPU/gfx11_dasm_vop3_from_vop2.txt | 4 +--
.../AMDGPU/gfx11_dasm_vop3_from_vopc.txt | 4 +--
.../AMDGPU/gfx11_dasm_vop3_from_vopcx.txt | 4 +--
.../Disassembler/AMDGPU/gfx11_dasm_vop3p.txt | 4 +--
.../AMDGPU/gfx11_dasm_vop3p_dpp16.txt | 4 +--
.../AMDGPU/gfx11_dasm_vop3p_dpp8.txt | 4 +--
.../Disassembler/AMDGPU/gfx11_dasm_vopc.txt | 4 +--
.../AMDGPU/gfx11_dasm_vopc_dpp16.txt | 4 +--
.../AMDGPU/gfx11_dasm_vopc_dpp8.txt | 4 +--
.../Disassembler/AMDGPU/gfx11_dasm_vopcx.txt | 4 +--
.../AMDGPU/gfx11_dasm_vopcx_dpp16.txt | 4 +--
.../AMDGPU/gfx11_dasm_vopcx_dpp8.txt | 4 +--
.../Disassembler/AMDGPU/gfx11_dasm_vopd.txt | 2 +-
.../AMDGPU/gfx11_dasm_vopd_features.txt | 2 +-
.../Disassembler/AMDGPU/gfx11_dasm_wmma.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx8-literal.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx8-literal16.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx8-trap.txt | 2 +-
llvm/test/MC/Disassembler/AMDGPU/gfx8_ds.txt | 2 +-
llvm/test/MC/Disassembler/AMDGPU/gfx8_exp.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx8_flat.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx8_mimg.txt | 2 +-
.../AMDGPU/gfx8_mimg_features.txt | 4 +--
.../MC/Disassembler/AMDGPU/gfx8_mtbuf.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx8_mubuf.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx8_smem.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx8_sop1.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx8_sop2.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx8_sopc.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx8_sopk.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx8_sopp.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx8_vintrp.txt | 4 +--
.../test/MC/Disassembler/AMDGPU/gfx8_vop1.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx8_vop1_dpp.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx8_vop1_sdwa.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx8_vop2.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx8_vop2_dpp.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx8_vop2_sdwa.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx8_vop3.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx8_vop3c.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx8_vop3cx.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx8_vopc.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx8_vopc_sdwa.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx8_vopcx.txt | 2 +-
.../Disassembler/AMDGPU/gfx8_vopcx_sdwa.txt | 2 +-
.../AMDGPU/gfx9-aperture-regs.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx9-bool-regs.txt | 2 +-
.../Disassembler/AMDGPU/gfx9-lds_direct.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx9-trap.txt | 2 +-
.../AMDGPU/gfx908-atomic-fadd-insts.txt | 2 +-
.../Disassembler/AMDGPU/gfx908-dl-insts.txt | 4 +--
.../Disassembler/AMDGPU/gfx908-xdl-insts.txt | 6 ++--
.../MC/Disassembler/AMDGPU/gfx908_mai.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx90a-dpp64.txt | 2 +-
.../Disassembler/AMDGPU/gfx90a_features.txt | 2 +-
.../Disassembler/AMDGPU/gfx90a_ldst_acc.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx90a_mai.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx90a_mimg.txt | 2 +-
.../Disassembler/AMDGPU/gfx940_features.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx940_flat.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx940_mai.txt | 2 +-
llvm/test/MC/Disassembler/AMDGPU/gfx9_ds.txt | 2 +-
llvm/test/MC/Disassembler/AMDGPU/gfx9_exp.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx9_flat.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx9_mimg.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx9_mubuf.txt | 2 +-
.../AMDGPU/gfx9_sdwa_features.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx9_smem.txt | 2 +-
.../AMDGPU/gfx9_smem_features.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx9_sop1.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx9_sop2.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx9_sopc.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx9_sopk.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx9_sopp.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx9_vintrp.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx9_vop1.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx9_vop1_dpp.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx9_vop1_sdwa.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx9_vop2.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx9_vop2_dpp.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx9_vop2_sdwa.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx9_vop3.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx9_vop3c.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx9_vop3cx.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx9_vop3p.txt | 2 +-
.../Disassembler/AMDGPU/gfx9_vop3p_opsel.txt | 2 +-
.../test/MC/Disassembler/AMDGPU/gfx9_vopc.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx9_vopc_sdwa.txt | 2 +-
.../MC/Disassembler/AMDGPU/gfx9_vopcx.txt | 2 +-
.../Disassembler/AMDGPU/gfx9_vopcx_sdwa.txt | 2 +-
llvm/test/MC/Disassembler/AMDGPU/mad_mix.txt | 4 +--
.../MC/Disassembler/AMDGPU/si-support.txt | 2 +-
.../Mips/micromips32r3/valid-fp64-el.txt | 2 +-
.../Mips/micromips32r3/valid-fp64.txt | 2 +-
.../Mips/mips32/valid-fp64-el.txt | 2 +-
.../Disassembler/Mips/mips32/valid-fp64.txt | 2 +-
.../Mips/mips32r2/valid-fp64-el.txt | 2 +-
.../Disassembler/Mips/mips32r2/valid-fp64.txt | 2 +-
.../Mips/mips32r3/valid-fp64-el.txt | 2 +-
.../Disassembler/Mips/mips32r3/valid-fp64.txt | 2 +-
.../Mips/mips32r5/valid-fp64-el.txt | 2 +-
.../Disassembler/Mips/mips32r5/valid-fp64.txt | 2 +-
llvm/test/MC/Hexagon/J2_trap1_dep.s | 4 +--
.../MC/Hexagon/PacketRules/bundle_option.s | 2 +-
.../MC/Hexagon/PacketRules/hvx_vshuff_vdeal.s | 2 +-
.../PacketRules/hvx_vshuff_vdeal_dup.s | 2 +-
.../Hexagon/PacketRules/newvalue_producers.s | 2 +-
.../PacketRules/newvalue_producers_pass.s | 2 +-
.../Hexagon/PacketRules/registers_readonly.s | 2 +-
.../test/MC/Hexagon/PacketRules/restrict_ax.s | 2 +-
.../restrict_no_slot1_store_pass.s | 2 +-
.../Hexagon/PacketRules/restrict_slot1_aok.s | 2 +-
.../PacketRules/restrict_slot1_aok_pass.s | 2 +-
llvm/test/MC/Hexagon/PacketRules/solo.s | 2 +-
llvm/test/MC/Hexagon/arch-support.s | 32 +++++++++----------
llvm/test/MC/Hexagon/bug15961.s | 2 +-
llvm/test/MC/Hexagon/bug18767.s | 2 +-
llvm/test/MC/Hexagon/bug24609.s | 2 +-
llvm/test/MC/Hexagon/bug28416.s | 2 +-
llvm/test/MC/Hexagon/bug_28748.s | 2 +-
llvm/test/MC/Hexagon/c4_newval.s | 2 +-
llvm/test/MC/Hexagon/cmpyrw.s | 2 +-
llvm/test/MC/Hexagon/common-redeclare.s | 2 +-
llvm/test/MC/Hexagon/dcfetch-symbol.s | 2 +-
llvm/test/MC/Hexagon/dealloc-return-jump.s | 2 +-
llvm/test/MC/Hexagon/decode_acc_type.s | 2 +-
llvm/test/MC/Hexagon/dis-duplex-p0.s | 2 +-
llvm/test/MC/Hexagon/double-vector-producer.s | 2 +-
llvm/test/MC/Hexagon/duplex-addi-global-imm.s | 2 +-
llvm/test/MC/Hexagon/elf-flags.s | 8 ++---
llvm/test/MC/Hexagon/equ.s | 2 +-
llvm/test/MC/Hexagon/ext-callt-rel.s | 2 +-
llvm/test/MC/Hexagon/extender.s | 2 +-
llvm/test/MC/Hexagon/extensions/v67_hvx.s | 2 +-
llvm/test/MC/Hexagon/extensions/v67t_audio.s | 2 +-
llvm/test/MC/Hexagon/fixups.s | 2 +-
llvm/test/MC/Hexagon/got.s | 2 +-
llvm/test/MC/Hexagon/gprel-shflag.s | 2 +-
llvm/test/MC/Hexagon/guest.s | 2 +-
llvm/test/MC/Hexagon/hex-immediates.s | 2 +-
llvm/test/MC/Hexagon/hvx-double-implies-hvx.s | 2 +-
.../Hexagon/hvx-swapped-regpairs-alias-neg.s | 2 +-
llvm/test/MC/Hexagon/hvx-swapped-regpairs.s | 4 +--
llvm/test/MC/Hexagon/hvx-tmp-accum-no-erros.s | 2 +-
llvm/test/MC/Hexagon/hvx-tmp-accum.s | 2 +-
llvm/test/MC/Hexagon/hvx_cur_alias.s | 2 +-
llvm/test/MC/Hexagon/inval_immed.s | 2 +-
llvm/test/MC/Hexagon/load-GPRel.s | 2 +-
llvm/test/MC/Hexagon/missing_label.s | 2 +-
llvm/test/MC/Hexagon/multiple-pc4.s | 2 +-
llvm/test/MC/Hexagon/multiple_errs.s | 2 +-
llvm/test/MC/Hexagon/non-relocatable.s | 2 +-
llvm/test/MC/Hexagon/not-over.s | 2 +-
llvm/test/MC/Hexagon/not_found.s | 2 +-
llvm/test/MC/Hexagon/nowarn.s | 6 ++--
llvm/test/MC/Hexagon/offset.s | 2 +-
llvm/test/MC/Hexagon/operand-range.s | 2 +-
llvm/test/MC/Hexagon/parse-pound-hi.s | 2 +-
llvm/test/MC/Hexagon/pcrel.s | 2 +-
llvm/test/MC/Hexagon/plt-rel.s | 2 +-
llvm/test/MC/Hexagon/quad_regs.s | 2 +-
llvm/test/MC/Hexagon/register-alt-names.s | 2 +-
llvm/test/MC/Hexagon/registers_readonly.s | 2 +-
llvm/test/MC/Hexagon/ro-c9.s | 2 +-
llvm/test/MC/Hexagon/ro-cc9.s | 2 +-
llvm/test/MC/Hexagon/smallcore_dis.s | 4 +--
llvm/test/MC/Hexagon/solo-axok.s | 2 +-
llvm/test/MC/Hexagon/store-GPRel.s | 2 +-
llvm/test/MC/Hexagon/sysregs.s | 2 +-
llvm/test/MC/Hexagon/sysregs2.s | 2 +-
llvm/test/MC/Hexagon/sysregs3.s | 2 +-
llvm/test/MC/Hexagon/tied-ops.s | 2 +-
llvm/test/MC/Hexagon/tprel_noextend.s | 2 +-
llvm/test/MC/Hexagon/two-extenders.s | 2 +-
llvm/test/MC/Hexagon/v60-misc.s | 2 +-
llvm/test/MC/Hexagon/v62_all.s | 2 +-
llvm/test/MC/Hexagon/v62_jumps.s | 2 +-
llvm/test/MC/Hexagon/v62a.s | 2 +-
llvm/test/MC/Hexagon/v62a_regs.s | 4 +--
llvm/test/MC/Hexagon/v65_all.s | 2 +-
llvm/test/MC/Hexagon/v66.s | 2 +-
llvm/test/MC/Hexagon/v67.s | 2 +-
llvm/test/MC/Hexagon/v67_all.s | 2 +-
llvm/test/MC/Hexagon/v67t_align.s | 2 +-
llvm/test/MC/Hexagon/v67t_arch.s | 4 +--
llvm/test/MC/Hexagon/v67t_option.s | 2 +-
llvm/test/MC/Hexagon/vgather-new.s | 2 +-
llvm/test/MC/Hexagon/vpred_defs.s | 2 +-
llvm/test/MC/Hexagon/vscatter-slot.s | 2 +-
llvm/test/MC/Hexagon/vtmp_def.s | 2 +-
llvm/test/MC/Hexagon/z-instructions.s | 2 +-
llvm/test/MC/Hexagon/zreg-post-inc.s | 2 +-
llvm/test/MC/Lanai/conditional_inst.s | 2 +-
llvm/test/MC/Lanai/memory.s | 2 +-
llvm/test/MC/Lanai/v11.s | 2 +-
llvm/test/MC/Mips/bopt-directive.s | 2 +-
llvm/test/MC/Mips/branch-pseudos-bad.s | 2 +-
llvm/test/MC/Mips/branch-pseudos.s | 4 +--
llvm/test/MC/Mips/cpload-bad.s | 2 +-
llvm/test/MC/Mips/cprestore-bad.s | 2 +-
llvm/test/MC/Mips/crc/invalid.s | 4 +--
llvm/test/MC/Mips/crc/module-nocrc.s | 4 +--
llvm/test/MC/Mips/elf_basic.s | 4 +--
llvm/test/MC/Mips/end-directive.s | 2 +-
llvm/test/MC/Mips/ginv/module-noginv.s | 4 +--
llvm/test/MC/Mips/insn-directive.s | 4 +--
llvm/test/MC/Mips/macro-aliases.s | 2 +-
llvm/test/MC/Mips/macro-bcc-imm-bad.s | 2 +-
llvm/test/MC/Mips/macro-bcc-imm.s | 2 +-
llvm/test/MC/Mips/macro-ddiv-bad.s | 8 ++---
llvm/test/MC/Mips/macro-ddivu-bad.s | 8 ++---
llvm/test/MC/Mips/macro-div-bad.s | 8 ++---
llvm/test/MC/Mips/macro-divu-bad.s | 8 ++---
llvm/test/MC/Mips/macro-dla-bad.s | 2 +-
llvm/test/MC/Mips/macro-la-bad.s | 6 ++--
llvm/test/MC/Mips/macro-li-bad.s | 6 ++--
llvm/test/MC/Mips/macro-seq.s | 4 +--
llvm/test/MC/Mips/macro-sge.s | 4 +--
llvm/test/MC/Mips/macro-sge64.s | 4 +--
llvm/test/MC/Mips/macro-sgt.s | 4 +--
llvm/test/MC/Mips/macro-sgt64.s | 4 +--
llvm/test/MC/Mips/macro-sle.s | 4 +--
llvm/test/MC/Mips/macro-sle64.s | 4 +--
llvm/test/MC/Mips/macro-sne.s | 4 +--
llvm/test/MC/Mips/memory-offsets.s | 2 +-
llvm/test/MC/Mips/micromips-bad-branches.s | 2 +-
.../test/MC/Mips/micromips-diagnostic-fixup.s | 2 +-
llvm/test/MC/Mips/micromips-pc16-fixup.s | 2 +-
llvm/test/MC/Mips/micromips64-unsupported.s | 8 ++---
llvm/test/MC/Mips/mips-bad-branches.s | 2 +-
llvm/test/MC/Mips/mips-data-directives.s | 4 +--
llvm/test/MC/Mips/mips-diagnostic-fixup.s | 2 +-
llvm/test/MC/Mips/mips-expansions-bad.s | 6 ++--
llvm/test/MC/Mips/mips-pc16-fixup.s | 2 +-
llvm/test/MC/Mips/mips-pdr-bad.s | 2 +-
llvm/test/MC/Mips/mips-pdr.s | 4 +--
llvm/test/MC/Mips/mips-reginfo-fp32.s | 2 +-
llvm/test/MC/Mips/mips-reginfo-fp64.s | 6 ++--
llvm/test/MC/Mips/mips16/invalid.s | 2 +-
llvm/test/MC/Mips/mips16/valid.s | 2 +-
llvm/test/MC/Mips/mips32r2/valid-fp64.s | 2 +-
llvm/test/MC/Mips/mips32r3/valid-fp64.s | 2 +-
llvm/test/MC/Mips/mips32r5/valid-fp64.s | 2 +-
llvm/test/MC/Mips/mips64/abiflags.s | 4 +--
llvm/test/MC/Mips/mips64extins.s | 4 +--
llvm/test/MC/Mips/mips64r2/abiflags.s | 4 +--
llvm/test/MC/Mips/mips64r3/abiflags.s | 4 +--
llvm/test/MC/Mips/mips64r5/abiflags.s | 4 +--
llvm/test/MC/Mips/module-softfloat.s | 4 +--
llvm/test/MC/Mips/msa/set-msa-directive-bad.s | 2 +-
llvm/test/MC/Mips/msa/set-msa-directive.s | 2 +-
llvm/test/MC/Mips/msa/test_2r.s | 2 +-
llvm/test/MC/Mips/msa/test_2r_msa64.s | 2 +-
llvm/test/MC/Mips/msa/test_2rf.s | 2 +-
llvm/test/MC/Mips/msa/test_3r.s | 2 +-
llvm/test/MC/Mips/msa/test_3rf.s | 2 +-
llvm/test/MC/Mips/msa/test_bit.s | 2 +-
llvm/test/MC/Mips/msa/test_cbranch.s | 2 +-
llvm/test/MC/Mips/msa/test_ctrlregs.s | 2 +-
llvm/test/MC/Mips/msa/test_dlsa.s | 2 +-
llvm/test/MC/Mips/msa/test_elm.s | 2 +-
llvm/test/MC/Mips/msa/test_elm_insert.s | 2 +-
llvm/test/MC/Mips/msa/test_elm_insert_msa64.s | 2 +-
llvm/test/MC/Mips/msa/test_elm_insve.s | 2 +-
llvm/test/MC/Mips/msa/test_elm_msa64.s | 2 +-
llvm/test/MC/Mips/msa/test_i10.s | 2 +-
llvm/test/MC/Mips/msa/test_i5.s | 2 +-
llvm/test/MC/Mips/msa/test_i8.s | 2 +-
llvm/test/MC/Mips/msa/test_lsa.s | 2 +-
llvm/test/MC/Mips/msa/test_mi10.s | 2 +-
llvm/test/MC/Mips/msa/test_vec.s | 2 +-
llvm/test/MC/Mips/mt/abiflag.s | 2 +-
llvm/test/MC/Mips/mt/invalid-wrong-error.s | 2 +-
llvm/test/MC/Mips/mt/invalid.s | 2 +-
.../mftr-mttr-aliases-invalid-wrong-error.s | 2 +-
.../MC/Mips/mt/mftr-mttr-aliases-invalid.s | 2 +-
llvm/test/MC/Mips/mt/mftr-mttr-aliases.s | 2 +-
.../MC/Mips/mt/mftr-mttr-reserved-valid.s | 2 +-
.../MC/Mips/mt/module-directive-invalid.s | 2 +-
llvm/test/MC/Mips/mt/module-directive.s | 4 +--
llvm/test/MC/Mips/mt/set-directive.s | 4 +--
llvm/test/MC/Mips/mt/valid.s | 2 +-
llvm/test/MC/Mips/rotations32-bad.s | 10 +++---
llvm/test/MC/Mips/rotations32.s | 10 +++---
llvm/test/MC/Mips/rotations64.s | 10 +++---
llvm/test/MC/Mips/set-defined-symbol.s | 2 +-
llvm/test/MC/Mips/set-mips16-directive.s | 2 +-
llvm/test/MC/Mips/set-nomacro.s | 2 +-
llvm/test/MC/Mips/tls-symbols.s | 4 +--
llvm/test/MC/Mips/virt/invalid64.s | 2 +-
llvm/test/MC/Mips/virt/module-novirt.s | 4 +--
llvm/test/MC/Sparc/leon-instructions.s | 10 +++---
llvm/test/MC/Sparc/leon-pwrpsr-instruction.s | 2 +-
llvm/test/MC/Sparc/sparc-alu-instructions.s | 4 +--
llvm/test/MC/Sparc/sparc-asm-errors.s | 4 +--
llvm/test/MC/Sparc/sparc-assembly-exprs.s | 6 ++--
.../test/MC/Sparc/sparc-atomic-instructions.s | 4 +--
llvm/test/MC/Sparc/sparc-cas-instructions.s | 6 ++--
llvm/test/MC/Sparc/sparc-coproc.s | 2 +-
llvm/test/MC/Sparc/sparc-ctrl-instructions.s | 4 +--
llvm/test/MC/Sparc/sparc-directive-xword.s | 2 +-
llvm/test/MC/Sparc/sparc-directives.s | 4 +--
llvm/test/MC/Sparc/sparc-fixups.s | 2 +-
llvm/test/MC/Sparc/sparc-fp-instructions.s | 2 +-
.../MC/Sparc/sparc-mem-asi-instructions.s | 4 +--
llvm/test/MC/Sparc/sparc-mem-instructions.s | 4 +--
llvm/test/MC/Sparc/sparc-misc-instructions.s | 4 +--
llvm/test/MC/Sparc/sparc-nop-data.s | 4 +--
llvm/test/MC/Sparc/sparc-pic.s | 4 +--
llvm/test/MC/Sparc/sparc-relocations.s | 4 +--
llvm/test/MC/Sparc/sparc-special-registers.s | 4 +--
.../MC/Sparc/sparc-synthetic-instructions.s | 8 ++---
llvm/test/MC/Sparc/sparc-tls-relocations.s | 12 +++----
llvm/test/MC/Sparc/sparc-traps.s | 2 +-
llvm/test/MC/Sparc/sparc-v9-traps.s | 2 +-
llvm/test/MC/Sparc/sparc-vis.s | 2 +-
llvm/test/MC/Sparc/sparc64-bpr-offset.s | 2 +-
llvm/test/MC/Sparc/sparcv8-instructions.s | 2 +-
llvm/test/MC/Sparc/sparcv9-asi-names.s | 2 +-
.../MC/Sparc/sparcv9-atomic-instructions.s | 2 +-
llvm/test/MC/Sparc/sparcv9-instructions.s | 4 +--
.../MC/Sparc/sparcv9-synthetic-instructions.s | 4 +--
llvm/test/Object/AMDGPU/objdump.s | 2 +-
706 files changed, 1402 insertions(+), 1402 deletions(-)
diff --git a/llvm/test/MC/AMDGPU/accvgpr-altnames.s b/llvm/test/MC/AMDGPU/accvgpr-altnames.s
index b0445f0192860b3..0a2dd642e50dfb9 100644
--- a/llvm/test/MC/AMDGPU/accvgpr-altnames.s
+++ b/llvm/test/MC/AMDGPU/accvgpr-altnames.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck -check-prefix=GFX908 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck -check-prefix=GFX908 %s
v_accvgpr_read_b32 v2, acc0
// GFX908: v_accvgpr_read_b32 v2, a0 ; encoding: [0x02,0x40,0xd8,0xd3,0x00,0x01,0x00,0x18]
diff --git a/llvm/test/MC/AMDGPU/add-sub-no-carry.s b/llvm/test/MC/AMDGPU/add-sub-no-carry.s
index 674efc44b8869b3..741749b85530ee8 100644
--- a/llvm/test/MC/AMDGPU/add-sub-no-carry.s
+++ b/llvm/test/MC/AMDGPU/add-sub-no-carry.s
@@ -1,7 +1,7 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GFX9 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GFX9 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck --check-prefix=ERR-VI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck --check-prefix=ERR-SICI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji %s 2>&1 | FileCheck --check-prefix=ERR-VI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck --check-prefix=ERR-SICI --implicit-check-not=error: %s
// FIXME: pre-gfx9 errors should be more useful
diff --git a/llvm/test/MC/AMDGPU/atomic-fadd-insts.s b/llvm/test/MC/AMDGPU/atomic-fadd-insts.s
index 4b892a64d4916f1..e112cce30cffe1b 100644
--- a/llvm/test/MC/AMDGPU/atomic-fadd-insts.s
+++ b/llvm/test/MC/AMDGPU/atomic-fadd-insts.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck --check-prefix=GFX908 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck --check-prefix=GFX908-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck --check-prefix=GFX908 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck --check-prefix=GFX908-ERR --implicit-check-not=error: %s
buffer_atomic_add_f32 v5, off, s[8:11], s3 offset:4095
// GFX908: encoding: [0xff,0x0f,0x34,0xe1,0x00,0x05,0x02,0x03]
diff --git a/llvm/test/MC/AMDGPU/branch-comment.s b/llvm/test/MC/AMDGPU/branch-comment.s
index 443f0b308580901..bb5547bce1fee7b 100644
--- a/llvm/test/MC/AMDGPU/branch-comment.s
+++ b/llvm/test/MC/AMDGPU/branch-comment.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -filetype=obj %s | llvm-objcopy -S -K keep_symbol - | llvm-objdump -d --mcpu=fiji - | FileCheck %s --check-prefix=BIN
+// RUN: llvm-mc -triple=amdgcn -mcpu=fiji -filetype=obj %s | llvm-objcopy -S -K keep_symbol - | llvm-objdump -d --mcpu=fiji - | FileCheck %s --check-prefix=BIN
// FIXME: Immediate operands to sopp_br instructions are currently scaled by a
// factor of 4, are unsigned, are always PC relative, don't accept most
diff --git a/llvm/test/MC/AMDGPU/buf-fmt-d16-packed.s b/llvm/test/MC/AMDGPU/buf-fmt-d16-packed.s
index 6821547c5cbb092..3c236d67927c514 100644
--- a/llvm/test/MC/AMDGPU/buf-fmt-d16-packed.s
+++ b/llvm/test/MC/AMDGPU/buf-fmt-d16-packed.s
@@ -1,7 +1,7 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx810 -show-encoding %s | FileCheck -check-prefix=PACKED %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=PACKED %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx810 -show-encoding %s | FileCheck -check-prefix=PACKED %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=PACKED %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji 2>&1 %s | FileCheck -check-prefix=UNPACKED-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji 2>&1 %s | FileCheck -check-prefix=UNPACKED-ERR --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AMDGPU/buf-fmt-d16-unpacked.s b/llvm/test/MC/AMDGPU/buf-fmt-d16-unpacked.s
index a6baee79c132333..779152d5c69b921 100644
--- a/llvm/test/MC/AMDGPU/buf-fmt-d16-unpacked.s
+++ b/llvm/test/MC/AMDGPU/buf-fmt-d16-unpacked.s
@@ -1,6 +1,6 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck -check-prefix=UNPACKED %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx810 2>&1 %s | FileCheck -check-prefix=PACKED-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 2>&1 %s | FileCheck -check-prefix=PACKED-ERR --implicit-check-not=error: %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck -check-prefix=UNPACKED %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx810 2>&1 %s | FileCheck -check-prefix=PACKED-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 2>&1 %s | FileCheck -check-prefix=PACKED-ERR --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AMDGPU/buffer_wbinv1l_vol_vi.s b/llvm/test/MC/AMDGPU/buffer_wbinv1l_vol_vi.s
index 144818481b03fe5..c0e929898655cf2 100644
--- a/llvm/test/MC/AMDGPU/buffer_wbinv1l_vol_vi.s
+++ b/llvm/test/MC/AMDGPU/buffer_wbinv1l_vol_vi.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
buffer_wbinvl1_vol
// VI: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xfc,0xe0,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/cpol-err.s b/llvm/test/MC/AMDGPU/cpol-err.s
index 2de359b8c461d03..a5fffeb5a6e4de3 100644
--- a/llvm/test/MC/AMDGPU/cpol-err.s
+++ b/llvm/test/MC/AMDGPU/cpol-err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
scratch_load_ubyte v1, v2, off cpol:2
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
diff --git a/llvm/test/MC/AMDGPU/dl-insts-err.s b/llvm/test/MC/AMDGPU/dl-insts-err.s
index a57ea66a9b5fbb2..56a3cca199785cf 100644
--- a/llvm/test/MC/AMDGPU/dl-insts-err.s
+++ b/llvm/test/MC/AMDGPU/dl-insts-err.s
@@ -1,8 +1,8 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx800 %s 2>&1 | FileCheck %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx906 %s 2>&1 | FileCheck %s --check-prefix=GFX906-GFX908
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck %s --check-prefix=GFX906-GFX908
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1013 %s 2>&1 | FileCheck %s --check-prefix=GFX1013
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx800 %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx906 %s 2>&1 | FileCheck %s --check-prefix=GFX906-GFX908
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck %s --check-prefix=GFX906-GFX908
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1013 %s 2>&1 | FileCheck %s --check-prefix=GFX1013
//
// Test unsupported GPUs.
diff --git a/llvm/test/MC/AMDGPU/dl-insts.s b/llvm/test/MC/AMDGPU/dl-insts.s
index fee1566a351f5d2..00e9bec7eb0a239 100644
--- a/llvm/test/MC/AMDGPU/dl-insts.s
+++ b/llvm/test/MC/AMDGPU/dl-insts.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx906 -show-encoding %s | FileCheck %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx906 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck %s
//
// VOP2 Instructions.
diff --git a/llvm/test/MC/AMDGPU/dpp-err.s b/llvm/test/MC/AMDGPU/dpp-err.s
index 5e22993d7be7c4b..65279fb82ba5b8d 100644
--- a/llvm/test/MC/AMDGPU/dpp-err.s
+++ b/llvm/test/MC/AMDGPU/dpp-err.s
@@ -1,9 +1,9 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GFX89 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX89 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GFX89-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX89-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefix=GFX10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GFX89 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX89 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GFX89-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX89-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefix=GFX10-ERR --implicit-check-not=error: %s
v_mov_b32_dpp v0, v1 row_share:1 row_mask:0x1 bank_mask:0x1
// GFX89-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
diff --git a/llvm/test/MC/AMDGPU/dpp64.s b/llvm/test/MC/AMDGPU/dpp64.s
index 6fb781d7e535ab5..b915dff06f06b64 100644
--- a/llvm/test/MC/AMDGPU/dpp64.s
+++ b/llvm/test/MC/AMDGPU/dpp64.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck %s --check-prefix=GFX90A
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=GFX900 --implicit-check-not=error:
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck %s --check-prefix=GFX90A
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=GFX900 --implicit-check-not=error:
// GFX90A: v_ceil_f64_dpp v[0:1], v[2:3] row_newbcast:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x30,0x00,0x7e,0x02,0x51,0x01,0xff]
// GFX900: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand.
diff --git a/llvm/test/MC/AMDGPU/ds-err.s b/llvm/test/MC/AMDGPU/ds-err.s
index e8541bc9a575840..bc2a2fff354ffe0 100644
--- a/llvm/test/MC/AMDGPU/ds-err.s
+++ b/llvm/test/MC/AMDGPU/ds-err.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --implicit-check-not=error: %s
// offset too big
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/ds-gfx9.s b/llvm/test/MC/AMDGPU/ds-gfx9.s
index 4f0caef4e8f96bf..54e619cd5e01529 100644
--- a/llvm/test/MC/AMDGPU/ds-gfx9.s
+++ b/llvm/test/MC/AMDGPU/ds-gfx9.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga 2>&1 %s | FileCheck -check-prefix=VI-ERR --implicit-check-not=error: %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga 2>&1 %s | FileCheck -check-prefix=VI-ERR --implicit-check-not=error: %s
ds_read_u8_d16 v8, v2
// GFX9: ds_read_u8_d16 v8, v2 ; encoding: [0x00,0x00,0xac,0xd8,0x02,0x00,0x00,0x08]
diff --git a/llvm/test/MC/AMDGPU/ds.s b/llvm/test/MC/AMDGPU/ds.s
index ec5b063a7e26f57..fd436fe9fe0ddbc 100644
--- a/llvm/test/MC/AMDGPU/ds.s
+++ b/llvm/test/MC/AMDGPU/ds.s
@@ -1,11 +1,11 @@
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefixes=CI,SICI
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
-
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefixes=CI,SICI
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
+
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
//===----------------------------------------------------------------------===//
// Checks for 16-bit Offsets
diff --git a/llvm/test/MC/AMDGPU/elf-notes-verify-amdgcn.s b/llvm/test/MC/AMDGPU/elf-notes-verify-amdgcn.s
index dc72bbb2a2313dd..8eb1ac6d46124a7 100644
--- a/llvm/test/MC/AMDGPU/elf-notes-verify-amdgcn.s
+++ b/llvm/test/MC/AMDGPU/elf-notes-verify-amdgcn.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch amdgcn %s 2>&1 | FileCheck --check-prefix=GCN %s
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck --check-prefix=GCN %s
// GCN: :[[@LINE+1]]:{{[0-9]+}}: error: .amd_amdgpu_hsa_metadata directive is not available on non-amdhsa OSes
.amd_amdgpu_hsa_metadata
diff --git a/llvm/test/MC/AMDGPU/elf-notes-verify-r600.s b/llvm/test/MC/AMDGPU/elf-notes-verify-r600.s
index 47ab1607580c052..f6f936260b53b67 100644
--- a/llvm/test/MC/AMDGPU/elf-notes-verify-r600.s
+++ b/llvm/test/MC/AMDGPU/elf-notes-verify-r600.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch r600 %s 2>&1 | FileCheck --check-prefix=R600 %s
+// RUN: not llvm-mc -triple=r600 %s 2>&1 | FileCheck --check-prefix=R600 %s
// R600: :[[@LINE+1]]:{{[0-9]+}}: error: .amd_amdgpu_isa directive is not available on non-amdgcn architectures
.amd_amdgpu_isa "r600"
diff --git a/llvm/test/MC/AMDGPU/exp-err.s b/llvm/test/MC/AMDGPU/exp-err.s
index c7df7b424f2cdf4..5d84f22a5714edb 100644
--- a/llvm/test/MC/AMDGPU/exp-err.s
+++ b/llvm/test/MC/AMDGPU/exp-err.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefixes=GCN,GFX68 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefixes=GCN,GFX68 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck -check-prefixes=GCN,GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck -check-prefixes=GCN,GFX68 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefixes=GCN,GFX68 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck -check-prefixes=GCN,GFX11 --implicit-check-not=error: %s
exp mrt8 v3, v2, v1, v0
// GCN: :[[@LINE-1]]:5: error: invalid exp target
diff --git a/llvm/test/MC/AMDGPU/exp-gfx10.s b/llvm/test/MC/AMDGPU/exp-gfx10.s
index 5e503efff1a236b..295d85f218034b4 100644
--- a/llvm/test/MC/AMDGPU/exp-gfx10.s
+++ b/llvm/test/MC/AMDGPU/exp-gfx10.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=verde %s 2>&1 | FileCheck -check-prefix=SIVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=SIVI --implicit-check-not=error: %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=verde %s 2>&1 | FileCheck -check-prefix=SIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=SIVI --implicit-check-not=error: %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
exp prim v1, off, off, off
// SIVI: :[[@LINE-1]]:5: error: exp target is not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/exp-pregfx11.s b/llvm/test/MC/AMDGPU/exp-pregfx11.s
index 8a8d0bfc42ef445..5cd491646637bde 100644
--- a/llvm/test/MC/AMDGPU/exp-pregfx11.s
+++ b/llvm/test/MC/AMDGPU/exp-pregfx11.s
@@ -1,7 +1,7 @@
-// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck -check-prefix=SI %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GFX89 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX89 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -show-encoding %s | FileCheck -check-prefix=SI %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GFX89 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX89 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
exp null v4, v3, v2, v1
// SI: exp null v4, v3, v2, v1 ; encoding: [0x9f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
diff --git a/llvm/test/MC/AMDGPU/exp.s b/llvm/test/MC/AMDGPU/exp.s
index 321075057a21ad1..a2fa09b71496c67 100644
--- a/llvm/test/MC/AMDGPU/exp.s
+++ b/llvm/test/MC/AMDGPU/exp.s
@@ -1,8 +1,8 @@
-// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck -check-prefix=SI %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GFX89 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX89 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -show-encoding %s | FileCheck -check-prefix=SI %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GFX89 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX89 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
exp mrt0 off, off, off, off
// SI: exp mrt0 off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/expressions-gfx10.s b/llvm/test/MC/AMDGPU/expressions-gfx10.s
index e4e91b16359f6b4..fc029a3d8e51916 100644
--- a/llvm/test/MC/AMDGPU/expressions-gfx10.s
+++ b/llvm/test/MC/AMDGPU/expressions-gfx10.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck %s --check-prefix=GFX10
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck -check-prefix=NOGFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck %s --check-prefix=GFX10
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck -check-prefix=NOGFX10 --implicit-check-not=error: %s
i1=1
diff --git a/llvm/test/MC/AMDGPU/expressions-gfx9.s b/llvm/test/MC/AMDGPU/expressions-gfx9.s
index b1ba10429c1a39b..903053b2ddab57a 100644
--- a/llvm/test/MC/AMDGPU/expressions-gfx9.s
+++ b/llvm/test/MC/AMDGPU/expressions-gfx9.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=NOGFX9 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=NOGFX9 --implicit-check-not=error:
//===----------------------------------------------------------------------===//
// Relocatable expressions cannot be used with SDWA modifiers.
diff --git a/llvm/test/MC/AMDGPU/expressions.s b/llvm/test/MC/AMDGPU/expressions.s
index bd04c71f49508f0..5df128a122af07a 100644
--- a/llvm/test/MC/AMDGPU/expressions.s
+++ b/llvm/test/MC/AMDGPU/expressions.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck %s --check-prefix=NOVI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji %s 2>&1 | FileCheck %s --check-prefix=NOVI --implicit-check-not=error:
//===----------------------------------------------------------------------===//
// Floating-point expressions are not supported
diff --git a/llvm/test/MC/AMDGPU/flat-gfx10.s b/llvm/test/MC/AMDGPU/flat-gfx10.s
index b5e0febcf910ae5..80aedced88f4008 100644
--- a/llvm/test/MC/AMDGPU/flat-gfx10.s
+++ b/llvm/test/MC/AMDGPU/flat-gfx10.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefix=GFX10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefix=GFX10-ERR --implicit-check-not=error: %s
flat_load_dword v1, v[3:4]
// GFX10: encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x7d,0x01]
diff --git a/llvm/test/MC/AMDGPU/flat-gfx9.s b/llvm/test/MC/AMDGPU/flat-gfx9.s
index 779e6c8e54f24ad..23f508669bc0e84 100644
--- a/llvm/test/MC/AMDGPU/flat-gfx9.s
+++ b/llvm/test/MC/AMDGPU/flat-gfx9.s
@@ -1,8 +1,8 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 2>&1 %s | FileCheck -check-prefix=GFX9-ERR -check-prefix=GCNERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga 2>&1 %s | FileCheck -check-prefix=VI-ERR -check-prefix=GCNERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 2>&1 %s | FileCheck -check-prefix=GFX9-ERR -check-prefix=GCNERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga 2>&1 %s | FileCheck -check-prefix=VI-ERR -check-prefix=GCNERR --implicit-check-not=error: %s
flat_load_dword v1, v[3:4] offset:0
diff --git a/llvm/test/MC/AMDGPU/flat-global.s b/llvm/test/MC/AMDGPU/flat-global.s
index 284ebd46a347954..e81fae86b055833 100644
--- a/llvm/test/MC/AMDGPU/flat-global.s
+++ b/llvm/test/MC/AMDGPU/flat-global.s
@@ -1,9 +1,9 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefixes=GFX9,GCN %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 2>&1 %s | FileCheck -check-prefix=GFX9-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga 2>&1 %s | FileCheck -check-prefix=VI-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefixes=GFX9,GCN %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 2>&1 %s | FileCheck -check-prefix=GFX9-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga 2>&1 %s | FileCheck -check-prefix=VI-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefix=GFX10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefix=GFX10-ERR --implicit-check-not=error: %s
global_load_ubyte v1, v[3:4], off
// GFX10: encoding: [0x00,0x80,0x20,0xdc,0x03,0x00,0x7d,0x01]
diff --git a/llvm/test/MC/AMDGPU/flat-scratch-gfx940.s b/llvm/test/MC/AMDGPU/flat-scratch-gfx940.s
index 3af48bcd8ea189a..fde3d2057b2ad13 100644
--- a/llvm/test/MC/AMDGPU/flat-scratch-gfx940.s
+++ b/llvm/test/MC/AMDGPU/flat-scratch-gfx940.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -show-encoding %s | FileCheck -check-prefix=GFX940 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx940 -show-encoding %s | FileCheck -check-prefix=GFX940 %s
scratch_load_dword a2, v4, s6
// GFX940: scratch_load_dword a2, v4, s6 ; encoding: [0x00,0x60,0x50,0xdc,0x04,0x00,0x86,0x02]
diff --git a/llvm/test/MC/AMDGPU/flat-scratch-instructions.s b/llvm/test/MC/AMDGPU/flat-scratch-instructions.s
index 512cf69aee0b1de..607d0d1abdade87 100644
--- a/llvm/test/MC/AMDGPU/flat-scratch-instructions.s
+++ b/llvm/test/MC/AMDGPU/flat-scratch-instructions.s
@@ -1,9 +1,9 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 2>&1 %s | FileCheck -check-prefix=GFX9-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga 2>&1 %s | FileCheck -check-prefix=VI-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 2>&1 %s | FileCheck -check-prefix=GFX9-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga 2>&1 %s | FileCheck -check-prefix=VI-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefix=GFX10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefix=GFX10-ERR --implicit-check-not=error: %s
scratch_load_ubyte v1, v2, off
// GFX10: encoding: [0x00,0x40,0x20,0xdc,0x02,0x00,0x7d,0x01]
diff --git a/llvm/test/MC/AMDGPU/flat-scratch-st-mode.s b/llvm/test/MC/AMDGPU/flat-scratch-st-mode.s
index 6455acc1bffd415..a1d64efa8f11b13 100644
--- a/llvm/test/MC/AMDGPU/flat-scratch-st-mode.s
+++ b/llvm/test/MC/AMDGPU/flat-scratch-st-mode.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga 2>&1 %s | FileCheck -check-prefix=VI-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 2>&1 %s | FileCheck -check-prefix=GFX9_10-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 2>&1 %s | FileCheck --check-prefixes=GFX9_10-ERR --implicit-check-not=error: %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefixes=GFX1030 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga 2>&1 %s | FileCheck -check-prefix=VI-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 2>&1 %s | FileCheck -check-prefix=GFX9_10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 2>&1 %s | FileCheck --check-prefixes=GFX9_10-ERR --implicit-check-not=error: %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefixes=GFX1030 %s
scratch_load_ubyte v1, off, off
// GFX1030: encoding: [0x00,0x40,0x20,0xdc,0x00,0x00,0x7f,0x01]
diff --git a/llvm/test/MC/AMDGPU/flat-scratch.s b/llvm/test/MC/AMDGPU/flat-scratch.s
index 19059a6e8e0dbb2..c4e8e6ef6a2cf7a 100644
--- a/llvm/test/MC/AMDGPU/flat-scratch.s
+++ b/llvm/test/MC/AMDGPU/flat-scratch.s
@@ -1,8 +1,8 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck -check-prefix=NOCI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s | FileCheck -check-prefix=CI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck -check-prefix=NOCI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=hawaii -show-encoding %s | FileCheck -check-prefix=CI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
s_mov_b64 flat_scratch, -1
// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
diff --git a/llvm/test/MC/AMDGPU/flat.s b/llvm/test/MC/AMDGPU/flat.s
index 32c6e59976772ee..42be909bbbbbd33 100644
--- a/llvm/test/MC/AMDGPU/flat.s
+++ b/llvm/test/MC/AMDGPU/flat.s
@@ -1,9 +1,9 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CIVI --check-prefix=CI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=CIVI --check-prefix=VI
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CIVI --check-prefix=CI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=CIVI --check-prefix=VI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --check-prefix=NOVI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --check-prefix=NOVI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSI --implicit-check-not=error:
//===----------------------------------------------------------------------===//
// Operands
diff --git a/llvm/test/MC/AMDGPU/fma-mix.s b/llvm/test/MC/AMDGPU/fma-mix.s
index d70c76045d5e201..a6bb6a4cc3e00b7 100644
--- a/llvm/test/MC/AMDGPU/fma-mix.s
+++ b/llvm/test/MC/AMDGPU/fma-mix.s
@@ -1,6 +1,6 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx904 -show-encoding %s | FileCheck -check-prefix=GFX9-FMAMIX %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx906 -show-encoding %s | FileCheck -check-prefix=GFX9-FMAMIX %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX9-MADMIX-ERR --implicit-check-not=error: %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx904 -show-encoding %s | FileCheck -check-prefix=GFX9-FMAMIX %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx906 -show-encoding %s | FileCheck -check-prefix=GFX9-FMAMIX %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX9-MADMIX-ERR --implicit-check-not=error: %s
v_fma_mix_f32 v0, v1, v2, v3
// GFX9-FMAMIX: v_fma_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
diff --git a/llvm/test/MC/AMDGPU/gfx10-constant-bus.s b/llvm/test/MC/AMDGPU/gfx10-constant-bus.s
index 7478415440d3a57..793d9fdb53dd5a0 100644
--- a/llvm/test/MC/AMDGPU/gfx10-constant-bus.s
+++ b/llvm/test/MC/AMDGPU/gfx10-constant-bus.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefixes=GCN,GFX10 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefixes=GCN-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefixes=GCN,GFX11 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,GFX11-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefixes=GCN,GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefixes=GCN-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefixes=GCN,GFX11 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,GFX11-ERR --implicit-check-not=error: %s
//-----------------------------------------------------------------------------------------
// On GFX10 we can use two scalar operands (except for 64-bit shift instructions)
diff --git a/llvm/test/MC/AMDGPU/gfx10-vop2be-literal.s b/llvm/test/MC/AMDGPU/gfx10-vop2be-literal.s
index 827496244843881..01b11b1098a118f 100644
--- a/llvm/test/MC/AMDGPU/gfx10-vop2be-literal.s
+++ b/llvm/test/MC/AMDGPU/gfx10-vop2be-literal.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
v_add_co_ci_u32_e32 v3, vcc_lo, 12345, v3, vcc_lo
// GFX10: v_add_co_ci_u32_e32 v3, vcc_lo, 0x3039, v3, vcc_lo ; encoding: [0xff,0x06,0x06,0x50,0x39,0x30,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx1011_dlops.s b/llvm/test/MC/AMDGPU/gfx1011_dlops.s
index 18e831eb58beb80..5780c182af843ca 100644
--- a/llvm/test/MC/AMDGPU/gfx1011_dlops.s
+++ b/llvm/test/MC/AMDGPU/gfx1011_dlops.s
@@ -1,12 +1,12 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1011 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1012 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1031 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1032 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1033 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1034 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1035 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1036 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1011 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1012 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1031 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1032 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1033 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1034 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1035 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1036 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
v_dot2_f32_f16 v0, v1, v2, v3
// GFX10: encoding: [0x00,0x40,0x13,0xcc,0x01,0x05,0x0e,0x1c]
diff --git a/llvm/test/MC/AMDGPU/gfx1011_err.s b/llvm/test/MC/AMDGPU/gfx1011_err.s
index bedff0ec49e8403..4b37aaf221e395f 100644
--- a/llvm/test/MC/AMDGPU/gfx1011_err.s
+++ b/llvm/test/MC/AMDGPU/gfx1011_err.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1011 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1012 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1011 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1012 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
v_dot8c_i32_i4 v5, v1, v2
// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx1013.s b/llvm/test/MC/AMDGPU/gfx1013.s
index b99265feaad9d09..a4180c3d93a23e4 100644
--- a/llvm/test/MC/AMDGPU/gfx1013.s
+++ b/llvm/test/MC/AMDGPU/gfx1013.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck %s
image_bvh64_intersect_ray v[5:8], v[1:12], s[8:11]
// CHECK: [0x01,0x9f,0x9c,0xf1,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx1030_err.s b/llvm/test/MC/AMDGPU/gfx1030_err.s
index 1bab041909ab4ab..10ffa9b73a04f5f 100644
--- a/llvm/test/MC/AMDGPU/gfx1030_err.s
+++ b/llvm/test/MC/AMDGPU/gfx1030_err.s
@@ -1,10 +1,10 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1031 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1032 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1033 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1034 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1035 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1036 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1030 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1031 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1032 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1033 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1034 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1035 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1036 %s 2>&1 | FileCheck --check-prefix=GFX10 --implicit-check-not=error: %s
v_dot8c_i32_i4 v5, v1, v2
// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx1030_new.s b/llvm/test/MC/AMDGPU/gfx1030_new.s
index 19907d690b55679..e03bc9b0df773fd 100644
--- a/llvm/test/MC/AMDGPU/gfx1030_new.s
+++ b/llvm/test/MC/AMDGPU/gfx1030_new.s
@@ -1,10 +1,10 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1031 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1032 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1033 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1034 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1035 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1036 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1031 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1032 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1033 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1034 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1035 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1036 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
global_load_dword_addtid v1, s[2:3] offset:16
// GFX10: encoding: [0x10,0x80,0x58,0xdc,0x00,0x00,0x02,0x01]
diff --git a/llvm/test/MC/AMDGPU/gfx1030_unsupported.s b/llvm/test/MC/AMDGPU/gfx1030_unsupported.s
index 57cfb2f2514cd93..9112a30b0b7bd06 100644
--- a/llvm/test/MC/AMDGPU/gfx1030_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx1030_unsupported.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1030 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
v_mul_lo_i32 v0, v1, v2
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_dpp16.s b/llvm/test/MC/AMDGPU/gfx10_asm_dpp16.s
index ca5a3abd39e574e..77df1f62b224327 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_dpp16.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_dpp8.s b/llvm/test/MC/AMDGPU/gfx10_asm_dpp8.s
index 2a291e7de0db674..260d06d2e4cb58d 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_dpp8.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7]
// GFX10: encoding: [0xe9,0x02,0x0a,0x7e,0x01,0x88,0xc6,0xfa]
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_ds.s b/llvm/test/MC/AMDGPU/gfx10_asm_ds.s
index 14670eb6a8ad603..abe3586e3d0ea7d 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_ds.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_ds.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
//===----------------------------------------------------------------------===//
// ENC_DS.
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_err.s b/llvm/test/MC/AMDGPU/gfx10_asm_err.s
index 590504b73114e6e..ef12ba2a66b1940 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_err.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_err.s
@@ -1,9 +1,9 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx601 %s 2>&1 | FileCheck --check-prefixes=GFX6-7,GFX6-8,GFX6-9 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx701 %s 2>&1 | FileCheck --check-prefixes=GFX6-7,GFX6-8,GFX6-9 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx801 %s 2>&1 | FileCheck --check-prefixes=GFX6-8,GFX6-9,GFX8-9 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --check-prefixes=GFX6-9,GFX8-9 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx601 %s 2>&1 | FileCheck --check-prefixes=GFX6-7,GFX6-8,GFX6-9 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx701 %s 2>&1 | FileCheck --check-prefixes=GFX6-7,GFX6-8,GFX6-9 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx801 %s 2>&1 | FileCheck --check-prefixes=GFX6-8,GFX6-9,GFX8-9 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --check-prefixes=GFX6-9,GFX8-9 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10 --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// ENC_DS.
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_flat.s b/llvm/test/MC/AMDGPU/gfx10_asm_flat.s
index daf06082daab6f4..7340e48db3e84b6 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_flat.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_flat.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
//===----------------------------------------------------------------------===//
// ENC_FLAT.
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
index 45ecf93a1d306db..7b137289aa81767 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
@@ -1,4 +1,4 @@
-; RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefixes=GFX10 %s
+; RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefixes=GFX10 %s
image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
; GFX10: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x1f,0x00,0xf0,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s b/llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s
index 8fc33ae9acadac4..8deb16ebeb2043e 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefixes=NOGFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefixes=NOGFX10 --implicit-check-not=error: %s
// TODO: more helpful error message for missing dim operand
image_load v[0:3], v0, s[0:7] dmask:0xf unorm
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s
index 73951bd6c298e73..99c9c4aee4a761c 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
//===----------------------------------------------------------------------===//
// ENC_MUBUF.
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_smem.s b/llvm/test/MC/AMDGPU/gfx10_asm_smem.s
index ef4b460f67ab630..25c9e8f35093e26 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_smem.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_smem.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
//===----------------------------------------------------------------------===//
// ENC_SMEM.
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_sop.s b/llvm/test/MC/AMDGPU/gfx10_asm_sop.s
index 80c5d1dd24d0147..8f1cde76c6aa3cf 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_sop.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_sop.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
//===----------------------------------------------------------------------===//
// ENC_SOP1.
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
index 799eff52dae5b2b..1cfafebe2c3cd4c 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=GFX10-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=GFX10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=GFX10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=GFX10-ERR --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// ENC_VOP1.
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
index b1b54005bee285c..bf8e18ec1451235 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// ENC_VOP2.
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
index b05bab15e20086a..09d833d0ce4b821 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W64-ERR --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// ENC_VOP3.
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx10_asm_vopc.s
index f850741e379f9d9..521394829069320 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_vopc.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vopc.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// ENC_VOPC - v_cmp_* opcodes.
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s b/llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
index 3a036f32bf5e1f5..fc8fe95a9cf2d1c 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// ENC_VOPC, VOP3 variant.
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vopc_sdwa.s b/llvm/test/MC/AMDGPU/gfx10_asm_vopc_sdwa.s
index 3cb859da3946590..8808ab9ff2f9c88 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_vopc_sdwa.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vopc_sdwa.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// ENC_VOPC, SDWA variant.
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vopcx.s b/llvm/test/MC/AMDGPU/gfx10_asm_vopcx.s
index 618fb30b8c09ff3..f441feb88db4364 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_vopcx.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vopcx.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
//===----------------------------------------------------------------------===//
// ENC_VOPC - v_cmpx_* opcodes.
diff --git a/llvm/test/MC/AMDGPU/gfx10_err_pos.s b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
index 5b907e9f0509151..1d34f00ee0f9213 100644
--- a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+WavefrontSize32,-WavefrontSize64 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+WavefrontSize32,-WavefrontSize64 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
//==============================================================================
// operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx10_unsupported.s b/llvm/test/MC/AMDGPU/gfx10_unsupported.s
index b36722e0f8e43c8..341ae5726c0efa2 100644
--- a/llvm/test/MC/AMDGPU/gfx10_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx10_unsupported.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=CHECK,GFX1010 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=CHECK,GFX1010 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=CHECK,GFX1010 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=CHECK,GFX1010 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
buffer_atomic_add_f32 v0, v2, s[4:7], 0 idxen glc
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx10_unsupported_dpp.s b/llvm/test/MC/AMDGPU/gfx10_unsupported_dpp.s
index 852dd2cd9c1bb24..35c70fedb4661f3 100644
--- a/llvm/test/MC/AMDGPU/gfx10_unsupported_dpp.s
+++ b/llvm/test/MC/AMDGPU/gfx10_unsupported_dpp.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
v_add_co_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
diff --git a/llvm/test/MC/AMDGPU/gfx10_unsupported_e32.s b/llvm/test/MC/AMDGPU/gfx10_unsupported_e32.s
index a371fdbd8d53e18..cdcc6644824322b 100644
--- a/llvm/test/MC/AMDGPU/gfx10_unsupported_e32.s
+++ b/llvm/test/MC/AMDGPU/gfx10_unsupported_e32.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
v_add_co_u32_e32 v2, vcc, s0, v2
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
diff --git a/llvm/test/MC/AMDGPU/gfx10_unsupported_e64.s b/llvm/test/MC/AMDGPU/gfx10_unsupported_e64.s
index b07c603bcf4cb32..994a4c1b5f04ea0 100644
--- a/llvm/test/MC/AMDGPU/gfx10_unsupported_e64.s
+++ b/llvm/test/MC/AMDGPU/gfx10_unsupported_e64.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
v_swap_b32_e64 v1, v2
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e64 variant of this instruction is not supported
diff --git a/llvm/test/MC/AMDGPU/gfx10_unsupported_e64_dpp.s b/llvm/test/MC/AMDGPU/gfx10_unsupported_e64_dpp.s
index 941c812b5ea43cb..bfc8b9a64845c2d 100644
--- a/llvm/test/MC/AMDGPU/gfx10_unsupported_e64_dpp.s
+++ b/llvm/test/MC/AMDGPU/gfx10_unsupported_e64_dpp.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
v_add3_u32_e64_dpp v5, v1, s1, v0 dpp8:[7,6,5,4,3,2,1,0]
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e64_dpp variant of this instruction is not supported
diff --git a/llvm/test/MC/AMDGPU/gfx10_unsupported_sdwa.s b/llvm/test/MC/AMDGPU/gfx10_unsupported_sdwa.s
index 098597c2f9d29a9..b28c652335218ea 100644
--- a/llvm/test/MC/AMDGPU/gfx10_unsupported_sdwa.s
+++ b/llvm/test/MC/AMDGPU/gfx10_unsupported_sdwa.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
v_add_co_u32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
diff --git a/llvm/test/MC/AMDGPU/gfx11-promotions.s b/llvm/test/MC/AMDGPU/gfx11-promotions.s
index 042e1c4a405a333..6be33afb5671b97 100644
--- a/llvm/test/MC/AMDGPU/gfx11-promotions.s
+++ b/llvm/test/MC/AMDGPU/gfx11-promotions.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s | FileCheck --check-prefix=GFX11 %s
// Check opcode promotions and forced suffices.
// 1. When a suffix is optional, check that it may be omitted.
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_ds.s b/llvm/test/MC/AMDGPU/gfx11_asm_ds.s
index 4e95aba5d65154c..34442add86f211c 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_ds.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_ds.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
ds_nop
// GFX11: [0x00,0x00,0x50,0xd8,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_err.s
index f668b2458aef5ac..e475a1d5190777e 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
s_delay_alu
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_exp.s b/llvm/test/MC/AMDGPU/gfx11_asm_exp.s
index 6613f4836a800af..ede3710bcbb3826 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_exp.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_exp.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=PREGFX11 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefix=PREGFX11 --implicit-check-not=error: %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=PREGFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefix=PREGFX11 --implicit-check-not=error: %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 --implicit-check-not=error: %s
exp dual_src_blend0 v4, v3, v2, v1
// PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: exp target is not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_flat.s b/llvm/test/MC/AMDGPU/gfx11_asm_flat.s
index b0c212d4dadac37..300988646d8bab4 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_flat.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_flat.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
//===----------------------------------------------------------------------===//
// FLAT.
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_flat_errs.s b/llvm/test/MC/AMDGPU/gfx11_asm_flat_errs.s
index f085f2dd2d828f9..83e4d8f0b9fca7b 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_flat_errs.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_flat_errs.s
@@ -1,8 +1,8 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga 2>&1 %s | FileCheck -check-prefix=VI-GFX9_10-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 2>&1 %s | FileCheck -check-prefix=VI-GFX9_10-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 2>&1 %s | FileCheck --check-prefix=VI-GFX9_10-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030 2>&1 %s | FileCheck --check-prefix=VI-GFX9_10-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 2>&1 %s | FileCheck --check-prefix=GFX11-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga 2>&1 %s | FileCheck -check-prefix=VI-GFX9_10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 2>&1 %s | FileCheck -check-prefix=VI-GFX9_10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 2>&1 %s | FileCheck --check-prefix=VI-GFX9_10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1030 2>&1 %s | FileCheck --check-prefix=VI-GFX9_10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 2>&1 %s | FileCheck --check-prefix=GFX11-ERR --implicit-check-not=error: %s
// FLAT
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_ldsdir.s b/llvm/test/MC/AMDGPU/gfx11_asm_ldsdir.s
index d01557865ad4db5..8a8daab9a3a7e03 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_ldsdir.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_ldsdir.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
lds_direct_load v1 wait_vdst:15
// GFX11: lds_direct_load v1 wait_vdst:15 ; encoding: [0x01,0x00,0x1f,0xce]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_ldsdir_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_ldsdir_err.s
index b4318a05767bb17..75795d90c3234ed 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_ldsdir_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_ldsdir_err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX11 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX11 %s
lds_param_load v17, attr33.x
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: out of bounds interpolation attribute number
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx11_asm_mimg.s
index 1f1cdd70e2dfce9..6d467dfa1d8e187 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_mimg.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_mimg.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck %s --check-prefix=GFX11
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck %s --check-prefix=GFX11
image_atomic_add v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
// GFX11: [0x80,0x03,0x30,0xf0,0x02,0x01,0x03,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_mimg_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_mimg_err.s
index cc24d39bb45dbde..9dc88690d95628a 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_mimg_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_mimg_err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefixes=NOGFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefixes=NOGFX11 --implicit-check-not=error: %s
image_sample_d v[64:66], [v32, v16, v8, v4, v2, v1], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2D
// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_mimg_features.s b/llvm/test/MC/AMDGPU/gfx11_asm_mimg_features.s
index 6736009685cb384..1c8c7cf6823f229 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_mimg_features.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_mimg_features.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
// GFX11: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x80,0x0f,0x00,0xf0,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_mtbuf.s b/llvm/test/MC/AMDGPU/gfx11_asm_mtbuf.s
index f34b8d684ff6534..eea5f3a7c65cc8b 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_mtbuf.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_mtbuf.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR --implicit-check-not=error: %s
tbuffer_load_d16_format_x v4, off, s[8:11], s3, format:[BUF_FMT_8_UNORM] offset:4095
// GFX11: encoding: [0xff,0x0f,0x0c,0xe8,0x00,0x04,0x02,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_mtbuf_alias.s b/llvm/test/MC/AMDGPU/gfx11_asm_mtbuf_alias.s
index 226fccc9bf89740..187d18e9045a8bb 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_mtbuf_alias.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_mtbuf_alias.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR --implicit-check-not=error: %s
tbuffer_load_format_d16_x v4, off, s[8:11], s3, format:[BUF_FMT_8_UNORM] offset:4095
// GFX11: encoding: [0xff,0x0f,0x0c,0xe8,0x00,0x04,0x02,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx11_asm_mubuf.s
index db8d72f3124bae6..a5efde4219c4a02 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_mubuf.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_mubuf.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR --implicit-check-not=error: %s
buffer_gl0_inv
// GFX11: encoding: [0x00,0x00,0xac,0xe0,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_mubuf_alias.s b/llvm/test/MC/AMDGPU/gfx11_asm_mubuf_alias.s
index 02bcf6791a881d0..5456d68f4c06842 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_mubuf_alias.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_mubuf_alias.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR --implicit-check-not=error: %s
buffer_load_dword v5, off, s[8:11], s3 offset:4095
// GFX11: encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_operands.s b/llvm/test/MC/AMDGPU/gfx11_asm_operands.s
index abf70235d4f499a..d3efcf1987318c0 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_operands.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_operands.s
@@ -1,6 +1,6 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR %s
// On GFX11+, EXECZ and VCCZ are no longer allowed to be used as sources to SALU and VALU instructions.
// The inline constants are removed. VCCZ and EXECZ still exist and can be use for conditional branches.
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_smem.s b/llvm/test/MC/AMDGPU/gfx11_asm_smem.s
index 71538d6ad7e4008..1d6b94760907589 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_smem.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_smem.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// ENC_SMEM.
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_smem_alias.s b/llvm/test/MC/AMDGPU/gfx11_asm_smem_alias.s
index 9f177e24dadcf29..9331931940906ad 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_smem_alias.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_smem_alias.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
//===----------------------------------------------------------------------===//
// ENC_SMEM.
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_sop1.s b/llvm/test/MC/AMDGPU/gfx11_asm_sop1.s
index ec28c1547d4e40c..8a7f64331317edc 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_sop1.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_sop1.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1100 %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1100 %s | FileCheck --check-prefix=GFX11 %s
s_mov_b32 s0, s1
// GFX11: encoding: [0x01,0x00,0x80,0xbe]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_sop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_sop2.s
index f80e557449c9c38..cd9b686d3f6c5b8 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_sop2.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_sop2.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1100 %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1100 %s | FileCheck --check-prefix=GFX11 %s
s_add_u32 s0, s1, s2
// GFX11: encoding: [0x01,0x02,0x00,0x80]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_sopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_sopc.s
index 7fb3f2cc120b9f2..ae83782a24c5ce8 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_sopc.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_sopc.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1100 %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1100 %s | FileCheck --check-prefix=GFX11 %s
s_cmp_eq_i32 s0, s1
// GFX11: encoding: [0x00,0x01,0x00,0xbf]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_sopk.s b/llvm/test/MC/AMDGPU/gfx11_asm_sopk.s
index e8e4c201cf80320..5b19f8bca3becfd 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_sopk.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_sopk.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1100 %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1100 %s | FileCheck --check-prefix=GFX11 %s
s_movk_i32 s0, 0x1234
// GFX11: encoding: [0x34,0x12,0x00,0xb0]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_sopk_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_sopk_err.s
index ad766ea75a0e9bc..e7a8db1fa7e325c 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_sopk_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_sopk_err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck %s -check-prefix=GFX11 --implicit-check-not=error: --strict-whitespace
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck %s -check-prefix=GFX11 --implicit-check-not=error: --strict-whitespace
s_waitcnt_vscnt s0, 0x1234
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: src0 must be null
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s
index aac0c74887a4c88..8d7fed65a776366 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
//===----------------------------------------------------------------------===//
// s_waitcnt
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vinterp.s b/llvm/test/MC/AMDGPU/gfx11_asm_vinterp.s
index fa64243c156d43c..0a3396b454b9c0a 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vinterp.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vinterp.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
v_interp_p10_f32 v0, v1, v2, v3
// GFX11: v_interp_p10_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0x00,0xcd,0x01,0x05,0x0e,0x04]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vinterp_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vinterp_err.s
index e13ff635a32ee6a..1d6769dbd4d6a08 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vinterp_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vinterp_err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck %s -check-prefix=GFX11-ERR --implicit-check-not=error: --strict-whitespace
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck %s -check-prefix=GFX11-ERR --implicit-check-not=error: --strict-whitespace
//===----------------------------------------------------------------------===//
// VINTERP src operands must be VGPRs.
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
index 5c01a2a253eab9e..0aeb9b35ff378cb 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
v_bfrev_b32_e32 v5, v1
// GFX11: encoding: [0x01,0x71,0x0a,0x7e]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
index 99b44c15ed42724..8c6873e2cbe3228 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0]
// GFX11: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
index 2b14ca5dd52bed9..a765d333db2b74d 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
v_bfrev_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: encoding: [0xe9,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
index 2ebb06fb7f9071b..1f350ae6863849e 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
v_ceil_f16_e32 v128, 0xfe0b
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
index ed8b1d5b7237b39..601551efe00c2b9 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s
v_ceil_f16 v128, 0xfe0b
// GFX11: v_ceil_f16_e64
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
index 1f9cb7f06720ef2..2f71eaebb1e4f0b 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo
// W32: encoding: [0x01,0x05,0x0a,0x40]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
index 30a9ad0b66e9d23..af090a270fbeb83 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0]
// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
index 62b23e9568aa1c0..29dd341873f5528 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
// W32: encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s
index fc08dff0c2f7693..164a49dcdd47b61 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
v_fmaak_f32 v0, 0xff32, v0, 0
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
index d4bf86f64e60ffc..12697dfe259fde9 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
v_add_f16_e32 v255, v1, v2
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
index 876b7b88f50b1db..9c67b6499dd58bb 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s
v_add_f16 v255, v1, v2
// GFX11: v_add_f16_e64
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
index a0beee1c7eb66db..9a94162005e1f78 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
v_add3_u32 v5, v1, v2, s3
// GFX11: encoding: [0x05,0x00,0x55,0xd6,0x01,0x05,0x0e,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_alias.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_alias.s
index 2dcc977f98323a4..857f2fdfc41bf8a 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_alias.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_alias.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
v_cvt_pknorm_i16_f16 v5, v1, v2
// GFX11: v_cvt_pk_norm_i16_f16 {{.*}} encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
index d4853b0d7b65a0a..147d6c5d0789c90 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR,W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR,W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR,W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR,W64-ERR --implicit-check-not=error: %s
v_add3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
// GFX11: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop1.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop1.s
index bb52e60cd91e05a..9a65c6687f3f84d 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop1.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
v_bfrev_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0]
// GFX11: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s
index a499a9244d54279..3592679831d43b8 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=W64-ERR --implicit-check-not=error: %s
v_add_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 quad_perm:[3,2,1,0]
// W32: [0x05,0x06,0x20,0xd5,0xfa,0x04,0x0e,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s
index a78fa10226c68af..9a9a903085dd782 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
v_cmp_class_f16_e64_dpp s5, v1, v2 quad_perm:[3,2,1,0]
// W32: [0x05,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopcx.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopcx.s
index 7adb698c0327332..81ec15bb48f863c 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopcx.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopcx.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
v_cmpx_class_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
index 1fba5911276ef00..4c00148f7a89598 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR,W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR,W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR,W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX11-ERR,W64-ERR --implicit-check-not=error: %s
v_add3_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: [0x05,0x00,0x55,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop1.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop1.s
index f8478673e4fc21c..3897b82785f65b5 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop1.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
v_bfrev_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: [0x05,0x00,0xb8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s
index 6e1a65d7d3210f3..2ae47cf36b62df3 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=W64-ERR --implicit-check-not=error: %s
v_add_co_ci_u32_e64_dpp v5, s6, v1, v2, s3 dpp8:[7,6,5,4,3,2,1,0]
// W32: [0x05,0x06,0x20,0xd5,0xe9,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s
index 9df1b050b579b61..83ae41d81df6917 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
v_cmp_class_f16_e64_dpp s5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// W32: [0x05,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopcx.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopcx.s
index dfd8d8809d4dd1f..8c26c769a1962e6 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopcx.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopcx.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
v_cmpx_class_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: [0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s
index f1189d058085951..9fc17a6a27147ba 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1.s
index a67cb0bf4cf851e..fb4e9108fe1d1a0 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
v_bfrev_b32_e64 v5, v1
// GFX11: encoding: [0x05,0x00,0xb8,0xd5,0x01,0x01,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
index 43c71617bb3851f..242c8a79fdd6f5a 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
v_add_co_ci_u32_e64 v5, s6, v1, 0xaf123456, s3
// W32: encoding: [0x05,0x06,0x20,0xd5,0x01,0xff,0x0d,0x00,0x56,0x34,0x12,0xaf]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
index d333240d8a47106..3a6a61891d29326 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
v_cmp_class_f16_e64 s5, v1, v2
// W32: encoding: [0x05,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s
index bb3434a1bb15d9a..f50a47777f641d3 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
v_cmpx_class_f16_e64 v1, v2
// GFX11: encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3p.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3p.s
index 4426ec4bbbeb5a0..45a320a3e358e63 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3p.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3p.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1100 %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1100 %s | FileCheck --check-prefix=GFX11 %s
v_dot2_f32_bf16 v5, v1, v2, v3
// GFX11: [0x05,0x40,0x1a,0xcc,0x01,0x05,0x0e,0x1c]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp16.s
index ac403909b502ee7..2cfb8abd4e97909 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp16.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,0,0] neg_hi:[0,0,0] quad_perm:[2,2,3,1] bound_ctrl:0 fi:1
// GFX11: v_dot2_f32_f16_e64_dpp v0, v1, v2, v3 quad_perm:[2,2,3,1] row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x00,0x00,0x13,0xcc,0xfa,0x04,0x0e,0x04,0x01,0x7a,0x04,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp8.s
index aa23d7a7d4b4cc5..2656ba0cf1807ec 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp8.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
v_fma_mix_f32 v0, v1, v2, v3 dpp8:[2,2,2,2,4,4,4,4]
// GFX11: encoding: [0x00,0x00,0x20,0xcc,0xe9,0x04,0x0e,0x04,0x01,0x92,0x44,0x92]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_features.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_features.s
index 3c89a6468b3b2df..ecfb0d9aac68bb2 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_features.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3p_features.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1100 %s | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1100 %s | FileCheck --check-prefix=GFX11 %s
//
// Test op_sel/op_sel_hi
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
index 81c58e206f92da1..c9272f24e25a8c9 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
v_cmp_class_f16_e32 vcc_lo, v1, v2
// W32: encoding: [0x01,0x05,0xfa,0x7c]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s
index 0d14b664aba8fe4..802562f38f44fdd 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
v_cmp_class_f16_dpp vcc_lo, v1, v2 quad_perm:[3,2,1,0]
// W32: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s
index 10f09b1225518ce..e6ff8faa3aebc24 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
v_cmp_class_f16_dpp vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// W32: encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
index d3de2cbf12b83b5..889293b1a0f2343 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
v_cmp_class_f16_e32 vcc, v1, v255
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
index 1e6754b1927b39b..b16caed8b275f75 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 %s
v_cmp_class_f16 vcc, v1, v255
// GFX11: v_cmp_class_f16_e64
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx.s
index 5e2f3bec9a24f80..2512f1a4b94b5e2 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
v_cmpx_class_f16_e32 v1, v2
// GFX11: encoding: [0x01,0x05,0xfa,0x7d]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp16.s
index 6b047a27db2daaa..b9903f51b332dcf 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp16.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
v_cmpx_class_f16_dpp v1, v2 quad_perm:[3,2,1,0]
// GFX11: encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp8.s
index 8aaa5f344713022..5f5d3c03038307d 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp8.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
v_cmpx_class_f16_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: encoding: [0xe9,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
index 0cea363b42d974e..c37d15b7abc79bd 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
v_cmpx_class_f16_e32 v1, v255
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s
index 074fd10952776c5..a279bd381848e82 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 %s
v_cmpx_class_f16 v1, v255
// GFX11: v_cmpx_class_f16_e64
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopd.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopd.s
index 3bae40ae0b40de9..0556861276b071f 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopd.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopd.s
@@ -1,6 +1,6 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefixes=W64-ERR --implicit-check-not=error: %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefixes=W64-ERR --implicit-check-not=error: %s
v_dual_add_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3
// GFX11: encoding: [0x04,0x05,0x08,0xc9,0x01,0x07,0x06,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopd_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopd_err.s
index 4fc954cb32e4ef4..3c5905b14e06cf1 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopd_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopd_err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck %s -check-prefix=GFX11 --implicit-check-not=error: --strict-whitespace
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck %s -check-prefix=GFX11 --implicit-check-not=error: --strict-whitespace
//===----------------------------------------------------------------------===//
// A VOPD instruction can use only one literal.
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopd_features.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopd_features.s
index fd8569bc0a9b36e..c442800eb06dbf2 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopd_features.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopd_features.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
//===----------------------------------------------------------------------===//
// A VOPD instruction can use one or more literals,
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_wmma.s b/llvm/test/MC/AMDGPU/gfx11_asm_wmma.s
index e5b8ec97c3d8bca..74cdd02a8351191 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_wmma.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_wmma.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W32 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=W64 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
//
// Test v_wmma_f32_16x16x16_f16
diff --git a/llvm/test/MC/AMDGPU/gfx11_unsupported.s b/llvm/test/MC/AMDGPU/gfx11_unsupported.s
index 67fba5699dd6be5..4c2d4d3890cbb6a 100644
--- a/llvm/test/MC/AMDGPU/gfx11_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx11_unsupported.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
buffer_atomic_add_f64 v[2:3], off, s[12:15], s4 offset:4095
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx11_unsupported_dpp.s b/llvm/test/MC/AMDGPU/gfx11_unsupported_dpp.s
index fb895869e07d6ea..e9e0c5210238e22 100644
--- a/llvm/test/MC/AMDGPU/gfx11_unsupported_dpp.s
+++ b/llvm/test/MC/AMDGPU/gfx11_unsupported_dpp.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
v_add_co_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: dpp variant of this instruction is not supported
diff --git a/llvm/test/MC/AMDGPU/gfx11_unsupported_e32.s b/llvm/test/MC/AMDGPU/gfx11_unsupported_e32.s
index 5915b4848093bcb..21a3fbedb694daa 100644
--- a/llvm/test/MC/AMDGPU/gfx11_unsupported_e32.s
+++ b/llvm/test/MC/AMDGPU/gfx11_unsupported_e32.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
v_add_co_u32_e32 v2, vcc, s0, v2
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
diff --git a/llvm/test/MC/AMDGPU/gfx11_unsupported_e64.s b/llvm/test/MC/AMDGPU/gfx11_unsupported_e64.s
index 6feccebe6360395..a4310f3b5378fe8 100644
--- a/llvm/test/MC/AMDGPU/gfx11_unsupported_e64.s
+++ b/llvm/test/MC/AMDGPU/gfx11_unsupported_e64.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
v_dot2c_f32_f16_e64 v0, v1, v2
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e64 variant of this instruction is not supported
diff --git a/llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa.s b/llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa.s
index c16c3fe9be45896..9ca3861eb93600b 100644
--- a/llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa.s
+++ b/llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
v_add_co_ci_u32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_ds.s b/llvm/test/MC/AMDGPU/gfx7_asm_ds.s
index 6861970293c2770..eaa1b0510040ecf 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_ds.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_ds.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
ds_add_u32 v1, v2 offset:65535
// CHECK: [0xff,0xff,0x00,0xd8,0x01,0x02,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_exp.s b/llvm/test/MC/AMDGPU/gfx7_asm_exp.s
index 8c5fafa405642d2..df143726d847548 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_exp.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_exp.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
exp mrt0 v0, v0, v0, v0
// CHECK: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_flat.s b/llvm/test/MC/AMDGPU/gfx7_asm_flat.s
index c240b263b967a32..46f93a6986e9969 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_flat.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_flat.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
flat_load_ubyte v5, v[1:2]
// CHECK: [0x00,0x00,0x20,0xdc,0x01,0x00,0x00,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx7_asm_mimg.s
index 250c00a6321b07b..9fab33c74a68df3 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_mimg.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_mimg.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
image_load v5, v1, s[8:15] dmask:0x1
// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_mtbuf.s b/llvm/test/MC/AMDGPU/gfx7_asm_mtbuf.s
index 61d180b75319590..c93e4282232cb51 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_mtbuf.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_mtbuf.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
tbuffer_load_format_x v5, off, s[8:11], s3 offset:4095
// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s
index 18e4f8ba7fc419a..2fd450a65dce889 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
buffer_load_format_x v5, off, s[8:11], s3 offset:4095
// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_smrd.s b/llvm/test/MC/AMDGPU/gfx7_asm_smrd.s
index 2b44cdc851acb23..c12299e247f200d 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_smrd.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_smrd.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
s_load_dword s5, s[2:3], s2
// CHECK: [0x02,0x82,0x02,0xc0]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_sop1.s b/llvm/test/MC/AMDGPU/gfx7_asm_sop1.s
index ecff976fe54ee37..ead56ff2a9346bc 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_sop1.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_sop1.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
s_mov_b32 s5, s1
// CHECK: [0x01,0x03,0x85,0xbe]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_sop2.s b/llvm/test/MC/AMDGPU/gfx7_asm_sop2.s
index aa9caaf69f8e87b..3d828e796712574 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_sop2.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_sop2.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
s_add_u32 s5, s1, s2
// CHECK: [0x01,0x02,0x05,0x80]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_sopc.s b/llvm/test/MC/AMDGPU/gfx7_asm_sopc.s
index ec0f43b90ed07ff..ae238bd8bb312e0 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_sopc.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_sopc.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
s_cmp_eq_i32 s1, s2
// CHECK: [0x01,0x02,0x00,0xbf]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_sopk.s b/llvm/test/MC/AMDGPU/gfx7_asm_sopk.s
index c3283dec6ba6b92..caa1eddfd708e06 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_sopk.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_sopk.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
s_movk_i32 s5, 0x3141
// CHECK: [0x41,0x31,0x05,0xb0]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx7_asm_sopp.s
index 2cea9ec5695c2a9..01458f8ae0087f8 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_sopp.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_sopp.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
s_nop 0x3141
// CHECK: [0x41,0x31,0x80,0xbf]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_vintrp.s b/llvm/test/MC/AMDGPU/gfx7_asm_vintrp.s
index 4dfa9e05e6586d5..e3670110178b0aa 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_vintrp.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_vintrp.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
v_interp_p1_f32 v5, v1, attr0.x
// CHECK: [0x01,0x00,0x14,0xc8]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx7_asm_vop1.s
index d42bfb1c021ce34..b17e6aba56eb3f1 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_vop1.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
v_nop
// CHECK: [0x00,0x00,0x00,0x7e]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx7_asm_vop2.s
index fe71cba45d3ee17..3fb562fb4b2b6e1 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_vop2.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
v_cndmask_b32 v5, v1, v2, vcc
// CHECK: [0x01,0x05,0x0a,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
index 804e1c2bf77bc53..48ff621ba9aa36a 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
v_nop_e64
// CHECK: [0x00,0x00,0x00,0xd3,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_vop3_e64.s b/llvm/test/MC/AMDGPU/gfx7_asm_vop3_e64.s
index 422412b4595e106..081fd7c09c5e3ac 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_vop3_e64.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_vop3_e64.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
v_mad_legacy_f32 v5, v1, v2, v3
// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x04]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx7_asm_vopc.s
index 1cb63dcd3f4b18c..f1a720e774ce826 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_vopc.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_vopc.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
v_cmp_f_f32 vcc, v1, v2
// CHECK: [0x01,0x05,0x00,0x7c]
diff --git a/llvm/test/MC/AMDGPU/gfx7_err_pos.s b/llvm/test/MC/AMDGPU/gfx7_err_pos.s
index b9473a26e62a506..9dcbd4a4074af4f 100644
--- a/llvm/test/MC/AMDGPU/gfx7_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx7_err_pos.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
//==============================================================================
// cache policy is not supported for SMRD instructions
diff --git a/llvm/test/MC/AMDGPU/gfx7_unsupported.s b/llvm/test/MC/AMDGPU/gfx7_unsupported.s
index c6b7c9ec6b437bc..bd4bb7b23586705 100644
--- a/llvm/test/MC/AMDGPU/gfx7_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx7_unsupported.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// Unsupported instructions.
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_ds.s b/llvm/test/MC/AMDGPU/gfx8_asm_ds.s
index da0297f7c3101c6..090d3b5ca11a47b 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_ds.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_ds.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
ds_add_u32 v1, v2 offset:65535
// CHECK: [0xff,0xff,0x00,0xd8,0x01,0x02,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_exp.s b/llvm/test/MC/AMDGPU/gfx8_asm_exp.s
index 9e049d7f84d5248..a83afb9e6c0ba87 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_exp.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_exp.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
exp mrt0 v0, v0, v0, v0
// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_flat.s b/llvm/test/MC/AMDGPU/gfx8_asm_flat.s
index 4a62f04f4183e59..4e622969623c83a 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_flat.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_flat.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
flat_load_ubyte v5, v[1:2]
// CHECK: [0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx8_asm_mimg.s
index abcd4b700e583dd..d5dcf4f3a7e089e 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_mimg.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_mimg.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
image_load v5, v1, s[8:15] dmask:0x1
// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_mtbuf.s b/llvm/test/MC/AMDGPU/gfx8_asm_mtbuf.s
index d748885b6796784..655a3be4528a626 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_mtbuf.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_mtbuf.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
tbuffer_load_format_x v5, off, s[8:11], s3 offset:4095
// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s
index 0099ed426aa69f4..e5f10c505a8d59b 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
buffer_load_format_x v5, off, s[8:11], s3 offset:4095
// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_smem.s b/llvm/test/MC/AMDGPU/gfx8_asm_smem.s
index 5cdee0f8858c9f5..c75781918dcc6e4 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_smem.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_smem.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
s_load_dword s5, s[2:3], s2
// CHECK: [0x41,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_sop1.s b/llvm/test/MC/AMDGPU/gfx8_asm_sop1.s
index f70a851239a4397..f185df85b2bf5b9 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_sop1.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_sop1.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
s_mov_b32 s5, s1
// CHECK: [0x01,0x00,0x85,0xbe]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_sop2.s b/llvm/test/MC/AMDGPU/gfx8_asm_sop2.s
index 121d0ad08fb9cc9..5ffcc081a13255c 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_sop2.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_sop2.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
s_add_u32 s5, s1, s2
// CHECK: [0x01,0x02,0x05,0x80]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_sopc.s b/llvm/test/MC/AMDGPU/gfx8_asm_sopc.s
index c6a6a9bc8b9ed8f..c8596fa246983f6 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_sopc.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_sopc.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
s_cmp_eq_i32 s1, s2
// CHECK: [0x01,0x02,0x00,0xbf]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_sopk.s b/llvm/test/MC/AMDGPU/gfx8_asm_sopk.s
index 56a66243b96b496..581d0cc4e58f8b3 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_sopk.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_sopk.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
s_movk_i32 s5, 0x3141
// CHECK: [0x41,0x31,0x05,0xb0]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx8_asm_sopp.s
index faa3c8595a235bc..7449c9638c153e9 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_sopp.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_sopp.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
s_nop 0x3141
// CHECK: [0x41,0x31,0x80,0xbf]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_vintrp.s b/llvm/test/MC/AMDGPU/gfx8_asm_vintrp.s
index 890cd728db9a427..918cd5b26116e85 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_vintrp.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_vintrp.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
v_interp_p1_f32 v5, v1, attr0.x
// CHECK: [0x01,0x00,0x14,0xd4]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx8_asm_vop1.s
index 52f249b6f423b1d..32ebbd9e1028a5a 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_vop1.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
v_nop
// CHECK: [0x00,0x00,0x00,0x7e]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx8_asm_vop2.s
index d3540bab1c89f82..1c355af950280ff 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_vop2.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
v_cndmask_b32 v5, v1, v2, vcc
// CHECK: [0x01,0x05,0x0a,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
index d4c31f14d3bfcab..36da95c448f28a7 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
v_interp_p1_f32_e64 v5, v2, attr0.x
// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_vop3_e64.s b/llvm/test/MC/AMDGPU/gfx8_asm_vop3_e64.s
index 8cee668043dbf39..cd92832528931a2 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_vop3_e64.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_vop3_e64.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
v_mad_legacy_f32 v5, v1, v2, v3
// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x04]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx8_asm_vopc.s
index 31e9ad58b7d780f..adbe3f6a2683973 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_vopc.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_vopc.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
v_cmp_class_f32 vcc, v1, v2
// CHECK: [0x01,0x05,0x20,0x7c]
diff --git a/llvm/test/MC/AMDGPU/gfx8_err_pos.s b/llvm/test/MC/AMDGPU/gfx8_err_pos.s
index 9a17ba167bcbef5..1e8457d54049a64 100644
--- a/llvm/test/MC/AMDGPU/gfx8_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx8_err_pos.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
//==============================================================================
// a16 modifier is not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx8_unsupported.s b/llvm/test/MC/AMDGPU/gfx8_unsupported.s
index 96bbf07998f86a4..aeed3d21ec5609f 100644
--- a/llvm/test/MC/AMDGPU/gfx8_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx8_unsupported.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// Unsupported instructions.
diff --git a/llvm/test/MC/AMDGPU/gfx9-asm-err.s b/llvm/test/MC/AMDGPU/gfx9-asm-err.s
index 6c7e0586b2ca61b..451fab99e12ade1 100644
--- a/llvm/test/MC/AMDGPU/gfx9-asm-err.s
+++ b/llvm/test/MC/AMDGPU/gfx9-asm-err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX9ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX9ERR --implicit-check-not=error: %s
v_cvt_f16_u16_e64 v5, 0.5
// GFX9ERR: :[[@LINE-1]]:{{[0-9]+}}: error: literal operands are not supported
diff --git a/llvm/test/MC/AMDGPU/gfx9-vop2be-literal.s b/llvm/test/MC/AMDGPU/gfx9-vop2be-literal.s
index 1782db6625c49e2..0a3aca0254693b3 100644
--- a/llvm/test/MC/AMDGPU/gfx9-vop2be-literal.s
+++ b/llvm/test/MC/AMDGPU/gfx9-vop2be-literal.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX9-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX9-ERR --implicit-check-not=error: %s
v_addc_co_u32_e32 v3, vcc, 12345, v3, vcc
// GFX9-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
diff --git a/llvm/test/MC/AMDGPU/gfx908_err_pos.s b/llvm/test/MC/AMDGPU/gfx908_err_pos.s
index a6f0b8a61708efa..84e640308c98994 100644
--- a/llvm/test/MC/AMDGPU/gfx908_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx908_err_pos.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
//==============================================================================
// inline constants are not allowed for this operand
diff --git a/llvm/test/MC/AMDGPU/gfx90a_asm_features.s b/llvm/test/MC/AMDGPU/gfx90a_asm_features.s
index 5e12d885ee73675..d5f2755582d25d8 100644
--- a/llvm/test/MC/AMDGPU/gfx90a_asm_features.s
+++ b/llvm/test/MC/AMDGPU/gfx90a_asm_features.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck --check-prefixes=GFX908,NOT-GFX90A --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefixes=GFX1010,NOT-GFX90A --implicit-check-not=error: %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck --check-prefix=GFX90A %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck --check-prefixes=GFX908,NOT-GFX90A --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefixes=GFX1010,NOT-GFX90A --implicit-check-not=error: %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck --check-prefix=GFX90A %s
// NOT-GFX90A: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU
// GFX90A: v_pk_fma_f32 v[8:9], v[0:1], s[0:1], v[4:5] ; encoding: [0x08,0x40,0xb0,0xd3,0x00,0x01,0x10,0x1c]
diff --git a/llvm/test/MC/AMDGPU/gfx90a_err.s b/llvm/test/MC/AMDGPU/gfx90a_err.s
index 47e231161fc9e1a..7b2acc61cfa6f1d 100644
--- a/llvm/test/MC/AMDGPU/gfx90a_err.s
+++ b/llvm/test/MC/AMDGPU/gfx90a_err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck --check-prefix=GFX90A --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck --check-prefix=GFX90A --implicit-check-not=error: %s
ds_add_src2_u32 v1
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx90a_err_pos.s b/llvm/test/MC/AMDGPU/gfx90a_err_pos.s
index f60178a6112cc01..791241ce109e753 100644
--- a/llvm/test/MC/AMDGPU/gfx90a_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx90a_err_pos.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
//==============================================================================
// vgpr must be even aligned
diff --git a/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s b/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
index 8b2f144815889e0..ee8218613a6dc64 100644
--- a/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
+++ b/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck --check-prefix=NOT-GFX90A --implicit-check-not=error: %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck --check-prefix=GFX90A %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck --check-prefix=NOT-GFX90A --implicit-check-not=error: %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck --check-prefix=GFX90A %s
// GFX90A: flat_load_ubyte a5, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x40,0xdc,0x02,0x00,0x80,0x05]
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx940_asm_features.s b/llvm/test/MC/AMDGPU/gfx940_asm_features.s
index a8f7b06a1fe3236..5ee9480677be92f 100644
--- a/llvm/test/MC/AMDGPU/gfx940_asm_features.s
+++ b/llvm/test/MC/AMDGPU/gfx940_asm_features.s
@@ -1,6 +1,6 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -show-encoding %s | FileCheck --check-prefix=GFX940 --strict-whitespace %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck --check-prefixes=NOT-GFX940,GFX90A --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefixes=NOT-GFX940,GFX10 --implicit-check-not=error: %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx940 -show-encoding %s | FileCheck --check-prefix=GFX940 --strict-whitespace %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck --check-prefixes=NOT-GFX940,GFX90A --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefixes=NOT-GFX940,GFX10 --implicit-check-not=error: %s
// NOT-GFX940: :[[@LINE+2]]:{{[0-9]+}}: error: invalid operand for instruction
// GFX940: global_load_dword v2, v[2:3], off sc0 ; encoding: [0x00,0x80,0x51,0xdc,0x02,0x00,0x7f,0x02]
diff --git a/llvm/test/MC/AMDGPU/gfx940_err.s b/llvm/test/MC/AMDGPU/gfx940_err.s
index ad52d8bd643a5a5..515b89513a8048f 100644
--- a/llvm/test/MC/AMDGPU/gfx940_err.s
+++ b/llvm/test/MC/AMDGPU/gfx940_err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx940 %s 2>&1 | FileCheck --check-prefix=GFX940 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx940 %s 2>&1 | FileCheck --check-prefix=GFX940 --implicit-check-not=error: %s
v_mac_f32 v0, v1, v2
// GFX940: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx940_err_pos.s b/llvm/test/MC/AMDGPU/gfx940_err_pos.s
index b13545a7f1b68c9..3823c0eb80277ea 100644
--- a/llvm/test/MC/AMDGPU/gfx940_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx940_err_pos.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx940 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx940 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
//==============================================================================
// instruction must not use sc0
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_ds.s b/llvm/test/MC/AMDGPU/gfx9_asm_ds.s
index bc33579b1038904..032a9f5cb668fac 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_ds.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_ds.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
ds_add_u32 v1, v2 offset:65535
// CHECK: [0xff,0xff,0x00,0xd8,0x01,0x02,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_exp.s b/llvm/test/MC/AMDGPU/gfx9_asm_exp.s
index 689a19ff4629287..23c37b15abbc46f 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_exp.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_exp.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
exp mrt0 v0, v0, v0, v0
// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_flat.s b/llvm/test/MC/AMDGPU/gfx9_asm_flat.s
index d0380675316745c..5cc3d2533a149e9 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_flat.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_flat.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
flat_load_ubyte v5, v[1:2] offset:4095
// CHECK: [0xff,0x0f,0x40,0xdc,0x01,0x00,0x00,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx9_asm_mimg.s
index ed65976380a536b..4a39f1e3874a82a 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_mimg.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_mimg.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
image_load v5, v1, s[8:15] dmask:0x1
// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_mtbuf.s b/llvm/test/MC/AMDGPU/gfx9_asm_mtbuf.s
index 59d18196fa61b27..57a9f618c0ca219 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_mtbuf.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_mtbuf.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
tbuffer_load_format_x v5, off, s[8:11], s3 offset:4095
// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s
index 40c051b71a7dbf8..3d4eb635f0f62cc 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
buffer_load_format_x v5, off, s[8:11], s3 offset:4095
// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_smem.s b/llvm/test/MC/AMDGPU/gfx9_asm_smem.s
index 1fe4ec3f4cc6f87..71a7b009e2c427b 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_smem.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_smem.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
s_load_dword s5, s[2:3], s0
// CHECK: [0x41,0x01,0x00,0xc0,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_sop1.s b/llvm/test/MC/AMDGPU/gfx9_asm_sop1.s
index d787c88f6168920..b25d2794f685d3b 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_sop1.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_sop1.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
s_mov_b32 s5, s1
// CHECK: [0x01,0x00,0x85,0xbe]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_sop2.s b/llvm/test/MC/AMDGPU/gfx9_asm_sop2.s
index 554e766760afe67..f9480e083820837 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_sop2.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_sop2.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
s_add_u32 s5, s1, s2
// CHECK: [0x01,0x02,0x05,0x80]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_sopc.s b/llvm/test/MC/AMDGPU/gfx9_asm_sopc.s
index 2001d9ab4f3b9cb..e47d50e4fe5ccd3 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_sopc.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_sopc.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
s_cmp_eq_i32 s1, s2
// CHECK: [0x01,0x02,0x00,0xbf]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_sopk.s b/llvm/test/MC/AMDGPU/gfx9_asm_sopk.s
index 23e2cd294f0a202..e15ea857271ec64 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_sopk.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_sopk.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
s_movk_i32 s5, 0x3141
// CHECK: [0x41,0x31,0x05,0xb0]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx9_asm_sopp.s
index 0a92d8c4b2392d2..b137285aa17e25c 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_sopp.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_sopp.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
s_nop 0x3141
// CHECK: [0x41,0x31,0x80,0xbf]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vintrp.s b/llvm/test/MC/AMDGPU/gfx9_asm_vintrp.s
index 06893eae141c3de..8653fe9d5746820 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_vintrp.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vintrp.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
v_interp_p1_f32 v5, v1, attr0.x
// CHECK: [0x01,0x00,0x14,0xd4]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx9_asm_vop1.s
index 1e48240162a5182..038b4d2185a427d 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vop1.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
v_nop
// CHECK: [0x00,0x00,0x00,0x7e]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx9_asm_vop2.s
index f5c6066f569c653..7b53da641b761e5 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vop2.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
v_cndmask_b32 v5, v1, v2, vcc
// CHECK: [0x01,0x05,0x0a,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
index 8781a01f1eb8efb..f76c49d2bb9e611 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
v_interp_p1_f32_e64 v5, v2, attr0.x
// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s b/llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s
index fab4042e70cdf75..f3f4cae22538a2a 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
v_mad_legacy_f32 v5, v1, v2, v3
// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x04]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vop3p.s b/llvm/test/MC/AMDGPU/gfx9_asm_vop3p.s
index 8cb69ad77d81445..ecffa14de913481 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_vop3p.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vop3p.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
v_pk_mad_i16 v5, v1, v2, v3
// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x0e,0x1c]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx9_asm_vopc.s
index 9d97f20cf016121..345afa2149dc778 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_vopc.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vopc.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
v_cmp_class_f32 vcc, v1, v2
// CHECK: [0x01,0x05,0x20,0x7c]
diff --git a/llvm/test/MC/AMDGPU/gfx9_err_pos.s b/llvm/test/MC/AMDGPU/gfx9_err_pos.s
index 088f240e566f914..350a699fe0d71c2 100644
--- a/llvm/test/MC/AMDGPU/gfx9_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx9_err_pos.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
//==============================================================================
// 'null' operand is not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx9_unsupported.s b/llvm/test/MC/AMDGPU/gfx9_unsupported.s
index 717d10186cff0b9..e6cece5d67f6bd6 100644
--- a/llvm/test/MC/AMDGPU/gfx9_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx9_unsupported.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// Unsupported instructions.
diff --git a/llvm/test/MC/AMDGPU/hsa_isa_version_attrs.s b/llvm/test/MC/AMDGPU/hsa_isa_version_attrs.s
index ed5b1f27396a02f..aafad9bbaf4c400 100644
--- a/llvm/test/MC/AMDGPU/hsa_isa_version_attrs.s
+++ b/llvm/test/MC/AMDGPU/hsa_isa_version_attrs.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx801 -mattr=-fast-fmaf -show-encoding %s | FileCheck --check-prefix=GFX8 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -mattr=-mad-mix-insts,-xnack -show-encoding %s | FileCheck --check-prefix=GFX9 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx801 -mattr=-fast-fmaf -show-encoding %s | FileCheck --check-prefix=GFX8 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -mattr=-mad-mix-insts,-xnack -show-encoding %s | FileCheck --check-prefix=GFX9 %s
.hsa_code_object_isa
// GFX8: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
diff --git a/llvm/test/MC/AMDGPU/inline-imm-inv2pi.s b/llvm/test/MC/AMDGPU/inline-imm-inv2pi.s
index e5ecfa293ba4d70..d730bb32c9f13b8 100644
--- a/llvm/test/MC/AMDGPU/inline-imm-inv2pi.s
+++ b/llvm/test/MC/AMDGPU/inline-imm-inv2pi.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=SI %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=SI %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
// The value inv2pi should not assert on any targets, but is
// printed differently depending on whether it's a legal inline
diff --git a/llvm/test/MC/AMDGPU/labels-branch-err.s b/llvm/test/MC/AMDGPU/labels-branch-err.s
index e7e8bd114a93563..c0bde3008df42f8 100644
--- a/llvm/test/MC/AMDGPU/labels-branch-err.s
+++ b/llvm/test/MC/AMDGPU/labels-branch-err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
+// RUN: not llvm-mc -triple=amdgcn -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
// ERROR: error: undefined label 'undef_label'
s_branch undef_label
diff --git a/llvm/test/MC/AMDGPU/labels-branch-gfx9.s b/llvm/test/MC/AMDGPU/labels-branch-gfx9.s
index 8bf6b968a709122..6f6719ca7eb4e12 100644
--- a/llvm/test/MC/AMDGPU/labels-branch-gfx9.s
+++ b/llvm/test/MC/AMDGPU/labels-branch-gfx9.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -filetype=obj %s | llvm-objdump -d --mcpu=gfx900 - | FileCheck %s --check-prefix=BIN
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -filetype=obj %s | llvm-objdump -d --mcpu=gfx900 - | FileCheck %s --check-prefix=BIN
loop_start:
diff --git a/llvm/test/MC/AMDGPU/labels-branch.s b/llvm/test/MC/AMDGPU/labels-branch.s
index 7315f0d54053b25..2858c6d9010ceea 100644
--- a/llvm/test/MC/AMDGPU/labels-branch.s
+++ b/llvm/test/MC/AMDGPU/labels-branch.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
-// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -filetype=obj %s | llvm-objdump -d --mcpu=fiji - | FileCheck %s --check-prefix=BIN
+// RUN: llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
+// RUN: llvm-mc -triple=amdgcn -mcpu=fiji -filetype=obj %s | llvm-objdump -d --mcpu=fiji - | FileCheck %s --check-prefix=BIN
loop_start:
s_branch loop_start
diff --git a/llvm/test/MC/AMDGPU/lds_direct-ci.s b/llvm/test/MC/AMDGPU/lds_direct-ci.s
index c8d3955042b20bb..d233f9874ecebd3 100644
--- a/llvm/test/MC/AMDGPU/lds_direct-ci.s
+++ b/llvm/test/MC/AMDGPU/lds_direct-ci.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CI
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CI
v_readfirstlane_b32 s0, lds_direct
// CI: v_readfirstlane_b32 s0, src_lds_direct ; encoding: [0xfe,0x04,0x00,0x7e]
diff --git a/llvm/test/MC/AMDGPU/lds_direct-err.s b/llvm/test/MC/AMDGPU/lds_direct-err.s
index 61ec7facf0c5aa4..fce011ec2be374f 100644
--- a/llvm/test/MC/AMDGPU/lds_direct-err.s
+++ b/llvm/test/MC/AMDGPU/lds_direct-err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=NOGFX9 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=NOGFX9 --implicit-check-not=error:
//---------------------------------------------------------------------------//
// lds_direct may be used only with vector ALU instructions
diff --git a/llvm/test/MC/AMDGPU/lds_direct-gfx10.s b/llvm/test/MC/AMDGPU/lds_direct-gfx10.s
index 58ca40afcb195dd..6043f2fec618dbf 100644
--- a/llvm/test/MC/AMDGPU/lds_direct-gfx10.s
+++ b/llvm/test/MC/AMDGPU/lds_direct-gfx10.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck %s --check-prefix=NOGFX10 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck %s --check-prefix=NOGFX10 --implicit-check-not=error:
v_readfirstlane_b32 s0, lds_direct
// GFX10: v_readfirstlane_b32 s0, src_lds_direct ; encoding: [0xfe,0x04,0x00,0x7e]
diff --git a/llvm/test/MC/AMDGPU/lds_direct.s b/llvm/test/MC/AMDGPU/lds_direct.s
index e8ca18933bf8cea..b20256b7aa7a3f0 100644
--- a/llvm/test/MC/AMDGPU/lds_direct.s
+++ b/llvm/test/MC/AMDGPU/lds_direct.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
//---------------------------------------------------------------------------//
// VOP1/3
diff --git a/llvm/test/MC/AMDGPU/literal16-err.s b/llvm/test/MC/AMDGPU/literal16-err.s
index d644a68f6052656..7eb228015bb53c2 100644
--- a/llvm/test/MC/AMDGPU/literal16-err.s
+++ b/llvm/test/MC/AMDGPU/literal16-err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
v_add_f16 v1, 0xfffff, v2
// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/literal16.s b/llvm/test/MC/AMDGPU/literal16.s
index e757a1257ec4ffa..fd8ab05ec3ab4ee 100644
--- a/llvm/test/MC/AMDGPU/literal16.s
+++ b/llvm/test/MC/AMDGPU/literal16.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
v_add_f16 v1, 0, v2
// VI: v_add_f16_e32 v1, 0, v2 ; encoding: [0x80,0x04,0x02,0x3e]
diff --git a/llvm/test/MC/AMDGPU/literals.s b/llvm/test/MC/AMDGPU/literals.s
index e37a4f9a404b6b8..8e5e8fd1886f416 100644
--- a/llvm/test/MC/AMDGPU/literals.s
+++ b/llvm/test/MC/AMDGPU/literals.s
@@ -1,14 +1,14 @@
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefixes=SICI,CI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GFX89
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefixes=GFX89,GFX9
-
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOSI,NOSICI,NOSICIVI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOSI,NOSICI,NOSICIVI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOSICI,NOCIVI,NOSICIVI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOSICIVI,NOVI,NOGFX89 --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOGFX89,NOGFX9 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefixes=SICI,CI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GFX89
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefixes=GFX89,GFX9
+
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOSI,NOSICI,NOSICIVI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOSI,NOSICI,NOSICIVI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOSICI,NOCIVI,NOSICIVI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOSICIVI,NOVI,NOGFX89 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOGFX89,NOGFX9 --implicit-check-not=error:
//---------------------------------------------------------------------------//
// fp literal, expected fp operand
diff --git a/llvm/test/MC/AMDGPU/literalv216-err.s b/llvm/test/MC/AMDGPU/literalv216-err.s
index 8afb78f400f7f89..73148711d0425b8 100644
--- a/llvm/test/MC/AMDGPU/literalv216-err.s
+++ b/llvm/test/MC/AMDGPU/literalv216-err.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX9 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefix=GFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX9 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefix=GFX10 --implicit-check-not=error: %s
v_pk_add_f16 v1, -17, v2
// GFX9: :[[@LINE-1]]:{{[0-9]+}}: error: literal operands are not supported
diff --git a/llvm/test/MC/AMDGPU/literalv216.s b/llvm/test/MC/AMDGPU/literalv216.s
index 245763df77d4013..5b1c7a76ca8531c 100644
--- a/llvm/test/MC/AMDGPU/literalv216.s
+++ b/llvm/test/MC/AMDGPU/literalv216.s
@@ -1,8 +1,8 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s -check-prefix=NOGFX9 --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck %s -check-prefix=NOGFX10 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s -check-prefix=NOGFX9 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck %s -check-prefix=NOGFX10 --implicit-check-not=error:
//===----------------------------------------------------------------------===//
// Inline constants
diff --git a/llvm/test/MC/AMDGPU/macro-examples.s b/llvm/test/MC/AMDGPU/macro-examples.s
index 10cbe88dc87af04..12e05920f40e16f 100644
--- a/llvm/test/MC/AMDGPU/macro-examples.s
+++ b/llvm/test/MC/AMDGPU/macro-examples.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=fiji %s | FileCheck %s --check-prefix=VI
+// RUN: llvm-mc -triple=amdgcn -mcpu=fiji %s | FileCheck %s --check-prefix=VI
//===----------------------------------------------------------------------===//
// Example of reg[expr] and reg[epxr1:expr2] syntax in macros.
diff --git a/llvm/test/MC/AMDGPU/mad-mix.s b/llvm/test/MC/AMDGPU/mad-mix.s
index 4b7be21b48976e9..bc8239d61e34950 100644
--- a/llvm/test/MC/AMDGPU/mad-mix.s
+++ b/llvm/test/MC/AMDGPU/mad-mix.s
@@ -1,6 +1,6 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9-MADMIX %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx904 %s 2>&1 | FileCheck -check-prefix=GFX9-FMAMIX-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx906 %s 2>&1 | FileCheck -check-prefix=GFX9-FMAMIX-ERR --implicit-check-not=error: %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9-MADMIX %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx904 %s 2>&1 | FileCheck -check-prefix=GFX9-FMAMIX-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx906 %s 2>&1 | FileCheck -check-prefix=GFX9-FMAMIX-ERR --implicit-check-not=error: %s
v_mad_mix_f32 v0, v1, v2, v3
// GFX9-MADMIX: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
diff --git a/llvm/test/MC/AMDGPU/mai-err-gfx940.s b/llvm/test/MC/AMDGPU/mai-err-gfx940.s
index 170176615781d55..810788555a71efd 100644
--- a/llvm/test/MC/AMDGPU/mai-err-gfx940.s
+++ b/llvm/test/MC/AMDGPU/mai-err-gfx940.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx940 %s 2>&1 | FileCheck -check-prefix=GFX940 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx940 %s 2>&1 | FileCheck -check-prefix=GFX940 %s
v_mfma_f32_32x32x2bf16 a[0:31], v0, v1, 0
// GFX940: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/mai-err.s b/llvm/test/MC/AMDGPU/mai-err.s
index 2caa6a128bf9d5f..af28d1f0f6622ea 100644
--- a/llvm/test/MC/AMDGPU/mai-err.s
+++ b/llvm/test/MC/AMDGPU/mai-err.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck -check-prefix=GFX908 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX900 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck -check-prefix=GFX908 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX900 --implicit-check-not=error: %s
v_accvgpr_read_b32 v0, v0
// GFX908: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/mai-gfx90a.s b/llvm/test/MC/AMDGPU/mai-gfx90a.s
index 5314c7607417297..176854e67832253 100644
--- a/llvm/test/MC/AMDGPU/mai-gfx90a.s
+++ b/llvm/test/MC/AMDGPU/mai-gfx90a.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck -check-prefix=GFX90A %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck -check-prefix=GFX90A %s
v_accvgpr_read_b32 v2, a0
// GFX90A: v_accvgpr_read_b32 v2, a0 ; encoding: [0x02,0x40,0xd8,0xd3,0x00,0x01,0x00,0x18]
diff --git a/llvm/test/MC/AMDGPU/mai-gfx940.s b/llvm/test/MC/AMDGPU/mai-gfx940.s
index 25e3f6804172bec..f6343ad26cfa448 100644
--- a/llvm/test/MC/AMDGPU/mai-gfx940.s
+++ b/llvm/test/MC/AMDGPU/mai-gfx940.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -show-encoding %s | FileCheck -check-prefix=GFX940 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck -check-prefix=GFX90A %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx940 -show-encoding %s | FileCheck -check-prefix=GFX940 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck -check-prefix=GFX90A %s
//===----------------------------------------------------------------------===//
// Misc opcodes.
diff --git a/llvm/test/MC/AMDGPU/mai.s b/llvm/test/MC/AMDGPU/mai.s
index 31b2fdb1116e50c..475c99e13e4f8c4 100644
--- a/llvm/test/MC/AMDGPU/mai.s
+++ b/llvm/test/MC/AMDGPU/mai.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck -check-prefix=GFX908 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck -check-prefix=NOGFX908 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck -check-prefix=GFX908 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck -check-prefix=NOGFX908 --implicit-check-not=error: %s
v_accvgpr_read_b32 v2, a0
// GFX908: v_accvgpr_read_b32 v2, a0 ; encoding: [0x02,0x40,0xd8,0xd3,0x00,0x01,0x00,0x18]
diff --git a/llvm/test/MC/AMDGPU/max-branch-distance.s b/llvm/test/MC/AMDGPU/max-branch-distance.s
index 3fdd3629d59eb09..0e3337a7e04b4eb 100644
--- a/llvm/test/MC/AMDGPU/max-branch-distance.s
+++ b/llvm/test/MC/AMDGPU/max-branch-distance.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
+// RUN: not llvm-mc -triple=amdgcn -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
// ERROR: max-branch-distance.s:7:3: error: branch size exceeds simm16
// fill v_nop
diff --git a/llvm/test/MC/AMDGPU/mimg-err-gfx940.s b/llvm/test/MC/AMDGPU/mimg-err-gfx940.s
index 06b54103fd4a880..5d2892745633289 100644
--- a/llvm/test/MC/AMDGPU/mimg-err-gfx940.s
+++ b/llvm/test/MC/AMDGPU/mimg-err-gfx940.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx940 %s 2>&1 | FileCheck %s --check-prefix=NOGFX940 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx940 %s 2>&1 | FileCheck %s --check-prefix=NOGFX940 --implicit-check-not=error:
image_load v[4:6], v[238:241], s[28:35] dmask:0x7 unorm
// NOGFX940: :[[@LINE-1]]:{{[0-9]+}}: error:
diff --git a/llvm/test/MC/AMDGPU/mimg-err.s b/llvm/test/MC/AMDGPU/mimg-err.s
index 51820bce326c8c1..6cf92f29c27b78e 100644
--- a/llvm/test/MC/AMDGPU/mimg-err.s
+++ b/llvm/test/MC/AMDGPU/mimg-err.s
@@ -1,8 +1,8 @@
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOGCN --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOGCN --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck %s --check-prefix=NOGCN --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=NOGFX9 --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck %s --check-prefix=NOGFX90A --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOGCN --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOGCN --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji %s 2>&1 | FileCheck %s --check-prefix=NOGCN --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=NOGFX9 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck %s --check-prefix=NOGFX90A --implicit-check-not=error:
//===----------------------------------------------------------------------===//
// Image Load/Store
diff --git a/llvm/test/MC/AMDGPU/mimg-gfx90a.s b/llvm/test/MC/AMDGPU/mimg-gfx90a.s
index 92ddb2ed9d2c5a2..ee606410f795ffb 100644
--- a/llvm/test/MC/AMDGPU/mimg-gfx90a.s
+++ b/llvm/test/MC/AMDGPU/mimg-gfx90a.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck --check-prefix=GFX90A %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck --check-prefix=GFX90A %s
image_load v[4:6], v[238:241], s[28:35] dmask:0x7 unorm
// GFX90A: image_load v[4:6], v[238:241], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x00,0xf0,0xee,0x04,0x07,0x00]
diff --git a/llvm/test/MC/AMDGPU/mimg.s b/llvm/test/MC/AMDGPU/mimg.s
index 071599ea129fc68..38927b40f334754 100644
--- a/llvm/test/MC/AMDGPU/mimg.s
+++ b/llvm/test/MC/AMDGPU/mimg.s
@@ -1,16 +1,16 @@
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=SICIVI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=SICIVI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=SICIVI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICIVI --check-prefix=VI --check-prefix=GFX89 --check-prefix=GFX8_0
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx810 -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICIVI --check-prefix=VI --check-prefix=GFX89 --check-prefix=GFX8_1
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX9 --check-prefix=GFX89
-
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck %s --check-prefix=NOVI --check-prefix=NOGFX8_0 --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx810 %s 2>&1 | FileCheck %s --check-prefix=NOVI --check-prefix=NOGFX8_1 --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=NOGFX9 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=SICIVI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=SICIVI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=SICIVI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICIVI --check-prefix=VI --check-prefix=GFX89 --check-prefix=GFX8_0
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx810 -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICIVI --check-prefix=VI --check-prefix=GFX89 --check-prefix=GFX8_1
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX9 --check-prefix=GFX89
+
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji %s 2>&1 | FileCheck %s --check-prefix=NOVI --check-prefix=NOGFX8_0 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx810 %s 2>&1 | FileCheck %s --check-prefix=NOVI --check-prefix=NOGFX8_1 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=NOGFX9 --implicit-check-not=error:
//===----------------------------------------------------------------------===//
// Image Load/Store
diff --git a/llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s b/llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
index 7a6b49ae6babcd8..d76dc8c9fff63f1 100644
--- a/llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
+++ b/llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck --check-prefixes=GFX90A --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck --check-prefixes=GFX90A --implicit-check-not=error: %s
v_add_f64 v[1:2], v[1:2], v[1:2]
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: vgpr tuples must be 64 bit aligned
diff --git a/llvm/test/MC/AMDGPU/mtbuf-gfx10.s b/llvm/test/MC/AMDGPU/mtbuf-gfx10.s
index c486cd0ebd0047f..f235280874c4aed 100644
--- a/llvm/test/MC/AMDGPU/mtbuf-gfx10.s
+++ b/llvm/test/MC/AMDGPU/mtbuf-gfx10.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefix=GFX10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefix=GFX10-ERR --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// Positive tests for legacy format syntax.
diff --git a/llvm/test/MC/AMDGPU/mtbuf.s b/llvm/test/MC/AMDGPU/mtbuf.s
index 4ae3c44ce0767a8..2a35b7ffc700d76 100644
--- a/llvm/test/MC/AMDGPU/mtbuf.s
+++ b/llvm/test/MC/AMDGPU/mtbuf.s
@@ -1,10 +1,10 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck -check-prefix=SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck -check-prefix=SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,SICI-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,SICI-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,VI-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,SICI-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,SICI-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,VI-ERR --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// Positive tests for legacy dfmt/nfmt syntax.
diff --git a/llvm/test/MC/AMDGPU/mubuf-gfx10.s b/llvm/test/MC/AMDGPU/mubuf-gfx10.s
index 155055145283075..e0f1feb43bee90d 100644
--- a/llvm/test/MC/AMDGPU/mubuf-gfx10.s
+++ b/llvm/test/MC/AMDGPU/mubuf-gfx10.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
buffer_load_sbyte off, s[8:11], s3 glc slc lds
// GFX10: buffer_load_sbyte off, s[8:11], s3 glc slc lds ; encoding: [0x00,0x40,0x25,0xe0,0x00,0x00,0x42,0x03]
diff --git a/llvm/test/MC/AMDGPU/mubuf-gfx9.s b/llvm/test/MC/AMDGPU/mubuf-gfx9.s
index 90f0cdf75375065..994d82f56a2ecf4 100644
--- a/llvm/test/MC/AMDGPU/mubuf-gfx9.s
+++ b/llvm/test/MC/AMDGPU/mubuf-gfx9.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga 2>&1 %s | FileCheck -check-prefix=VI-ERR --implicit-check-not=error: %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga 2>&1 %s | FileCheck -check-prefix=VI-ERR --implicit-check-not=error: %s
buffer_load_ubyte_d16 v1, off, s[4:7], s1
// VI-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/mubuf.s b/llvm/test/MC/AMDGPU/mubuf.s
index 0daca9860986b37..600580ac515560a 100644
--- a/llvm/test/MC/AMDGPU/mubuf.s
+++ b/llvm/test/MC/AMDGPU/mubuf.s
@@ -1,10 +1,10 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefixes=SI,SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck --check-prefixes=CI,SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefixes=SI,SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck --check-prefixes=CI,SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefixes=NOSI,NOSICIVI,NOSICI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck --check-prefixes=NOCI,NOSICIVI,NOSICI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --check-prefixes=NOVI,NOSICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefixes=NOSI,NOSICIVI,NOSICI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck --check-prefixes=NOCI,NOSICIVI,NOSICI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --check-prefixes=NOVI,NOSICIVI --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// Test for different operand combinations
diff --git a/llvm/test/MC/AMDGPU/offset-expr.s b/llvm/test/MC/AMDGPU/offset-expr.s
index 7ec05c7531283c6..92a9bf1b4ce9a9b 100644
--- a/llvm/test/MC/AMDGPU/offset-expr.s
+++ b/llvm/test/MC/AMDGPU/offset-expr.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx906 -filetype=obj %s | llvm-objdump -d --mcpu=gfx906 - | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx906 -filetype=obj %s | llvm-objdump -d --mcpu=gfx906 - | FileCheck %s
// Check that the offset is correctly calculated.
diff --git a/llvm/test/MC/AMDGPU/offsetbug_once.s b/llvm/test/MC/AMDGPU/offsetbug_once.s
index f357c40f3c948d6..e0bd71d675c287d 100644
--- a/llvm/test/MC/AMDGPU/offsetbug_once.s
+++ b/llvm/test/MC/AMDGPU/offsetbug_once.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -d --mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -d --mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
s_getpc_b64 s[0:1]
s_cbranch_vccnz BB0_1
// GFX10: s_cbranch_vccnz BB0_1 ; encoding: [A,A,0x87,0xbf]
diff --git a/llvm/test/MC/AMDGPU/offsetbug_one_and_one.s b/llvm/test/MC/AMDGPU/offsetbug_one_and_one.s
index 875ea44b225cf0a..7023ae80e6b6677 100644
--- a/llvm/test/MC/AMDGPU/offsetbug_one_and_one.s
+++ b/llvm/test/MC/AMDGPU/offsetbug_one_and_one.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -d --mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -d --mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
s_getpc_b64 s[0:1]
s_cbranch_vccnz BB0_1
// GFX10: s_cbranch_vccnz BB0_1 ; encoding: [A,A,0x87,0xbf]
diff --git a/llvm/test/MC/AMDGPU/offsetbug_twice.s b/llvm/test/MC/AMDGPU/offsetbug_twice.s
index 1bcc1adc258161d..b5fa183c8d8b7ff 100644
--- a/llvm/test/MC/AMDGPU/offsetbug_twice.s
+++ b/llvm/test/MC/AMDGPU/offsetbug_twice.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -d --mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -d --mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
s_getpc_b64 s[0:1]
s_cbranch_vccnz BB0_2
// GFX10: s_cbranch_vccnz BB0_2 ; encoding: [A,A,0x87,0xbf]
diff --git a/llvm/test/MC/AMDGPU/out-of-range-registers.s b/llvm/test/MC/AMDGPU/out-of-range-registers.s
index cd602d9854e3052..fda8d5524e68761 100644
--- a/llvm/test/MC/AMDGPU/out-of-range-registers.s
+++ b/llvm/test/MC/AMDGPU/out-of-range-registers.s
@@ -1,12 +1,12 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,SICIVI9-ERR,SIVICI-ERR,SI-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,SICIVI9-ERR,SIVICI-ERR,VI-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,GFX9-ERR,SICIVI9-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,GFX10-ERR --implicit-check-not=error: %s
-
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=SIVICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefixes=SIVICI,CIVI9 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefixes=GFX9,CIVI9 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,SICIVI9-ERR,SIVICI-ERR,SI-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,SICIVI9-ERR,SIVICI-ERR,VI-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,GFX9-ERR,SICIVI9-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefixes=GCN-ERR,GFX10-ERR --implicit-check-not=error: %s
+
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=SIVICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefixes=SIVICI,CIVI9 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefixes=GFX9,CIVI9 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
s_add_i32 s106, s0, s1
// GCN-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range
diff --git a/llvm/test/MC/AMDGPU/reg-syntax-err.s b/llvm/test/MC/AMDGPU/reg-syntax-err.s
index 7307953c0c4e676..dff58c976265f36 100644
--- a/llvm/test/MC/AMDGPU/reg-syntax-err.s
+++ b/llvm/test/MC/AMDGPU/reg-syntax-err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
s_mov_b32 s1, s 1
// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/reg-syntax-extra.s b/llvm/test/MC/AMDGPU/reg-syntax-extra.s
index 492e78b981f63c5..216efe95c0e8292 100644
--- a/llvm/test/MC/AMDGPU/reg-syntax-extra.s
+++ b/llvm/test/MC/AMDGPU/reg-syntax-extra.s
@@ -1,11 +1,11 @@
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefixes=GCN,VI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefixes=GCN,GFX10 %s
-
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefixes=NOSICI,NOSICIVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck --check-prefix=NOVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefix=NOGFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefixes=GCN,VI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefixes=GCN,GFX10 %s
+
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefixes=NOSICI,NOSICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji %s 2>&1 | FileCheck --check-prefix=NOVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefix=NOGFX10 --implicit-check-not=error: %s
s_mov_b32 [ttmp5], [ttmp3]
// SICI: s_mov_b32 ttmp5, ttmp3 ; encoding: [0x73,0x03,0xf5,0xbe]
diff --git a/llvm/test/MC/AMDGPU/regression/bug28165.s b/llvm/test/MC/AMDGPU/regression/bug28165.s
index 375eb338c0a6ae8..1e31f204e8995f5 100644
--- a/llvm/test/MC/AMDGPU/regression/bug28165.s
+++ b/llvm/test/MC/AMDGPU/regression/bug28165.s
@@ -1,7 +1,7 @@
-// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
-// RUN: llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefixes=GCN,VI
+// RUN: llvm-mc -triple=amdgcn -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
+// RUN: llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefixes=GCN,VI
// SICI: v_cmp_eq_f64_e32 vcc, 0.5, v[254:255] ; encoding: [0xf0,0xfc,0x45,0x7c]
// VI: v_cmp_eq_f64_e32 vcc, 0.5, v[254:255] ; encoding: [0xf0,0xfc,0xc5,0x7c]
diff --git a/llvm/test/MC/AMDGPU/regression/bug28168.s b/llvm/test/MC/AMDGPU/regression/bug28168.s
index e65414856e722a6..4b2604d0581b2a1 100644
--- a/llvm/test/MC/AMDGPU/regression/bug28168.s
+++ b/llvm/test/MC/AMDGPU/regression/bug28168.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CI
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CI
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
v_mqsad_pk_u16_u8 v[2:3], s[0:1], 1, v[254:255]
// CI: [0x02,0x00,0xe6,0xd2,0x00,0x02,0xf9,0x07]
diff --git a/llvm/test/MC/AMDGPU/regression/bug28413.s b/llvm/test/MC/AMDGPU/regression/bug28413.s
index f301764b4a6814f..5fbf9f37d4a8de9 100644
--- a/llvm/test/MC/AMDGPU/regression/bug28413.s
+++ b/llvm/test/MC/AMDGPU/regression/bug28413.s
@@ -1,7 +1,7 @@
-// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
-// RUN: llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefixes=GCN,VI
+// RUN: llvm-mc -triple=amdgcn -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
+// RUN: llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefixes=GCN,VI
v_cmp_eq_i32 vcc, 0.5, v0
// SICI: v_cmp_eq_i32_e32 vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x04,0x7d]
diff --git a/llvm/test/MC/AMDGPU/regression/bug28538.s b/llvm/test/MC/AMDGPU/regression/bug28538.s
index 1dba3c0098bd36f..dd66a51fbfa32ed 100644
--- a/llvm/test/MC/AMDGPU/regression/bug28538.s
+++ b/llvm/test/MC/AMDGPU/regression/bug28538.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --check-prefix=NOVI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --check-prefix=NOVI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: not a valid operand.
// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: invalid row_bcast value
diff --git a/llvm/test/MC/AMDGPU/s_endpgm.s b/llvm/test/MC/AMDGPU/s_endpgm.s
index 6a9d3ea285faadf..59170f1497b2d79 100644
--- a/llvm/test/MC/AMDGPU/s_endpgm.s
+++ b/llvm/test/MC/AMDGPU/s_endpgm.s
@@ -1,6 +1,6 @@
-// RUN: llvm-mc -arch=amdgcn %s | FileCheck -strict-whitespace %s -check-prefix=WHITESPACE
-// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -filetype=obj %s | llvm-objcopy -S -K keep_symbol - | llvm-objdump -d --mcpu=gfx900 - | FileCheck %s --check-prefix=BIN
+// RUN: llvm-mc -triple=amdgcn %s | FileCheck -strict-whitespace %s -check-prefix=WHITESPACE
+// RUN: llvm-mc -triple=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -filetype=obj %s | llvm-objcopy -S -K keep_symbol - | llvm-objdump -d --mcpu=gfx900 - | FileCheck %s --check-prefix=BIN
// WHITESPACE: s_endpgm{{$}}
// GCN: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
diff --git a/llvm/test/MC/AMDGPU/smem-err.s b/llvm/test/MC/AMDGPU/smem-err.s
index 2c4c32d521f75f0..091509cdc26a5e7 100644
--- a/llvm/test/MC/AMDGPU/smem-err.s
+++ b/llvm/test/MC/AMDGPU/smem-err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
s_memtime exec
// NOVI: :[[@LINE-1]]:11: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/smem.s b/llvm/test/MC/AMDGPU/smem.s
index 0e33d95cd04e4a5..c2785c139cca777 100644
--- a/llvm/test/MC/AMDGPU/smem.s
+++ b/llvm/test/MC/AMDGPU/smem.s
@@ -1,17 +1,17 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck -check-prefix=SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=kaveri -show-encoding %s | FileCheck -check-prefix=SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck --check-prefixes=VI,GFX89 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefixes=GFX89,GFX9 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1012 -show-encoding %s | FileCheck --check-prefixes=GFX10,GFX1012 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefixes=NOSICI,NOSICIGFX10,NOSICIGFX1030,NOSICIVIGFX1030 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck --check-prefixes=NOSICI,NOSICIGFX10,NOSICIGFX1030,NOSICIVIGFX1030 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=kaveri %s 2>&1 | FileCheck --check-prefixes=NOSICI,NOSICIGFX10,NOSICIGFX1030,NOSICIVIGFX1030 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --check-prefixes=NOVI,NOSICIVIGFX1030 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --check-prefixes=NOGFX9GFX10,NOGFX9GFX1012,NOGFX9 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1012 %s 2>&1 | FileCheck --check-prefixes=NOSICIGFX10,NOGFX9GFX10,NOGFX9GFX1012,NOGFX10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030 %s 2>&1 | FileCheck --check-prefixes=NOSICIGFX1030,NOSICIVIGFX1030,NOSICIGFX10,NOGFX9GFX10,NOGFX1030,NOGFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck -check-prefix=SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=kaveri -show-encoding %s | FileCheck -check-prefix=SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck --check-prefixes=VI,GFX89 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefixes=GFX89,GFX9 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1012 -show-encoding %s | FileCheck --check-prefixes=GFX10,GFX1012 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefixes=NOSICI,NOSICIGFX10,NOSICIGFX1030,NOSICIVIGFX1030 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck --check-prefixes=NOSICI,NOSICIGFX10,NOSICIGFX1030,NOSICIVIGFX1030 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=kaveri %s 2>&1 | FileCheck --check-prefixes=NOSICI,NOSICIGFX10,NOSICIGFX1030,NOSICIVIGFX1030 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --check-prefixes=NOVI,NOSICIVIGFX1030 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --check-prefixes=NOGFX9GFX10,NOGFX9GFX1012,NOGFX9 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1012 %s 2>&1 | FileCheck --check-prefixes=NOSICIGFX10,NOGFX9GFX10,NOGFX9GFX1012,NOGFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1030 %s 2>&1 | FileCheck --check-prefixes=NOSICIGFX1030,NOSICIVIGFX1030,NOSICIGFX10,NOGFX9GFX10,NOGFX1030,NOGFX10 --implicit-check-not=error: %s
s_dcache_wb
// GFX89: s_dcache_wb ; encoding: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/smrd-err.s b/llvm/test/MC/AMDGPU/smrd-err.s
index b217c34ce85c382..11d6658cffb8b08 100644
--- a/llvm/test/MC/AMDGPU/smrd-err.s
+++ b/llvm/test/MC/AMDGPU/smrd-err.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tahiti %s | FileCheck -check-prefix=SI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tahiti %s | FileCheck -check-prefix=SI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
s_load_dwordx4 s[100:103], s[2:3], s4
// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
diff --git a/llvm/test/MC/AMDGPU/smrd.s b/llvm/test/MC/AMDGPU/smrd.s
index f5f57acb227c8ba..b3b3824f1988ca5 100644
--- a/llvm/test/MC/AMDGPU/smrd.s
+++ b/llvm/test/MC/AMDGPU/smrd.s
@@ -1,11 +1,11 @@
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefix=GCN %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck --check-prefixes=GCN,CI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=VI %s
-
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck %s --check-prefix=NOVI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefix=GCN %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck --check-prefixes=GCN,CI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=VI %s
+
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji %s 2>&1 | FileCheck %s --check-prefix=NOVI --implicit-check-not=error:
//===----------------------------------------------------------------------===//
// Offset Handling
diff --git a/llvm/test/MC/AMDGPU/sop1-err.s b/llvm/test/MC/AMDGPU/sop1-err.s
index 14feba7950477fd..18b1f912b1d556a 100644
--- a/llvm/test/MC/AMDGPU/sop1-err.s
+++ b/llvm/test/MC/AMDGPU/sop1-err.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --check-prefixes=GCN,VI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --check-prefixes=GCN,VI --implicit-check-not=error: %s
s_mov_b32 v1, s2
// GCN: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/sop1.s b/llvm/test/MC/AMDGPU/sop1.s
index 73227c05c67c839..6e5f329142d2a4d 100644
--- a/llvm/test/MC/AMDGPU/sop1.s
+++ b/llvm/test/MC/AMDGPU/sop1.s
@@ -1,12 +1,12 @@
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=GFX89 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefixes=GFX89,GFX9 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
-
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck --check-prefixes=NOSICI,NOSICIVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck --check-prefixes=NOSICIVI,NOGFX89 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --check-prefixes=NOGFX9,NOGFX89 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 2>&1 %s | FileCheck --check-prefix=GFX10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck --check-prefix=SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=GFX89 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefixes=GFX89,GFX9 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck --check-prefixes=NOSICI,NOSICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji %s 2>&1 | FileCheck --check-prefixes=NOSICIVI,NOGFX89 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --check-prefixes=NOGFX9,NOGFX89 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 2>&1 %s | FileCheck --check-prefix=GFX10-ERR --implicit-check-not=error: %s
s_mov_b32 s1, s2
// SICI: s_mov_b32 s1, s2 ; encoding: [0x02,0x03,0x81,0xbe]
diff --git a/llvm/test/MC/AMDGPU/sop2-err.s b/llvm/test/MC/AMDGPU/sop2-err.s
index b095f1c6a174b17..eb68d03c1ce0840 100644
--- a/llvm/test/MC/AMDGPU/sop2-err.s
+++ b/llvm/test/MC/AMDGPU/sop2-err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
s_cbranch_g_fork 100, s[6:7]
// GCN: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/sop2.s b/llvm/test/MC/AMDGPU/sop2.s
index 26537be40c8a580..fbf1dbf97d51a4d 100644
--- a/llvm/test/MC/AMDGPU/sop2.s
+++ b/llvm/test/MC/AMDGPU/sop2.s
@@ -1,16 +1,16 @@
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefixes=GCN,GFX89 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefixes=GCN,GFX89,GFX9 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefixes=GCN,GFX10 %s
-
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck --check-prefix=NOSICIVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefix=NOSICIVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck --check-prefix=NOSICIVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck --check-prefixes=NOSICIVI,NOGFX89 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --check-prefixes=NOGFX9,NOGFX89 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 2>&1 %s | FileCheck --check-prefix=GFX10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefixes=GCN,GFX89 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefixes=GCN,GFX89,GFX9 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefixes=GCN,GFX10 %s
+
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck --check-prefix=NOSICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefix=NOSICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck --check-prefix=NOSICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji %s 2>&1 | FileCheck --check-prefixes=NOSICIVI,NOGFX89 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --check-prefixes=NOGFX9,NOGFX89 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 2>&1 %s | FileCheck --check-prefix=GFX10-ERR --implicit-check-not=error: %s
s_add_u32 s1, s2, s3
// GCN: s_add_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x80]
diff --git a/llvm/test/MC/AMDGPU/sopc-err.s b/llvm/test/MC/AMDGPU/sopc-err.s
index 60d2badf986884c..8f74038e4f04d0d 100644
--- a/llvm/test/MC/AMDGPU/sopc-err.s
+++ b/llvm/test/MC/AMDGPU/sopc-err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI --implicit-check-not=error: %s
s_set_gpr_idx_on s0, s1
// VI: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
diff --git a/llvm/test/MC/AMDGPU/sopc.s b/llvm/test/MC/AMDGPU/sopc.s
index c3a79d8b5f1622d..73564f99f697437 100644
--- a/llvm/test/MC/AMDGPU/sopc.s
+++ b/llvm/test/MC/AMDGPU/sopc.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=GCN %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefixes=GCN,VI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefix=GFX10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=GCN %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefixes=GCN,VI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefix=GFX10-ERR --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// SOPC Instructions
diff --git a/llvm/test/MC/AMDGPU/sopk-err.s b/llvm/test/MC/AMDGPU/sopk-err.s
index 88bcd0ca07d5d43..504ee1d11cbc97d 100644
--- a/llvm/test/MC/AMDGPU/sopk-err.s
+++ b/llvm/test/MC/AMDGPU/sopk-err.s
@@ -1,16 +1,16 @@
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefix=SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck --check-prefix=VI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
-
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefixes=GCN,SICIVI-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefixes=GCN,SICIVI-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefixes=GCN,SICIVI-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefixes=GCN,GFX9-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefixes=GCN,GFX10-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck -check-prefixes=GCN,GFX11-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck --check-prefix=SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefix=SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck --check-prefix=VI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
+
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck -check-prefixes=GCN,SICIVI-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefixes=GCN,SICIVI-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefixes=GCN,SICIVI-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefixes=GCN,GFX9-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefixes=GCN,GFX10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck -check-prefixes=GCN,GFX11-ERR --implicit-check-not=error: %s
s_setreg_b32 0x1f803, s2
// GCN: :[[@LINE-1]]:{{[0-9]+}}: error: invalid immediate: only 16-bit values are legal
diff --git a/llvm/test/MC/AMDGPU/sopk.s b/llvm/test/MC/AMDGPU/sopk.s
index c769c7534b2dee0..2b20c35aa7719ae 100644
--- a/llvm/test/MC/AMDGPU/sopk.s
+++ b/llvm/test/MC/AMDGPU/sopk.s
@@ -1,16 +1,16 @@
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefixes=GCN,VI9,VI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefixes=GCN,VI9,GFX9 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefixes=GCN,GFX10 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefixes=GCN,GFX11 %s
-
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=NOSICIVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICIVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck -check-prefix=NOSICIVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --check-prefix=NOGFX9 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefix=NOGFX10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefix=NOGFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefixes=GCN,SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefixes=GCN,VI9,VI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefixes=GCN,VI9,GFX9 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefixes=GCN,GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefixes=GCN,GFX11 %s
+
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck -check-prefix=NOSICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji %s 2>&1 | FileCheck -check-prefix=NOSICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck --check-prefix=NOGFX9 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefix=NOGFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefix=NOGFX11 --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// Instructions
diff --git a/llvm/test/MC/AMDGPU/sopp-err.s b/llvm/test/MC/AMDGPU/sopp-err.s
index 0e43b89dcf0f0f2..c7f28faa55763be 100644
--- a/llvm/test/MC/AMDGPU/sopp-err.s
+++ b/llvm/test/MC/AMDGPU/sopp-err.s
@@ -1,8 +1,8 @@
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck --check-prefixes=GCN,PREGFX11,SICI,SICIVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefixes=GCN,PREGFX11,SICI,SICIVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck --check-prefixes=GCN,PREGFX11,VI,SICIVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefixes=GCN,PREGFX11,GFX10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefixes=GCN,GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck --check-prefixes=GCN,PREGFX11,SICI,SICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefixes=GCN,PREGFX11,SICI,SICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji %s 2>&1 | FileCheck --check-prefixes=GCN,PREGFX11,VI,SICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefixes=GCN,PREGFX11,GFX10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefixes=GCN,GFX11 --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// sendmsg
diff --git a/llvm/test/MC/AMDGPU/sopp-gfx10.s b/llvm/test/MC/AMDGPU/sopp-gfx10.s
index eb08a609719343d..f50ed92cc988feb 100644
--- a/llvm/test/MC/AMDGPU/sopp-gfx10.s
+++ b/llvm/test/MC/AMDGPU/sopp-gfx10.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
//===----------------------------------------------------------------------===//
// s_sendmsg
diff --git a/llvm/test/MC/AMDGPU/sopp-gfx9.s b/llvm/test/MC/AMDGPU/sopp-gfx9.s
index 48045b8e1ecad04..e760d497896fa56 100644
--- a/llvm/test/MC/AMDGPU/sopp-gfx9.s
+++ b/llvm/test/MC/AMDGPU/sopp-gfx9.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GFX9 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GFX9 %s
//===----------------------------------------------------------------------===//
// s_waitcnt
diff --git a/llvm/test/MC/AMDGPU/sopp.s b/llvm/test/MC/AMDGPU/sopp.s
index a5faa76a0932875..7771573df1ecbfa 100644
--- a/llvm/test/MC/AMDGPU/sopp.s
+++ b/llvm/test/MC/AMDGPU/sopp.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefixes=GCN,SI %s
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
-// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefixes=GCN,VI %s
+// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck --check-prefixes=GCN,SI %s
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefixes=GCN,VI %s
//===----------------------------------------------------------------------===//
// Edge Cases
diff --git a/llvm/test/MC/AMDGPU/sym_kernel_scope.s b/llvm/test/MC/AMDGPU/sym_kernel_scope.s
index 3e2857120904116..2e6e9d7e3960de4 100644
--- a/llvm/test/MC/AMDGPU/sym_kernel_scope.s
+++ b/llvm/test/MC/AMDGPU/sym_kernel_scope.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s
.byte .kernel.sgpr_count
// CHECK: .byte 0
diff --git a/llvm/test/MC/AMDGPU/sym_kernel_scope_agpr.s b/llvm/test/MC/AMDGPU/sym_kernel_scope_agpr.s
index ea065ea9ef5a94f..9602f91aec57f6e 100644
--- a/llvm/test/MC/AMDGPU/sym_kernel_scope_agpr.s
+++ b/llvm/test/MC/AMDGPU/sym_kernel_scope_agpr.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck -check-prefixes=GFX90A %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck -check-prefixes=GFX908 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck -check-prefixes=GFX90A %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck -check-prefixes=GFX908 %s
// Based on sym_kernel_scope.s
.byte .kernel.agpr_count
diff --git a/llvm/test/MC/AMDGPU/sym_option.s b/llvm/test/MC/AMDGPU/sym_option.s
index 48ce5df46f8cd66..33f16dc74dc94fc 100644
--- a/llvm/test/MC/AMDGPU/sym_option.s
+++ b/llvm/test/MC/AMDGPU/sym_option.s
@@ -1,12 +1,12 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tahiti %s | FileCheck %s --check-prefix=SI
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire %s | FileCheck %s --check-prefix=BONAIRE
-// RUN: llvm-mc -arch=amdgcn -mcpu=hawaii %s | FileCheck %s --check-prefix=HAWAII
-// RUN: llvm-mc -arch=amdgcn -mcpu=kabini %s | FileCheck %s --check-prefix=KABINI
-// RUN: llvm-mc -arch=amdgcn -mcpu=iceland %s | FileCheck %s --check-prefix=ICELAND
-// RUN: llvm-mc -arch=amdgcn -mcpu=carrizo %s | FileCheck %s --check-prefix=CARRIZO
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga %s | FileCheck %s --check-prefix=TONGA
-// RUN: llvm-mc -arch=amdgcn -mcpu=fiji %s | FileCheck %s --check-prefix=FIJI
-// RUN: llvm-mc -arch=amdgcn -mcpu=stoney %s | FileCheck %s --check-prefix=STONEY
+// RUN: llvm-mc -triple=amdgcn -mcpu=tahiti %s | FileCheck %s --check-prefix=SI
+// RUN: llvm-mc -triple=amdgcn -mcpu=bonaire %s | FileCheck %s --check-prefix=BONAIRE
+// RUN: llvm-mc -triple=amdgcn -mcpu=hawaii %s | FileCheck %s --check-prefix=HAWAII
+// RUN: llvm-mc -triple=amdgcn -mcpu=kabini %s | FileCheck %s --check-prefix=KABINI
+// RUN: llvm-mc -triple=amdgcn -mcpu=iceland %s | FileCheck %s --check-prefix=ICELAND
+// RUN: llvm-mc -triple=amdgcn -mcpu=carrizo %s | FileCheck %s --check-prefix=CARRIZO
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga %s | FileCheck %s --check-prefix=TONGA
+// RUN: llvm-mc -triple=amdgcn -mcpu=fiji %s | FileCheck %s --check-prefix=FIJI
+// RUN: llvm-mc -triple=amdgcn -mcpu=stoney %s | FileCheck %s --check-prefix=STONEY
.byte .option.machine_version_major
// SI: .byte 6
diff --git a/llvm/test/MC/AMDGPU/trap.s b/llvm/test/MC/AMDGPU/trap.s
index 13ad7b00e3a10e8..366ba7f43aaaef6 100644
--- a/llvm/test/MC/AMDGPU/trap.s
+++ b/llvm/test/MC/AMDGPU/trap.s
@@ -1,12 +1,12 @@
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
-
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=NOGFX9 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
+
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=NOGFX9 --implicit-check-not=error:
//===----------------------------------------------------------------------===//
// Trap Handler related - 32 bit registers
diff --git a/llvm/test/MC/AMDGPU/v_illegal-atomics.s b/llvm/test/MC/AMDGPU/v_illegal-atomics.s
index 9ee9acda7252589..175f017ad9caae8 100644
--- a/llvm/test/MC/AMDGPU/v_illegal-atomics.s
+++ b/llvm/test/MC/AMDGPU/v_illegal-atomics.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefix=GFX1030 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX1100 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefix=GFX1030 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX1100 %s
v_illegal
// GFX1030: encoding: [0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/vcmpx-gfx10.s b/llvm/test/MC/AMDGPU/vcmpx-gfx10.s
index eeccc4b88e77e17..15e7159568d40b4 100644
--- a/llvm/test/MC/AMDGPU/vcmpx-gfx10.s
+++ b/llvm/test/MC/AMDGPU/vcmpx-gfx10.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
// GFX10: v_cmpx_le_f32_e64 v1, v0 ; encoding: [0x7e,0x00,0x13,0xd4,0x01,0x01,0x02,0x00]
v_cmpx_le_f32_e64 v1, v0
diff --git a/llvm/test/MC/AMDGPU/vintrp-e64-err.s b/llvm/test/MC/AMDGPU/vintrp-e64-err.s
index 41f7b539c570fe8..663f48dfde0ebb5 100644
--- a/llvm/test/MC/AMDGPU/vintrp-e64-err.s
+++ b/llvm/test/MC/AMDGPU/vintrp-e64-err.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck %s --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck %s --implicit-check-not=error:
v_interp_p1_f32_e64 v5, 0.5, attr0.w
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/vintrp-err.s b/llvm/test/MC/AMDGPU/vintrp-err.s
index 05c26d5ae9419a3..6cda6d13276b393 100644
--- a/llvm/test/MC/AMDGPU/vintrp-err.s
+++ b/llvm/test/MC/AMDGPU/vintrp-err.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
v_interp_p1_f32 v0, v1
// GCN: :[[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
diff --git a/llvm/test/MC/AMDGPU/vintrp.s b/llvm/test/MC/AMDGPU/vintrp.s
index fbeb540b712864e..db15f8eb4499dda 100644
--- a/llvm/test/MC/AMDGPU/vintrp.s
+++ b/llvm/test/MC/AMDGPU/vintrp.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck -check-prefix=SI %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
+// RUN: llvm-mc -triple=amdgcn -show-encoding %s | FileCheck -check-prefix=SI %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
v_interp_p1_f32 v1, v0, attr0.x
// SI: v_interp_p1_f32 v1, v0, attr0.x ; encoding: [0x00,0x00,0x04,0xc8]
diff --git a/llvm/test/MC/AMDGPU/vop-err.s b/llvm/test/MC/AMDGPU/vop-err.s
index 6bf8272183aa209..4af69a5752ac983 100644
--- a/llvm/test/MC/AMDGPU/vop-err.s
+++ b/llvm/test/MC/AMDGPU/vop-err.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --implicit-check-not=error: %s
// GENERIC LIMITATIONS ON VOP FORMATS: CONSTANT BUS RESTRICTIONS
diff --git a/llvm/test/MC/AMDGPU/vop1-gfx9-err.s b/llvm/test/MC/AMDGPU/vop1-gfx9-err.s
index 317bbfa354111ff..71290eb80686427 100644
--- a/llvm/test/MC/AMDGPU/vop1-gfx9-err.s
+++ b/llvm/test/MC/AMDGPU/vop1-gfx9-err.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefixes=GCN,GFX9 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefixes=GCN,VI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck -check-prefixes=GCN,CI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefixes=GCN,GFX9 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefixes=GCN,VI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck -check-prefixes=GCN,CI --implicit-check-not=error: %s
v_swap_b32 v1, 1
// CI: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/vop1-gfx9.s b/llvm/test/MC/AMDGPU/vop1-gfx9.s
index b88d872b28e5630..c810298a61e1901 100644
--- a/llvm/test/MC/AMDGPU/vop1-gfx9.s
+++ b/llvm/test/MC/AMDGPU/vop1-gfx9.s
@@ -1,7 +1,7 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
v_swap_b32 v1, v2
// GFX9: v_swap_b32 v1, v2 ; encoding: [0x02,0xa3,0x02,0x7e]
diff --git a/llvm/test/MC/AMDGPU/vop1.s b/llvm/test/MC/AMDGPU/vop1.s
index 914627bebf92755..f7e5db7fa3d39f0 100644
--- a/llvm/test/MC/AMDGPU/vop1.s
+++ b/llvm/test/MC/AMDGPU/vop1.s
@@ -1,12 +1,12 @@
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefixes=GCN,CI,SICI,CIVI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefixes=GCN,CIVI,VI
-
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s -check-prefix=NOVI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefixes=GCN,CI,SICI,CIVI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefixes=GCN,CIVI,VI
+
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s -check-prefix=NOVI --implicit-check-not=error:
// Force 32-bit encoding
diff --git a/llvm/test/MC/AMDGPU/vop2-err.s b/llvm/test/MC/AMDGPU/vop2-err.s
index a951e0697588d21..122fbd7134911a0 100644
--- a/llvm/test/MC/AMDGPU/vop2-err.s
+++ b/llvm/test/MC/AMDGPU/vop2-err.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// Generic checks
diff --git a/llvm/test/MC/AMDGPU/vop2.s b/llvm/test/MC/AMDGPU/vop2.s
index c5e8e684fd12750..ade7ce95f17584a 100644
--- a/llvm/test/MC/AMDGPU/vop2.s
+++ b/llvm/test/MC/AMDGPU/vop2.s
@@ -1,12 +1,12 @@
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=VI
-
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s -check-prefix=NOVI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=VI
+
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s -check-prefix=NOVI --implicit-check-not=error:
//===----------------------------------------------------------------------===//
// Generic Checks for floating-point instructions (These have modifiers).
diff --git a/llvm/test/MC/AMDGPU/vop3-convert.s b/llvm/test/MC/AMDGPU/vop3-convert.s
index ebf4251fb71d234..0f33a81c6ea0fee 100644
--- a/llvm/test/MC/AMDGPU/vop3-convert.s
+++ b/llvm/test/MC/AMDGPU/vop3-convert.s
@@ -1,12 +1,12 @@
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefixes=GCN,VI
-
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s -check-prefix=NOVI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefixes=GCN,SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefixes=GCN,VI
+
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s -check-prefix=NOVI --implicit-check-not=error:
v_mov_b32 [v1], [v2]
// GCN: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
diff --git a/llvm/test/MC/AMDGPU/vop3-errs.s b/llvm/test/MC/AMDGPU/vop3-errs.s
index 3e3bde0e8373fc5..e600151410389d1 100644
--- a/llvm/test/MC/AMDGPU/vop3-errs.s
+++ b/llvm/test/MC/AMDGPU/vop3-errs.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=GFX67 --check-prefix=GCN --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=GFX67 --check-prefix=GCN --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck %s --check-prefix=GFX89 --check-prefix=GCN --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=GFX89 --check-prefix=GCN --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefix=GFX67 --check-prefix=GCN --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=GFX67 --check-prefix=GCN --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji %s 2>&1 | FileCheck %s --check-prefix=GFX89 --check-prefix=GCN --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=GFX89 --check-prefix=GCN --implicit-check-not=error:
v_add_f32_e64 v0, v1
// GCN: :[[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
diff --git a/llvm/test/MC/AMDGPU/vop3-gfx10.s b/llvm/test/MC/AMDGPU/vop3-gfx10.s
index dc0e8579571e875..50810e82647b1a2 100644
--- a/llvm/test/MC/AMDGPU/vop3-gfx10.s
+++ b/llvm/test/MC/AMDGPU/vop3-gfx10.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
v_mad_i16 v5, v1, 4.0, v3
// GFX10: v_mad_i16 v5, v1, 0x4400, v3 ; encoding: [0x05,0x00,0x5e,0xd7,0x01,0xff,0x0d,0x04,0x00,0x44,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/vop3-gfx9.s b/llvm/test/MC/AMDGPU/vop3-gfx9.s
index c7fa8c2e14b4d85..b61f690d20233c8 100644
--- a/llvm/test/MC/AMDGPU/vop3-gfx9.s
+++ b/llvm/test/MC/AMDGPU/vop3-gfx9.s
@@ -1,11 +1,11 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s | FileCheck -check-prefix=SICI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GFX9 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefixes=NOSICI,NOGCN --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck -check-prefixes=NOSICI,NOGCN --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefixes=NOVI,NOGCN --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=NOGFX9 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=hawaii -show-encoding %s | FileCheck -check-prefix=SICI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GFX9 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefixes=NOSICI,NOGCN --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck -check-prefixes=NOSICI,NOGCN --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefixes=NOVI,NOGCN --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=NOGFX9 --implicit-check-not=error: %s
v_lshl_add_u32 v1, v2, v3, v4
// GFX9: v_lshl_add_u32 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xfd,0xd1,0x02,0x07,0x12,0x04]
diff --git a/llvm/test/MC/AMDGPU/vop3-literal.s b/llvm/test/MC/AMDGPU/vop3-literal.s
index 4b89d9f16a091cc..d97ded08769a4ec 100644
--- a/llvm/test/MC/AMDGPU/vop3-literal.s
+++ b/llvm/test/MC/AMDGPU/vop3-literal.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck -check-prefix=GFX10-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX9-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck -check-prefix=GFX10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX9-ERR --implicit-check-not=error: %s
v_bfe_u32 v0, 0x3039, v1, s1
// GFX10: v_bfe_u32 v0, 0x3039, v1, s1 ; encoding: [0x00,0x00,0x48,0xd5,0xff,0x02,0x06,0x00,0x39,0x30,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/vop3-modifiers-err.s b/llvm/test/MC/AMDGPU/vop3-modifiers-err.s
index 1163e8ccbd6d40d..fc113874d7a72c2 100644
--- a/llvm/test/MC/AMDGPU/vop3-modifiers-err.s
+++ b/llvm/test/MC/AMDGPU/vop3-modifiers-err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --implicit-check-not=error: %s
//---------------------------------------------------------------------------//
// VOP3 Modifiers
diff --git a/llvm/test/MC/AMDGPU/vop3-modifiers.s b/llvm/test/MC/AMDGPU/vop3-modifiers.s
index 8c9767bda26ded7..aa86f84cfb23426 100644
--- a/llvm/test/MC/AMDGPU/vop3-modifiers.s
+++ b/llvm/test/MC/AMDGPU/vop3-modifiers.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
//---------------------------------------------------------------------------//
// VOP1/VOP3 F16
diff --git a/llvm/test/MC/AMDGPU/vop3-vop1-nosrc.s b/llvm/test/MC/AMDGPU/vop3-vop1-nosrc.s
index ae90d0dc3f60891..3b68d515ebcb775 100644
--- a/llvm/test/MC/AMDGPU/vop3-vop1-nosrc.s
+++ b/llvm/test/MC/AMDGPU/vop3-vop1-nosrc.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
+// RUN: llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
// XFAIL: *
// FIXME: We should be printing _e64 suffixes for these.
diff --git a/llvm/test/MC/AMDGPU/vop3.s b/llvm/test/MC/AMDGPU/vop3.s
index ae8f814e086ae75..27fcf5e1ba33728 100644
--- a/llvm/test/MC/AMDGPU/vop3.s
+++ b/llvm/test/MC/AMDGPU/vop3.s
@@ -1,14 +1,14 @@
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s | FileCheck %s --check-prefix=CI --check-prefix=SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
+// RUN: not llvm-mc -triple=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=hawaii -show-encoding %s | FileCheck %s --check-prefix=CI --check-prefix=SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
// Make sure interp instructions disassemble regardless of lds bank count
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx810 -show-encoding %s | FileCheck %s --check-prefix=VI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx810 -show-encoding %s | FileCheck %s --check-prefix=VI
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck %s -check-prefix=NOCI --check-prefix=NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --check-prefix=NOVI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx810 %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck %s -check-prefix=NOCI --check-prefix=NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --check-prefix=NOVI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx810 %s 2>&1 | FileCheck -check-prefix=NOVI --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
// VOPC Instructions
diff --git a/llvm/test/MC/AMDGPU/vop3p-err.s b/llvm/test/MC/AMDGPU/vop3p-err.s
index 5eb3e8dc25bee25..549f8ee216d9cf5 100644
--- a/llvm/test/MC/AMDGPU/vop3p-err.s
+++ b/llvm/test/MC/AMDGPU/vop3p-err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX9 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX9 --implicit-check-not=error: %s
// GFX9: :[[@LINE+1]]:25: error: invalid operand for instruction
v_pk_add_u16 v1, v2, v3 op_sel
diff --git a/llvm/test/MC/AMDGPU/vop3p.s b/llvm/test/MC/AMDGPU/vop3p.s
index 197da25734be92f..a84ada261abe89f 100644
--- a/llvm/test/MC/AMDGPU/vop3p.s
+++ b/llvm/test/MC/AMDGPU/vop3p.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
//
// Test op_sel/op_sel_hi
//
diff --git a/llvm/test/MC/AMDGPU/vop_dpp.s b/llvm/test/MC/AMDGPU/vop_dpp.s
index eb6c9924ad5e8ed..b2251f5b3e33be6 100644
--- a/llvm/test/MC/AMDGPU/vop_dpp.s
+++ b/llvm/test/MC/AMDGPU/vop_dpp.s
@@ -1,11 +1,11 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefixes=VI,VI9
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefixes=GFX9,VI9
-
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefixes=NOSICI,NOCI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --check-prefix=NOVI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=NOGFX9 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefixes=VI,VI9
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefixes=GFX9,VI9
+
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefixes=NOSICI,NOCI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --check-prefix=NOVI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=NOGFX9 --implicit-check-not=error:
//===----------------------------------------------------------------------===//
// Check dpp_ctrl values
diff --git a/llvm/test/MC/AMDGPU/vop_dpp_expr.s b/llvm/test/MC/AMDGPU/vop_dpp_expr.s
index 6ca3a0ee9d31c0d..280f4e5ff8d2525 100644
--- a/llvm/test/MC/AMDGPU/vop_dpp_expr.s
+++ b/llvm/test/MC/AMDGPU/vop_dpp_expr.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI9
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=VI9
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI9
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=VI9
zero = 0
two = 2
diff --git a/llvm/test/MC/AMDGPU/vop_sdwa.s b/llvm/test/MC/AMDGPU/vop_sdwa.s
index 2d7a9ac0f19ccaf..6c8482aaddd994f 100644
--- a/llvm/test/MC/AMDGPU/vop_sdwa.s
+++ b/llvm/test/MC/AMDGPU/vop_sdwa.s
@@ -1,11 +1,11 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefixes=VI,GFX89
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefixes=GFX9,GFX89
-
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefixes=NOCI,NOSICI --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --check-prefixes=NOVI,NOGFX89 --implicit-check-not=error:
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefixes=NOGFX9,NOGFX89 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefixes=VI,GFX89
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefixes=GFX9,GFX89
+
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefixes=NOSI,NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefixes=NOCI,NOSICI --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --check-prefixes=NOVI,NOGFX89 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefixes=NOGFX9,NOGFX89 --implicit-check-not=error:
//---------------------------------------------------------------------------//
// Check SDWA operands
diff --git a/llvm/test/MC/AMDGPU/vopc-errs.s b/llvm/test/MC/AMDGPU/vopc-errs.s
index 469063d0ebdf7f3..316684b892662ca 100644
--- a/llvm/test/MC/AMDGPU/vopc-errs.s
+++ b/llvm/test/MC/AMDGPU/vopc-errs.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --implicit-check-not=error: %s
// Force 32-bit encoding with non-vcc result
diff --git a/llvm/test/MC/AMDGPU/vopc-vi.s b/llvm/test/MC/AMDGPU/vopc-vi.s
index 91fb117867b13ba..28711d2bec8769b 100644
--- a/llvm/test/MC/AMDGPU/vopc-vi.s
+++ b/llvm/test/MC/AMDGPU/vopc-vi.s
@@ -1,6 +1,6 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck -check-prefix=VI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck -check-prefix=NOSICI --implicit-check-not=error: %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck -check-prefix=VI %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICI --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck -check-prefix=NOSICI --implicit-check-not=error: %s
v_cmp_class_f16 vcc, v2, v4
// VI: v_cmp_class_f16_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x28,0x7c]
diff --git a/llvm/test/MC/AMDGPU/vopc.s b/llvm/test/MC/AMDGPU/vopc.s
index fb95abdf8dda99f..55289c0a463fa97 100644
--- a/llvm/test/MC/AMDGPU/vopc.s
+++ b/llvm/test/MC/AMDGPU/vopc.s
@@ -1,6 +1,6 @@
-// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
-// RUN: llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
+// RUN: llvm-mc -triple=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
+// RUN: llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
//===----------------------------------------------------------------------===//
// Generic Checks
diff --git a/llvm/test/MC/AMDGPU/wave32.s b/llvm/test/MC/AMDGPU/wave32.s
index b707bfc4c37427d..c52693076e2c5ee 100644
--- a/llvm/test/MC/AMDGPU/wave32.s
+++ b/llvm/test/MC/AMDGPU/wave32.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck -check-prefix=GFX1032 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck -check-prefix=GFX1064 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck -check-prefix=GFX1032-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck -check-prefix=GFX1064-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck -check-prefix=GFX1032 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck -check-prefix=GFX1064 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck -check-prefix=GFX1032-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck -check-prefix=GFX1064-ERR --implicit-check-not=error: %s
v_cmp_ge_i32_e32 s0, v0
// GFX1032: v_cmp_ge_i32_e32 vcc_lo, s0, v0 ; encoding: [0x00,0x00,0x0c,0x7d]
diff --git a/llvm/test/MC/AMDGPU/wave_any.s b/llvm/test/MC/AMDGPU/wave_any.s
index e5b014049c7367f..825a0abc1722400 100644
--- a/llvm/test/MC/AMDGPU/wave_any.s
+++ b/llvm/test/MC/AMDGPU/wave_any.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
v_cmp_ge_i32_e32 s0, v0
// GFX10: v_cmp_ge_i32_e32 vcc, s0, v0 ; encoding: [0x00,0x00,0x0c,0x7d]
diff --git a/llvm/test/MC/AMDGPU/xdl-insts-err.s b/llvm/test/MC/AMDGPU/xdl-insts-err.s
index a5083ed1a3a179a..22f0e03f9f3f5eb 100644
--- a/llvm/test/MC/AMDGPU/xdl-insts-err.s
+++ b/llvm/test/MC/AMDGPU/xdl-insts-err.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx906 %s 2>&1 | FileCheck --check-prefix=GFX906-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck --check-prefix=GFX908-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx906 %s 2>&1 | FileCheck --check-prefix=GFX906-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck --check-prefix=GFX908-ERR --implicit-check-not=error: %s
// GFX906-ERR: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU
v_dot2c_f32_f16 v0, v1, v2
diff --git a/llvm/test/MC/AMDGPU/xdl-insts-gfx1011-gfx1012.s b/llvm/test/MC/AMDGPU/xdl-insts-gfx1011-gfx1012.s
index 312acb78ac3d6d7..d06373d44dc5bb9 100644
--- a/llvm/test/MC/AMDGPU/xdl-insts-gfx1011-gfx1012.s
+++ b/llvm/test/MC/AMDGPU/xdl-insts-gfx1011-gfx1012.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1011 -show-encoding %s | FileCheck %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1012 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1011 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1012 -show-encoding %s | FileCheck %s
v_dot2c_f32_f16_e32 v5, v1, v2
// CHECK: encoding: [0x01,0x05,0x0a,0x04]
diff --git a/llvm/test/MC/AMDGPU/xdl-insts-gfx908.s b/llvm/test/MC/AMDGPU/xdl-insts-gfx908.s
index 22a1f1316ea24e4..be2041454b10c88 100644
--- a/llvm/test/MC/AMDGPU/xdl-insts-gfx908.s
+++ b/llvm/test/MC/AMDGPU/xdl-insts-gfx908.s
@@ -1,6 +1,6 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a -show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx940 -show-encoding %s | FileCheck %s
// CHECK: encoding: [0x01,0x05,0x0a,0x6e]
v_dot2c_f32_f16 v5, v1, v2
diff --git a/llvm/test/MC/AMDGPU/xnack-mask.s b/llvm/test/MC/AMDGPU/xnack-mask.s
index e10b167bd49377f..1a07e921f750354 100644
--- a/llvm/test/MC/AMDGPU/xnack-mask.s
+++ b/llvm/test/MC/AMDGPU/xnack-mask.s
@@ -1,10 +1,10 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1001 -mattr=-xnack %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1001 -mattr=-xnack %s 2>&1 | FileCheck -check-prefix=NOSICIVI10 --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=stoney -mattr=+xnack %s 2>&1 | FileCheck -check-prefix=XNACKERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=stoney -mattr=+xnack -show-encoding %s | FileCheck -check-prefix=XNACK %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=stoney -mattr=+xnack %s 2>&1 | FileCheck -check-prefix=XNACKERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=stoney -mattr=+xnack -show-encoding %s | FileCheck -check-prefix=XNACK %s
s_mov_b64 xnack_mask, -1
// NOSICIVI10: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
diff --git a/llvm/test/MC/Disassembler/AMDGPU/buf_fmt_packed_d16.txt b/llvm/test/MC/Disassembler/AMDGPU/buf_fmt_packed_d16.txt
index a7599f29fa0a621..355758175699762 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/buf_fmt_packed_d16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/buf_fmt_packed_d16.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx810 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=PACKED
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=PACKED
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx810 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=PACKED
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=PACKED
# PACKED: buffer_load_format_d16_x v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x01,0x01,0x01]
0x00,0x00,0x20,0xe0,0x00,0x01,0x01,0x01
diff --git a/llvm/test/MC/Disassembler/AMDGPU/buf_fmt_unpacked_d16.txt b/llvm/test/MC/Disassembler/AMDGPU/buf_fmt_unpacked_d16.txt
index 9c78e97c8e3ca41..be688136187d553 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/buf_fmt_unpacked_d16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/buf_fmt_unpacked_d16.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=fiji -disassemble -show-encoding < %s | FileCheck %s -check-prefix=UNPACKED
+# RUN: llvm-mc -triple=amdgcn -mcpu=fiji -disassemble -show-encoding < %s | FileCheck %s -check-prefix=UNPACKED
# UNPACKED: buffer_load_format_d16_x v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x01,0x01,0x01]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt b/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
index 346996938633e46..8da7e5ac2d88b38 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
@@ -1,6 +1,6 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefix=GCN %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefixes=GFX11,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefixes=GFX11,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefix=GCN %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefixes=GFX11,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefixes=GFX11,W64 %s
# GCN: warning: invalid instruction encoding
0xdf,0x00,0x00,0x02
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10-null-reg.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10-null-reg.txt
index b7e9d574e142a77..66df0c2de2590d9 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10-null-reg.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10-null-reg.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding --disassemble < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding --disassemble < %s | FileCheck -check-prefix=GFX10 %s
0x7d,0x04,0x00,0x10
# GFX10: v_mul_f32_e32 v0, null, v2 ; encoding: [0x7d,0x04,0x00,0x10]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10-sgpr-max.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10-sgpr-max.txt
index 70a92e9100087f2..37312bf06762c14 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10-sgpr-max.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10-sgpr-max.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
# GFX10: v_mov_b32_e32 v0, s105 ; encoding: [0x69,0x02,0x00,0x7e]
0x69,0x02,0x00,0x7e
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10-vop2be-literal.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10-vop2be-literal.txt
index b28a1a71eeb9d86..a50b0ae76cbaade 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10-vop2be-literal.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10-vop2be-literal.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
# GFX10: v_add_co_ci_u32_e32 v3, vcc_lo, 0x3039, v3, vcc_lo ; encoding: [0xff,0x06,0x06,0x50,0x39,0x30,0x00,0x00]
0xff,0x06,0x06,0x50,0x39,0x30,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10-vop3-literal.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10-vop3-literal.txt
index 51f72a718804770..015ce3e963fb31e 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10-vop3-literal.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10-vop3-literal.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
# GFX10: v_bfe_u32 v0, 0x3039, v1, s1 ; encoding: [0x00,0x00,0x48,0xd5,0xff,0x02,0x06,0x00,0x39,0x30,0x00,0x00]
0x00,0x00,0x48,0xd5,0xff,0x02,0x06,0x00,0x39,0x30,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10-wave32.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10-wave32.txt
index 790c2931a67e66b..7d15f041bd770e1 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10-wave32.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10-wave32.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX1032 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64,-wavefrontsize32 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX1064 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX1032 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64,-wavefrontsize32 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX1064 %s
# GFX1032: v_cmp_lt_f32_e32 vcc_lo, s2, v4
# GFX1064: v_cmp_lt_f32_e32 vcc, s2, v4
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1011-xdl-insts.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1011-xdl-insts.txt
index 2f2fd81e0c21d19..914b6a7db7ddeb3 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1011-xdl-insts.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1011-xdl-insts.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1011 -disassemble -show-encoding < %s | FileCheck %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1012 -disassemble -show-encoding < %s | FileCheck %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1011 -disassemble -show-encoding < %s | FileCheck %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1012 -disassemble -show-encoding < %s | FileCheck %s
# CHECK: v_dot2c_f32_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x04]
0x01,0x05,0x0a,0x04
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1011_dlops.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1011_dlops.txt
index 41406aba22b754b..972673542f4cea9 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1011_dlops.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1011_dlops.txt
@@ -1,12 +1,12 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1011 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1012 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1030 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1031 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1032 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1033 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1034 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1035 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1036 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1011 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1012 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1030 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1031 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1032 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1033 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1034 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1035 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1036 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
# GFX10: v_dot2_f32_f16 v0, v1, v2, v3 ; encoding: [0x00,0x40,0x13,0xcc,0x01,0x05,0x0e,0x1c]
0x00,0x40,0x13,0xcc,0x01,0x05,0x0e,0x1c
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1030_new.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1030_new.txt
index cdd7eeabf2fb56e..129f70d2914018a 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1030_new.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1030_new.txt
@@ -1,10 +1,10 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1030 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1031 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1032 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1033 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1034 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1035 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1036 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1030 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1031 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1032 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1033 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1034 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1035 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1036 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX10 %s
# GFX10: global_load_dword_addtid v1, s[2:3] offset:16
0x10,0x80,0x58,0xdc,0x00,0x00,0x02,0x01
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_ds.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_ds.txt
index 8433882ac279cd4..b57ea682aaeafab 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_ds.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_ds.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
# GFX10: ds_add_f32 v0, v1 ; encoding: [0x00,0x00,0x54,0xd8,0x00,0x01,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_exp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_exp.txt
index 2bca44369014206..0fe4fc8d5b15f40 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_exp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_exp.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GXF10
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GXF10
# GXF10: exp mrt0 v1, v2, v3, v4 ; encoding: [0x0f,0x00,0x00,0xf8,0x01,0x02,0x03,0x04]
0x0f,0x00,0x00,0xf8,0x01,0x02,0x03,0x04
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_flat.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_flat.txt
index aabd9de2a3b2bad..9754b8c597a17e0 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_flat.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_flat.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
#===------------------------------------------------------------------------===#
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
index 481a3184509b2d3..8f3da34ea24739a 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10 %s
#===------------------------------------------------------------------------===#
# MIMG, regular address
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_mtbuf.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_mtbuf.txt
index 4007c5f0dea703b..950ce783baba2e4 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_mtbuf.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_mtbuf.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX10
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX10
# GFX10: tbuffer_load_format_d16_x v0, off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
0x00,0x00,0xb0,0xe8,0x00,0x00,0x20,0x80
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_mubuf.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_mubuf.txt
index caf4546e94cfd8c..6fbe77e43ad4288 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_mubuf.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_mubuf.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
# GFX10: buffer_atomic_add v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0xc8,0xe0,0x00,0xff,0x02,0x03]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_smem.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_smem.txt
index f2fbac05abffd24..0417f94353be05b 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_smem.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_smem.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
# GFX10: s_atc_probe 7, s[4:5], 0x64 ; encoding: [0xc2,0x01,0x98,0xf4,0x64,0x00,0x00,0xfa]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_sop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_sop1.txt
index 684cdc07d2da6c3..b5578bb4fd200dd 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_sop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_sop1.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
# GFX10: s_abs_i32 exec_hi, s1 ; encoding: [0x01,0x34,0xff,0xbe]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_sop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_sop2.txt
index fdcb28ab55a3f82..85e1de86513a1e1 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_sop2.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_sop2.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
# GFX10: s_absdiff_i32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x96]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_sopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_sopc.txt
index e2207a19a2b68c9..baa5c5f06a1ff78 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_sopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_sopc.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
# GFX10: s_bitcmp0_b32 exec_hi, s1 ; encoding: [0x7f,0x01,0x0c,0xbf]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_sopk.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_sopk.txt
index 7b3c591dc0f8579..1878f8b4672276e 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_sopk.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_sopk.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
# GFX10: s_addk_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0xff,0xb7]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_sopp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_sopp.txt
index 874f6f6b3cf175a..8022439c72d528c 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_sopp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_sopp.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
# GFX10: s_barrier ; encoding: [0x00,0x00,0x8a,0xbf]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1.txt
index 5804f498cb3e84f..ee1114f4ab32ba7 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
# GFX10: v_bfrev_b32_e32 v255, v1 ; encoding: [0x01,0x71,0xfe,0x7f]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1_dpp16.txt
index 54b9abea720b4ef..d80b2dd748281bb 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1_dpp16.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
# GFX10: v_bfrev_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x70,0xfe,0x7f,0x01,0xe4,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1_dpp8.txt
index b520dcfe918b73c..b354990ddfdefbc 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1_dpp8.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10 %s
# GFX10: v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0x02,0x0a,0x7e,0x01,0x88,0xc6,0xfa]
0xe9,0x02,0x0a,0x7e,0x01,0x88,0xc6,0xfa
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1_sdwa.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1_sdwa.txt
index c7eaee952326e72..0739ba3973f3439 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1_sdwa.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1_sdwa.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
# GFX10: v_bfrev_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x70,0xfe,0x7f,0x01,0x06,0x06,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2.txt
index 80e7a3f94ec0638..b759912204db82b 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W64 %s
# W32: v_add_co_ci_u32_e32 v255, vcc_lo, v1, v2, vcc_lo ; encoding: [0x01,0x05,0xfe,0x51]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_dpp16.txt
index 998ef19dca75c16..0d098496af09154 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_dpp16.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W64 %s
# GFX10: v_add_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x65,0x01,0xe4,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_dpp8.txt
index cee1163a9f0523c..819a27647c1bae9 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_dpp8.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10,W64 %s
# GFX10: v_add_f32_dpp v5, v1, v2 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0x04,0x0a,0x06,0x01,0x88,0xc6,0xfa]
0xe9,0x04,0x0a,0x06,0x01,0x88,0xc6,0xfa
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_sdwa.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_sdwa.txt
index 474640471018e2f..3dece53d48d29e2 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_sdwa.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_sdwa.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W64 %s
# W32: v_add_co_ci_u32_sdwa v255, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x51,0x01,0x06,0x06,0x06]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
index 0785ba2ea2eb6e0..4c0170ca4e4747c 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX10,W64 %s
# GFX10: v_add3_u32 v255, v1, v2, v3 ; encoding: [0xff,0x00,0x6d,0xd7,0x01,0x05,0x0e,0x04]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
index 66b69e7c7c1f2a6..f682c5aa65b1617 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=W64 %s
# W32: v_cmp_class_f32_e64 s10, -1, v2 ; encoding: [0x0a,0x00,0x88,0xd4,0xc1,0x04,0x02,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3cx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3cx.txt
index b76ad301a6e3382..d70f07dd835d718 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3cx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3cx.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
# GFX10: v_cmpx_class_f16_e64 -1, v2 ; encoding: [0x7e,0x00,0x9f,0xd4,0xc1,0x04,0x02,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3p_literalv216.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3p_literalv216.txt
index b124281903faca1..e42d0de5db86f78 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3p_literalv216.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3p_literalv216.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -disassemble -show-encoding %s | FileCheck -check-prefix=GFX10 %s
#===----------------------------------------------------------------------===//
# Inline constants
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopc.txt
index e6a019a47239c38..3aeb21349f6f066 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopc.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=W64 %s
# W32: v_cmp_class_f32_e32 vcc_lo, -1, v2 ; encoding: [0xc1,0x04,0x10,0x7d]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopc_sdwa.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopc_sdwa.txt
index 3e04f424e64fa04..5b9ff0333e98a14 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopc_sdwa.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopc_sdwa.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=W64 %s
# W32: v_cmp_class_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x10,0x7d,0x01,0xe4,0x06,0x06]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopcx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopcx.txt
index d41dc9992e5875f..4ed855b97453d25 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopcx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopcx.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
# GFX10: v_cmpx_class_f16_e32 -1, v2 ; encoding: [0xc1,0x04,0x3e,0x7d]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopcx_sdwa.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopcx_sdwa.txt
index 01973a89ba63ef6..c94d883fcf9131a 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopcx_sdwa.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vopcx_sdwa.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX10 %s
# GFX10: v_cmpx_eq_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x16,0x06]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ds.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ds.txt
index 0d2129a85248bfc..5c4f5829cdaf1de 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ds.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ds.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
# GFX11: ds_add_f32 v0, v1 ; encoding: [0x00,0x00,0x54,0xd8,0x00,0x01,0x00,0x00]
0x00,0x00,0x54,0xd8,0x00,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_exp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_exp.txt
index ffdd30597ddd821..fae271b2fc7cf82 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_exp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_exp.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s -check-prefix=GFX11
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s -check-prefix=GFX11
# GFX11: exp dual_src_blend0 v4, v3, v2, v1 ; encoding: [0x5f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01]
0x5f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_flat.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_flat.txt
index a2ee4b4d24df14b..e83fbe31801f8aa 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_flat.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_flat.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX11
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX11
#===------------------------------------------------------------------------===#
# FLAT
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ldsdir.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ldsdir.txt
index 274dc960124f269..018af4646c1f9c1 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ldsdir.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ldsdir.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
# GFX11: lds_direct_load v10 wait_vdst:6 ; encoding: [0x0a,0x00,0x16,0xce]
0x0a,0x00,0x16,0xce
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg.txt
index 8461a5ebfceb8bb..969279877af24b2 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
# GFX11: image_atomic_add v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x80,0x03,0x30,0xf0,0x02,0x01,0x03,0x00]
0x80,0x03,0x30,0xf0,0x02,0x01,0x03,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg_features.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg_features.txt
index d8183142775affd..46488a9aa4ec704 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg_features.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg_features.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
# GFX11: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x80,0x0f,0x00,0xf0,0x00,0x00,0x00,0x00]
0x80,0x0f,0x00,0xf0,0x00,0x00,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mtbuf.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mtbuf.txt
index f844df8d3d17bf2..d28c996044836a2 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mtbuf.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mtbuf.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
# GFX11: tbuffer_load_d16_format_x v4, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x0c,0xe8,0x00,0x04,0x02,0x03]
0xff,0x0f,0x0c,0xe8,0x00,0x04,0x02,0x03
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mubuf.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mubuf.txt
index 752a60366c57a72..f231b1bb07a4341 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mubuf.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mubuf.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
# GFX11: buffer_gl0_inv ; encoding: [0x00,0x00,0xac,0xe0,0x00,0x00,0x00,0x00]
0x00,0x00,0xac,0xe0,0x00,0x00,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_smem.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_smem.txt
index 2a1f8e2b736682e..83f6a3da3ad7b43 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_smem.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_smem.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
# GFX11: s_atc_probe 7, s[4:5], 0x64 ; encoding: [0xc2,0x01,0x88,0xf4,0x64,0x00,0x00,0xf8]
0xc2,0x01,0x88,0xf4,0x64,0x00,0x00,0xf8
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt
index e4ea924d6c90c3f..fbb95450dbbe2f2 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
# GFX11: s_abs_i32 exec_hi, s1 ; encoding: [0x01,0x15,0xff,0xbe]
0x01,0x15,0xff,0xbe
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop2.txt
index d24a22e8baa2c9c..e57648235df620e 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop2.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop2.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
# GFX11: s_absdiff_i32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x83]
0x01,0x02,0x7f,0x83
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopc.txt
index 439bc3529459fc5..af2905f14dd0161 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopc.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
# GFX11: s_bitcmp0_b32 exec_hi, s1 ; encoding: [0x7f,0x01,0x0c,0xbf]
0x7f,0x01,0x0c,0xbf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopk.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopk.txt
index 7f6329bf2a3110c..f1717bd92832ed3 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopk.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopk.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
# GFX11: s_addk_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0xff,0xb7]
0x34,0x12,0xff,0xb7
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt
index 098a68ff48d31b6..3b122c834b8755b 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sopp.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
# GFX11: s_barrier ; encoding: [0x00,0x00,0xbd,0xbf]
0x00,0x00,0xbd,0xbf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vinterp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vinterp.txt
index a0b098ddbd6da03..da1f129fcf40e73 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vinterp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vinterp.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble %s | FileCheck -strict-whitespace -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble %s | FileCheck -strict-whitespace -check-prefix=GFX11 %s
# GFX11: v_interp_p10_f32 v0, v1, v2, v3{{$}}
0x00,0x00,0x00,0xcd,0x01,0x05,0x0e,0x04
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
index 583d61fe80ecc20..7156fb19d2bb052 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
# GFX11: v_bfrev_b32_e32 v5, v1 ; encoding: [0x01,0x71,0x0a,0x7e]
0x01,0x71,0x0a,0x7e
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp16.txt
index f3251954f9e10f8..8758305258387cc 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp16.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
# GFX11: v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x1b,0x00,0xff]
0xfa,0x70,0x0a,0x7e,0x01,0x1b,0x00,0xff
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp8.txt
index 0e4e8fc49023516..a3531410ac401f1 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1_dpp8.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
# GFX11: v_bfrev_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05]
0xe9,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt
index 2fcae1c4a119ece..146db5a923a2506 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
# W32: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo ; encoding: [0x01,0x05,0x0a,0x40]
# W64: v_add_co_ci_u32_e32 v5, vcc, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x40]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt
index 7f80bf637f3cc91..dd41cfa2a10455b 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff]
# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp8.txt
index 1bdd77d2651b3ae..97f9b67b4eea318 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp8.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
# W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05]
# W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
index cc6c48a059c47f9..7674c02185b5f23 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
# GFX11: v_add3_u32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x55,0xd6,0x01,0x05,0x0e,0x00]
0x05,0x00,0x55,0xd6,0x01,0x05,0x0e,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
index e9da1905f177fbe..8b4dca4f5bd11ef 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
# GFX11: v_add3_u32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop1.txt
index 19a5c3611833799..cf29efa5ff56bb1 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop1.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
# GFX11: v_bfrev_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop2.txt
index 69a7122e438317e..a0838e09bf4578e 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop2.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop2.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
# W32: v_add_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
# W64: v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x0c,0x20,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt
index 480aacaaafb90fc..4575418801c5ca7 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x0a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopcx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopcx.txt
index 6ee9669f5378433..26168974198e885 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopcx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopcx.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
# GFX11: v_cmpx_class_f16_e64_dpp v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
0x7e,0x00,0xfd,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
index f91216a7469c54d..78470d4707494d9 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
# GFX11: v_add3_u32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x55,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
0x05,0x00,0x55,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt
index 4ea57003eeeb93c..bfda6d10c2f6d47 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
# GFX11: v_bfrev_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
0x05,0x00,0xb8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop2.txt
index f0165884ba71feb..5aa68cba4a393c3 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop2.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop2.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
# W32: v_add_co_ci_u32_e64_dpp v5, s12, v1, v2, s6 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0c,0x20,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
# W64: v_add_co_ci_u32_e64_dpp v5, s[12:13], v1, v2, s[6:7] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x0c,0x20,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt
index a682f2a886ea2b6..5f21c9b92f6f879 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
# W32: v_cmp_class_f16_e64_dpp s10, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
# W64: v_cmp_class_f16_e64_dpp s[10:11], v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x0a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopcx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopcx.txt
index 09f92517f545fc0..70ece76fcc9e180 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopcx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopcx.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
# GFX11: v_cmpx_class_f16_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
0x7e,0x00,0xfd,0xd4,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop1.txt
index cba7fa924be2c4f..770e3c6e7a6f309 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop1.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
# GFX11: v_bfrev_b32_e64 v5, v1 ; encoding: [0x05,0x00,0xb8,0xd5,0x01,0x01,0x00,0x00]
0x05,0x00,0xb8,0xd5,0x01,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt
index 3141e8f4b2cbbaa..503d644b61b5818 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
# W32: v_add_co_ci_u32_e64 v5, s12, v1, 0xaf123456, s6 ; encoding: [0x05,0x0c,0x20,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf]
# W64: v_add_co_ci_u32_e64 v5, s[12:13], v1, 0xaf123456, s[6:7] ; encoding: [0x05,0x0c,0x20,0xd5,0x01,0xff,0x19,0x00,0x56,0x34,0x12,0xaf]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
index 8952c8c4aabd94c..f4a8b99a45f464d 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s
# W32: v_cmp_class_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00]
# W64: v_cmp_class_f16_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopcx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopcx.txt
index d300bc4d2056642..555a6aa6a0fbb74 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopcx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopcx.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
# GFX11: v_cmpx_class_f16_e64 v1, v2 ; encoding: [0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
0x7e,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p.txt
index 9f146b8818c44c8..bc2cb5f06c4f496 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
# GFX11: v_dot2_f32_bf16 v5, v1, v2, v3 ; encoding: [0x05,0x40,0x1a,0xcc,0x01,0x05,0x0e,0x1c]
0x05,0x40,0x1a,0xcc,0x01,0x05,0x0e,0x1c
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p_dpp16.txt
index 8f14b1033e87523..6b230367c8313f8 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p_dpp16.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
# GFX11: v_dot2_f32_f16_e64_dpp v0, v1, v2, v3 neg_lo:[1,1,0] neg_hi:[1,0,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xe ; encoding: [0x00,0x05,0x13,0xcc,0xfa,0x04,0x0e,0x64,0x01,0x1b,0x00,0xfe]
0x00,0x05,0x13,0xcc,0xfa,0x04,0x0e,0x64,0x01,0x1b,0x00,0xfe
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p_dpp8.txt
index 60066f4babb0927..89c9b54d7cfeec4 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p_dpp8.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
# GFX11: v_dot2_f32_f16_e64_dpp v0, v1, v2, v3 neg_lo:[0,1,1] neg_hi:[1,0,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x00,0x05,0x13,0xcc,0xe9,0x04,0x0e,0xc4,0x01,0x77,0x39,0x05]
0x00,0x05,0x13,0xcc,0xe9,0x04,0x0e,0xc4,0x01,0x77,0x39,0x05
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
index f4f3801bcc30dea..f426c1cd7e79f97 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64
# W32: v_cmp_class_f16_e32 vcc_lo, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c]
# W64: v_cmp_class_f16_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0xfa,0x7c]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt
index bfd23afbe81033e..59d635bbe2bf327 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64
# W32: v_cmp_class_f16 vcc_lo, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff]
# W64: v_cmp_class_f16 vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt
index 69aab1d4f41dc08..29a55cb70dc4839 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W32
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=W64
# W32: v_cmp_class_f16 vcc_lo, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05]
# W64: v_cmp_class_f16 vcc, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7c,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx.txt
index 7b314c67eaf5cc9..b5538bf0a98f8b8 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
# GFX11: v_cmpx_class_f16_e32 v1, v2 ; encoding: [0x01,0x05,0xfa,0x7d]
0x01,0x05,0xfa,0x7d
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp16.txt
index ddc5ce2a432b581..a47440f5092d1bc 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp16.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
# GFX11: v_cmpx_class_f16 v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0xfa,0x7d,0x01,0x1b,0x00,0xff]
0xfa,0x04,0xfa,0x7d,0x01,0x1b,0x00,0xff
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp8.txt
index b4feaa65bcf7e41..fd1c626ea51be9d 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp8.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
# GFX11: v_cmpx_class_f16 v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05]
0xe9,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopd.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopd.txt
index a5f21592050cbf7..bd8f4c667d4ffab 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopd.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopd.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX11
# GFX11: v_dual_add_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x08,0xc9,0x01,0x07,0x06,0xff]
0x04,0x05,0x08,0xc9,0x01,0x07,0x06,0xff
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopd_features.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopd_features.txt
index 5f9e66843daf30c..2c4e7d646a1753c 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopd_features.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopd_features.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX11 %s
#===------------------------------------------------------------------------===#
# Check instructions with several literals
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_wmma.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_wmma.txt
index b09e5c459e25b76..fff7a807bfd6c86 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_wmma.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_wmma.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=W32 %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=W64 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=W32 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=W64 %s
# Test v_wmma_f32_16x16x16_f16
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8-literal.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8-literal.txt
index 05483ccd0008d9b..d2c24f3fbaef549 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8-literal.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8-literal.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding %s | FileCheck -check-prefix=VI %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding %s | FileCheck -check-prefix=VI %s
# VI: v_fract_f64_e32 v[0:1], 0.15915494309189532 ; encoding: [0xf8,0x64,0x00,0x7e]
0xf8,0x64,0x00,0x7e
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8-literal16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8-literal16.txt
index 466932e8691e088..c5751de810d90b4 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8-literal16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8-literal16.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding %s | FileCheck -check-prefix=VI %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding %s | FileCheck -check-prefix=VI %s
# VI: v_add_f16_e32 v1, 0.5, v3 ; encoding: [0xf0,0x06,0x02,0x3e]
0xf0 0x06 0x02 0x3e
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8-trap.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8-trap.txt
index eb254134cc53ea8..e5c4a5278e7f443 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8-trap.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8-trap.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
#===----------------------------------------------------------------------===#
# Trap Handler related - 32 bit registers
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_ds.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_ds.txt
index 73c40dee8523d2a..f9cc491a7f9214b 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_ds.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_ds.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: ds_add_u32 v1, v2 offset:65535 ; encoding: [0xff,0xff,0x00,0xd8,0x01,0x02,0x00,0x00]
0xff,0xff,0x00,0xd8,0x01,0x02,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_exp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_exp.txt
index 126a66111da312a..c6be9a48afbc0d7 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_exp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_exp.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_flat.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_flat.txt
index 456306164b96ff9..56891898409f93f 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_flat.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_flat.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: flat_load_ubyte v5, v[1:2] ; encoding: [0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0x05]
0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0x05
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg.txt
index 048d1570c810387..d6e56d37c3ba822 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: image_load v5, v1, s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg_features.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg_features.txt
index cc59789c62be504..292af1850db8638 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg_features.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg_features.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI -check-prefix=GFX80
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx810 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI -check-prefix=GFX81
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI -check-prefix=GFX80
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx810 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI -check-prefix=GFX81
#===------------------------------------------------------------------------===#
# Image load/store
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_mtbuf.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_mtbuf.txt
index d32545f7f48c96c..f6c5a459e6c8943 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_mtbuf.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_mtbuf.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
# VI: tbuffer_load_format_x v1, off, s[4:7], s1 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] ; encoding: [0x00,0x00,0x78,0xe9,0x00,0x01,0x01,0x01]
0x00 0x00 0x78 0xe9 0x00 0x01 0x01 0x01
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_mubuf.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_mubuf.txt
index d0c9ddf9beecc5d..759fd0309819ef5 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_mubuf.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_mubuf.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: buffer_load_format_x v5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x03]
0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x03
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_smem.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_smem.txt
index 8d3670cd62f9c4f..f141a5ade23a788 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_smem.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_smem.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: s_load_dword s5, s[2:3], s2 ; encoding: [0x41,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
0x41,0x01,0x00,0xc0,0x02,0x00,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_sop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_sop1.txt
index 995748ecc2a120c..1aab1d9cbdad131 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_sop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_sop1.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: s_mov_b32 s5, s1 ; encoding: [0x01,0x00,0x85,0xbe]
0x01,0x00,0x85,0xbe
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_sop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_sop2.txt
index 2bf624b9ade355d..5b12d7561befa79 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_sop2.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_sop2.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: s_add_u32 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0x80]
0x01,0x02,0x05,0x80
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_sopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_sopc.txt
index 9adae0dfa002ad0..3e06d2d726b129f 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_sopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_sopc.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: s_cmp_eq_i32 s1, s2 ; encoding: [0x01,0x02,0x00,0xbf]
0x01,0x02,0x00,0xbf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_sopk.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_sopk.txt
index 6293dfad0ef514b..40d6ac6699640b3 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_sopk.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_sopk.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: s_movk_i32 s5, 0x3141 ; encoding: [0x41,0x31,0x05,0xb0]
0x41,0x31,0x05,0xb0
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_sopp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_sopp.txt
index e91d03b2dec62c2..0a309101caf122c 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_sopp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_sopp.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: s_nop 0x3141 ; encoding: [0x41,0x31,0x80,0xbf]
0x41,0x31,0x80,0xbf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vintrp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vintrp.txt
index a960c4ac61843a8..0400893dba456df 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vintrp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vintrp.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=fiji -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=fiji -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_interp_p1_f32_e32 v5, v1, attr0.x ; encoding: [0x01,0x00,0x14,0xd4]
0x01,0x00,0x14,0xd4
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1.txt
index 4f0d998e08eb8ca..a35b940cadd86c0 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
0x00,0x00,0x00,0x7e
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1_dpp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1_dpp.txt
index 9fa36a4c9518667..673481e44ae4050 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1_dpp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1_dpp.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x00]
0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1_sdwa.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1_sdwa.txt
index f0f1b26953f00e2..8fe5d54323ba203 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1_sdwa.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1_sdwa.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2.txt
index ce2fc3824b9c84e..69587d3ca1a9258 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_cndmask_b32_e32 v5, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x00]
0x01,0x05,0x0a,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_dpp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_dpp.txt
index 7233bf801372f3f..62855036b9ebf5f 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_dpp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_dpp.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x00]
0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_sdwa.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_sdwa.txt
index f3f25f4c519ac91..45048b85c7a2f3c 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_sdwa.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_sdwa.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt
index 2b07d620fdad248..4488ad88de8848b 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_interp_p1_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3c.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3c.txt
index e955d5891d99537..57d6207a2343178 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3c.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3c.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_cmp_class_f32_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3cx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3cx.txt
index 43f9667883f01d9..b70a44b6126471f 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3cx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3cx.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_cmpx_class_f32_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
0x0a,0x00,0x11,0xd0,0x01,0x05,0x02,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopc.txt
index d12fce686fa65a5..28a46eab474a080 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopc.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_cmp_class_f32_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x20,0x7c]
0x01,0x05,0x20,0x7c
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopc_sdwa.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopc_sdwa.txt
index 5c61596e6881f26..6ec8c25221116aa 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopc_sdwa.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopc_sdwa.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_cmp_class_f32 vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x06]
0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x06
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopcx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopcx.txt
index 468b9e655a5b979..c819a03a69670de 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopcx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopcx.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_cmpx_class_f32_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x22,0x7c]
0x01,0x05,0x22,0x7c
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopcx_sdwa.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopcx_sdwa.txt
index 7cf1a07b846027f..e7e1590edc990e3 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopcx_sdwa.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vopcx_sdwa.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_cmpx_class_f32 vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x06]
0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x06
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9-aperture-regs.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9-aperture-regs.txt
index 1af85415d137ee7..8048789eae503d8 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9-aperture-regs.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9-aperture-regs.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX9 %s
# GFX9: v_mov_b32_e32 v1, src_shared_base ; encoding: [0xeb,0x02,0x02,0x7e]
0xeb 0x02 0x02 0x7e
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9-bool-regs.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9-bool-regs.txt
index 216d58b70942469..b084263e4a5edfa 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9-bool-regs.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9-bool-regs.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding %s | FileCheck -check-prefix=GFX9 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding %s | FileCheck -check-prefix=GFX9 %s
# GFX9: buffer_atomic_add v0, off, s[0:3], src_scc offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0x00,0x00,0xfd]
0xff,0x0f,0x08,0xe1,0x00,0x00,0x00,0xfd
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9-lds_direct.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9-lds_direct.txt
index 7ab114578abe74c..4740237c93732a2 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9-lds_direct.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9-lds_direct.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX9
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX9
# GFX9: v_mov_b32_e32 v0, src_lds_direct ; encoding: [0xfe,0x02,0x00,0x7e]
0xfe,0x02,0x00,0x7e
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9-trap.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9-trap.txt
index 0b140c42168a5f6..ece637685ab56ab 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9-trap.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9-trap.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
#===----------------------------------------------------------------------===#
# Trap Handler related - 32 bit registers
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx908-atomic-fadd-insts.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx908-atomic-fadd-insts.txt
index 20988a40f98e367..cd3b66769045dc3 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx908-atomic-fadd-insts.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx908-atomic-fadd-insts.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx908 -disassemble -show-encoding < %s | FileCheck %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx908 -disassemble -show-encoding < %s | FileCheck %s
# CHECK: buffer_atomic_add_f32 v5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x34,0xe1,0x00,0x05,0x02,0x03]
0xff,0x0f,0x34,0xe1,0x00,0x05,0x02,0x03
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx908-dl-insts.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx908-dl-insts.txt
index 256c6072cdd7780..aa3b4c7f03837ab 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx908-dl-insts.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx908-dl-insts.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx906 -disassemble -show-encoding < %s | FileCheck %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx908 -disassemble -show-encoding < %s | FileCheck %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx906 -disassemble -show-encoding < %s | FileCheck %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx908 -disassemble -show-encoding < %s | FileCheck %s
# CHECK: v_fmac_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x76]
0x01,0x05,0x0a,0x76
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx908-xdl-insts.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx908-xdl-insts.txt
index b643007015d478d..be23058ff424d90 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx908-xdl-insts.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx908-xdl-insts.txt
@@ -1,6 +1,6 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx908 -disassemble -show-encoding < %s | FileCheck %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx90a -disassemble -show-encoding < %s | FileCheck %s
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -disassemble -show-encoding < %s | FileCheck %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx908 -disassemble -show-encoding < %s | FileCheck %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a -disassemble -show-encoding < %s | FileCheck %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx940 -disassemble -show-encoding < %s | FileCheck %s
# CHECK: v_dot2c_f32_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x6e]
0x01,0x05,0x0a,0x6e
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx908_mai.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx908_mai.txt
index 7f45302e383be6e..2f3de6dc282397d 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx908_mai.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx908_mai.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx908 -show-encoding -disassemble %s | FileCheck -check-prefix=GFX908 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx908 -show-encoding -disassemble %s | FileCheck -check-prefix=GFX908 %s
# GFX908: v_accvgpr_read_b32 v2, a0 ; encoding: [0x02,0x40,0xd8,0xd3,0x00,0x01,0x00,0x18]
0x02,0x40,0xd8,0xd3,0x00,0x01,0x00,0x18
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx90a-dpp64.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx90a-dpp64.txt
index b11d2b422134550..ef194eb021e1509 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx90a-dpp64.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx90a-dpp64.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx90a -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX90A
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX90A
# GFX90A: v_ceil_f64_dpp v[0:1], v[2:3] row_newbcast:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x30,0x00,0x7e,0x02,0x51,0x01,0xff]
0xfa,0x30,0x00,0x7e,0x02,0x51,0x01,0xff
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_features.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_features.txt
index 6778d9855dd6946..8746ee79c8f556b 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_features.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_features.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx90a -disassemble -show-encoding %s | FileCheck --check-prefix=GFX90A %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a -disassemble -show-encoding %s | FileCheck --check-prefix=GFX90A %s
# GFX90A: v_pk_fma_f32 v[8:9], v[0:1], s[0:1], v[4:5] ; encoding: [0x08,0x40,0xb0,0xd3,0x00,0x01,0x10,0x1c]
0x08,0x40,0xb0,0xd3,0x00,0x01,0x10,0x1c
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt
index 770eea7bc43f156..b8cc7ac604da2ff 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx90a -disassemble -show-encoding %s | FileCheck --check-prefix=GFX90A %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a -disassemble -show-encoding %s | FileCheck --check-prefix=GFX90A %s
# GFX90A: flat_load_ubyte a5, v[2:3] offset:4095 ; encoding: [0xff,0x0f,0x40,0xdc,0x02,0x00,0x80,0x05]
0xff,0x0f,0x40,0xdc,0x02,0x00,0x80,0x05
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_mai.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_mai.txt
index 6d4a4760d8eb170..eca0ee57ef8b005 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_mai.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_mai.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx90a -show-encoding -disassemble %s | FileCheck -check-prefix=GFX90A %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a -show-encoding -disassemble %s | FileCheck -check-prefix=GFX90A %s
# GFX90A: v_accvgpr_read_b32 v2, a0 ; encoding: [0x02,0x40,0xd8,0xd3,0x00,0x01,0x00,0x18]
0x02,0x40,0xd8,0xd3,0x00,0x01,0x00,0x18
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_mimg.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_mimg.txt
index b902fca9288ce45..0f2dca4cb578362 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_mimg.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_mimg.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx90a -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX90A
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx90a -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX90A
# GFX90A: image_load v[4:6], v238, s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x00,0xf0,0xee,0x04,0x07,0x00]
0x00,0x17,0x00,0xf0,0xee,0x04,0x07,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx940_features.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx940_features.txt
index 01eef8b646f4c60..9575e50f16312fb 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx940_features.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx940_features.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -disassemble -show-encoding %s | FileCheck -strict-whitespace --check-prefix=GFX940 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx940 -disassemble -show-encoding %s | FileCheck -strict-whitespace --check-prefix=GFX940 %s
# GFX940: global_load_dword v2, v[2:3], off sc0 ; encoding: [0x00,0x80,0x51,0xdc,0x02,0x00,0x7f,0x02]
0x00,0x80,0x51,0xdc,0x02,0x00,0x7f,0x02
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx940_flat.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx940_flat.txt
index b3182c98cb1b726..856fcd894638c91 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx940_flat.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx940_flat.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -show-encoding -disassemble %s | FileCheck -check-prefix=GFX940 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx940 -show-encoding -disassemble %s | FileCheck -check-prefix=GFX940 %s
# GFX940: scratch_load_dword a2, v4, s6 ; encoding: [0x00,0x60,0x50,0xdc,0x04,0x00,0x86,0x02]
0x00,0x60,0x50,0xdc,0x04,0x00,0x86,0x02
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx940_mai.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx940_mai.txt
index 0742cf1b5c720d9..e6951bc5dc68427 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx940_mai.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx940_mai.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx940 -show-encoding -disassemble %s | FileCheck -check-prefix=GFX940 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx940 -show-encoding -disassemble %s | FileCheck -check-prefix=GFX940 %s
# GFX940: v_accvgpr_write_b32 a10, s20 ; encoding: [0x0a,0x40,0xd9,0xd3,0x14,0x00,0x00,0x18]
0x0a,0x40,0xd9,0xd3,0x14,0x00,0x00,0x18
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_ds.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_ds.txt
index 3f66c9f560cf018..58a44e1250542fe 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_ds.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_ds.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: ds_add_u32 v1, v2 offset:65535 ; encoding: [0xff,0xff,0x00,0xd8,0x01,0x02,0x00,0x00]
0xff,0xff,0x00,0xd8,0x01,0x02,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_exp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_exp.txt
index 651de5b50f7c69b..c8c17d87e3902c5 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_exp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_exp.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_flat.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_flat.txt
index f5540eed2a0c765..0ee659e207c915d 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_flat.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_flat.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: flat_load_ubyte v5, v[1:2] offset:4095 ; encoding: [0xff,0x0f,0x40,0xdc,0x01,0x00,0x00,0x05]
0xff,0x0f,0x40,0xdc,0x01,0x00,0x00,0x05
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_mimg.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_mimg.txt
index 21120a679b70927..f3c5dec1b161737 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_mimg.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_mimg.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: image_load v5, v1, s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_mubuf.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_mubuf.txt
index dae9ee805905d34..4cf5aecdb2be79c 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_mubuf.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_mubuf.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: buffer_load_format_x v5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x03]
0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x03
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_sdwa_features.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_sdwa_features.txt
index 94b98505092e17c..3408024d9257aca 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_sdwa_features.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_sdwa_features.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
#-----------------------------------------------------------------------------#
# Input modifiers
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem.txt
index f00c989deb52681..9e9ba19dd09eb18 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: s_load_dword s5, s[2:3], s0 ; encoding: [0x41,0x01,0x00,0xc0,0x00,0x00,0x00,0x00]
0x41,0x01,0x00,0xc0,0x00,0x00,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem_features.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem_features.txt
index c2573060a1e9d6d..63a8b292e8ee9d0 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem_features.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem_features.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
#===------------------------------------------------------------------------===#
# s_scratch
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_sop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_sop1.txt
index 94063f1c587d735..cad9491e0d0ba91 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_sop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_sop1.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: s_mov_b32 s5, s1 ; encoding: [0x01,0x00,0x85,0xbe]
0x01,0x00,0x85,0xbe
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_sop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_sop2.txt
index 79a09ff921a96d7..8bd778ec1872934 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_sop2.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_sop2.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: s_add_u32 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0x80]
0x01,0x02,0x05,0x80
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_sopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_sopc.txt
index 0d65ede1afba722..4e6a7550534b380 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_sopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_sopc.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: s_cmp_eq_i32 s1, s2 ; encoding: [0x01,0x02,0x00,0xbf]
0x01,0x02,0x00,0xbf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_sopk.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_sopk.txt
index ec4277829529b72..e296d2a3a1fa47d 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_sopk.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_sopk.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: s_movk_i32 s5, 0x3141 ; encoding: [0x41,0x31,0x05,0xb0]
0x41,0x31,0x05,0xb0
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_sopp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_sopp.txt
index bd83e0cd4f6e521..6647b1fb657c502 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_sopp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_sopp.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: s_nop 0x3141 ; encoding: [0x41,0x31,0x80,0xbf]
0x41,0x31,0x80,0xbf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vintrp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vintrp.txt
index ba20fc3baa577aa..1c685aa47214465 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vintrp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vintrp.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_interp_p1_f32_e32 v5, v1, attr0.x ; encoding: [0x01,0x00,0x14,0xd4]
0x01,0x00,0x14,0xd4
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1.txt
index 51d2f68277b5a14..5bbd0ab3f45eeb4 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
0x00,0x00,0x00,0x7e
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1_dpp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1_dpp.txt
index c6df564d28cb8c1..f1f24202ad7fed9 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1_dpp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1_dpp.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x00]
0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1_sdwa.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1_sdwa.txt
index 0194b0ef5ef36d6..a5ed931ffd99957 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1_sdwa.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1_sdwa.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2.txt
index 40c325cb6ce3f82..f64b852a14bffe8 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_cndmask_b32_e32 v5, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x00]
0x01,0x05,0x0a,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_dpp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_dpp.txt
index 352f15f13b6c237..d678d8bdd795877 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_dpp.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_dpp.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x00]
0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_sdwa.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_sdwa.txt
index e04168f0fe345e9..9b141b603946938 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_sdwa.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_sdwa.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
index e3ed9778f6fb4d1..618e0815254148b 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_interp_p1_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3c.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3c.txt
index ab406ad526a6f8e..26131cf217e7693 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3c.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3c.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_cmp_class_f32_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3cx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3cx.txt
index 6d117f1436b8868..f1c8480b1f0ef02 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3cx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3cx.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_cmpx_class_f32_e64 s[10:11], v1, v2 ; encoding: [0x0a,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
0x0a,0x00,0x11,0xd0,0x01,0x05,0x02,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3p.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3p.txt
index 052087c0992ef74..215453d0331d41d 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3p.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3p.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_pk_mad_i16 v5, v1, v2, v3 ; encoding: [0x05,0x40,0x80,0xd3,0x01,0x05,0x0e,0x1c]
0x05,0x40,0x80,0xd3,0x01,0x05,0x0e,0x1c
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3p_opsel.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3p_opsel.txt
index 2269bdd814c323e..2abbc989a0ada39 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3p_opsel.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3p_opsel.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s
# Check that we can disassemble opcodes w/o src2 with any op_sel_hi value for src2
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopc.txt
index 3a803ba44e6a546..9952093bd1e1c93 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopc.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_cmp_class_f32_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x20,0x7c]
0x01,0x05,0x20,0x7c
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopc_sdwa.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopc_sdwa.txt
index 06add8bdf39e97f..cf8ea6054454381 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopc_sdwa.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopc_sdwa.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x06]
0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x06
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopcx.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopcx.txt
index 7398b42a0ef82ab..ed64f87d1dd6f6d 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopcx.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopcx.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_cmpx_class_f32_e32 vcc, v1, v2 ; encoding: [0x01,0x05,0x22,0x7c]
0x01,0x05,0x22,0x7c
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopcx_sdwa.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopcx_sdwa.txt
index e54110b635c2e5c..4b280ed02f1dcc9 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopcx_sdwa.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vopcx_sdwa.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s
# CHECK: v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x06]
0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x06
diff --git a/llvm/test/MC/Disassembler/AMDGPU/mad_mix.txt b/llvm/test/MC/Disassembler/AMDGPU/mad_mix.txt
index b328400b52c460e..6d73e588b48c861 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/mad_mix.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/mad_mix.txt
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX900
-# RUN: llvm-mc -arch=amdgcn -mcpu=gfx906 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX906
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX900
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx906 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX906
# GFX900: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
# GFX906: v_fma_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/si-support.txt b/llvm/test/MC/Disassembler/AMDGPU/si-support.txt
index 5538983597f76ff..f62d89ff7b0e9ec 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/si-support.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/si-support.txt
@@ -1,4 +1,4 @@
-# RUN: not --crash llvm-mc -arch=amdgcn -mcpu=tahiti -disassemble < %s 2>&1 | FileCheck %s
+# RUN: not --crash llvm-mc -triple=amdgcn -mcpu=tahiti -disassemble < %s 2>&1 | FileCheck %s
# CHECK: LLVM ERROR: Disassembly not yet supported for subtarget
0x00 0x00 0x00 0x7e
diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt
index 59b7f7e5a570f60..fbf8a57e84b0d3c 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r3 -mattr=+micromips,+fp64 %s \
+# RUN: llvm-mc --disassemble -triple=mipsel -mcpu=mips32r3 -mattr=+micromips,+fp64 %s \
# RUN: | FileCheck %s
0x0c 0x54 0x3b 0x0a # CHECK: sqrt.s $f0, $f12
diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt
index 6cc1bb4bbfec88a..95d000df309bac8 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 %s \
+# RUN: llvm-mc --disassemble -triple=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 %s \
# RUN: | FileCheck %s
0x54 0x0c 0x0a 0x3b # CHECK: sqrt.s $f0, $f12
diff --git a/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt
index c1b46f02d9a3ab8..85713cbbd732ae0 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32 -mattr=+fp64 %s | \
+# RUN: llvm-mc --disassemble -triple=mipsel -mcpu=mips32 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
diff --git a/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64.txt
index 08e7e54c4c0e7a6..d7de3beb55d52f2 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32 -mattr=+fp64 %s | \
+# RUN: llvm-mc --disassemble -triple=mips -mcpu=mips32 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt
index 73cd1969cb4b726..f84ea86ad5ef92a 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r2 -mattr=+fp64 %s | \
+# RUN: llvm-mc --disassemble -triple=mipsel -mcpu=mips32r2 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt
index ce99e18f26dd88c..acacbc54b42d0ce 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r2 -mattr=+fp64 %s | \
+# RUN: llvm-mc --disassemble -triple=mips -mcpu=mips32r2 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt
index a8291cfe64af7bc..d976a39b51a0bdc 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r3 -mattr=+fp64 %s | \
+# RUN: llvm-mc --disassemble -triple=mipsel -mcpu=mips32r3 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt
index 572faad447379ea..637ffd420e6c064 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r3 -mattr=+fp64 %s | \
+# RUN: llvm-mc --disassemble -triple=mips -mcpu=mips32r3 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt
index 33569c0af8b0b33..a110e707629e619 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r5 -mattr=+fp64 %s | \
+# RUN: llvm-mc --disassemble -triple=mipsel -mcpu=mips32r5 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt
index 5116a69fbcaad89..ae6da7f676d7f25 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r5 -mattr=+fp64 %s | \
+# RUN: llvm-mc --disassemble -triple=mips -mcpu=mips32r5 -mattr=+fp64 %s | \
# RUN: FileCheck %s
0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12
diff --git a/llvm/test/MC/Hexagon/J2_trap1_dep.s b/llvm/test/MC/Hexagon/J2_trap1_dep.s
index ab054d1783dc696..ea5d66e18a5919b 100644
--- a/llvm/test/MC/Hexagon/J2_trap1_dep.s
+++ b/llvm/test/MC/Hexagon/J2_trap1_dep.s
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv62 -d - | FileCheck %s --check-prefix=CHECK-V62
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv65 -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv65 -d - | FileCheck %s --check-prefix=CHECK-V65
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv62 -d - | FileCheck %s --check-prefix=CHECK-V62
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv65 -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv65 -d - | FileCheck %s --check-prefix=CHECK-V65
# CHECK-V62: trap1(#0)
# CHECK-V65: trap1(r0,#0)
diff --git a/llvm/test/MC/Hexagon/PacketRules/bundle_option.s b/llvm/test/MC/Hexagon/PacketRules/bundle_option.s
index 29f5a24fbda7dbe..5e63019bcce203e 100644
--- a/llvm/test/MC/Hexagon/PacketRules/bundle_option.s
+++ b/llvm/test/MC/Hexagon/PacketRules/bundle_option.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t
+# RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t
{ nop }:junk
# CHECK: 3:9: error: 'junk' is not a valid bundle option
diff --git a/llvm/test/MC/Hexagon/PacketRules/hvx_vshuff_vdeal.s b/llvm/test/MC/Hexagon/PacketRules/hvx_vshuff_vdeal.s
index 028062f260f7a73..05e31191c0a51de 100644
--- a/llvm/test/MC/Hexagon/PacketRules/hvx_vshuff_vdeal.s
+++ b/llvm/test/MC/Hexagon/PacketRules/hvx_vshuff_vdeal.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj -o %t %s 2>&1 | FileCheck --implicit-check-not=error: %s
+# RUN: not llvm-mc -triple=hexagon -mv65 -mhvx -filetype=obj -o %t %s 2>&1 | FileCheck --implicit-check-not=error: %s
{ v1 = v2; vshuff(v1,v3,r0) }
# CHECK: error: register `V1' modified more than once
diff --git a/llvm/test/MC/Hexagon/PacketRules/hvx_vshuff_vdeal_dup.s b/llvm/test/MC/Hexagon/PacketRules/hvx_vshuff_vdeal_dup.s
index a435511990d199a..830e648106a5912 100644
--- a/llvm/test/MC/Hexagon/PacketRules/hvx_vshuff_vdeal_dup.s
+++ b/llvm/test/MC/Hexagon/PacketRules/hvx_vshuff_vdeal_dup.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=hexagon -mv65 -mhvx -filetype=obj %s 2>&1 | FileCheck %s
{ vshuff(v0,v0,r0) }
# CHECK: error: register `V0' modified more than once
diff --git a/llvm/test/MC/Hexagon/PacketRules/newvalue_producers.s b/llvm/test/MC/Hexagon/PacketRules/newvalue_producers.s
index e419d81a6368f03..b9165ed4d1aa425 100644
--- a/llvm/test/MC/Hexagon/PacketRules/newvalue_producers.s
+++ b/llvm/test/MC/Hexagon/PacketRules/newvalue_producers.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -mhvx -filetype=asm %s 2>%t; FileCheck %s <%t
+# RUN: not llvm-mc -triple=hexagon -mhvx -filetype=asm %s 2>%t; FileCheck %s <%t
{ r0=memw(r1=##0)
memw(r0)=r1.new }
diff --git a/llvm/test/MC/Hexagon/PacketRules/newvalue_producers_pass.s b/llvm/test/MC/Hexagon/PacketRules/newvalue_producers_pass.s
index e1c4bad9fecac51..e5ebcea626bc75b 100644
--- a/llvm/test/MC/Hexagon/PacketRules/newvalue_producers_pass.s
+++ b/llvm/test/MC/Hexagon/PacketRules/newvalue_producers_pass.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mhvx -mcpu=hexagonv65 -filetype=obj %s | llvm-objdump --no-print-imm-hex --mattr=+hvxv65 -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mhvx -mcpu=hexagonv65 -filetype=obj %s | llvm-objdump --no-print-imm-hex --mattr=+hvxv65 -d - | FileCheck %s
{ r0=r0
memw(r0)=r0.new }
diff --git a/llvm/test/MC/Hexagon/PacketRules/registers_readonly.s b/llvm/test/MC/Hexagon/PacketRules/registers_readonly.s
index ec11858971177c0..e3759614da7af05 100644
--- a/llvm/test/MC/Hexagon/PacketRules/registers_readonly.s
+++ b/llvm/test/MC/Hexagon/PacketRules/registers_readonly.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=obj %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=hexagon -filetype=obj %s 2>&1 | FileCheck %s
# CHECK: 4:3: error: Cannot write to read-only register `PC'
{ pc = r0
diff --git a/llvm/test/MC/Hexagon/PacketRules/restrict_ax.s b/llvm/test/MC/Hexagon/PacketRules/restrict_ax.s
index 58c86b28e754f33..a18a926081c25a5 100644
--- a/llvm/test/MC/Hexagon/PacketRules/restrict_ax.s
+++ b/llvm/test/MC/Hexagon/PacketRules/restrict_ax.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t
+# RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t
{ r0=memw_locked(r0)
r1=sfadd(r0,r0) }
diff --git a/llvm/test/MC/Hexagon/PacketRules/restrict_no_slot1_store_pass.s b/llvm/test/MC/Hexagon/PacketRules/restrict_no_slot1_store_pass.s
index fc85c776ae4c329..94d37ea8ef149af 100644
--- a/llvm/test/MC/Hexagon/PacketRules/restrict_no_slot1_store_pass.s
+++ b/llvm/test/MC/Hexagon/PacketRules/restrict_no_slot1_store_pass.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
{ r0=sub(#1,r0)
r1=sub(#1, r0)
diff --git a/llvm/test/MC/Hexagon/PacketRules/restrict_slot1_aok.s b/llvm/test/MC/Hexagon/PacketRules/restrict_slot1_aok.s
index 669c43cebcd831a..1ef8e3097f04741 100644
--- a/llvm/test/MC/Hexagon/PacketRules/restrict_slot1_aok.s
+++ b/llvm/test/MC/Hexagon/PacketRules/restrict_slot1_aok.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2>&1 | FileCheck %s
{ r0=sub(#1,r0)
r1=sub(#1, r0)
diff --git a/llvm/test/MC/Hexagon/PacketRules/restrict_slot1_aok_pass.s b/llvm/test/MC/Hexagon/PacketRules/restrict_slot1_aok_pass.s
index 0b439eb232da04a..c7282edeb4bbcbf 100644
--- a/llvm/test/MC/Hexagon/PacketRules/restrict_slot1_aok_pass.s
+++ b/llvm/test/MC/Hexagon/PacketRules/restrict_slot1_aok_pass.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
{ r0=sub(#1,r0)
r1=sub(#1, r0)
diff --git a/llvm/test/MC/Hexagon/PacketRules/solo.s b/llvm/test/MC/Hexagon/PacketRules/solo.s
index 86107d52f1fc1ad..51505d551d17793 100644
--- a/llvm/test/MC/Hexagon/PacketRules/solo.s
+++ b/llvm/test/MC/Hexagon/PacketRules/solo.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t
+# RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t
{ brkpt
r0 = r0 }
diff --git a/llvm/test/MC/Hexagon/arch-support.s b/llvm/test/MC/Hexagon/arch-support.s
index 1782ebb1ecc3d2b..01a15bce5c4116e 100644
--- a/llvm/test/MC/Hexagon/arch-support.s
+++ b/llvm/test/MC/Hexagon/arch-support.s
@@ -1,20 +1,20 @@
-# RUN: llvm-mc -arch=hexagon -mv5 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V5 %s
-# RUN: llvm-mc -arch=hexagon -mv55 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V55 %s
-# RUN: llvm-mc -arch=hexagon -mv60 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V60 %s
-# RUN: llvm-mc -arch=hexagon -mv62 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V62 %s
-# RUN: llvm-mc -arch=hexagon -mv65 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V65 %s
-# RUN: llvm-mc -arch=hexagon -mv67 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V67 %s
-# RUN: llvm-mc -arch=hexagon -mv68 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V68 %s
-# RUN: llvm-mc -arch=hexagon -mv69 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V69 %s
+# RUN: llvm-mc -triple=hexagon -mv5 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V5 %s
+# RUN: llvm-mc -triple=hexagon -mv55 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V55 %s
+# RUN: llvm-mc -triple=hexagon -mv60 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V60 %s
+# RUN: llvm-mc -triple=hexagon -mv62 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V62 %s
+# RUN: llvm-mc -triple=hexagon -mv65 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V65 %s
+# RUN: llvm-mc -triple=hexagon -mv67 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V67 %s
+# RUN: llvm-mc -triple=hexagon -mv68 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V68 %s
+# RUN: llvm-mc -triple=hexagon -mv69 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V69 %s
-# RUN: llvm-mc -arch=hexagon -mv5 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
-# RUN: llvm-mc -arch=hexagon -mv55 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
-# RUN: llvm-mc -arch=hexagon -mv60 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
-# RUN: llvm-mc -arch=hexagon -mv62 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
-# RUN: llvm-mc -arch=hexagon -mv65 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
-# RUN: llvm-mc -arch=hexagon -mv67 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
-# RUN: llvm-mc -arch=hexagon -mv68 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
-# RUN: llvm-mc -arch=hexagon -mv69 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
+# RUN: llvm-mc -triple=hexagon -mv5 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
+# RUN: llvm-mc -triple=hexagon -mv55 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
+# RUN: llvm-mc -triple=hexagon -mv60 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
+# RUN: llvm-mc -triple=hexagon -mv62 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
+# RUN: llvm-mc -triple=hexagon -mv65 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
+# RUN: llvm-mc -triple=hexagon -mv67 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
+# RUN: llvm-mc -triple=hexagon -mv68 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
+# RUN: llvm-mc -triple=hexagon -mv69 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s
.text
r1 = r1
diff --git a/llvm/test/MC/Hexagon/bug15961.s b/llvm/test/MC/Hexagon/bug15961.s
index 7173aa0b7be9d3b..aa662ba9d76ee84 100644
--- a/llvm/test/MC/Hexagon/bug15961.s
+++ b/llvm/test/MC/Hexagon/bug15961.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mv65 -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mv65 -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
#
{
diff --git a/llvm/test/MC/Hexagon/bug18767.s b/llvm/test/MC/Hexagon/bug18767.s
index 35604f379cacfb9..956aee45756c07f 100644
--- a/llvm/test/MC/Hexagon/bug18767.s
+++ b/llvm/test/MC/Hexagon/bug18767.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s < %t
+# RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2>%t; FileCheck %s < %t
.L_:
{
diff --git a/llvm/test/MC/Hexagon/bug24609.s b/llvm/test/MC/Hexagon/bug24609.s
index b64b5b817f006f6..e3da5e244ac9b59 100644
--- a/llvm/test/MC/Hexagon/bug24609.s
+++ b/llvm/test/MC/Hexagon/bug24609.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
{ p0 = cmp.eq(r0,#0) ; if (p0.new) dealloc_return:t }
diff --git a/llvm/test/MC/Hexagon/bug28416.s b/llvm/test/MC/Hexagon/bug28416.s
index 237d577a7a486b0..b464c75a3838ffa 100644
--- a/llvm/test/MC/Hexagon/bug28416.s
+++ b/llvm/test/MC/Hexagon/bug28416.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj -o - %s | llvm-objdump -d -
+# RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d -
# r0 = r6 and jump ##undefined should compound to J4_jumpsetr
# CHECK: { immext(#0)
diff --git a/llvm/test/MC/Hexagon/bug_28748.s b/llvm/test/MC/Hexagon/bug_28748.s
index 74543f20ba002c7..24f24a796dc1863 100644
--- a/llvm/test/MC/Hexagon/bug_28748.s
+++ b/llvm/test/MC/Hexagon/bug_28748.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv65 -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv65 -d - | FileCheck --implicit-check-not='{' %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv65 -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv65 -d - | FileCheck --implicit-check-not='{' %s
# This case requires compounding only some of the instructions which are
# possible compounds. Compounding all possible opcodes is ideal for code size
diff --git a/llvm/test/MC/Hexagon/c4_newval.s b/llvm/test/MC/Hexagon/c4_newval.s
index 356a3695c58d17f..db07b1728de29ad 100644
--- a/llvm/test/MC/Hexagon/c4_newval.s
+++ b/llvm/test/MC/Hexagon/c4_newval.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon %s 2>%t; FileCheck --implicit-check-not=error: %s <%t
+# RUN: not llvm-mc -triple=hexagon %s 2>%t; FileCheck --implicit-check-not=error: %s <%t
.Lfoo:
{ p3:0 = r0
diff --git a/llvm/test/MC/Hexagon/cmpyrw.s b/llvm/test/MC/Hexagon/cmpyrw.s
index c93205f43ab6d7c..d22f06db22cd4e3 100644
--- a/llvm/test/MC/Hexagon/cmpyrw.s
+++ b/llvm/test/MC/Hexagon/cmpyrw.s
@@ -1,3 +1,3 @@
-# RUN: llvm-mc -arch=hexagon -mv67t -filetype=obj %s | llvm-objdump --mcpu=hexagonv67t --mattr=+audio -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mv67t -filetype=obj %s | llvm-objdump --mcpu=hexagonv67t --mattr=+audio -d - | FileCheck %s
r23:22 = cmpyrw(r15:14,r21:20*)
# CHECK: r23:22 = cmpyrw(r15:14,r21:20*)
diff --git a/llvm/test/MC/Hexagon/common-redeclare.s b/llvm/test/MC/Hexagon/common-redeclare.s
index 1babad14255741f..91ab645fe35837c 100644
--- a/llvm/test/MC/Hexagon/common-redeclare.s
+++ b/llvm/test/MC/Hexagon/common-redeclare.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -t - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -t - | FileCheck %s
# CHECK: 00000062 O *COM* 00000008 quartet_table_isqrt
diff --git a/llvm/test/MC/Hexagon/dcfetch-symbol.s b/llvm/test/MC/Hexagon/dcfetch-symbol.s
index 8309439a2aaa042..ad182fa47819be8 100644
--- a/llvm/test/MC/Hexagon/dcfetch-symbol.s
+++ b/llvm/test/MC/Hexagon/dcfetch-symbol.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=obj %s
+# RUN: not llvm-mc -triple=hexagon -filetype=obj %s
#CHECK: 9400c000 { dcfetch(r0 + #0) }
diff --git a/llvm/test/MC/Hexagon/dealloc-return-jump.s b/llvm/test/MC/Hexagon/dealloc-return-jump.s
index 0d480bef85d2bd5..fae0804ab52737b 100644
--- a/llvm/test/MC/Hexagon/dealloc-return-jump.s
+++ b/llvm/test/MC/Hexagon/dealloc-return-jump.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -o - %s
+# RUN: not llvm-mc -triple=hexagon -mcpu=hexagonv62 -filetype=obj -o - %s
# Check that a duplex involving dealloc_return is correctly checked
# dealloc_return cannot be involved in a double jump packet
diff --git a/llvm/test/MC/Hexagon/decode_acc_type.s b/llvm/test/MC/Hexagon/decode_acc_type.s
index e822ed3945c5b00..98a0d5d1c52ab8b 100644
--- a/llvm/test/MC/Hexagon/decode_acc_type.s
+++ b/llvm/test/MC/Hexagon/decode_acc_type.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
#
# Currently ignore if there is one or two #'s
diff --git a/llvm/test/MC/Hexagon/dis-duplex-p0.s b/llvm/test/MC/Hexagon/dis-duplex-p0.s
index e41ff9ec606b30f..0ed688e028e9e0e 100644
--- a/llvm/test/MC/Hexagon/dis-duplex-p0.s
+++ b/llvm/test/MC/Hexagon/dis-duplex-p0.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=hexagon -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+// RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
{ r7 = #-1
r6 = #-1 }
diff --git a/llvm/test/MC/Hexagon/double-vector-producer.s b/llvm/test/MC/Hexagon/double-vector-producer.s
index e10917b06fb4229..d1e5c5d6882de6d 100644
--- a/llvm/test/MC/Hexagon/double-vector-producer.s
+++ b/llvm/test/MC/Hexagon/double-vector-producer.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s | llvm-objdump -d - | FileCheck %s
{
v1:0 = vshuff(v1,v0,r7)
v2.w = vadd(v13.w,v15.w)
diff --git a/llvm/test/MC/Hexagon/duplex-addi-global-imm.s b/llvm/test/MC/Hexagon/duplex-addi-global-imm.s
index e8e338c6a582bac..dd27be01ae4007e 100644
--- a/llvm/test/MC/Hexagon/duplex-addi-global-imm.s
+++ b/llvm/test/MC/Hexagon/duplex-addi-global-imm.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -show-encoding %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -show-encoding %s | FileCheck %s
# Check that we generate a duplex for this packet.
# CHECK: encoding: [A,0x40'A',A,A,0x01'B',0x28'B',B,0x20'B']
diff --git a/llvm/test/MC/Hexagon/elf-flags.s b/llvm/test/MC/Hexagon/elf-flags.s
index d392e7e1db24dbc..f6df80d57a257c2 100644
--- a/llvm/test/MC/Hexagon/elf-flags.s
+++ b/llvm/test/MC/Hexagon/elf-flags.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv5 --filetype=obj %s -o - | llvm-readelf --file-headers - | FileCheck --check-prefix=CHECK-V5 %s
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv55 --filetype=obj %s -o - | llvm-readelf --file-headers - | FileCheck --check-prefix=CHECK-V55 %s
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 --filetype=obj %s -o - | llvm-readelf --file-headers - | FileCheck --check-prefix=CHECK-V60 %s
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 --filetype=obj %s -o - | llvm-readelf --file-headers - | FileCheck --check-prefix=CHECK-V62 %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv5 --filetype=obj %s -o - | llvm-readelf --file-headers - | FileCheck --check-prefix=CHECK-V5 %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv55 --filetype=obj %s -o - | llvm-readelf --file-headers - | FileCheck --check-prefix=CHECK-V55 %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 --filetype=obj %s -o - | llvm-readelf --file-headers - | FileCheck --check-prefix=CHECK-V60 %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv62 --filetype=obj %s -o - | llvm-readelf --file-headers - | FileCheck --check-prefix=CHECK-V62 %s
# CHECK-V5: Flags: 0x4
# CHECK-V55: Flags: 0x5
diff --git a/llvm/test/MC/Hexagon/equ.s b/llvm/test/MC/Hexagon/equ.s
index fbf09edbbc1e0e1..900c2ac3eb39308 100644
--- a/llvm/test/MC/Hexagon/equ.s
+++ b/llvm/test/MC/Hexagon/equ.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon %s 2> %t
+# RUN: not llvm-mc -triple=hexagon %s 2> %t
# RUN: FileCheck < %t %s
.equ a, 0
diff --git a/llvm/test/MC/Hexagon/ext-callt-rel.s b/llvm/test/MC/Hexagon/ext-callt-rel.s
index 344a8fbc11b94e4..ced09805f8c8870 100644
--- a/llvm/test/MC/Hexagon/ext-callt-rel.s
+++ b/llvm/test/MC/Hexagon/ext-callt-rel.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s -o - | llvm-objdump -r - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s -o - | llvm-objdump -r - | FileCheck %s
if (p0) call foo
#CHECK: R_HEX_B32_PCREL_X
diff --git a/llvm/test/MC/Hexagon/extender.s b/llvm/test/MC/Hexagon/extender.s
index 2b27901c30a7eaa..d2f15ccb2c19dd6 100644
--- a/llvm/test/MC/Hexagon/extender.s
+++ b/llvm/test/MC/Hexagon/extender.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
#
# STrib_abs_V4
diff --git a/llvm/test/MC/Hexagon/extensions/v67_hvx.s b/llvm/test/MC/Hexagon/extensions/v67_hvx.s
index 2b1923cb6dd5966..f1f77979540ec8d 100644
--- a/llvm/test/MC/Hexagon/extensions/v67_hvx.s
+++ b/llvm/test/MC/Hexagon/extensions/v67_hvx.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67 -mhvx -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv67 --mattr=+hvx -d - | FileCheck --implicit-check-not='{' %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv67 -mhvx -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv67 --mattr=+hvx -d - | FileCheck --implicit-check-not='{' %s
diff --git a/llvm/test/MC/Hexagon/extensions/v67t_audio.s b/llvm/test/MC/Hexagon/extensions/v67t_audio.s
index e941f94146e3366..04d004f5f12a4f9 100644
--- a/llvm/test/MC/Hexagon/extensions/v67t_audio.s
+++ b/llvm/test/MC/Hexagon/extensions/v67t_audio.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv67t -d - | FileCheck --implicit-check-not='{' %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv67t -d - | FileCheck --implicit-check-not='{' %s
diff --git a/llvm/test/MC/Hexagon/fixups.s b/llvm/test/MC/Hexagon/fixups.s
index 8f86db7ae18f181..d6fee5b028e2375 100644
--- a/llvm/test/MC/Hexagon/fixups.s
+++ b/llvm/test/MC/Hexagon/fixups.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
.text
# CHECK-LABEL: 0:
diff --git a/llvm/test/MC/Hexagon/got.s b/llvm/test/MC/Hexagon/got.s
index 85409ee4a900dc7..bffe989a98a57d8 100644
--- a/llvm/test/MC/Hexagon/got.s
+++ b/llvm/test/MC/Hexagon/got.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -r - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -r - | FileCheck %s
#
# make sure the fixups emitted match what is
diff --git a/llvm/test/MC/Hexagon/gprel-shflag.s b/llvm/test/MC/Hexagon/gprel-shflag.s
index 6a8a9a027b69175..2d27bc7a16b28ae 100644
--- a/llvm/test/MC/Hexagon/gprel-shflag.s
+++ b/llvm/test/MC/Hexagon/gprel-shflag.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=asm %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=asm %s | FileCheck %s
# Make sure the assembler can parse and print the "s" flag for Hexaon's
# small-data section.
diff --git a/llvm/test/MC/Hexagon/guest.s b/llvm/test/MC/Hexagon/guest.s
index 8f8d7c410ef4023..60fdd94bc573872 100644
--- a/llvm/test/MC/Hexagon/guest.s
+++ b/llvm/test/MC/Hexagon/guest.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
r0=gpmucnt4
# CHECK: { r0 = gpmucnt4 }
diff --git a/llvm/test/MC/Hexagon/hex-immediates.s b/llvm/test/MC/Hexagon/hex-immediates.s
index 8a0ed9a810e87cf..6bdd00cf7f719ac 100644
--- a/llvm/test/MC/Hexagon/hex-immediates.s
+++ b/llvm/test/MC/Hexagon/hex-immediates.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -filetype=obj -arch=hexagon %s | llvm-objdump -d --print-imm-hex - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=hexagon %s | llvm-objdump -d --print-imm-hex - | FileCheck %s
# CHECK: r3 = ##0x70000240
r3 = ##1879048768
diff --git a/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s b/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s
index a2de7e290e8e383..5c409ab733022d6 100644
--- a/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s
+++ b/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -filetype=obj -arch=hexagon -mv65 -mattr=+hvxv65,+hvx-length128b %s | llvm-objdump -d --mattr=+hvx - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=hexagon -mv65 -mattr=+hvxv65,+hvx-length128b %s | llvm-objdump -d --mattr=+hvx - | FileCheck %s
# CHECK: vhist
vhist
diff --git a/llvm/test/MC/Hexagon/hvx-swapped-regpairs-alias-neg.s b/llvm/test/MC/Hexagon/hvx-swapped-regpairs-alias-neg.s
index 1988f90dc56e39c..5a0b628c992a40e 100644
--- a/llvm/test/MC/Hexagon/hvx-swapped-regpairs-alias-neg.s
+++ b/llvm/test/MC/Hexagon/hvx-swapped-regpairs-alias-neg.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -mcpu=hexagonv67 -mhvx -filetype=asm %s 2>%t; FileCheck --implicit-check-not="error:" %s <%t
+# RUN: not llvm-mc -triple=hexagon -mcpu=hexagonv67 -mhvx -filetype=asm %s 2>%t; FileCheck --implicit-check-not="error:" %s <%t
{
v1:0 = #0
diff --git a/llvm/test/MC/Hexagon/hvx-swapped-regpairs.s b/llvm/test/MC/Hexagon/hvx-swapped-regpairs.s
index 18bfafed2f98646..8fd722621876d59 100644
--- a/llvm/test/MC/Hexagon/hvx-swapped-regpairs.s
+++ b/llvm/test/MC/Hexagon/hvx-swapped-regpairs.s
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -filetype=obj -arch=hexagon -mcpu=hexagonv67 -mhvx %s | llvm-objdump --no-print-imm-hex -d --mcpu=hexagonv67 --mattr=+hvx - | FileCheck %s
-# RUN: not llvm-mc -arch=hexagon -mcpu=hexagonv65 -mhvx -filetype=asm %s 2>%t; FileCheck --check-prefix=CHECK-V65 --implicit-check-not="error:" %s <%t
+# RUN: llvm-mc -filetype=obj -triple=hexagon -mcpu=hexagonv67 -mhvx %s | llvm-objdump --no-print-imm-hex -d --mcpu=hexagonv67 --mattr=+hvx - | FileCheck %s
+# RUN: not llvm-mc -triple=hexagon -mcpu=hexagonv65 -mhvx -filetype=asm %s 2>%t; FileCheck --check-prefix=CHECK-V65 --implicit-check-not="error:" %s <%t
v1:0.w = vadd(v0.h, v1.h) // Normal
# CHECK: 1ca1c080
diff --git a/llvm/test/MC/Hexagon/hvx-tmp-accum-no-erros.s b/llvm/test/MC/Hexagon/hvx-tmp-accum-no-erros.s
index 255851c7dae0110..a43c8084dbfa038 100644
--- a/llvm/test/MC/Hexagon/hvx-tmp-accum-no-erros.s
+++ b/llvm/test/MC/Hexagon/hvx-tmp-accum-no-erros.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mattr=+hvxv68 -filetype=obj %s | llvm-objdump --no-print-imm-hex --mattr=+hvxv68 -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mattr=+hvxv68 -filetype=obj %s | llvm-objdump --no-print-imm-hex --mattr=+hvxv68 -d - | FileCheck %s
# packet w/accum with register different from one loaded to
{
diff --git a/llvm/test/MC/Hexagon/hvx-tmp-accum.s b/llvm/test/MC/Hexagon/hvx-tmp-accum.s
index d5871696bb9b89f..4adf9028e8b6c00 100644
--- a/llvm/test/MC/Hexagon/hvx-tmp-accum.s
+++ b/llvm/test/MC/Hexagon/hvx-tmp-accum.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -mhvx -filetype=asm %s 2>%t; FileCheck --implicit-check-not="error:" %s <%t
+# RUN: not llvm-mc -triple=hexagon -mhvx -filetype=asm %s 2>%t; FileCheck --implicit-check-not="error:" %s <%t
{
v0.tmp = vmem(r0+#0)
v0 += vrmpyub(v1, r1)
diff --git a/llvm/test/MC/Hexagon/hvx_cur_alias.s b/llvm/test/MC/Hexagon/hvx_cur_alias.s
index ed16659d4522f52..66f7595381e040f 100644
--- a/llvm/test/MC/Hexagon/hvx_cur_alias.s
+++ b/llvm/test/MC/Hexagon/hvx_cur_alias.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s 2>&1 | llvm-objdump --mattr=+hvx -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s 2>&1 | llvm-objdump --mattr=+hvx -d - | FileCheck %s
{ v2.cur = vmem(r11++m0)
v5:4.h = vmpa(v3:2.ub,v5:4.ub)
diff --git a/llvm/test/MC/Hexagon/inval_immed.s b/llvm/test/MC/Hexagon/inval_immed.s
index 12600b09eff897f..41604ff4ef23e7a 100644
--- a/llvm/test/MC/Hexagon/inval_immed.s
+++ b/llvm/test/MC/Hexagon/inval_immed.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -filetype=asm -arch=hexagon %s 2>%t; FileCheck %s < %t
+# RUN: not llvm-mc -filetype=asm -triple=hexagon %s 2>%t; FileCheck %s < %t
.text
r0 = mpyi(r0,#m9)
diff --git a/llvm/test/MC/Hexagon/load-GPRel.s b/llvm/test/MC/Hexagon/load-GPRel.s
index 613094a63f6ffd5..0d8959d034eacca 100644
--- a/llvm/test/MC/Hexagon/load-GPRel.s
+++ b/llvm/test/MC/Hexagon/load-GPRel.s
@@ -1,4 +1,4 @@
-#RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+#RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
# Check encoding bits for GP-relative loads.
diff --git a/llvm/test/MC/Hexagon/missing_label.s b/llvm/test/MC/Hexagon/missing_label.s
index f916f2f4310a4c6..dc270c2a3e2c246 100644
--- a/llvm/test/MC/Hexagon/missing_label.s
+++ b/llvm/test/MC/Hexagon/missing_label.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
#
.I1:
diff --git a/llvm/test/MC/Hexagon/multiple-pc4.s b/llvm/test/MC/Hexagon/multiple-pc4.s
index 697991961a5ddbf..df759ff8b0b97f3 100644
--- a/llvm/test/MC/Hexagon/multiple-pc4.s
+++ b/llvm/test/MC/Hexagon/multiple-pc4.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck --implicit-check-not=error: %s <%t
+# RUN: llvm-mc -triple=hexagon -filetype=asm %s 2>%t; FileCheck --implicit-check-not=error: %s <%t
# Check that multiple changes to a predicate in a packet are caught.
diff --git a/llvm/test/MC/Hexagon/multiple_errs.s b/llvm/test/MC/Hexagon/multiple_errs.s
index cd04c0efbd360e1..03afbac966b7fde 100644
--- a/llvm/test/MC/Hexagon/multiple_errs.s
+++ b/llvm/test/MC/Hexagon/multiple_errs.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2> %t; FileCheck %s < %t
+# RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2> %t; FileCheck %s < %t
#
{
diff --git a/llvm/test/MC/Hexagon/non-relocatable.s b/llvm/test/MC/Hexagon/non-relocatable.s
index 72a17901c622677..698e67ac1bed657 100644
--- a/llvm/test/MC/Hexagon/non-relocatable.s
+++ b/llvm/test/MC/Hexagon/non-relocatable.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=obj %s 2>%t; FileCheck %s <%t
+# RUN: not llvm-mc -triple=hexagon -filetype=obj %s 2>%t; FileCheck %s <%t
# Don't allow a symbolic operand for an insn that cannot take a
# relocation.
diff --git a/llvm/test/MC/Hexagon/not-over.s b/llvm/test/MC/Hexagon/not-over.s
index c31ce5312305090..01204724506084c 100644
--- a/llvm/test/MC/Hexagon/not-over.s
+++ b/llvm/test/MC/Hexagon/not-over.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t
+# RUN: llvm-mc -triple=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t
#
# Check that proper packets are not wrongly flagged as invalid.
diff --git a/llvm/test/MC/Hexagon/not_found.s b/llvm/test/MC/Hexagon/not_found.s
index 9f1ba4d76e5dc43..3654af11f583fc2 100644
--- a/llvm/test/MC/Hexagon/not_found.s
+++ b/llvm/test/MC/Hexagon/not_found.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=asm junk123.s 2>%t ; FileCheck -DMSG=%errc_ENOENT %s < %t
+# RUN: not llvm-mc -triple=hexagon -filetype=asm junk123.s 2>%t ; FileCheck -DMSG=%errc_ENOENT %s < %t
#
# CHECK: junk123.s: [[MSG]]
diff --git a/llvm/test/MC/Hexagon/nowarn.s b/llvm/test/MC/Hexagon/nowarn.s
index f5b24ebe59063a0..ed0d7ddabd26942 100644
--- a/llvm/test/MC/Hexagon/nowarn.s
+++ b/llvm/test/MC/Hexagon/nowarn.s
@@ -1,6 +1,6 @@
-# RUN: llvm-mc -arch=hexagon -mhvx --filetype=asm %s -o - 2>&1 | FileCheck %s
-# RUN: llvm-mc --no-warn -arch=hexagon -mhvx --filetype=obj %s -o - | llvm-objdump -d - | FileCheck --check-prefix=CHECK-NOWARN %s
-# RUN: not llvm-mc --fatal-warnings -arch=hexagon -mhvx --filetype=asm %s 2>&1 | FileCheck --check-prefix=CHECK-FATAL-WARN %s
+# RUN: llvm-mc -triple=hexagon -mhvx --filetype=asm %s -o - 2>&1 | FileCheck %s
+# RUN: llvm-mc --no-warn -triple=hexagon -mhvx --filetype=obj %s -o - | llvm-objdump -d - | FileCheck --check-prefix=CHECK-NOWARN %s
+# RUN: not llvm-mc --fatal-warnings -triple=hexagon -mhvx --filetype=asm %s 2>&1 | FileCheck --check-prefix=CHECK-FATAL-WARN %s
.text
.warning
diff --git a/llvm/test/MC/Hexagon/offset.s b/llvm/test/MC/Hexagon/offset.s
index 5cd60daff06e781..9cc8e8b3dcdc40a 100644
--- a/llvm/test/MC/Hexagon/offset.s
+++ b/llvm/test/MC/Hexagon/offset.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -t - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -t - | FileCheck %s
#
sym_a:
diff --git a/llvm/test/MC/Hexagon/operand-range.s b/llvm/test/MC/Hexagon/operand-range.s
index c38aab7060ddf16..868b38ff6fcc734 100644
--- a/llvm/test/MC/Hexagon/operand-range.s
+++ b/llvm/test/MC/Hexagon/operand-range.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2>&1 | FileCheck %s
# Expect errors here, insn needs to be extended
R1 = mpyi(R2, #-256)
diff --git a/llvm/test/MC/Hexagon/parse-pound-hi.s b/llvm/test/MC/Hexagon/parse-pound-hi.s
index a1f73ec1953c3f9..5f51764be4d3e4b 100644
--- a/llvm/test/MC/Hexagon/parse-pound-hi.s
+++ b/llvm/test/MC/Hexagon/parse-pound-hi.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
memw(gp+#hi_htc_version) = r3
#CHECK: 4880c300 { memw(gp+#0) = r3 }
diff --git a/llvm/test/MC/Hexagon/pcrel.s b/llvm/test/MC/Hexagon/pcrel.s
index 368fea5c2b303cc..282f09d405a9c23 100644
--- a/llvm/test/MC/Hexagon/pcrel.s
+++ b/llvm/test/MC/Hexagon/pcrel.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -r - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -r - | FileCheck %s
#
# make sure the fixups emitted match what is
diff --git a/llvm/test/MC/Hexagon/plt-rel.s b/llvm/test/MC/Hexagon/plt-rel.s
index 90526c660ab5b83..bdd8091655b929c 100644
--- a/llvm/test/MC/Hexagon/plt-rel.s
+++ b/llvm/test/MC/Hexagon/plt-rel.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d -r - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d -r - | FileCheck %s
call foo at GDPLT
# CHECK: R_HEX_GD_PLT_B22_PCREL
diff --git a/llvm/test/MC/Hexagon/quad_regs.s b/llvm/test/MC/Hexagon/quad_regs.s
index 3041d60307ecdcd..68fbde0bce9967f 100644
--- a/llvm/test/MC/Hexagon/quad_regs.s
+++ b/llvm/test/MC/Hexagon/quad_regs.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv66 --mattr=+hvx -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv66 --mattr=+hvx -d - | FileCheck %s
# Test for quad register parsing and printing
# CHECK: { v3:0.w = vrmpyz(v0.b,r0.b) }
diff --git a/llvm/test/MC/Hexagon/register-alt-names.s b/llvm/test/MC/Hexagon/register-alt-names.s
index 3e514661887e257..3c9ab753dfff8b0 100644
--- a/llvm/test/MC/Hexagon/register-alt-names.s
+++ b/llvm/test/MC/Hexagon/register-alt-names.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon < %s | FileCheck %s
# CHECK: r0 = r31
r0 = lr
diff --git a/llvm/test/MC/Hexagon/registers_readonly.s b/llvm/test/MC/Hexagon/registers_readonly.s
index cf109feef0361ad..cb9032b494ea4e3 100644
--- a/llvm/test/MC/Hexagon/registers_readonly.s
+++ b/llvm/test/MC/Hexagon/registers_readonly.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=obj -mv5 %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=hexagon -filetype=obj -mv5 %s 2>&1 | FileCheck %s
# CHECK: 4:1: error: Cannot write to read-only register `PC'
pc = r0
diff --git a/llvm/test/MC/Hexagon/ro-c9.s b/llvm/test/MC/Hexagon/ro-c9.s
index 6771430cb95ccef..5dd3f8320c23d1f 100644
--- a/llvm/test/MC/Hexagon/ro-c9.s
+++ b/llvm/test/MC/Hexagon/ro-c9.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=asm %s 2> %t; FileCheck %s < %t
+# RUN: llvm-mc -triple=hexagon -filetype=asm %s 2> %t; FileCheck %s < %t
# Check that changes to a read-only register is caught.
diff --git a/llvm/test/MC/Hexagon/ro-cc9.s b/llvm/test/MC/Hexagon/ro-cc9.s
index 0596ca1627f9b74..2080ab6c13cc454 100644
--- a/llvm/test/MC/Hexagon/ro-cc9.s
+++ b/llvm/test/MC/Hexagon/ro-cc9.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2> %t; FileCheck %s < %t
+# RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2> %t; FileCheck %s < %t
#
# Check that changes to a read-only register is caught.
diff --git a/llvm/test/MC/Hexagon/smallcore_dis.s b/llvm/test/MC/Hexagon/smallcore_dis.s
index 898b9008bfc4907..a5ea7663706e933 100644
--- a/llvm/test/MC/Hexagon/smallcore_dis.s
+++ b/llvm/test/MC/Hexagon/smallcore_dis.s
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv67t -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv67t -d - | FileCheck %s
.text
{
diff --git a/llvm/test/MC/Hexagon/solo-axok.s b/llvm/test/MC/Hexagon/solo-axok.s
index 2df5796e628dffc..a0d6e12fc9dc285 100644
--- a/llvm/test/MC/Hexagon/solo-axok.s
+++ b/llvm/test/MC/Hexagon/solo-axok.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=asm -mcpu=hexagonv55 %s 2>%t; FileCheck %s < %t
+# RUN: not llvm-mc -triple=hexagon -filetype=asm -mcpu=hexagonv55 %s 2>%t; FileCheck %s < %t
#
{
sp=asrh(r6)
diff --git a/llvm/test/MC/Hexagon/store-GPRel.s b/llvm/test/MC/Hexagon/store-GPRel.s
index 8e0fde54f9383c4..683e746985bbc13 100644
--- a/llvm/test/MC/Hexagon/store-GPRel.s
+++ b/llvm/test/MC/Hexagon/store-GPRel.s
@@ -1,4 +1,4 @@
-#RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d -r - | FileCheck %s
+#RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d -r - | FileCheck %s
# Check encoding bits for gp-rel stores.
diff --git a/llvm/test/MC/Hexagon/sysregs.s b/llvm/test/MC/Hexagon/sysregs.s
index 0a708a370830eff..3a11d6b5abe0704 100644
--- a/llvm/test/MC/Hexagon/sysregs.s
+++ b/llvm/test/MC/Hexagon/sysregs.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=asm %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=asm %s | FileCheck %s
#
r1:0=s75:74
diff --git a/llvm/test/MC/Hexagon/sysregs2.s b/llvm/test/MC/Hexagon/sysregs2.s
index 1017fabed7c8278..0447b6dcb0e7cf9 100644
--- a/llvm/test/MC/Hexagon/sysregs2.s
+++ b/llvm/test/MC/Hexagon/sysregs2.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
#
sgp1:0=r1:0
diff --git a/llvm/test/MC/Hexagon/sysregs3.s b/llvm/test/MC/Hexagon/sysregs3.s
index 03ff7d73b2a92fe..0409f150336d862 100644
--- a/llvm/test/MC/Hexagon/sysregs3.s
+++ b/llvm/test/MC/Hexagon/sysregs3.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
#
# Verify exceptions to the grouping rules for some registers.
diff --git a/llvm/test/MC/Hexagon/tied-ops.s b/llvm/test/MC/Hexagon/tied-ops.s
index a18e9e475c2c0c4..b71d5c6bcc73c37 100644
--- a/llvm/test/MC/Hexagon/tied-ops.s
+++ b/llvm/test/MC/Hexagon/tied-ops.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=asm %s 2> %t; FileCheck %s < %t
+# RUN: llvm-mc -triple=hexagon -filetype=asm %s 2> %t; FileCheck %s < %t
# Check that tied operands are caught
diff --git a/llvm/test/MC/Hexagon/tprel_noextend.s b/llvm/test/MC/Hexagon/tprel_noextend.s
index 0bc17c6ce576a1a..83c820369707c36 100644
--- a/llvm/test/MC/Hexagon/tprel_noextend.s
+++ b/llvm/test/MC/Hexagon/tprel_noextend.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
#
# CHECK-NOT: immext
diff --git a/llvm/test/MC/Hexagon/two-extenders.s b/llvm/test/MC/Hexagon/two-extenders.s
index 42f317b2e3f79d4..58e49b63cca4ff3 100644
--- a/llvm/test/MC/Hexagon/two-extenders.s
+++ b/llvm/test/MC/Hexagon/two-extenders.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
#
# In packets with two extensions assembler is not extending both instructions
diff --git a/llvm/test/MC/Hexagon/v60-misc.s b/llvm/test/MC/Hexagon/v60-misc.s
index c27377b7ce1e876..6fbe16b30ef76d3 100644
--- a/llvm/test/MC/Hexagon/v60-misc.s
+++ b/llvm/test/MC/Hexagon/v60-misc.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s | llvm-objdump --no-print-imm-hex --arch=hexagon --mcpu=hexagonv60 --mattr=+hvx -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s | llvm-objdump --no-print-imm-hex --triple=hexagon --mcpu=hexagonv60 --mattr=+hvx -d - | FileCheck %s
.L0:
diff --git a/llvm/test/MC/Hexagon/v62_all.s b/llvm/test/MC/Hexagon/v62_all.s
index b752ba2c2a82fb6..559aee35c44653d 100644
--- a/llvm/test/MC/Hexagon/v62_all.s
+++ b/llvm/test/MC/Hexagon/v62_all.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -mhvx %s | llvm-objdump --no-print-imm-hex --arch=hexagon --mcpu=hexagonv62 --mattr=+hvx -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv62 -filetype=obj -mhvx %s | llvm-objdump --no-print-imm-hex --triple=hexagon --mcpu=hexagonv62 --mattr=+hvx -d - | FileCheck %s
// V6_lvsplatb
// Vd32.b=vsplat(Rt32)
diff --git a/llvm/test/MC/Hexagon/v62_jumps.s b/llvm/test/MC/Hexagon/v62_jumps.s
index d1a1585619d231d..de498f25f2e95b8 100644
--- a/llvm/test/MC/Hexagon/v62_jumps.s
+++ b/llvm/test/MC/Hexagon/v62_jumps.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump --arch=hexagon --mcpu=hexagonv62 -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump --triple=hexagon --mcpu=hexagonv62 -d - | FileCheck %s
# verify compound is split into single instructions if needed
{
diff --git a/llvm/test/MC/Hexagon/v62a.s b/llvm/test/MC/Hexagon/v62a.s
index 4c6a25e26fde52b..968608c1c8b7234 100644
--- a/llvm/test/MC/Hexagon/v62a.s
+++ b/llvm/test/MC/Hexagon/v62a.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -o - %s | llvm-objdump --arch=hexagon --arch=hexagon --mcpu=hexagonv62 -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -o - %s | llvm-objdump --triple=hexagon --triple=hexagon --mcpu=hexagonv62 -d - | FileCheck %s
r31:30=vabsdiffb(r29:28, r27:26)
# CHECK: e8fadc1e { r31:30 = vabsdiffb(r29:28,r27:26)
diff --git a/llvm/test/MC/Hexagon/v62a_regs.s b/llvm/test/MC/Hexagon/v62a_regs.s
index 2d31b837afd4b10..334d8d4c00f817d 100644
--- a/llvm/test/MC/Hexagon/v62a_regs.s
+++ b/llvm/test/MC/Hexagon/v62a_regs.s
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-V62
-# RUN: not llvm-mc -arch=hexagon -mcpu=hexagonv60 -filetype=asm %s 2>%t; FileCheck -check-prefix=CHECK-NOV62 %s < %t
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-V62
+# RUN: not llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=asm %s 2>%t; FileCheck -check-prefix=CHECK-NOV62 %s < %t
#
# Assure that v62 added registers are understood
diff --git a/llvm/test/MC/Hexagon/v65_all.s b/llvm/test/MC/Hexagon/v65_all.s
index 28b20cc9bdc4e9e..da50b881453b0ac 100644
--- a/llvm/test/MC/Hexagon/v65_all.s
+++ b/llvm/test/MC/Hexagon/v65_all.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv65 --mattr=+hvx -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mv65 -mhvx -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv65 --mattr=+hvx -d - | FileCheck %s
// Warning: This file is auto generated by mktest.py. Do not edit!
// Created on: 2016-06-01 @ 17:33:01
diff --git a/llvm/test/MC/Hexagon/v66.s b/llvm/test/MC/Hexagon/v66.s
index c692a5953f7fe42..79f00c7d8fbe231 100644
--- a/llvm/test/MC/Hexagon/v66.s
+++ b/llvm/test/MC/Hexagon/v66.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv66 --mattr=+hvx -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv66 --mattr=+hvx -d - | FileCheck %s
# CHECK: 1d8362e4 { v4.w = vsatdw(v2.w,v3.w)
{
diff --git a/llvm/test/MC/Hexagon/v67.s b/llvm/test/MC/Hexagon/v67.s
index 6ca632ed37beadb..2a6727819d00c99 100644
--- a/llvm/test/MC/Hexagon/v67.s
+++ b/llvm/test/MC/Hexagon/v67.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mv67 -mattr=+hvx,+hvx-length128B -filetype=obj %s | llvm-objdump --mcpu=hexagonv67 --mattr=+hvx -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mv67 -mattr=+hvx,+hvx-length128B -filetype=obj %s | llvm-objdump --mcpu=hexagonv67 --mattr=+hvx -d - | FileCheck %s
# CHECK: 1a81e0e2 { v2.uw = vrotr(v0.uw,v1.uw) }
v2.uw=vrotr(v0.uw, v1.uw)
diff --git a/llvm/test/MC/Hexagon/v67_all.s b/llvm/test/MC/Hexagon/v67_all.s
index e7428a3a9a20f00..d2326c94cbbf349 100644
--- a/llvm/test/MC/Hexagon/v67_all.s
+++ b/llvm/test/MC/Hexagon/v67_all.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mv67 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv67 --mattr=+hvx -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mv67 -mhvx -filetype=obj %s | llvm-objdump --mcpu=hexagonv67 --mattr=+hvx -d - | FileCheck %s
# CHECK: { v3:0.w = vrmpyz(v0.b,r0.ub) }
V3:0.w=vrmpyz(v0.b,r0.ub)
diff --git a/llvm/test/MC/Hexagon/v67t_align.s b/llvm/test/MC/Hexagon/v67t_align.s
index 26aff1eee549d11..546429863fc44ef 100644
--- a/llvm/test/MC/Hexagon/v67t_align.s
+++ b/llvm/test/MC/Hexagon/v67t_align.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump -d - | FileCheck %s
{ r0=r0 }
.align 32
diff --git a/llvm/test/MC/Hexagon/v67t_arch.s b/llvm/test/MC/Hexagon/v67t_arch.s
index a65bfecde79fb7c..d9f91ddbbce00b0 100644
--- a/llvm/test/MC/Hexagon/v67t_arch.s
+++ b/llvm/test/MC/Hexagon/v67t_arch.s
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv67t -mhvx -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv67t -mhvx -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
r1=memw(r0)
{ r0=r0
diff --git a/llvm/test/MC/Hexagon/v67t_option.s b/llvm/test/MC/Hexagon/v67t_option.s
index f6a55e9c051669f..a8096781f1c5358 100644
--- a/llvm/test/MC/Hexagon/v67t_option.s
+++ b/llvm/test/MC/Hexagon/v67t_option.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mv67t -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mv67t -filetype=obj %s | llvm-objdump -d - | FileCheck %s
{ r0=r0 }
.align 32
{ r0=r0 }
diff --git a/llvm/test/MC/Hexagon/vgather-new.s b/llvm/test/MC/Hexagon/vgather-new.s
index 679aaefa72eaf92..83d5662fc13b1eb 100644
--- a/llvm/test/MC/Hexagon/vgather-new.s
+++ b/llvm/test/MC/Hexagon/vgather-new.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=hexagon -mcpu=hexagonv65 -mhvx -show-encoding %s -o - | FileCheck %s
+// RUN: llvm-mc -triple=hexagon -mcpu=hexagonv65 -mhvx -show-encoding %s -o - | FileCheck %s
// TypeCVI_FIRST was set incorrectly, causing vgather not to be considered
// a vector instruction. This resulted in an incorrect encoding of the vtmp.new
diff --git a/llvm/test/MC/Hexagon/vpred_defs.s b/llvm/test/MC/Hexagon/vpred_defs.s
index 92c15a3e575809a..6a05337c0740648 100644
--- a/llvm/test/MC/Hexagon/vpred_defs.s
+++ b/llvm/test/MC/Hexagon/vpred_defs.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mv65 -filetype=asm -mhvx %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mv65 -filetype=asm -mhvx %s | FileCheck %s
# CHECK-NOT: error: register `{{.+}}' modified more than once
diff --git a/llvm/test/MC/Hexagon/vscatter-slot.s b/llvm/test/MC/Hexagon/vscatter-slot.s
index 6c806de2f983b50..1a8ff319e0c3301 100644
--- a/llvm/test/MC/Hexagon/vscatter-slot.s
+++ b/llvm/test/MC/Hexagon/vscatter-slot.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mv65 -mhvx -filetype=asm < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mv65 -mhvx -filetype=asm < %s | FileCheck %s
# Test that a slot error is not reported for a packet with a load and a
# vscatter.
diff --git a/llvm/test/MC/Hexagon/vtmp_def.s b/llvm/test/MC/Hexagon/vtmp_def.s
index 26d257efadde897..8ed9ab8bccb45e6 100644
--- a/llvm/test/MC/Hexagon/vtmp_def.s
+++ b/llvm/test/MC/Hexagon/vtmp_def.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=hexagon -mv65 -mhvx -filetype=obj %s 2>&1 | FileCheck %s
# CHECK: register `VTMP' modified more than once
{ vtmp.h=vgather(r0, m0, v1:0.w).h
diff --git a/llvm/test/MC/Hexagon/z-instructions.s b/llvm/test/MC/Hexagon/z-instructions.s
index 6041ffa077cd968..f245094560922e7 100644
--- a/llvm/test/MC/Hexagon/z-instructions.s
+++ b/llvm/test/MC/Hexagon/z-instructions.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv66 --mattr=+hvx -d - | FileCheck --implicit-check-not='{' %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv66 --mattr=+hvx -d - | FileCheck --implicit-check-not='{' %s
# CHECK: 2d00c000 { z = vmem(r0++#0) }
z = vmem(r0++#0)
diff --git a/llvm/test/MC/Hexagon/zreg-post-inc.s b/llvm/test/MC/Hexagon/zreg-post-inc.s
index 696e18d9ea7b4a2..c491edc3cae8674 100644
--- a/llvm/test/MC/Hexagon/zreg-post-inc.s
+++ b/llvm/test/MC/Hexagon/zreg-post-inc.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=obj -mhvx -mcpu=hexagonv66 %s 2> %t; FileCheck --implicit-check-not=error: %s <%t
+# RUN: not llvm-mc -triple=hexagon -filetype=obj -mhvx -mcpu=hexagonv66 %s 2> %t; FileCheck --implicit-check-not=error: %s <%t
{
if (p0) memb(r14+#8)=r4.new
diff --git a/llvm/test/MC/Lanai/conditional_inst.s b/llvm/test/MC/Lanai/conditional_inst.s
index 58d9b634e4b613b..d167d1af00eb3af 100644
--- a/llvm/test/MC/Lanai/conditional_inst.s
+++ b/llvm/test/MC/Lanai/conditional_inst.s
@@ -1,4 +1,4 @@
-! RUN: llvm-mc -arch=lanai -show-encoding -show-inst < %s | FileCheck %s
+! RUN: llvm-mc -triple=lanai -show-encoding -show-inst < %s | FileCheck %s
.text
.align 4
diff --git a/llvm/test/MC/Lanai/memory.s b/llvm/test/MC/Lanai/memory.s
index d34f917c7405513..398cb8e123711d1 100644
--- a/llvm/test/MC/Lanai/memory.s
+++ b/llvm/test/MC/Lanai/memory.s
@@ -1,4 +1,4 @@
-! RUN: llvm-mc -arch=lanai -show-encoding -show-inst < %s | FileCheck %s
+! RUN: llvm-mc -triple=lanai -show-encoding -show-inst < %s | FileCheck %s
! Checking the machine instructions generated from ASM instructions for ALU
! operations.
diff --git a/llvm/test/MC/Lanai/v11.s b/llvm/test/MC/Lanai/v11.s
index 621c47de0235c44..ce7bb5395ce5d37 100644
--- a/llvm/test/MC/Lanai/v11.s
+++ b/llvm/test/MC/Lanai/v11.s
@@ -1,4 +1,4 @@
-! RUN: llvm-mc -arch=lanai -show-encoding %s | FileCheck %s
+! RUN: llvm-mc -triple=lanai -show-encoding %s | FileCheck %s
add %r17, 0, %r21
! CHECK: 0x0a,0xc4,0x00,0x00
diff --git a/llvm/test/MC/Mips/bopt-directive.s b/llvm/test/MC/Mips/bopt-directive.s
index 63e2a05281a83cd..41d9065b5b2f8f3 100644
--- a/llvm/test/MC/Mips/bopt-directive.s
+++ b/llvm/test/MC/Mips/bopt-directive.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=mips -mcpu=mips32 %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -triple=mips -mcpu=mips32 %s 2>&1 | FileCheck %s
# We don't support the bopt option in the integrated assembler. Given it's
# single pass nature, it would be quite difficult to implement currently.
diff --git a/llvm/test/MC/Mips/branch-pseudos-bad.s b/llvm/test/MC/Mips/branch-pseudos-bad.s
index f2fa74fdcee0a19..c23164d90461939 100644
--- a/llvm/test/MC/Mips/branch-pseudos-bad.s
+++ b/llvm/test/MC/Mips/branch-pseudos-bad.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32 2>&1 | FileCheck %s
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32 2>&1 | FileCheck %s
# Check for errors when using conditional branch pseudos after .set noat.
.set noat
diff --git a/llvm/test/MC/Mips/branch-pseudos.s b/llvm/test/MC/Mips/branch-pseudos.s
index 9c4abdbbfad01ea..9d277163cbf0b97 100644
--- a/llvm/test/MC/Mips/branch-pseudos.s
+++ b/llvm/test/MC/Mips/branch-pseudos.s
@@ -1,5 +1,5 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -show-encoding | FileCheck %s
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32 2>&1 | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32 -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32 2>&1 | \
# RUN: FileCheck %s --check-prefix=WARNING
.text
diff --git a/llvm/test/MC/Mips/cpload-bad.s b/llvm/test/MC/Mips/cpload-bad.s
index 803610af922ff6d..be234bcdf555a95 100644
--- a/llvm/test/MC/Mips/cpload-bad.s
+++ b/llvm/test/MC/Mips/cpload-bad.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r2 2>%t1
# RUN: FileCheck %s < %t1 -check-prefix=ASM
.text
diff --git a/llvm/test/MC/Mips/cprestore-bad.s b/llvm/test/MC/Mips/cprestore-bad.s
index cfd62a4ed988bb4..27faf3c4ab5030a 100644
--- a/llvm/test/MC/Mips/cprestore-bad.s
+++ b/llvm/test/MC/Mips/cprestore-bad.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32 2>%t1
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32 2>%t1
# RUN: FileCheck %s < %t1
.text
diff --git a/llvm/test/MC/Mips/crc/invalid.s b/llvm/test/MC/Mips/crc/invalid.s
index f8e0fba7da0ab66..cf1124e0783a8ef 100644
--- a/llvm/test/MC/Mips/crc/invalid.s
+++ b/llvm/test/MC/Mips/crc/invalid.s
@@ -1,8 +1,8 @@
# Instructions that are invalid.
#
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 -mattr=+crc 2>%t1
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r6 -mattr=+crc 2>%t1
# RUN: FileCheck %s < %t1
-# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 -mattr=+crc 2>%t1
+# RUN: not llvm-mc %s -triple=mips64 -mcpu=mips64r6 -mattr=+crc 2>%t1
# RUN: FileCheck %s < %t1
.set noat
diff --git a/llvm/test/MC/Mips/crc/module-nocrc.s b/llvm/test/MC/Mips/crc/module-nocrc.s
index 193ed360b57447d..b136f01bdcb0106 100644
--- a/llvm/test/MC/Mips/crc/module-nocrc.s
+++ b/llvm/test/MC/Mips/crc/module-nocrc.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -mattr=+crc | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r6 -mattr=+crc | \
# RUN: FileCheck %s -check-prefix=CHECK-ASM
#
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -filetype=obj -o - -mattr=+crc | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r6 -filetype=obj -o - -mattr=+crc | \
# RUN: llvm-readobj -A - | \
# RUN: FileCheck %s -check-prefix=CHECK-OBJ
diff --git a/llvm/test/MC/Mips/elf_basic.s b/llvm/test/MC/Mips/elf_basic.s
index be6e24823c62136..cd55201d1196ba3 100644
--- a/llvm/test/MC/Mips/elf_basic.s
+++ b/llvm/test/MC/Mips/elf_basic.s
@@ -3,9 +3,9 @@
// 32 bit little endian
// RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux %s -o - | llvm-readobj -h - | FileCheck -check-prefix=CHECK-LE32 %s
// 64 bit big endian
-// RUN: llvm-mc -filetype=obj -arch=mips64 -triple mips64-unknown-linux %s -o - | llvm-readobj -h - | FileCheck -check-prefix=CHECK-BE64 %s
+// RUN: llvm-mc -filetype=obj -triple=mips64 -triple mips64-unknown-linux %s -o - | llvm-readobj -h - | FileCheck -check-prefix=CHECK-BE64 %s
// 64 bit little endian
-// RUN: llvm-mc -filetype=obj -arch=mips64el -triple mips64el-unknown-linux %s -o - | llvm-readobj -h - | FileCheck -check-prefix=CHECK-LE64 %s
+// RUN: llvm-mc -filetype=obj -triple=mips64el -triple mips64el-unknown-linux %s -o - | llvm-readobj -h - | FileCheck -check-prefix=CHECK-LE64 %s
// Check that we produce 32 bit with each endian.
diff --git a/llvm/test/MC/Mips/end-directive.s b/llvm/test/MC/Mips/end-directive.s
index 6545acb1613e0ee..acc0f25a3b9763e 100644
--- a/llvm/test/MC/Mips/end-directive.s
+++ b/llvm/test/MC/Mips/end-directive.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=mips -mcpu=mips32 -filetype=obj %s -o - | \
+# RUN: llvm-mc -triple=mips -mcpu=mips32 -filetype=obj %s -o - | \
# RUN: llvm-readobj --symbols - | FileCheck %s
# Check that the assembler doesn't choke on .align between a symbol and the
diff --git a/llvm/test/MC/Mips/ginv/module-noginv.s b/llvm/test/MC/Mips/ginv/module-noginv.s
index 611d72c52d56100..577800329b5e1b6 100644
--- a/llvm/test/MC/Mips/ginv/module-noginv.s
+++ b/llvm/test/MC/Mips/ginv/module-noginv.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -mattr=+ginv | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r6 -mattr=+ginv | \
# RUN: FileCheck %s -check-prefix=CHECK-ASM
#
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -filetype=obj -o - -mattr=+ginv | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r6 -filetype=obj -o - -mattr=+ginv | \
# RUN: llvm-readobj -A - | \
# RUN: FileCheck %s -check-prefix=CHECK-OBJ
diff --git a/llvm/test/MC/Mips/insn-directive.s b/llvm/test/MC/Mips/insn-directive.s
index 05e37ffb67cc8a4..75819ae2f51af8f 100644
--- a/llvm/test/MC/Mips/insn-directive.s
+++ b/llvm/test/MC/Mips/insn-directive.s
@@ -1,6 +1,6 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32 | FileCheck %s --check-prefix=ASM
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32 | FileCheck %s --check-prefix=ASM
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32 -filetype=obj -o - | \
# RUN: llvm-readobj --symbols - | FileCheck %s --check-prefix=OBJ
.set micromips
diff --git a/llvm/test/MC/Mips/macro-aliases.s b/llvm/test/MC/Mips/macro-aliases.s
index 85677ee4631f2c2..6488432372139f4 100644
--- a/llvm/test/MC/Mips/macro-aliases.s
+++ b/llvm/test/MC/Mips/macro-aliases.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=mips -mcpu=mips32r2 %s -show-inst | FileCheck %s
+# RUN: llvm-mc -triple=mips -mcpu=mips32r2 %s -show-inst | FileCheck %s
# Test that subu accepts constant operands and inverts them when
# rendering the operand.
diff --git a/llvm/test/MC/Mips/macro-bcc-imm-bad.s b/llvm/test/MC/Mips/macro-bcc-imm-bad.s
index bcf08bdc34d5d47..c56666dbeba030b 100644
--- a/llvm/test/MC/Mips/macro-bcc-imm-bad.s
+++ b/llvm/test/MC/Mips/macro-bcc-imm-bad.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=ALL
.text
diff --git a/llvm/test/MC/Mips/macro-bcc-imm.s b/llvm/test/MC/Mips/macro-bcc-imm.s
index fdee6ec3670e666..afc3e59b9379506 100644
--- a/llvm/test/MC/Mips/macro-bcc-imm.s
+++ b/llvm/test/MC/Mips/macro-bcc-imm.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -show-encoding 2>&1 | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -show-encoding 2>&1 | \
# RUN: FileCheck %s --check-prefix=ALL
.text
diff --git a/llvm/test/MC/Mips/macro-ddiv-bad.s b/llvm/test/MC/Mips/macro-ddiv-bad.s
index 1abcab66142f32c..d8713d9948859bd 100644
--- a/llvm/test/MC/Mips/macro-ddiv-bad.s
+++ b/llvm/test/MC/Mips/macro-ddiv-bad.s
@@ -1,10 +1,10 @@
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
-# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips64 -mcpu=mips64r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \
+# RUN: llvm-mc %s -triple=mips64 -mcpu=mips64r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=MIPS64-NOT-R6
.text
diff --git a/llvm/test/MC/Mips/macro-ddivu-bad.s b/llvm/test/MC/Mips/macro-ddivu-bad.s
index 1abcab66142f32c..d8713d9948859bd 100644
--- a/llvm/test/MC/Mips/macro-ddivu-bad.s
+++ b/llvm/test/MC/Mips/macro-ddivu-bad.s
@@ -1,10 +1,10 @@
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
-# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips64 -mcpu=mips64r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \
+# RUN: llvm-mc %s -triple=mips64 -mcpu=mips64r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=MIPS64-NOT-R6
.text
diff --git a/llvm/test/MC/Mips/macro-div-bad.s b/llvm/test/MC/Mips/macro-div-bad.s
index 4d93a1a9a69d39f..154316a4e9631fe 100644
--- a/llvm/test/MC/Mips/macro-div-bad.s
+++ b/llvm/test/MC/Mips/macro-div-bad.s
@@ -1,10 +1,10 @@
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6
-# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips64 -mcpu=mips64r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \
+# RUN: llvm-mc %s -triple=mips64 -mcpu=mips64r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6
.text
diff --git a/llvm/test/MC/Mips/macro-divu-bad.s b/llvm/test/MC/Mips/macro-divu-bad.s
index b5b492ec682807c..59289528d2527da 100644
--- a/llvm/test/MC/Mips/macro-divu-bad.s
+++ b/llvm/test/MC/Mips/macro-divu-bad.s
@@ -1,10 +1,10 @@
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6
-# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips64 -mcpu=mips64r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \
+# RUN: llvm-mc %s -triple=mips64 -mcpu=mips64r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6
.text
diff --git a/llvm/test/MC/Mips/macro-dla-bad.s b/llvm/test/MC/Mips/macro-dla-bad.s
index cd377f4557ca637..7dc64555a88f09e 100644
--- a/llvm/test/MC/Mips/macro-dla-bad.s
+++ b/llvm/test/MC/Mips/macro-dla-bad.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips3 -target-abi n64 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips64 -mcpu=mips3 -target-abi n64 2>&1 | \
# RUN: FileCheck %s
.text
diff --git a/llvm/test/MC/Mips/macro-la-bad.s b/llvm/test/MC/Mips/macro-la-bad.s
index 70b8facc2db954f..7728785041ffc9e 100644
--- a/llvm/test/MC/Mips/macro-la-bad.s
+++ b/llvm/test/MC/Mips/macro-la-bad.s
@@ -1,8 +1,8 @@
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r2 2>%t1
# RUN: FileCheck %s < %t1 --check-prefix=O32
-# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips64 -mcpu=mips64 -target-abi n32 2>&1 | \
# RUN: FileCheck %s --check-prefix=N32
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 | \
+# RUN: llvm-mc %s -triple=mips64 -mcpu=mips64 -target-abi n64 2>&1 | \
# RUN: FileCheck %s --check-prefix=N64
.text
diff --git a/llvm/test/MC/Mips/macro-li-bad.s b/llvm/test/MC/Mips/macro-li-bad.s
index 29eedce713ab1bb..b1dfa4228806199 100644
--- a/llvm/test/MC/Mips/macro-li-bad.s
+++ b/llvm/test/MC/Mips/macro-li-bad.s
@@ -1,8 +1,8 @@
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r2 2>%t1
# RUN: FileCheck %s < %t1 --check-prefix=32-BIT
-# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips64 -mcpu=mips64 -target-abi n32 2>&1 | \
# RUN: FileCheck %s --check-prefix=64-BIT
-# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips64 -mcpu=mips64 -target-abi n64 2>&1 | \
# RUN: FileCheck %s --check-prefix=64-BIT
.text
diff --git a/llvm/test/MC/Mips/macro-seq.s b/llvm/test/MC/Mips/macro-seq.s
index 814f198a07bd83c..404247edbecc783 100644
--- a/llvm/test/MC/Mips/macro-seq.s
+++ b/llvm/test/MC/Mips/macro-seq.s
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=mips -mcpu=mips1 < %s | FileCheck --check-prefixes=ALL,MIPS32 %s
-# RUN: llvm-mc -arch=mips -mcpu=mips64 < %s | FileCheck --check-prefixes=ALL,MIPS64 %s
+# RUN: llvm-mc -triple=mips -mcpu=mips1 < %s | FileCheck --check-prefixes=ALL,MIPS32 %s
+# RUN: llvm-mc -triple=mips -mcpu=mips64 < %s | FileCheck --check-prefixes=ALL,MIPS64 %s
# ALL: .text
seq $2, $11, $0
diff --git a/llvm/test/MC/Mips/macro-sge.s b/llvm/test/MC/Mips/macro-sge.s
index d8189e55425d2cf..97bf1531a3ce1a9 100644
--- a/llvm/test/MC/Mips/macro-sge.s
+++ b/llvm/test/MC/Mips/macro-sge.s
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips1 < %s | FileCheck %s
-# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s | FileCheck %s
+# RUN: llvm-mc -triple=mips -show-encoding -mcpu=mips1 < %s | FileCheck %s
+# RUN: llvm-mc -triple=mips -show-encoding -mcpu=mips64 < %s | FileCheck %s
sge $4, $5
# CHECK: slt $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2a]
diff --git a/llvm/test/MC/Mips/macro-sge64.s b/llvm/test/MC/Mips/macro-sge64.s
index 7875baf01288eac..e7c210c77714faa 100644
--- a/llvm/test/MC/Mips/macro-sge64.s
+++ b/llvm/test/MC/Mips/macro-sge64.s
@@ -1,6 +1,6 @@
-# RUN: not llvm-mc -arch=mips -mcpu=mips1 < %s 2>&1 \
+# RUN: not llvm-mc -triple=mips -mcpu=mips1 < %s 2>&1 \
# RUN: | FileCheck --check-prefix=MIPS32 %s
-# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s \
+# RUN: llvm-mc -triple=mips -show-encoding -mcpu=mips64 < %s \
# RUN: | FileCheck --check-prefix=MIPS64 %s
sge $4, $5, 0x100000000
diff --git a/llvm/test/MC/Mips/macro-sgt.s b/llvm/test/MC/Mips/macro-sgt.s
index e49a02daaf0b23f..0baecc74a88415b 100644
--- a/llvm/test/MC/Mips/macro-sgt.s
+++ b/llvm/test/MC/Mips/macro-sgt.s
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips1 < %s | FileCheck %s
-# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s | FileCheck %s
+# RUN: llvm-mc -triple=mips -show-encoding -mcpu=mips1 < %s | FileCheck %s
+# RUN: llvm-mc -triple=mips -show-encoding -mcpu=mips64 < %s | FileCheck %s
sgt $4, $5
# CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
diff --git a/llvm/test/MC/Mips/macro-sgt64.s b/llvm/test/MC/Mips/macro-sgt64.s
index e878561b846053c..6091ce9f565c2db 100644
--- a/llvm/test/MC/Mips/macro-sgt64.s
+++ b/llvm/test/MC/Mips/macro-sgt64.s
@@ -1,6 +1,6 @@
-# RUN: not llvm-mc -arch=mips -mcpu=mips1 < %s 2>&1 \
+# RUN: not llvm-mc -triple=mips -mcpu=mips1 < %s 2>&1 \
# RUN: | FileCheck --check-prefix=MIPS32 %s
-# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s \
+# RUN: llvm-mc -triple=mips -show-encoding -mcpu=mips64 < %s \
# RUN: | FileCheck --check-prefix=MIPS64 %s
sgt $4, $5, 0x100000000
diff --git a/llvm/test/MC/Mips/macro-sle.s b/llvm/test/MC/Mips/macro-sle.s
index 6d93ce5b820b2e4..a7e3d56b3a8ca6c 100644
--- a/llvm/test/MC/Mips/macro-sle.s
+++ b/llvm/test/MC/Mips/macro-sle.s
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips1 < %s | FileCheck %s
-# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s | FileCheck %s
+# RUN: llvm-mc -triple=mips -show-encoding -mcpu=mips1 < %s | FileCheck %s
+# RUN: llvm-mc -triple=mips -show-encoding -mcpu=mips64 < %s | FileCheck %s
sle $4, $5
# CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
diff --git a/llvm/test/MC/Mips/macro-sle64.s b/llvm/test/MC/Mips/macro-sle64.s
index 62ad7c81f9dda5f..91f137091b01225 100644
--- a/llvm/test/MC/Mips/macro-sle64.s
+++ b/llvm/test/MC/Mips/macro-sle64.s
@@ -1,6 +1,6 @@
-# RUN: not llvm-mc -arch=mips -mcpu=mips1 < %s 2>&1 \
+# RUN: not llvm-mc -triple=mips -mcpu=mips1 < %s 2>&1 \
# RUN: | FileCheck --check-prefix=MIPS32 %s
-# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s \
+# RUN: llvm-mc -triple=mips -show-encoding -mcpu=mips64 < %s \
# RUN: | FileCheck --check-prefix=MIPS64 %s
sle $4, $5, 0x100000000
diff --git a/llvm/test/MC/Mips/macro-sne.s b/llvm/test/MC/Mips/macro-sne.s
index 497e1d604c41af1..89e50e3618f12e4 100644
--- a/llvm/test/MC/Mips/macro-sne.s
+++ b/llvm/test/MC/Mips/macro-sne.s
@@ -1,6 +1,6 @@
-# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips1 < %s \
+# RUN: llvm-mc -triple=mips -show-encoding -mcpu=mips1 < %s \
# RUN: | FileCheck --check-prefixes=ALL,MIPS32 %s
-# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s \
+# RUN: llvm-mc -triple=mips -show-encoding -mcpu=mips64 < %s \
# RUN: | FileCheck --check-prefixes=ALL,MIPS64 %s
sne $4, $5, $6
diff --git a/llvm/test/MC/Mips/memory-offsets.s b/llvm/test/MC/Mips/memory-offsets.s
index 7fd1e7e503cd31c..895d8c6ba5fcfba 100644
--- a/llvm/test/MC/Mips/memory-offsets.s
+++ b/llvm/test/MC/Mips/memory-offsets.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=mips -mcpu=mips32 -show-encoding %s | FileCheck %s
+# RUN: llvm-mc -triple=mips -mcpu=mips32 -show-encoding %s | FileCheck %s
# Check that parseMemOperand handles expressions such as <int>, (<int>),
# <expr>, <expr> op <expr>, (<expr>) op (<expr>).
diff --git a/llvm/test/MC/Mips/micromips-bad-branches.s b/llvm/test/MC/Mips/micromips-bad-branches.s
index f64cd9f9e5bdb10..caded616adec380 100644
--- a/llvm/test/MC/Mips/micromips-bad-branches.s
+++ b/llvm/test/MC/Mips/micromips-bad-branches.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+msa -arch=mips -mattr=+micromips 2>&1 | FileCheck %s
+# RUN: not llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+msa -triple=mips -mattr=+micromips 2>&1 | FileCheck %s
#
# CHECK: error: branch to misaligned address
# CHECK: b -65535
diff --git a/llvm/test/MC/Mips/micromips-diagnostic-fixup.s b/llvm/test/MC/Mips/micromips-diagnostic-fixup.s
index 4a94f9a3cd51898..aac076f1343ad1a 100644
--- a/llvm/test/MC/Mips/micromips-diagnostic-fixup.s
+++ b/llvm/test/MC/Mips/micromips-diagnostic-fixup.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -arch=mips -mattr=+micromips 2>&1 -filetype=obj | FileCheck %s
+# RUN: not llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -triple=mips -mattr=+micromips 2>&1 -filetype=obj | FileCheck %s
# Two instructions, to check that this is not a fatal error
# CHECK: error: out of range PC16 fixup
diff --git a/llvm/test/MC/Mips/micromips-pc16-fixup.s b/llvm/test/MC/Mips/micromips-pc16-fixup.s
index 7725b4e6f0eb182..ce97880bdfe8468 100644
--- a/llvm/test/MC/Mips/micromips-pc16-fixup.s
+++ b/llvm/test/MC/Mips/micromips-pc16-fixup.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 -arch=mips -mattr=+micromips 2>&1 -filetype=obj | FileCheck %s
+# RUN: llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 -triple=mips -mattr=+micromips 2>&1 -filetype=obj | FileCheck %s
#
# CHECK-NOT: error: out of range PC16 fixup
diff --git a/llvm/test/MC/Mips/micromips64-unsupported.s b/llvm/test/MC/Mips/micromips64-unsupported.s
index bc38cfb41f74ae2..5d67f82cd6a76c0 100644
--- a/llvm/test/MC/Mips/micromips64-unsupported.s
+++ b/llvm/test/MC/Mips/micromips64-unsupported.s
@@ -1,8 +1,8 @@
-# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 -target-abi n64 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64R6
-# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 -target-abi n32 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64R6
+# RUN: not llvm-mc %s -triple=mips64 -mcpu=mips64r6 -target-abi n64 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64R6
+# RUN: not llvm-mc %s -triple=mips64 -mcpu=mips64r6 -target-abi n32 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64R6
-# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64
-# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64
+# RUN: not llvm-mc %s -triple=mips64 -mcpu=mips64 -target-abi n64 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64
+# RUN: not llvm-mc %s -triple=mips64 -mcpu=mips64 -target-abi n32 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64
# 64R6: microMIPS64R6 is not supported
# 64: microMIPS64 is not supported
diff --git a/llvm/test/MC/Mips/mips-bad-branches.s b/llvm/test/MC/Mips/mips-bad-branches.s
index 321b3c45f873a74..d713792eff13a64 100644
--- a/llvm/test/MC/Mips/mips-bad-branches.s
+++ b/llvm/test/MC/Mips/mips-bad-branches.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -arch=mips 2>&1 | FileCheck %s
+# RUN: not llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -triple=mips 2>&1 | FileCheck %s
#
# CHECK: error: branch to misaligned address
# CHECK: b -131069
diff --git a/llvm/test/MC/Mips/mips-data-directives.s b/llvm/test/MC/Mips/mips-data-directives.s
index e794aa06b0b4a0c..217f3f6f4729c16 100644
--- a/llvm/test/MC/Mips/mips-data-directives.s
+++ b/llvm/test/MC/Mips/mips-data-directives.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 | \
# RUN: FileCheck %s -check-prefix=CHECK-ASM
#
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -filetype=obj -o - | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -filetype=obj -o - | \
# RUN: llvm-readobj --sections --section-data --section-relocations - | \
# RUN: FileCheck %s -check-prefix=CHECK-OBJ
diff --git a/llvm/test/MC/Mips/mips-diagnostic-fixup.s b/llvm/test/MC/Mips/mips-diagnostic-fixup.s
index 7bfe0d6263db404..16d4d89b5d6894b 100644
--- a/llvm/test/MC/Mips/mips-diagnostic-fixup.s
+++ b/llvm/test/MC/Mips/mips-diagnostic-fixup.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -arch=mips 2>&1 -filetype=obj | FileCheck %s
+# RUN: not llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -triple=mips 2>&1 -filetype=obj | FileCheck %s
# Two instructions, to check that this is not a fatal error
# CHECK: error: out of range PC16 fixup
diff --git a/llvm/test/MC/Mips/mips-expansions-bad.s b/llvm/test/MC/Mips/mips-expansions-bad.s
index 9c1b07a769a83fd..1f1b8c7ce6e2312 100644
--- a/llvm/test/MC/Mips/mips-expansions-bad.s
+++ b/llvm/test/MC/Mips/mips-expansions-bad.s
@@ -1,8 +1,8 @@
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r2 2>%t1
# RUN: FileCheck %s < %t1 --check-prefix=32-BIT
-# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips64 -mcpu=mips64 -target-abi n32 2>&1 | \
# RUN: FileCheck %s --check-prefix=64-BIT
-# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 | \
+# RUN: not llvm-mc %s -triple=mips64 -mcpu=mips64 -target-abi n64 2>&1 | \
# RUN: FileCheck %s --check-prefix=64-BIT
.text
diff --git a/llvm/test/MC/Mips/mips-pc16-fixup.s b/llvm/test/MC/Mips/mips-pc16-fixup.s
index ae4c915d97d502c..064724719688bff 100644
--- a/llvm/test/MC/Mips/mips-pc16-fixup.s
+++ b/llvm/test/MC/Mips/mips-pc16-fixup.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 -arch=mips 2>&1 -filetype=obj | FileCheck %s
+# RUN: llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 -triple=mips 2>&1 -filetype=obj | FileCheck %s
#
# CHECK-NOT: error: out of range PC16 fixup
diff --git a/llvm/test/MC/Mips/mips-pdr-bad.s b/llvm/test/MC/Mips/mips-pdr-bad.s
index 40c6ba2a1f2e1a6..1e15a8893db2fcb 100644
--- a/llvm/test/MC/Mips/mips-pdr-bad.s
+++ b/llvm/test/MC/Mips/mips-pdr-bad.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r2 2>%t1
# RUN: FileCheck %s < %t1 -check-prefix=ASM
.text
diff --git a/llvm/test/MC/Mips/mips-pdr.s b/llvm/test/MC/Mips/mips-pdr.s
index a6a9646573a8d14..c66cbfa0a604857 100644
--- a/llvm/test/MC/Mips/mips-pdr.s
+++ b/llvm/test/MC/Mips/mips-pdr.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -filetype=asm | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -filetype=asm | \
# RUN: FileCheck %s -check-prefix=ASMOUT
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -filetype=obj -o - | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -filetype=obj -o - | \
# RUN: llvm-readobj -S --section-data -r - | \
# RUN: FileCheck %s -check-prefix=OBJOUT
diff --git a/llvm/test/MC/Mips/mips-reginfo-fp32.s b/llvm/test/MC/Mips/mips-reginfo-fp32.s
index f37ad7c96b59688..8328268facadbf3 100644
--- a/llvm/test/MC/Mips/mips-reginfo-fp32.s
+++ b/llvm/test/MC/Mips/mips-reginfo-fp32.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -filetype=obj -o - | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -filetype=obj -o - | \
# RUN: llvm-readobj -S --section-data - | \
# RUN: FileCheck %s
diff --git a/llvm/test/MC/Mips/mips-reginfo-fp64.s b/llvm/test/MC/Mips/mips-reginfo-fp64.s
index b7dee963082a63b..0a6dc65601348fb 100644
--- a/llvm/test/MC/Mips/mips-reginfo-fp64.s
+++ b/llvm/test/MC/Mips/mips-reginfo-fp64.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa,+fp64 -filetype=obj -o - | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa,+fp64 -filetype=obj -o - | \
# RUN: llvm-readobj -S --section-data - | \
# RUN: FileCheck %s -check-prefix=ELF32
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n32 -filetype=obj -o - | \
+# RUN: llvm-mc %s -triple=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n32 -filetype=obj -o - | \
# RUN: llvm-readobj -S --section-data - | \
# RUN: FileCheck %s -check-prefix=ELF32
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n64 -filetype=obj -o - | \
+# RUN: llvm-mc %s -triple=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n64 -filetype=obj -o - | \
# RUN: llvm-readobj -S --section-data - | \
# RUN: FileCheck %s -check-prefix=ELF64
diff --git a/llvm/test/MC/Mips/mips16/invalid.s b/llvm/test/MC/Mips/mips16/invalid.s
index 4ed3c91433315a2..ad28e40f7677fbf 100644
--- a/llvm/test/MC/Mips/mips16/invalid.s
+++ b/llvm/test/MC/Mips/mips16/invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mips16 < %s 2> %t
+# RUN: not llvm-mc -triple=mips -mcpu=mips32r2 -mattr=+mips16 < %s 2> %t
# RUN: FileCheck %s < %t
# Instructions which are invalid.
diff --git a/llvm/test/MC/Mips/mips16/valid.s b/llvm/test/MC/Mips/mips16/valid.s
index 887ff19c908eaec..942bfd1a00faba5 100644
--- a/llvm/test/MC/Mips/mips16/valid.s
+++ b/llvm/test/MC/Mips/mips16/valid.s
@@ -1,3 +1,3 @@
-# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mips16 -show-encoding -show-inst < %s
+# RUN: llvm-mc -triple=mips -mcpu=mips32r2 -mattr=+mips16 -show-encoding -show-inst < %s
nop
diff --git a/llvm/test/MC/Mips/mips32r2/valid-fp64.s b/llvm/test/MC/Mips/mips32r2/valid-fp64.s
index 56b5ab85fab0603..fa2dbd406d63dcd 100644
--- a/llvm/test/MC/Mips/mips32r2/valid-fp64.s
+++ b/llvm/test/MC/Mips/mips32r2/valid-fp64.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+fp64 -show-encoding -show-inst %s | \
+# RUN: llvm-mc -triple=mips -mcpu=mips32r2 -mattr=+fp64 -show-encoding -show-inst %s | \
# RUN: FileCheck %s
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
diff --git a/llvm/test/MC/Mips/mips32r3/valid-fp64.s b/llvm/test/MC/Mips/mips32r3/valid-fp64.s
index c228ff645d8c9ca..4f725a49a5600a4 100644
--- a/llvm/test/MC/Mips/mips32r3/valid-fp64.s
+++ b/llvm/test/MC/Mips/mips32r3/valid-fp64.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=mips -mcpu=mips32r3 -mattr=+fp64 -show-encoding -show-inst %s | \
+# RUN: llvm-mc -triple=mips -mcpu=mips32r3 -mattr=+fp64 -show-encoding -show-inst %s | \
# RUN: FileCheck %s
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
diff --git a/llvm/test/MC/Mips/mips32r5/valid-fp64.s b/llvm/test/MC/Mips/mips32r5/valid-fp64.s
index a7d4a01ec106dbb..4d3ea11e57e1165 100644
--- a/llvm/test/MC/Mips/mips32r5/valid-fp64.s
+++ b/llvm/test/MC/Mips/mips32r5/valid-fp64.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=mips -mcpu=mips32r5 -mattr=+fp64 -show-encoding -show-inst %s | \
+# RUN: llvm-mc -triple=mips -mcpu=mips32r5 -mattr=+fp64 -show-encoding -show-inst %s | \
# RUN: FileCheck %s
abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
diff --git a/llvm/test/MC/Mips/mips64/abiflags.s b/llvm/test/MC/Mips/mips64/abiflags.s
index bccfa775ddb0ec7..e2703f896cd7a40 100644
--- a/llvm/test/MC/Mips/mips64/abiflags.s
+++ b/llvm/test/MC/Mips/mips64/abiflags.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips64 -target-abi n64 | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips64 -target-abi n64 | \
# RUN: FileCheck %s -check-prefix=CHECK-ASM
#
-# RUN: llvm-mc %s -arch=mips -mcpu=mips64 -target-abi n64 -filetype=obj -o - | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips64 -target-abi n64 -filetype=obj -o - | \
# RUN: llvm-readobj --sections --section-data --section-relocations - | \
# RUN: FileCheck %s -check-prefix=CHECK-OBJ
diff --git a/llvm/test/MC/Mips/mips64extins.s b/llvm/test/MC/Mips/mips64extins.s
index 442ea206610a2d7..b54ac275cd46699 100644
--- a/llvm/test/MC/Mips/mips64extins.s
+++ b/llvm/test/MC/Mips/mips64extins.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc -arch=mips64el -filetype=obj -mcpu=mips64r2 -target-abi=n64 %s -o - \
+# RUN: llvm-mc -triple=mips64el -filetype=obj -mcpu=mips64r2 -target-abi=n64 %s -o - \
# RUN: | llvm-objdump --no-print-imm-hex -d - | FileCheck --check-prefix=OBJ %s
-# RUN: llvm-mc -arch=mips64el -mcpu=mips64r2 -target-abi=n64 %s -o - \
+# RUN: llvm-mc -triple=mips64el -mcpu=mips64r2 -target-abi=n64 %s -o - \
# RUN: | FileCheck --check-prefix=ASM %s
dext $2, $4, 5, 10 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
diff --git a/llvm/test/MC/Mips/mips64r2/abiflags.s b/llvm/test/MC/Mips/mips64r2/abiflags.s
index 799411d5afe8e64..f4e2a8625d962bd 100644
--- a/llvm/test/MC/Mips/mips64r2/abiflags.s
+++ b/llvm/test/MC/Mips/mips64r2/abiflags.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips64r2 -target-abi n64 | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips64r2 -target-abi n64 | \
# RUN: FileCheck %s -check-prefix=CHECK-ASM
#
-# RUN: llvm-mc %s -arch=mips -mcpu=mips64r2 -target-abi n64 -filetype=obj -o - | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips64r2 -target-abi n64 -filetype=obj -o - | \
# RUN: llvm-readobj --sections --section-data --section-relocations - | \
# RUN: FileCheck %s -check-prefix=CHECK-OBJ
diff --git a/llvm/test/MC/Mips/mips64r3/abiflags.s b/llvm/test/MC/Mips/mips64r3/abiflags.s
index 71da8e970bedac7..29822fa0b0976db 100644
--- a/llvm/test/MC/Mips/mips64r3/abiflags.s
+++ b/llvm/test/MC/Mips/mips64r3/abiflags.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips64r3 -target-abi n64 | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips64r3 -target-abi n64 | \
# RUN: FileCheck %s -check-prefix=CHECK-ASM
#
-# RUN: llvm-mc %s -arch=mips -mcpu=mips64r3 -target-abi n64 -filetype=obj -o - | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips64r3 -target-abi n64 -filetype=obj -o - | \
# RUN: llvm-readobj --sections --section-data --section-relocations - | \
# RUN: FileCheck %s -check-prefix=CHECK-OBJ
diff --git a/llvm/test/MC/Mips/mips64r5/abiflags.s b/llvm/test/MC/Mips/mips64r5/abiflags.s
index 71253eeb4135c3c..4cd10a9634d4aa3 100644
--- a/llvm/test/MC/Mips/mips64r5/abiflags.s
+++ b/llvm/test/MC/Mips/mips64r5/abiflags.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips64r5 -target-abi n64 | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips64r5 -target-abi n64 | \
# RUN: FileCheck %s -check-prefix=CHECK-ASM
#
-# RUN: llvm-mc %s -arch=mips -mcpu=mips64r5 -target-abi n64 -filetype=obj -o - | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips64r5 -target-abi n64 -filetype=obj -o - | \
# RUN: llvm-readobj --sections --section-data --section-relocations - | \
# RUN: FileCheck %s -check-prefix=CHECK-OBJ
diff --git a/llvm/test/MC/Mips/module-softfloat.s b/llvm/test/MC/Mips/module-softfloat.s
index 94ab7be63dccb16..c728b8030135958 100644
--- a/llvm/test/MC/Mips/module-softfloat.s
+++ b/llvm/test/MC/Mips/module-softfloat.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32 | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32 | \
# RUN: FileCheck %s -check-prefix=CHECK-ASM
#
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32 -filetype=obj -o - | \
# RUN: llvm-readobj -A - | \
# RUN: FileCheck %s -check-prefix=CHECK-OBJ
diff --git a/llvm/test/MC/Mips/msa/set-msa-directive-bad.s b/llvm/test/MC/Mips/msa/set-msa-directive-bad.s
index 02cb9a67e789317..1f6bba5e62f524f 100644
--- a/llvm/test/MC/Mips/msa/set-msa-directive-bad.s
+++ b/llvm/test/MC/Mips/msa/set-msa-directive-bad.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r2 2>%t1
# RUN: FileCheck %s < %t1
.set nomsa
diff --git a/llvm/test/MC/Mips/msa/set-msa-directive.s b/llvm/test/MC/Mips/msa/set-msa-directive.s
index 461ddba1945a180..cebe528fd3c5b5f 100644
--- a/llvm/test/MC/Mips/msa/set-msa-directive.s
+++ b/llvm/test/MC/Mips/msa/set-msa-directive.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 | FileCheck %s
# CHECK: .set msa
# CHECK: addvi.b $w14, $w12, 14
diff --git a/llvm/test/MC/Mips/msa/test_2r.s b/llvm/test/MC/Mips/msa/test_2r.s
index 01bea645e1a5489..3792be681613169 100644
--- a/llvm/test/MC/Mips/msa/test_2r.s
+++ b/llvm/test/MC/Mips/msa/test_2r.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: fill.b $w30, $9 # encoding: [0x7b,0x00,0x4f,0x9e]
# CHECK: fill.h $w31, $23 # encoding: [0x7b,0x01,0xbf,0xde]
diff --git a/llvm/test/MC/Mips/msa/test_2r_msa64.s b/llvm/test/MC/Mips/msa/test_2r_msa64.s
index f6e35c461469f02..391ca89abd526ee 100644
--- a/llvm/test/MC/Mips/msa/test_2r_msa64.s
+++ b/llvm/test/MC/Mips/msa/test_2r_msa64.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: fill.d $w27, $9 # encoding: [0x7b,0x03,0x4e,0xde]
diff --git a/llvm/test/MC/Mips/msa/test_2rf.s b/llvm/test/MC/Mips/msa/test_2rf.s
index 5d41545c3376ac2..a7932bb9067d7cb 100644
--- a/llvm/test/MC/Mips/msa/test_2rf.s
+++ b/llvm/test/MC/Mips/msa/test_2rf.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: fclass.w $w26, $w12 # encoding: [0x7b,0x20,0x66,0x9e]
# CHECK: fclass.d $w24, $w17 # encoding: [0x7b,0x21,0x8e,0x1e]
diff --git a/llvm/test/MC/Mips/msa/test_3r.s b/llvm/test/MC/Mips/msa/test_3r.s
index df2e1e112606e86..879d29a07ae12a6 100644
--- a/llvm/test/MC/Mips/msa/test_3r.s
+++ b/llvm/test/MC/Mips/msa/test_3r.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: add_a.b $w26, $w9, $w4 # encoding: [0x78,0x04,0x4e,0x90]
# CHECK: add_a.h $w23, $w27, $w31 # encoding: [0x78,0x3f,0xdd,0xd0]
diff --git a/llvm/test/MC/Mips/msa/test_3rf.s b/llvm/test/MC/Mips/msa/test_3rf.s
index c5896d78c5b9fb1..c5c8b18c6025f3c 100644
--- a/llvm/test/MC/Mips/msa/test_3rf.s
+++ b/llvm/test/MC/Mips/msa/test_3rf.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: fadd.w $w28, $w19, $w28 # encoding: [0x78,0x1c,0x9f,0x1b]
# CHECK: fadd.d $w13, $w2, $w29 # encoding: [0x78,0x3d,0x13,0x5b]
diff --git a/llvm/test/MC/Mips/msa/test_bit.s b/llvm/test/MC/Mips/msa/test_bit.s
index 85ebe54fea47da3..52b2fbae120fce9 100644
--- a/llvm/test/MC/Mips/msa/test_bit.s
+++ b/llvm/test/MC/Mips/msa/test_bit.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: bclri.b $w21, $w30, 2 # encoding: [0x79,0xf2,0xf5,0x49]
# CHECK: bclri.h $w24, $w21, 0 # encoding: [0x79,0xe0,0xae,0x09]
diff --git a/llvm/test/MC/Mips/msa/test_cbranch.s b/llvm/test/MC/Mips/msa/test_cbranch.s
index aa6779b1b46efb3..c7486b92125cb3c 100644
--- a/llvm/test/MC/Mips/msa/test_cbranch.s
+++ b/llvm/test/MC/Mips/msa/test_cbranch.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
#CHECK: bnz.b $w0, 4 # encoding: [0x47,0x80,0x00,0x01]
#CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/Mips/msa/test_ctrlregs.s b/llvm/test/MC/Mips/msa/test_ctrlregs.s
index 3329072b310d103..d0d33c035618d9b 100644
--- a/llvm/test/MC/Mips/msa/test_ctrlregs.s
+++ b/llvm/test/MC/Mips/msa/test_ctrlregs.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
#CHECK: cfcmsa $1, $0 # encoding: [0x78,0x7e,0x00,0x59]
#CHECK: cfcmsa $1, $0 # encoding: [0x78,0x7e,0x00,0x59]
diff --git a/llvm/test/MC/Mips/msa/test_dlsa.s b/llvm/test/MC/Mips/msa/test_dlsa.s
index 5e14571c84e70df..de1fac1086fec3a 100644
--- a/llvm/test/MC/Mips/msa/test_dlsa.s
+++ b/llvm/test/MC/Mips/msa/test_dlsa.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | \
+# RUN: llvm-mc %s -triple=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | \
# RUN: FileCheck %s
#
# CHECK: dlsa $8, $9, $10, 1 # encoding: [0x01,0x2a,0x40,0x15]
diff --git a/llvm/test/MC/Mips/msa/test_elm.s b/llvm/test/MC/Mips/msa/test_elm.s
index ca6f18c9584fa67..ea19b6c0ce8717a 100644
--- a/llvm/test/MC/Mips/msa/test_elm.s
+++ b/llvm/test/MC/Mips/msa/test_elm.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
copy_s.b $13, $w8[2] # CHECK: copy_s.b $13, $w8[2] # encoding: [0x78,0x82,0x43,0x59]
copy_s.h $1, $w25[0] # CHECK: copy_s.h $1, $w25[0] # encoding: [0x78,0xa0,0xc8,0x59]
diff --git a/llvm/test/MC/Mips/msa/test_elm_insert.s b/llvm/test/MC/Mips/msa/test_elm_insert.s
index d58a4e0b5e73969..c30073dd3a8f446 100644
--- a/llvm/test/MC/Mips/msa/test_elm_insert.s
+++ b/llvm/test/MC/Mips/msa/test_elm_insert.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: insert.b $w23[3], $sp # encoding: [0x79,0x03,0xed,0xd9]
# CHECK: insert.h $w20[2], $5 # encoding: [0x79,0x22,0x2d,0x19]
diff --git a/llvm/test/MC/Mips/msa/test_elm_insert_msa64.s b/llvm/test/MC/Mips/msa/test_elm_insert_msa64.s
index 4e99bdb4e9e54b7..3f6afeda361a2a1 100644
--- a/llvm/test/MC/Mips/msa/test_elm_insert_msa64.s
+++ b/llvm/test/MC/Mips/msa/test_elm_insert_msa64.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: insert.d $w1[1], $sp # encoding: [0x79,0x39,0xe8,0x59]
diff --git a/llvm/test/MC/Mips/msa/test_elm_insve.s b/llvm/test/MC/Mips/msa/test_elm_insve.s
index 0053322dc7c9ca5..c250f8b6df40185 100644
--- a/llvm/test/MC/Mips/msa/test_elm_insve.s
+++ b/llvm/test/MC/Mips/msa/test_elm_insve.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: insve.b $w25[3], $w9[0] # encoding: [0x79,0x43,0x4e,0x59]
# CHECK: insve.h $w24[2], $w2[0] # encoding: [0x79,0x62,0x16,0x19]
diff --git a/llvm/test/MC/Mips/msa/test_elm_msa64.s b/llvm/test/MC/Mips/msa/test_elm_msa64.s
index 8e4c540c50195b6..7a9569019c5ca34 100644
--- a/llvm/test/MC/Mips/msa/test_elm_msa64.s
+++ b/llvm/test/MC/Mips/msa/test_elm_msa64.s
@@ -1,3 +1,3 @@
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s
copy_s.d $19, $w31[0] # CHECK: copy_s.d $19, $w31[0] # encoding: [0x78,0xb8,0xfc,0xd9]
diff --git a/llvm/test/MC/Mips/msa/test_i10.s b/llvm/test/MC/Mips/msa/test_i10.s
index d89218ae105a953..25da48e9ee32497 100644
--- a/llvm/test/MC/Mips/msa/test_i10.s
+++ b/llvm/test/MC/Mips/msa/test_i10.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: ldi.b $w8, 198 # encoding: [0x7b,0x06,0x32,0x07]
# CHECK: ldi.h $w20, 313 # encoding: [0x7b,0x29,0xcd,0x07]
diff --git a/llvm/test/MC/Mips/msa/test_i5.s b/llvm/test/MC/Mips/msa/test_i5.s
index d923787550e8508..68279a8fd0207fd 100644
--- a/llvm/test/MC/Mips/msa/test_i5.s
+++ b/llvm/test/MC/Mips/msa/test_i5.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: addvi.b $w3, $w31, 30 # encoding: [0x78,0x1e,0xf8,0xc6]
# CHECK: addvi.h $w24, $w13, 26 # encoding: [0x78,0x3a,0x6e,0x06]
diff --git a/llvm/test/MC/Mips/msa/test_i8.s b/llvm/test/MC/Mips/msa/test_i8.s
index b520bb4452e7a4a..c41cac9dc55001d 100644
--- a/llvm/test/MC/Mips/msa/test_i8.s
+++ b/llvm/test/MC/Mips/msa/test_i8.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: andi.b $w2, $w29, 48 # encoding: [0x78,0x30,0xe8,0x80]
# CHECK: bmnzi.b $w6, $w22, 126 # encoding: [0x78,0x7e,0xb1,0x81]
diff --git a/llvm/test/MC/Mips/msa/test_lsa.s b/llvm/test/MC/Mips/msa/test_lsa.s
index 22fd0b3039ed350..4a20b3f75437fee 100644
--- a/llvm/test/MC/Mips/msa/test_lsa.s
+++ b/llvm/test/MC/Mips/msa/test_lsa.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: lsa $8, $9, $10, 1 # encoding: [0x01,0x2a,0x40,0x05]
# CHECK: lsa $8, $9, $10, 2 # encoding: [0x01,0x2a,0x40,0x45]
diff --git a/llvm/test/MC/Mips/msa/test_mi10.s b/llvm/test/MC/Mips/msa/test_mi10.s
index f20ffa29372b81f..e5c4e5b39f26199 100644
--- a/llvm/test/MC/Mips/msa/test_mi10.s
+++ b/llvm/test/MC/Mips/msa/test_mi10.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
ld.b $w0, -512($1) # CHECK: ld.b $w0, -512($1) # encoding: [0x7a,0x00,0x08,0x20]
ld.b $w1, 0($2) # CHECK: ld.b $w1, 0($2) # encoding: [0x78,0x00,0x10,0x60]
diff --git a/llvm/test/MC/Mips/msa/test_vec.s b/llvm/test/MC/Mips/msa/test_vec.s
index 3f989d3a5946504..d8630e5fa2bec6a 100644
--- a/llvm/test/MC/Mips/msa/test_vec.s
+++ b/llvm/test/MC/Mips/msa/test_vec.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
#
# CHECK: and.v $w25, $w20, $w27 # encoding: [0x78,0x1b,0xa6,0x5e]
# CHECK: bmnz.v $w17, $w6, $w7 # encoding: [0x78,0x87,0x34,0x5e]
diff --git a/llvm/test/MC/Mips/mt/abiflag.s b/llvm/test/MC/Mips/mt/abiflag.s
index 9f8592635bebfe1..f0d006650b184ed 100644
--- a/llvm/test/MC/Mips/mt/abiflag.s
+++ b/llvm/test/MC/Mips/mt/abiflag.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc < %s -arch=mips -mcpu=mips32r2 -mattr=+mt -filetype=obj -o - \
+# RUN: llvm-mc < %s -triple=mips -mcpu=mips32r2 -mattr=+mt -filetype=obj -o - \
# RUN: | llvm-readobj -A - | FileCheck %s
# Test that the usage of the MT ASE is recorded in .MIPS.abiflags
diff --git a/llvm/test/MC/Mips/mt/invalid-wrong-error.s b/llvm/test/MC/Mips/mt/invalid-wrong-error.s
index 6de852cf0cbe3b8..dd74921c49c2fcd 100644
--- a/llvm/test/MC/Mips/mt/invalid-wrong-error.s
+++ b/llvm/test/MC/Mips/mt/invalid-wrong-error.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt < %s 2>%t1
+# RUN: not llvm-mc -triple=mips -mcpu=mips32r2 -mattr=+mt < %s 2>%t1
# RUN: FileCheck %s < %t1
mftr 0($4), $5, 0, 0, 0 # CHECK: error: unexpected token in argument list
mttr 0($4), $5, 0, 0, 0 # CHECK: error: unexpected token in argument list
diff --git a/llvm/test/MC/Mips/mt/invalid.s b/llvm/test/MC/Mips/mt/invalid.s
index e459bc0becbd8a1..f58de96446bbc38 100644
--- a/llvm/test/MC/Mips/mt/invalid.s
+++ b/llvm/test/MC/Mips/mt/invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=mips -mcpu=mips32 -mattr=+mt < %s 2>%t1
+# RUN: not llvm-mc -triple=mips -mcpu=mips32 -mattr=+mt < %s 2>%t1
# RUN: FileCheck %s < %t1
dmt 4 # CHECK: error: invalid operand for instruction
dmt $4, $5 # CHECK: error: invalid operand for instruction
diff --git a/llvm/test/MC/Mips/mt/mftr-mttr-aliases-invalid-wrong-error.s b/llvm/test/MC/Mips/mt/mftr-mttr-aliases-invalid-wrong-error.s
index d931b499f26e086..b3a7e4e2629a116 100644
--- a/llvm/test/MC/Mips/mt/mftr-mttr-aliases-invalid-wrong-error.s
+++ b/llvm/test/MC/Mips/mt/mftr-mttr-aliases-invalid-wrong-error.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s 2>%t1
+# RUN: not llvm-mc -triple=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s 2>%t1
# RUN: FileCheck %s < %t1
# The integrated assembler produces a wrong or misleading error message.
diff --git a/llvm/test/MC/Mips/mt/mftr-mttr-aliases-invalid.s b/llvm/test/MC/Mips/mt/mftr-mttr-aliases-invalid.s
index 17d954030cd1216..c22dce76994c82c 100644
--- a/llvm/test/MC/Mips/mt/mftr-mttr-aliases-invalid.s
+++ b/llvm/test/MC/Mips/mt/mftr-mttr-aliases-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s 2>%t1
+# RUN: not llvm-mc -triple=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s 2>%t1
# RUN: FileCheck %s < %t1
mftc0 $4, 0($5) # CHECK: error: invalid operand for instruction
diff --git a/llvm/test/MC/Mips/mt/mftr-mttr-aliases.s b/llvm/test/MC/Mips/mt/mftr-mttr-aliases.s
index 92ed9f9281f2010..92e99fefc3dc166 100644
--- a/llvm/test/MC/Mips/mt/mftr-mttr-aliases.s
+++ b/llvm/test/MC/Mips/mt/mftr-mttr-aliases.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s | FileCheck %s
+# RUN: llvm-mc -triple=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s | FileCheck %s
# Check the various aliases of the m[ft]tr instruction.
diff --git a/llvm/test/MC/Mips/mt/mftr-mttr-reserved-valid.s b/llvm/test/MC/Mips/mt/mftr-mttr-reserved-valid.s
index c40e81bfc7d7540..1468806d1ab0c16 100644
--- a/llvm/test/MC/Mips/mt/mftr-mttr-reserved-valid.s
+++ b/llvm/test/MC/Mips/mt/mftr-mttr-reserved-valid.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s | FileCheck %s
+# RUN: llvm-mc -triple=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s | FileCheck %s
# The selector value and register values here are marked as reserved in the
# documentation, but GAS accepts them without warning.
diff --git a/llvm/test/MC/Mips/mt/module-directive-invalid.s b/llvm/test/MC/Mips/mt/module-directive-invalid.s
index 38baaa07cdc171d..e5e3a8c3f64d296 100644
--- a/llvm/test/MC/Mips/mt/module-directive-invalid.s
+++ b/llvm/test/MC/Mips/mt/module-directive-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=mips -mcpu=mips32r5 < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=mips -mcpu=mips32r5 < %s 2>&1 | FileCheck %s
# CHECK: error: .module directive must appear before any code
.set nomips16
diff --git a/llvm/test/MC/Mips/mt/module-directive.s b/llvm/test/MC/Mips/mt/module-directive.s
index 0b7430890082082..3a2bd48b9812c40 100644
--- a/llvm/test/MC/Mips/mt/module-directive.s
+++ b/llvm/test/MC/Mips/mt/module-directive.s
@@ -1,6 +1,6 @@
-# RUN: llvm-mc < %s -arch=mips -mcpu=mips32r2 -filetype=obj -o - | \
+# RUN: llvm-mc < %s -triple=mips -mcpu=mips32r2 -filetype=obj -o - | \
# RUN: llvm-readobj -A - | FileCheck --check-prefix=CHECK-OBJ %s
-# RUN: llvm-mc < %s -arch=mips -mcpu=mips32r2 -filetype=asm -o - | \
+# RUN: llvm-mc < %s -triple=mips -mcpu=mips32r2 -filetype=asm -o - | \
# RUN: FileCheck --check-prefix=CHECK-ASM %s
# Test that the .module directive sets the MT flag in .MIPS.abiflags when
diff --git a/llvm/test/MC/Mips/mt/set-directive.s b/llvm/test/MC/Mips/mt/set-directive.s
index 3593c2ddde5225f..8995c02ef5bd16f 100644
--- a/llvm/test/MC/Mips/mt/set-directive.s
+++ b/llvm/test/MC/Mips/mt/set-directive.s
@@ -1,6 +1,6 @@
-# RUN: llvm-mc < %s -arch=mips -mcpu=mips32r2 -filetype=obj -o - | \
+# RUN: llvm-mc < %s -triple=mips -mcpu=mips32r2 -filetype=obj -o - | \
# RUN: llvm-readobj -A - | FileCheck %s --check-prefix=CHECK-OBJ
-# RUN: llvm-mc < %s -arch=mips -mcpu=mips32r2 -filetype=asm -o - | \
+# RUN: llvm-mc < %s -triple=mips -mcpu=mips32r2 -filetype=asm -o - | \
# RUN: FileCheck %s --check-prefix=CHECK-ASM
# Test that the MT ASE flag in .MIPS.abiflags is _not_ set by .set.
diff --git a/llvm/test/MC/Mips/mt/valid.s b/llvm/test/MC/Mips/mt/valid.s
index 9fa07870a61f24a..8860f8b1088316d 100644
--- a/llvm/test/MC/Mips/mt/valid.s
+++ b/llvm/test/MC/Mips/mt/valid.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s \
+# RUN: llvm-mc -triple=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s \
# RUN: | FileCheck %s
dmt # CHECK: dmt # encoding: [0x41,0x60,0x0b,0xc1]
dmt $5 # CHECK: dmt $5 # encoding: [0x41,0x65,0x0b,0xc1]
diff --git a/llvm/test/MC/Mips/rotations32-bad.s b/llvm/test/MC/Mips/rotations32-bad.s
index 600000e7caef6d0..8eafb2413b313dd 100644
--- a/llvm/test/MC/Mips/rotations32-bad.s
+++ b/llvm/test/MC/Mips/rotations32-bad.s
@@ -1,12 +1,12 @@
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32 -show-encoding 2> %t1
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32 -show-encoding 2> %t1
# RUN: FileCheck %s < %t1
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 -show-encoding 2> %t1
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r2 -show-encoding 2> %t1
# RUN: FileCheck %s < %t1
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r3 -show-encoding 2> %t1
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r3 -show-encoding 2> %t1
# RUN: FileCheck %s < %t1
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r5 -show-encoding 2> %t1
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r5 -show-encoding 2> %t1
# RUN: FileCheck %s < %t1
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 -show-encoding 2> %t1
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips32r6 -show-encoding 2> %t1
# RUN: FileCheck %s < %t1
.text
diff --git a/llvm/test/MC/Mips/rotations32.s b/llvm/test/MC/Mips/rotations32.s
index 64207708aa94daa..5f44703d65094da 100644
--- a/llvm/test/MC/Mips/rotations32.s
+++ b/llvm/test/MC/Mips/rotations32.s
@@ -1,8 +1,8 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -show-encoding | FileCheck %s -check-prefix=CHECK-32
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r3 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r5 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32 -show-encoding | FileCheck %s -check-prefix=CHECK-32
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r2 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r3 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r5 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r6 -show-encoding | FileCheck %s -check-prefix=CHECK-32R
.text
foo:
diff --git a/llvm/test/MC/Mips/rotations64.s b/llvm/test/MC/Mips/rotations64.s
index f25b48ad87fdfa3..ca5494c1925e91a 100644
--- a/llvm/test/MC/Mips/rotations64.s
+++ b/llvm/test/MC/Mips/rotations64.s
@@ -1,8 +1,8 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips64 -show-encoding | FileCheck %s -check-prefix=CHECK-64
-# RUN: llvm-mc %s -arch=mips -mcpu=mips64r2 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
-# RUN: llvm-mc %s -arch=mips -mcpu=mips64r3 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
-# RUN: llvm-mc %s -arch=mips -mcpu=mips64r5 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
-# RUN: llvm-mc %s -arch=mips -mcpu=mips64r6 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
+# RUN: llvm-mc %s -triple=mips -mcpu=mips64 -show-encoding | FileCheck %s -check-prefix=CHECK-64
+# RUN: llvm-mc %s -triple=mips -mcpu=mips64r2 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
+# RUN: llvm-mc %s -triple=mips -mcpu=mips64r3 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
+# RUN: llvm-mc %s -triple=mips -mcpu=mips64r5 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
+# RUN: llvm-mc %s -triple=mips -mcpu=mips64r6 -show-encoding | FileCheck %s -check-prefix=CHECK-64R
.text
foo:
diff --git a/llvm/test/MC/Mips/set-defined-symbol.s b/llvm/test/MC/Mips/set-defined-symbol.s
index 061fec37bb21264..dd7924427c19ee9 100644
--- a/llvm/test/MC/Mips/set-defined-symbol.s
+++ b/llvm/test/MC/Mips/set-defined-symbol.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32 -filetype=obj -o - | \
# RUN: llvm-objdump -d -r - | FileCheck %s
.global foo
diff --git a/llvm/test/MC/Mips/set-mips16-directive.s b/llvm/test/MC/Mips/set-mips16-directive.s
index cf8090eaa280f56..9987c539126d4b5 100644
--- a/llvm/test/MC/Mips/set-mips16-directive.s
+++ b/llvm/test/MC/Mips/set-mips16-directive.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips | FileCheck %s
+# RUN: llvm-mc %s -triple=mips | FileCheck %s
# FIXME: Update this test when we have a more mature implementation of Mips16 in the IAS.
.text
diff --git a/llvm/test/MC/Mips/set-nomacro.s b/llvm/test/MC/Mips/set-nomacro.s
index f0e2f8883863764..302f0058e1ef9c0 100644
--- a/llvm/test/MC/Mips/set-nomacro.s
+++ b/llvm/test/MC/Mips/set-nomacro.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32 2>&1 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32 2>&1 | FileCheck %s
# CHECK-NOT: warning: macro instruction expanded into multiple instructions
.set macro
diff --git a/llvm/test/MC/Mips/tls-symbols.s b/llvm/test/MC/Mips/tls-symbols.s
index 964d57277ebfd82..49c01ef0d23e5af 100644
--- a/llvm/test/MC/Mips/tls-symbols.s
+++ b/llvm/test/MC/Mips/tls-symbols.s
@@ -1,6 +1,6 @@
-# RUN: llvm-mc -arch=mips < %s -position-independent -filetype=obj \
+# RUN: llvm-mc -triple=mips < %s -position-independent -filetype=obj \
# RUN: | llvm-readelf -s - | FileCheck %s
-# RUN: llvm-mc -arch=mips < %s -filetype=obj | llvm-readelf -s - | FileCheck %s
+# RUN: llvm-mc -triple=mips < %s -filetype=obj | llvm-readelf -s - | FileCheck %s
# Test that TLS relocations cause symbols to be marked as TLS symbols.
diff --git a/llvm/test/MC/Mips/virt/invalid64.s b/llvm/test/MC/Mips/virt/invalid64.s
index 8a9aede4b84eefd..c92795684f45692 100644
--- a/llvm/test/MC/Mips/virt/invalid64.s
+++ b/llvm/test/MC/Mips/virt/invalid64.s
@@ -1,6 +1,6 @@
# Instructions that are invalid.
#
-# RUN: not llvm-mc %s -arch=mips -mcpu=mips64r5 -mattr=+virt 2>%t1
+# RUN: not llvm-mc %s -triple=mips -mcpu=mips64r5 -mattr=+virt 2>%t1
# RUN: FileCheck %s < %t1
dmfgc0 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
diff --git a/llvm/test/MC/Mips/virt/module-novirt.s b/llvm/test/MC/Mips/virt/module-novirt.s
index 6b953d0c58576e0..5a500d5901fee01 100644
--- a/llvm/test/MC/Mips/virt/module-novirt.s
+++ b/llvm/test/MC/Mips/virt/module-novirt.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r5 -mattr=+virt | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r5 -mattr=+virt | \
# RUN: FileCheck %s -check-prefix=CHECK-ASM
#
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r5 -filetype=obj -o - -mattr=+virt | \
+# RUN: llvm-mc %s -triple=mips -mcpu=mips32r5 -filetype=obj -o - -mattr=+virt | \
# RUN: llvm-readobj -A - | \
# RUN: FileCheck %s -check-prefix=CHECK-OBJ
diff --git a/llvm/test/MC/Sparc/leon-instructions.s b/llvm/test/MC/Sparc/leon-instructions.s
index 210231a1a7d7edc..c2cfe70e399776e 100644
--- a/llvm/test/MC/Sparc/leon-instructions.s
+++ b/llvm/test/MC/Sparc/leon-instructions.s
@@ -1,8 +1,8 @@
-! RUN: llvm-mc %s -arch=sparc -mcpu=leon3 -show-encoding | FileCheck %s
-! RUN: llvm-mc %s -arch=sparc -mcpu=ut699 -show-encoding | FileCheck %s
-! RUN: llvm-mc %s -arch=sparc -mcpu=gr712rc -show-encoding | FileCheck %s
-! RUN: llvm-mc %s -arch=sparc -mcpu=leon4 -show-encoding | FileCheck %s
-! RUN: llvm-mc %s -arch=sparc -mcpu=gr740 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -mcpu=leon3 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -mcpu=ut699 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -mcpu=gr712rc -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -mcpu=leon4 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -mcpu=gr740 -show-encoding | FileCheck %s
! CHECK: umac %i0, %l6, %o2 ! encoding: [0x95,0xf6,0x00,0x16]
umac %i0, %l6, %o2
diff --git a/llvm/test/MC/Sparc/leon-pwrpsr-instruction.s b/llvm/test/MC/Sparc/leon-pwrpsr-instruction.s
index f6476c3e206f3c1..d3eb7c6cd3d42c2 100644
--- a/llvm/test/MC/Sparc/leon-pwrpsr-instruction.s
+++ b/llvm/test/MC/Sparc/leon-pwrpsr-instruction.s
@@ -1,4 +1,4 @@
-! RUN: llvm-mc %s -arch=sparc -mcpu=gr740 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -mcpu=gr740 -show-encoding | FileCheck %s
! CHECK: pwr %g0, 0, %psr ! encoding: [0x83,0x88,0x20,0x00]
pwr 0, %psr
diff --git a/llvm/test/MC/Sparc/sparc-alu-instructions.s b/llvm/test/MC/Sparc/sparc-alu-instructions.s
index b08ab43f13e956f..98a3dc22b77998f 100644
--- a/llvm/test/MC/Sparc/sparc-alu-instructions.s
+++ b/llvm/test/MC/Sparc/sparc-alu-instructions.s
@@ -1,5 +1,5 @@
-! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s
! CHECK: add %g0, %g0, %g0 ! encoding: [0x80,0x00,0x00,0x00]
add %g0, %g0, %g0
diff --git a/llvm/test/MC/Sparc/sparc-asm-errors.s b/llvm/test/MC/Sparc/sparc-asm-errors.s
index 3a52489b319f292..780f4e7fad787c4 100644
--- a/llvm/test/MC/Sparc/sparc-asm-errors.s
+++ b/llvm/test/MC/Sparc/sparc-asm-errors.s
@@ -1,5 +1,5 @@
-! RUN: not llvm-mc %s -arch=sparc -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=V8
-! RUN: not llvm-mc %s -arch=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=V9
+! RUN: not llvm-mc %s -triple=sparc -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=V8
+! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=V9
! Test the lower and upper bounds of 'set'
! CHECK: argument must be between
diff --git a/llvm/test/MC/Sparc/sparc-assembly-exprs.s b/llvm/test/MC/Sparc/sparc-assembly-exprs.s
index 36cd1d55c71fe08..e950f1635ab3aff 100644
--- a/llvm/test/MC/Sparc/sparc-assembly-exprs.s
+++ b/llvm/test/MC/Sparc/sparc-assembly-exprs.s
@@ -1,5 +1,5 @@
-! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
-! RUN: llvm-mc %s -arch=sparc -filetype=obj | llvm-objdump -r -d - | FileCheck %s --check-prefix=OBJDUMP
+! RUN: llvm-mc %s -triple=sparc -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -filetype=obj | llvm-objdump -r -d - | FileCheck %s --check-prefix=OBJDUMP
! CHECK: mov 1033, %o1 ! encoding: [0x92,0x10,0x24,0x09]
mov (0x400|9), %o1
@@ -39,7 +39,7 @@ symStart:
symEnd:
! "." is exactly like a temporary symbol equated to the current line.
-! RUN: llvm-mc %s -arch=sparc | FileCheck %s --check-prefix=DOTEXPR
+! RUN: llvm-mc %s -triple=sparc | FileCheck %s --check-prefix=DOTEXPR
! DOTEXPR: .Ltmp0
! DOTEXPR-NEXT: ba .Ltmp0+8
diff --git a/llvm/test/MC/Sparc/sparc-atomic-instructions.s b/llvm/test/MC/Sparc/sparc-atomic-instructions.s
index 2ed53e7c4f68719..0e5abccb53c6586 100644
--- a/llvm/test/MC/Sparc/sparc-atomic-instructions.s
+++ b/llvm/test/MC/Sparc/sparc-atomic-instructions.s
@@ -1,5 +1,5 @@
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
-! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s --check-prefix=V8
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
+! RUN: llvm-mc %s -triple=sparc -show-encoding | FileCheck %s --check-prefix=V8
! V8: stbar ! encoding: [0x81,0x43,0xc0,0x00]
! V9: stbar ! encoding: [0x81,0x43,0xc0,0x00]
diff --git a/llvm/test/MC/Sparc/sparc-cas-instructions.s b/llvm/test/MC/Sparc/sparc-cas-instructions.s
index 4e30fed378beb80..30ce3fd0b2d227b 100644
--- a/llvm/test/MC/Sparc/sparc-cas-instructions.s
+++ b/llvm/test/MC/Sparc/sparc-cas-instructions.s
@@ -1,6 +1,6 @@
-! RUN: not llvm-mc %s -arch=sparc -show-encoding 2>&1 | FileCheck %s --check-prefix=V8
-! RUN: not llvm-mc %s -arch=sparc -mattr=+hasleoncasa -show-encoding 2>&1 | FileCheck %s --check-prefix=LEON
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
+! RUN: not llvm-mc %s -triple=sparc -show-encoding 2>&1 | FileCheck %s --check-prefix=V8
+! RUN: not llvm-mc %s -triple=sparc -mattr=+hasleoncasa -show-encoding 2>&1 | FileCheck %s --check-prefix=LEON
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
! V8: error: instruction requires a CPU feature not currently enabled
! V9: cas [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
diff --git a/llvm/test/MC/Sparc/sparc-coproc.s b/llvm/test/MC/Sparc/sparc-coproc.s
index f83e415cf31e3a7..9fee09e58cf01df 100644
--- a/llvm/test/MC/Sparc/sparc-coproc.s
+++ b/llvm/test/MC/Sparc/sparc-coproc.s
@@ -1,4 +1,4 @@
-! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -show-encoding | FileCheck %s
! CHECK: ld [%i1], %c4 ! encoding: [0xc9,0x86,0x40,0x00]
! CHECK: ld [%i1+-15], %c4 ! encoding: [0xc9,0x86,0x7f,0xf1]
diff --git a/llvm/test/MC/Sparc/sparc-ctrl-instructions.s b/llvm/test/MC/Sparc/sparc-ctrl-instructions.s
index ef65bbe2c7893d0..109e7c9b0114872 100644
--- a/llvm/test/MC/Sparc/sparc-ctrl-instructions.s
+++ b/llvm/test/MC/Sparc/sparc-ctrl-instructions.s
@@ -1,5 +1,5 @@
-! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s
! CHECK: call foo ! encoding: [0b01AAAAAA,A,A,A]
! CHECK: ! fixup A - offset: 0, value: foo, kind: fixup_sparc_call30
diff --git a/llvm/test/MC/Sparc/sparc-directive-xword.s b/llvm/test/MC/Sparc/sparc-directive-xword.s
index 736f99fbce744f6..c73543e0b801e49 100644
--- a/llvm/test/MC/Sparc/sparc-directive-xword.s
+++ b/llvm/test/MC/Sparc/sparc-directive-xword.s
@@ -1,4 +1,4 @@
-! RUN: not llvm-mc %s -arch=sparc -show-encoding 2>&1 | FileCheck %s --check-prefix=SPARC32
+! RUN: not llvm-mc %s -triple=sparc -show-encoding 2>&1 | FileCheck %s --check-prefix=SPARC32
! RUN: llvm-mc %s -triple sparc64 -show-encoding | FileCheck %s --check-prefix=SPARC64
! RUN: llvm-mc %s -triple sparcv9 -show-encoding | FileCheck %s --check-prefix=SPARCV9
diff --git a/llvm/test/MC/Sparc/sparc-directives.s b/llvm/test/MC/Sparc/sparc-directives.s
index 1e1ce740c11d091..1ccec7b2ccc03d0 100644
--- a/llvm/test/MC/Sparc/sparc-directives.s
+++ b/llvm/test/MC/Sparc/sparc-directives.s
@@ -1,5 +1,5 @@
-! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s --check-prefix=SPARC32
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=SPARC64
+! RUN: llvm-mc %s -triple=sparc -show-encoding | FileCheck %s --check-prefix=SPARC32
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s --check-prefix=SPARC64
! '.proc' is documented to do nothing in the binutils assembler.
! so it should do nothing for clang either, i.e. not be an error.
diff --git a/llvm/test/MC/Sparc/sparc-fixups.s b/llvm/test/MC/Sparc/sparc-fixups.s
index cdf006e7cff5800..5f5bf6a330392c9 100644
--- a/llvm/test/MC/Sparc/sparc-fixups.s
+++ b/llvm/test/MC/Sparc/sparc-fixups.s
@@ -1,4 +1,4 @@
-! RUN: llvm-mc %s -arch=sparcv9 -filetype=obj | llvm-objdump -dr - | FileCheck %s
+! RUN: llvm-mc %s -triple=sparcv9 -filetype=obj | llvm-objdump -dr - | FileCheck %s
.text
! Check that fixups are correctly applied.
diff --git a/llvm/test/MC/Sparc/sparc-fp-instructions.s b/llvm/test/MC/Sparc/sparc-fp-instructions.s
index ae5ef37bf22d89f..662f55eea7a836e 100644
--- a/llvm/test/MC/Sparc/sparc-fp-instructions.s
+++ b/llvm/test/MC/Sparc/sparc-fp-instructions.s
@@ -1,4 +1,4 @@
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s
! CHECK: fitos %f0, %f4 ! encoding: [0x89,0xa0,0x18,0x80]
! CHECK: fitod %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x00]
diff --git a/llvm/test/MC/Sparc/sparc-mem-asi-instructions.s b/llvm/test/MC/Sparc/sparc-mem-asi-instructions.s
index f69e26fc3e6384b..39abe7b99cb40c3 100644
--- a/llvm/test/MC/Sparc/sparc-mem-asi-instructions.s
+++ b/llvm/test/MC/Sparc/sparc-mem-asi-instructions.s
@@ -1,5 +1,5 @@
-! RUN: not llvm-mc %s -arch=sparc -show-encoding 2>&1 | FileCheck %s --check-prefix=V8
-! RUN: not llvm-mc %s -arch=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefix=V9
+! RUN: not llvm-mc %s -triple=sparc -show-encoding 2>&1 | FileCheck %s --check-prefix=V8
+! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefix=V9
! V8: error: malformed ASI tag, must be a constant integer expression
! V8-NEXT: lduba [%i0] asi, %o2
diff --git a/llvm/test/MC/Sparc/sparc-mem-instructions.s b/llvm/test/MC/Sparc/sparc-mem-instructions.s
index cdcfcd588ba44e9..b087518b4586840 100644
--- a/llvm/test/MC/Sparc/sparc-mem-instructions.s
+++ b/llvm/test/MC/Sparc/sparc-mem-instructions.s
@@ -1,5 +1,5 @@
-! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s --check-prefix=V8
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
+! RUN: llvm-mc %s -triple=sparc -show-encoding | FileCheck %s --check-prefix=V8
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
! V8: ldsb [%i0+%l6], %o2 ! encoding: [0xd4,0x4e,0x00,0x16]
! V9: ldsb [%i0+%l6], %o2 ! encoding: [0xd4,0x4e,0x00,0x16]
diff --git a/llvm/test/MC/Sparc/sparc-misc-instructions.s b/llvm/test/MC/Sparc/sparc-misc-instructions.s
index 3ae7dee07edc18c..0547575eb3db519 100644
--- a/llvm/test/MC/Sparc/sparc-misc-instructions.s
+++ b/llvm/test/MC/Sparc/sparc-misc-instructions.s
@@ -1,5 +1,5 @@
-! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s
! CHECK: unimp 0 ! encoding: [0x00,0x00,0x00,0x00]
unimp
diff --git a/llvm/test/MC/Sparc/sparc-nop-data.s b/llvm/test/MC/Sparc/sparc-nop-data.s
index 1987dfd2885800c..7de1249969eb6d5 100644
--- a/llvm/test/MC/Sparc/sparc-nop-data.s
+++ b/llvm/test/MC/Sparc/sparc-nop-data.s
@@ -1,5 +1,5 @@
-! RUN: llvm-mc %s -arch=sparc -filetype=obj | llvm-readobj -S --sd - | FileCheck %s
-! RUN: llvm-mc %s -arch=sparcv9 -filetype=obj | llvm-readobj -S --sd - | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -filetype=obj | llvm-readobj -S --sd - | FileCheck %s
+! RUN: llvm-mc %s -triple=sparcv9 -filetype=obj | llvm-readobj -S --sd - | FileCheck %s
! CHECK: 0000: BA1F401D 01000000 01000000 01000000
! CHECK: 0010: BA1F401D
diff --git a/llvm/test/MC/Sparc/sparc-pic.s b/llvm/test/MC/Sparc/sparc-pic.s
index 859c6efc12ae7ab..6cfd6642c70b8a8 100644
--- a/llvm/test/MC/Sparc/sparc-pic.s
+++ b/llvm/test/MC/Sparc/sparc-pic.s
@@ -1,5 +1,5 @@
-! RUN: llvm-mc %s -arch=sparcv9 --position-independent -filetype=obj | llvm-readobj -r - | FileCheck --check-prefix=PIC %s
-! RUN: llvm-mc %s -arch=sparcv9 -filetype=obj | llvm-readobj -r - | FileCheck --check-prefix=NOPIC %s
+! RUN: llvm-mc %s -triple=sparcv9 --position-independent -filetype=obj | llvm-readobj -r - | FileCheck --check-prefix=PIC %s
+! RUN: llvm-mc %s -triple=sparcv9 -filetype=obj | llvm-readobj -r - | FileCheck --check-prefix=NOPIC %s
! PIC: Relocations [
diff --git a/llvm/test/MC/Sparc/sparc-relocations.s b/llvm/test/MC/Sparc/sparc-relocations.s
index f812105f503b10a..d99ddb7e2f802d5 100644
--- a/llvm/test/MC/Sparc/sparc-relocations.s
+++ b/llvm/test/MC/Sparc/sparc-relocations.s
@@ -1,5 +1,5 @@
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
-! RUN: llvm-mc %s -arch=sparcv9 -filetype=obj | llvm-readobj -r - | FileCheck %s --check-prefix=CHECK-OBJ
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparcv9 -filetype=obj | llvm-readobj -r - | FileCheck %s --check-prefix=CHECK-OBJ
! CHECK-OBJ: Format: elf64-sparc
! CHECK-OBJ: .rela.text {
diff --git a/llvm/test/MC/Sparc/sparc-special-registers.s b/llvm/test/MC/Sparc/sparc-special-registers.s
index 287a4e4069b3473..54f416211de3c83 100644
--- a/llvm/test/MC/Sparc/sparc-special-registers.s
+++ b/llvm/test/MC/Sparc/sparc-special-registers.s
@@ -1,5 +1,5 @@
-! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s --check-prefixes=CHECK,V8
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefixes=CHECK,V9
+! RUN: llvm-mc %s -triple=sparc -show-encoding | FileCheck %s --check-prefixes=CHECK,V8
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s --check-prefixes=CHECK,V9
! CHECK: rd %y, %i0 ! encoding: [0xb1,0x40,0x00,0x00]
rd %y, %i0
diff --git a/llvm/test/MC/Sparc/sparc-synthetic-instructions.s b/llvm/test/MC/Sparc/sparc-synthetic-instructions.s
index 3cea9fe48bc852f..5652f868419504a 100644
--- a/llvm/test/MC/Sparc/sparc-synthetic-instructions.s
+++ b/llvm/test/MC/Sparc/sparc-synthetic-instructions.s
@@ -1,5 +1,5 @@
-! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s
! Section A.3 Synthetic Instructions
! CHECK: cmp %g1, %g2 ! encoding: [0x80,0xa0,0x40,0x02]
@@ -169,8 +169,8 @@
! The following tests exercise 'set' in such a way that its output differs
! depending on whether targeting V8 or V9.
!
-! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s --check-prefix=V8
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
+! RUN: llvm-mc %s -triple=sparc -show-encoding | FileCheck %s --check-prefix=V8
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
! V8: mov -1, %o1 ! encoding: [0x92,0x10,0x3f,0xff]
! V9: sethi %hi(-1), %o1 ! encoding: [0x13,0b00AAAAAA,A,A]
diff --git a/llvm/test/MC/Sparc/sparc-tls-relocations.s b/llvm/test/MC/Sparc/sparc-tls-relocations.s
index 257fda74120c511..85fe96006a152ea 100644
--- a/llvm/test/MC/Sparc/sparc-tls-relocations.s
+++ b/llvm/test/MC/Sparc/sparc-tls-relocations.s
@@ -1,12 +1,12 @@
! Testing Sparc TLS relocations emission
! (for now a couple local ones).
!
-! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s --check-prefix=ASM
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=ASM
-! RUN: llvm-mc %s -arch=sparc -filetype=obj | llvm-readobj -r - | FileCheck %s --check-prefix=REL
-! RUN: llvm-mc %s -arch=sparcv9 -filetype=obj | llvm-readobj -r - | FileCheck %s --check-prefix=REL
-! RUN: llvm-mc %s -arch=sparc -filetype=obj | llvm-objdump -r -d - | FileCheck %s --check-prefix=OBJDUMP
-! RUN: llvm-mc %s -arch=sparcv9 -filetype=obj | llvm-objdump -r -d - | FileCheck %s --check-prefix=OBJDUMP
+! RUN: llvm-mc %s -triple=sparc -show-encoding | FileCheck %s --check-prefix=ASM
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s --check-prefix=ASM
+! RUN: llvm-mc %s -triple=sparc -filetype=obj | llvm-readobj -r - | FileCheck %s --check-prefix=REL
+! RUN: llvm-mc %s -triple=sparcv9 -filetype=obj | llvm-readobj -r - | FileCheck %s --check-prefix=REL
+! RUN: llvm-mc %s -triple=sparc -filetype=obj | llvm-objdump -r -d - | FileCheck %s --check-prefix=OBJDUMP
+! RUN: llvm-mc %s -triple=sparcv9 -filetype=obj | llvm-objdump -r -d - | FileCheck %s --check-prefix=OBJDUMP
! REL: Arch: sparc
! REL: Relocations [
diff --git a/llvm/test/MC/Sparc/sparc-traps.s b/llvm/test/MC/Sparc/sparc-traps.s
index 650477496f912d6..bc11b4c84c625a9 100644
--- a/llvm/test/MC/Sparc/sparc-traps.s
+++ b/llvm/test/MC/Sparc/sparc-traps.s
@@ -1,4 +1,4 @@
-! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -show-encoding | FileCheck %s
! CHECK: ta %i5 ! encoding: [0x91,0xd0,0x00,0x1d]
! CHECK: ta 82 ! encoding: [0x91,0xd0,0x20,0x52]
diff --git a/llvm/test/MC/Sparc/sparc-v9-traps.s b/llvm/test/MC/Sparc/sparc-v9-traps.s
index 8e5a48794ecf684..eac27df06070827 100644
--- a/llvm/test/MC/Sparc/sparc-v9-traps.s
+++ b/llvm/test/MC/Sparc/sparc-v9-traps.s
@@ -1,4 +1,4 @@
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s
! CHECK: ta %icc, %i5 ! encoding: [0x91,0xd0,0x00,0x1d]
! CHECK: ta %icc, 82 ! encoding: [0x91,0xd0,0x20,0x52]
diff --git a/llvm/test/MC/Sparc/sparc-vis.s b/llvm/test/MC/Sparc/sparc-vis.s
index 11ca564d48d18bf..77e1ab1432eed11 100644
--- a/llvm/test/MC/Sparc/sparc-vis.s
+++ b/llvm/test/MC/Sparc/sparc-vis.s
@@ -1,4 +1,4 @@
-! RUN: llvm-mc %s -arch=sparcv9 -mcpu=niagara -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparcv9 -mcpu=niagara -show-encoding | FileCheck %s
! CHECK: fzeros %f31 ! encoding: [0xbf,0xb0,0x0c,0x20]
fzeros %f31
diff --git a/llvm/test/MC/Sparc/sparc64-bpr-offset.s b/llvm/test/MC/Sparc/sparc64-bpr-offset.s
index 6c853c339c28595..c9d3821dea3e499 100644
--- a/llvm/test/MC/Sparc/sparc64-bpr-offset.s
+++ b/llvm/test/MC/Sparc/sparc64-bpr-offset.s
@@ -1,4 +1,4 @@
-! RUN: llvm-mc -arch=sparcv9 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=BIN
+! RUN: llvm-mc -triple=sparcv9 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=BIN
!! SPARCv9/SPARC64 BPr branches have different offset encoding from the others,
!! make sure that our offset bits don't trample on other fields.
diff --git a/llvm/test/MC/Sparc/sparcv8-instructions.s b/llvm/test/MC/Sparc/sparcv8-instructions.s
index 9071b45740c9fc4..a59c1b3b41fc426 100644
--- a/llvm/test/MC/Sparc/sparcv8-instructions.s
+++ b/llvm/test/MC/Sparc/sparcv8-instructions.s
@@ -1,4 +1,4 @@
-! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparc -show-encoding | FileCheck %s
! CHECK: fcmps %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x24]
! CHECK: fcmpd %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x44]
diff --git a/llvm/test/MC/Sparc/sparcv9-asi-names.s b/llvm/test/MC/Sparc/sparcv9-asi-names.s
index a27d1a0c30d8d61..7af4c96314dc3ee 100644
--- a/llvm/test/MC/Sparc/sparcv9-asi-names.s
+++ b/llvm/test/MC/Sparc/sparcv9-asi-names.s
@@ -1,4 +1,4 @@
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
!! Short names
! V9: casxa [%i0] #ASI_N, %l6, %o2 ! encoding: [0xd5,0xf6,0x00,0x96]
diff --git a/llvm/test/MC/Sparc/sparcv9-atomic-instructions.s b/llvm/test/MC/Sparc/sparcv9-atomic-instructions.s
index 4d28907fb863bd9..7c926e5ccc40b6b 100644
--- a/llvm/test/MC/Sparc/sparcv9-atomic-instructions.s
+++ b/llvm/test/MC/Sparc/sparcv9-atomic-instructions.s
@@ -1,4 +1,4 @@
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s
! CHECK: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore ! encoding: [0x81,0x43,0xe0,0x0f]
membar 15
diff --git a/llvm/test/MC/Sparc/sparcv9-instructions.s b/llvm/test/MC/Sparc/sparcv9-instructions.s
index 5fc31d1e939fd95..0ca2e50989ca961 100644
--- a/llvm/test/MC/Sparc/sparcv9-instructions.s
+++ b/llvm/test/MC/Sparc/sparcv9-instructions.s
@@ -1,5 +1,5 @@
-! RUN: not llvm-mc %s -arch=sparc -show-encoding 2>&1 | FileCheck %s --check-prefix=V8
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
+! RUN: not llvm-mc %s -triple=sparc -show-encoding 2>&1 | FileCheck %s --check-prefix=V8
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
! V8: error: invalid instruction mnemonic
! V8-NEXT: addc %g2, %g1, %g3
diff --git a/llvm/test/MC/Sparc/sparcv9-synthetic-instructions.s b/llvm/test/MC/Sparc/sparcv9-synthetic-instructions.s
index dfaab3fc9b15fbb..d387e56bf02a342 100644
--- a/llvm/test/MC/Sparc/sparcv9-synthetic-instructions.s
+++ b/llvm/test/MC/Sparc/sparcv9-synthetic-instructions.s
@@ -1,5 +1,5 @@
-! RUN: not llvm-mc %s -arch=sparc -show-encoding 2>&1 | FileCheck %s --check-prefix=V8
-! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
+! RUN: not llvm-mc %s -triple=sparc -show-encoding 2>&1 | FileCheck %s --check-prefix=V8
+! RUN: llvm-mc %s -triple=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
! V8: error: instruction requires a CPU feature not currently enabled
! V8-NEXT: setx 1, %g1, %o1
diff --git a/llvm/test/Object/AMDGPU/objdump.s b/llvm/test/Object/AMDGPU/objdump.s
index 60bb71730a69d78..07823b832369285 100644
--- a/llvm/test/Object/AMDGPU/objdump.s
+++ b/llvm/test/Object/AMDGPU/objdump.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=tonga %s -filetype=obj | llvm-objdump -d --arch-name=amdgcn --mcpu=tonga - | FileCheck %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=tonga %s -filetype=obj | llvm-objdump -d --arch-name=amdgcn --mcpu=tonga - | FileCheck %s
.text
>From b3f442c0c3f0c08f0fb292cc6903ffa7a4b1d990 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i at maskray.me>
Date: Mon, 11 Sep 2023 15:11:01 -0700
Subject: [PATCH 26/35] [test] Change llc -march= to -mtriple= & llvm-mc -arch=
to -triple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
---
llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll | 2 +-
llvm/test/CodeGen/Lanai/codemodel.ll | 8 ++++----
llvm/test/CodeGen/Lanai/mem_alu_combiner.ll | 4 ++--
llvm/test/CodeGen/Lanai/multiply.ll | 2 +-
llvm/test/CodeGen/Lanai/shift.ll | 2 +-
llvm/test/CodeGen/Mips/eh.ll | 4 ++--
llvm/test/CodeGen/Mips/insn-zero-size-bb.ll | 6 +++---
llvm/test/CodeGen/Mips/lw16-base-reg.ll | 2 +-
llvm/test/CodeGen/Mips/mips16ex.ll | 2 +-
llvm/test/CodeGen/RISCV/dwarf-eh.ll | 16 ++++++++--------
llvm/test/MC/Hexagon/inst_add.ll | 2 +-
llvm/test/MC/Hexagon/inst_select.ll | 2 +-
llvm/test/MC/Hexagon/inst_sxtb.ll | 2 +-
llvm/test/MC/Hexagon/inst_zxtb.ll | 2 +-
llvm/test/MC/Hexagon/inst_zxth.ll | 2 +-
llvm/test/MC/Hexagon/v62a.s | 2 +-
llvm/test/MC/Mips/mips64shift.ll | 4 ++--
llvm/test/MC/Mips/multi-64bit-func.ll | 4 ++--
llvm/test/MC/Mips/sext_64_32.ll | 2 +-
llvm/test/MC/Mips/sort-relocation-table.s | 2 +-
20 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll b/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll
index f1c398d3a7adda9..d6c7bd787cfdcfe 100644
--- a/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll
+++ b/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv55 -filetype=obj -o /dev/null
+; RUN: llc -mtriple=hexagon -mcpu=hexagonv55 -filetype=obj -o /dev/null
; REQUIRES: asserts
; There should be no output (nothing on stderr).
diff --git a/llvm/test/CodeGen/Lanai/codemodel.ll b/llvm/test/CodeGen/Lanai/codemodel.ll
index 72d1d65daf52d24..205f08d4d1478be 100644
--- a/llvm/test/CodeGen/Lanai/codemodel.ll
+++ b/llvm/test/CodeGen/Lanai/codemodel.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=lanai < %s | FileCheck %s
-; RUN: llc -march=lanai < %s -code-model=small | FileCheck -check-prefix CHECK-SMALL %s
-; RUN: not llc -march=lanai < %s -code-model=tiny 2>&1 | FileCheck -check-prefix CHECK-TINY %s
-; RUN: not llc -march=lanai < %s -code-model=kernel 2>&1 | FileCheck -check-prefix CHECK-KERNEL %s
+; RUN: llc -mtriple=lanai < %s | FileCheck %s
+; RUN: llc -mtriple=lanai < %s -code-model=small | FileCheck -check-prefix CHECK-SMALL %s
+; RUN: not llc -mtriple=lanai < %s -code-model=tiny 2>&1 | FileCheck -check-prefix CHECK-TINY %s
+; RUN: not llc -mtriple=lanai < %s -code-model=kernel 2>&1 | FileCheck -check-prefix CHECK-KERNEL %s
; CHECK-TINY: Target does not support the tiny CodeModel
; CHECK-KERNEL: Target does not support the kernel CodeModel
diff --git a/llvm/test/CodeGen/Lanai/mem_alu_combiner.ll b/llvm/test/CodeGen/Lanai/mem_alu_combiner.ll
index 4e6e77361444b3b..2dbe1268958d41a 100644
--- a/llvm/test/CodeGen/Lanai/mem_alu_combiner.ll
+++ b/llvm/test/CodeGen/Lanai/mem_alu_combiner.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=lanai | FileCheck %s
-; RUN: llc < %s -march=lanai -disable-lanai-mem-alu-combiner | \
+; RUN: llc < %s -mtriple=lanai | FileCheck %s
+; RUN: llc < %s -mtriple=lanai -disable-lanai-mem-alu-combiner | \
; RUN: FileCheck %s -check-prefix=CHECK-DIS
; CHECK-LABEL: sum,
diff --git a/llvm/test/CodeGen/Lanai/multiply.ll b/llvm/test/CodeGen/Lanai/multiply.ll
index c92a06c3f017098..dd6e70f28636b8e 100644
--- a/llvm/test/CodeGen/Lanai/multiply.ll
+++ b/llvm/test/CodeGen/Lanai/multiply.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=lanai < %s | FileCheck %s
+; RUN: llc -mtriple=lanai < %s | FileCheck %s
; Test the in place lowering of mul i32.
diff --git a/llvm/test/CodeGen/Lanai/shift.ll b/llvm/test/CodeGen/Lanai/shift.ll
index df5f91122ed8ba3..5bf2d63d07b1e01 100644
--- a/llvm/test/CodeGen/Lanai/shift.ll
+++ b/llvm/test/CodeGen/Lanai/shift.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=lanai | FileCheck %s
+; RUN: llc < %s -mtriple=lanai | FileCheck %s
; Test lowering of shifts.
diff --git a/llvm/test/CodeGen/Mips/eh.ll b/llvm/test/CodeGen/Mips/eh.ll
index 217059b4773138c..01a7e1fbacfede9 100644
--- a/llvm/test/CodeGen/Mips/eh.ll
+++ b/llvm/test/CodeGen/Mips/eh.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-EL
-; RUN: llc < %s -march=mips | FileCheck %s -check-prefix=CHECK-EB
+; RUN: llc < %s -mtriple=mipsel | FileCheck %s -check-prefix=CHECK-EL
+; RUN: llc < %s -mtriple=mips | FileCheck %s -check-prefix=CHECK-EB
@g1 = global double 0.000000e+00, align 8
@_ZTId = external constant ptr
diff --git a/llvm/test/CodeGen/Mips/insn-zero-size-bb.ll b/llvm/test/CodeGen/Mips/insn-zero-size-bb.ll
index d5d3ac3e1951a24..a5c16f8c45322e2 100644
--- a/llvm/test/CodeGen/Mips/insn-zero-size-bb.ll
+++ b/llvm/test/CodeGen/Mips/insn-zero-size-bb.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s
-; RUN: llc < %s -march=mips -mattr=mips16 | FileCheck %s
+; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s
+; RUN: llc < %s -mtriple=mips -mattr=mips16 | FileCheck %s
; Verify that we emit the .insn directive for zero-sized (empty) basic blocks.
; This only really matters for microMIPS and MIPS16.
diff --git a/llvm/test/CodeGen/Mips/lw16-base-reg.ll b/llvm/test/CodeGen/Mips/lw16-base-reg.ll
index f43e02e8d061653..c236b9a24b85fb9 100644
--- a/llvm/test/CodeGen/Mips/lw16-base-reg.ll
+++ b/llvm/test/CodeGen/Mips/lw16-base-reg.ll
@@ -1,4 +1,4 @@
-; RUN: llc %s -march=mips -mcpu=mips32r3 -mattr=micromips -filetype=asm \
+; RUN: llc %s -mtriple=mips -mcpu=mips32r3 -mattr=micromips -filetype=asm \
; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
; The purpose of this test is to check whether the CodeGen selects
diff --git a/llvm/test/CodeGen/Mips/mips16ex.ll b/llvm/test/CodeGen/Mips/mips16ex.ll
index 609f53bae649270..7dbccc7b223bdf9 100644
--- a/llvm/test/CodeGen/Mips/mips16ex.ll
+++ b/llvm/test/CodeGen/Mips/mips16ex.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
;16: main:
;16-NEXT: [[TMP:.*]]:
diff --git a/llvm/test/CodeGen/RISCV/dwarf-eh.ll b/llvm/test/CodeGen/RISCV/dwarf-eh.ll
index 2117c0cbd390fe9..39cc0d52c9fe184 100644
--- a/llvm/test/CodeGen/RISCV/dwarf-eh.ll
+++ b/llvm/test/CodeGen/RISCV/dwarf-eh.ll
@@ -1,18 +1,18 @@
-; RUN: llc -march=riscv32 --code-model=small < %s \
+; RUN: llc -mtriple=riscv32 --code-model=small < %s \
; RUN: | FileCheck %s
-; RUN: llc -march=riscv32 --code-model=medium < %s \
+; RUN: llc -mtriple=riscv32 --code-model=medium < %s \
; RUN: | FileCheck %s
-; RUN: llc -march=riscv32 --code-model=small -relocation-model=pic < %s \
+; RUN: llc -mtriple=riscv32 --code-model=small -relocation-model=pic < %s \
; RUN: | FileCheck %s
-; RUN: llc -march=riscv32 --code-model=medium -relocation-model=pic < %s \
+; RUN: llc -mtriple=riscv32 --code-model=medium -relocation-model=pic < %s \
; RUN: | FileCheck %s
-; RUN: llc -march=riscv64 --code-model=small < %s \
+; RUN: llc -mtriple=riscv64 --code-model=small < %s \
; RUN: | FileCheck %s
-; RUN: llc -march=riscv64 --code-model=medium < %s \
+; RUN: llc -mtriple=riscv64 --code-model=medium < %s \
; RUN: | FileCheck %s
-; RUN: llc -march=riscv64 --code-model=small -relocation-model=pic < %s \
+; RUN: llc -mtriple=riscv64 --code-model=small -relocation-model=pic < %s \
; RUN: | FileCheck %s
-; RUN: llc -march=riscv64 --code-model=medium -relocation-model=pic < %s \
+; RUN: llc -mtriple=riscv64 --code-model=medium -relocation-model=pic < %s \
; RUN: | FileCheck %s
declare void @throw_exception()
diff --git a/llvm/test/MC/Hexagon/inst_add.ll b/llvm/test/MC/Hexagon/inst_add.ll
index 826776952e05098..3e8e3fb98c27cc9 100644
--- a/llvm/test/MC/Hexagon/inst_add.ll
+++ b/llvm/test/MC/Hexagon/inst_add.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -filetype=obj %s -o - \
+; RUN: llc -mtriple=hexagon -filetype=obj %s -o - \
; RUN: | llvm-objdump -d - | FileCheck %s
define i32 @foo (i32 %a, i32 %b)
diff --git a/llvm/test/MC/Hexagon/inst_select.ll b/llvm/test/MC/Hexagon/inst_select.ll
index e7a8a32e89cbfc2..1f5b8238f2d1bb1 100644
--- a/llvm/test/MC/Hexagon/inst_select.ll
+++ b/llvm/test/MC/Hexagon/inst_select.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -filetype=obj %s -o - \
+; RUN: llc -mtriple=hexagon -filetype=obj %s -o - \
; RUN: | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
define i32 @foo (i1 %a, i32 %b, i32 %c)
diff --git a/llvm/test/MC/Hexagon/inst_sxtb.ll b/llvm/test/MC/Hexagon/inst_sxtb.ll
index 34219c72c99ee10..df4b5bcfa5937af 100644
--- a/llvm/test/MC/Hexagon/inst_sxtb.ll
+++ b/llvm/test/MC/Hexagon/inst_sxtb.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -filetype=obj %s -o - \
+; RUN: llc -mtriple=hexagon -filetype=obj %s -o - \
; RUN: | llvm-objdump -d - | FileCheck %s
define i32 @foo (i8 %a)
diff --git a/llvm/test/MC/Hexagon/inst_zxtb.ll b/llvm/test/MC/Hexagon/inst_zxtb.ll
index 86da5e52cac1dd0..b74fc2207088b75 100644
--- a/llvm/test/MC/Hexagon/inst_zxtb.ll
+++ b/llvm/test/MC/Hexagon/inst_zxtb.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -filetype=obj %s -o - \
+; RUN: llc -mtriple=hexagon -filetype=obj %s -o - \
; RUN: | llvm-objdump -d - | FileCheck %s
define i32 @foo (i8 %a)
diff --git a/llvm/test/MC/Hexagon/inst_zxth.ll b/llvm/test/MC/Hexagon/inst_zxth.ll
index 7b3d1b30648c109..90bbed7044ee2c8 100644
--- a/llvm/test/MC/Hexagon/inst_zxth.ll
+++ b/llvm/test/MC/Hexagon/inst_zxth.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -filetype=obj %s -o - \
+; RUN: llc -mtriple=hexagon -filetype=obj %s -o - \
; RUN: | llvm-objdump -d - | FileCheck %s
define i32 @foo (i16 %a)
diff --git a/llvm/test/MC/Hexagon/v62a.s b/llvm/test/MC/Hexagon/v62a.s
index 968608c1c8b7234..206f7777046a07e 100644
--- a/llvm/test/MC/Hexagon/v62a.s
+++ b/llvm/test/MC/Hexagon/v62a.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -o - %s | llvm-objdump --triple=hexagon --triple=hexagon --mcpu=hexagonv62 -d - | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv62 -filetype=obj -o - %s | llvm-objdump --triple=hexagon --triple=hexagon --mcpu=hexagonv62 -d - | FileCheck %s
r31:30=vabsdiffb(r29:28, r27:26)
# CHECK: e8fadc1e { r31:30 = vabsdiffb(r29:28,r27:26)
diff --git a/llvm/test/MC/Mips/mips64shift.ll b/llvm/test/MC/Mips/mips64shift.ll
index 288e4460d02357e..0d8cdad9c5c13a2 100644
--- a/llvm/test/MC/Mips/mips64shift.ll
+++ b/llvm/test/MC/Mips/mips64shift.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler %s -o - \
+; RUN: llc -mtriple=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler %s -o - \
; RUN: | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
-; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - \
+; RUN: llc -mtriple=mips64el -filetype=obj -mcpu=mips64r2 %s -o - \
; RUN: | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
define i64 @f3(i64 %a0) nounwind readnone {
diff --git a/llvm/test/MC/Mips/multi-64bit-func.ll b/llvm/test/MC/Mips/multi-64bit-func.ll
index 83577aa1628bd39..909399dcdb40cf7 100644
--- a/llvm/test/MC/Mips/multi-64bit-func.ll
+++ b/llvm/test/MC/Mips/multi-64bit-func.ll
@@ -1,8 +1,8 @@
; There is no real check here. If the test doesn't
; assert it passes.
-; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler < %s
+; RUN: llc -mtriple=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler < %s
; Run it again without extra nop in delay slot
-; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 < %s
+; RUN: llc -mtriple=mips64el -filetype=obj -mcpu=mips64r2 < %s
define i32 @bosco1(i32 %x) nounwind readnone {
entry:
diff --git a/llvm/test/MC/Mips/sext_64_32.ll b/llvm/test/MC/Mips/sext_64_32.ll
index ee80b5fa1ae7ced..4f1f739c207a9c1 100644
--- a/llvm/test/MC/Mips/sext_64_32.ll
+++ b/llvm/test/MC/Mips/sext_64_32.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | \
+; RUN: llc -mtriple=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | \
; RUN: llvm-objdump --no-print-imm-hex -d - | FileCheck %s
; Sign extend from 32 to 64 was creating nonsense opcodes
diff --git a/llvm/test/MC/Mips/sort-relocation-table.s b/llvm/test/MC/Mips/sort-relocation-table.s
index a6068ed76fc6da3..cc951956fd24a09 100644
--- a/llvm/test/MC/Mips/sort-relocation-table.s
+++ b/llvm/test/MC/Mips/sort-relocation-table.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -filetype=obj -arch mipsel %s | llvm-readobj -r - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=mipsel %s | llvm-readobj -r - | FileCheck %s
# Test the order of records in the relocation table.
#
>From 21051b40a1d03a9e91efba375bde8c922bfc961e Mon Sep 17 00:00:00 2001
From: Fangrui Song <i at maskray.me>
Date: Mon, 11 Sep 2023 15:18:32 -0700
Subject: [PATCH 27/35] [test] debug-info-correlate.ll requires an ELF target
triple
The test only applies to ELF. On Linux, when a default target triple is, say,
Mach-O, the test should be excluded as well.
---
.../test/Instrumentation/InstrProfiling/debug-info-correlate.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/Instrumentation/InstrProfiling/debug-info-correlate.ll b/llvm/test/Instrumentation/InstrProfiling/debug-info-correlate.ll
index 6ab7f055602cb2b..fd868ead5b78d21 100644
--- a/llvm/test/Instrumentation/InstrProfiling/debug-info-correlate.ll
+++ b/llvm/test/Instrumentation/InstrProfiling/debug-info-correlate.ll
@@ -2,7 +2,7 @@
; RUN: FileCheck < %t.ll --implicit-check-not "{{__llvm_prf_data|__llvm_prf_names}}" %s
; RUN: %llc_dwarf -O0 -filetype=obj < %t.ll | llvm-dwarfdump - | FileCheck --implicit-check-not "{{DW_TAG|NULL}}" %s --check-prefix CHECK-DWARF
-; REQUIRES: system-linux, object-emission
+; REQUIRES: target={{.*-linux.*}}, object-emission
@__profn_foo = private constant [3 x i8] c"foo"
; CHECK: @__profc_foo =
>From dba3333335ca1d864052e7cb53cc3167e34390ee Mon Sep 17 00:00:00 2001
From: erichkeane <ekeane at nvidia.com>
Date: Mon, 11 Sep 2023 15:32:16 -0700
Subject: [PATCH 28/35] Fix a few messed up links in the ReleaseNotes
---
clang/docs/ReleaseNotes.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index cc8b2c3808933cb..fc0972c20476d09 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -215,7 +215,7 @@ Bug Fixes in This Version
- Support MSVC predefined macro expressions in constant expressions and in
local structs.
- Correctly parse non-ascii identifiers that appear immediately after a line splicing
- (`#65156 <https://github.com/llvm/llvm-project/issues/65156>`_`)
+ (`#65156 <https://github.com/llvm/llvm-project/issues/65156>`_)
- Clang no longer considers the loss of ``__unaligned`` qualifier from objects as
an invalid conversion during method function overload resolution.
@@ -272,8 +272,8 @@ Bug Fixes to C++ Support
- Fix crash when the trailing return type of a generic and dependent
lambda refers to an init-capture.
- (`#65067 <https://github.com/llvm/llvm-project/issues/65067>`_` and
- `#63675 <https://github.com/llvm/llvm-project/issues/63675>`_`)
+ (`#65067 <https://github.com/llvm/llvm-project/issues/65067>`_ and
+ `#63675 <https://github.com/llvm/llvm-project/issues/63675>`_)
Bug Fixes to AST Handling
^^^^^^^^^^^^^^^^^^^^^^^^^
>From d48a0e8693ae7cf3f9ef4c497a1171588cfd6eed Mon Sep 17 00:00:00 2001
From: Amir Ayupov <aaupov at fb.com>
Date: Mon, 11 Sep 2023 15:53:38 -0700
Subject: [PATCH 29/35] [BOLT][NFC] Use formatv in DataAggregator/DataReader
prints
Reviewed By: #bolt, maksfb
Differential Revision: https://reviews.llvm.org/D154120
---
bolt/lib/Profile/DataAggregator.cpp | 37 +++++++++++------------------
bolt/lib/Profile/DataReader.cpp | 5 ++--
2 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/bolt/lib/Profile/DataAggregator.cpp b/bolt/lib/Profile/DataAggregator.cpp
index 02f7032c2c7e125..619b9aabd1b89b7 100644
--- a/bolt/lib/Profile/DataAggregator.cpp
+++ b/bolt/lib/Profile/DataAggregator.cpp
@@ -397,28 +397,20 @@ std::error_code DataAggregator::writeAutoFDOData(StringRef OutputFilename) {
};
OutFile << FallthroughLBRs.size() << "\n";
- for (const auto &AggrLBR : FallthroughLBRs) {
- const Trace &Trace = AggrLBR.first;
- const FTInfo &Info = AggrLBR.second;
- OutFile << Twine::utohexstr(filterAddress(Trace.From)) << "-"
- << Twine::utohexstr(filterAddress(Trace.To)) << ":"
- << (Info.InternCount + Info.ExternCount) << "\n";
+ for (const auto &[Trace, Info] : FallthroughLBRs) {
+ OutFile << formatv("{0:x}-{1:x}:{2}\n", filterAddress(Trace.From),
+ filterAddress(Trace.To),
+ Info.InternCount + Info.ExternCount);
}
OutFile << BasicSamples.size() << "\n";
- for (const auto &Sample : BasicSamples) {
- uint64_t PC = Sample.first;
- uint64_t HitCount = Sample.second;
- OutFile << Twine::utohexstr(filterAddress(PC)) << ":" << HitCount << "\n";
- }
+ for (const auto [PC, HitCount] : BasicSamples)
+ OutFile << formatv("{0:x}:{1}\n", filterAddress(PC), HitCount);
OutFile << BranchLBRs.size() << "\n";
- for (const auto &AggrLBR : BranchLBRs) {
- const Trace &Trace = AggrLBR.first;
- const BranchInfo &Info = AggrLBR.second;
- OutFile << Twine::utohexstr(filterAddress(Trace.From)) << "->"
- << Twine::utohexstr(filterAddress(Trace.To)) << ":"
- << Info.TakenCount << "\n";
+ for (const auto &[Trace, Info] : BranchLBRs) {
+ OutFile << formatv("{0:x}->{1:x}:{2}\n", filterAddress(Trace.From),
+ filterAddress(Trace.To), Info.TakenCount);
}
outs() << "PERF2BOLT: wrote " << FallthroughLBRs.size() << " unique traces, "
@@ -1983,12 +1975,11 @@ std::error_code DataAggregator::parseMMapEvents() {
}
LLVM_DEBUG({
- dbgs() << "FileName -> mmap info:\n";
- for (const std::pair<const StringRef, MMapInfo> &Pair : GlobalMMapInfo)
- dbgs() << " " << Pair.first << " : " << Pair.second.PID << " [0x"
- << Twine::utohexstr(Pair.second.MMapAddress) << ", "
- << Twine::utohexstr(Pair.second.Size) << " @ "
- << Twine::utohexstr(Pair.second.Offset) << "]\n";
+ dbgs() << "FileName -> mmap info:\n"
+ << " Filename : PID [MMapAddr, Size, Offset]\n";
+ for (const auto &[Name, MMap] : GlobalMMapInfo)
+ dbgs() << formatv(" {0} : {1} [{2:x}, {3:x} @ {4:x}]\n", Name, MMap.PID,
+ MMap.MMapAddress, MMap.Size, MMap.Offset);
});
StringRef NameToUse = llvm::sys::path::filename(BC->getFilename());
diff --git a/bolt/lib/Profile/DataReader.cpp b/bolt/lib/Profile/DataReader.cpp
index 0e12e8cb307002d..64873e0de4bab55 100644
--- a/bolt/lib/Profile/DataReader.cpp
+++ b/bolt/lib/Profile/DataReader.cpp
@@ -785,9 +785,8 @@ bool DataReader::recordBranch(BinaryFunction &BF, uint64_t From, uint64_t To,
FTBI.MispredictedCount += Mispreds;
ToBB = FTSuccessor;
} else {
- LLVM_DEBUG(dbgs() << "invalid branch in " << BF << '\n'
- << Twine::utohexstr(From) << " -> "
- << Twine::utohexstr(To) << '\n');
+ LLVM_DEBUG(dbgs() << "invalid branch in " << BF
+ << formatv(": {0:x} -> {1:x}\n", From, To));
return false;
}
}
>From e946ee1cb89d470f32596ab1513993466ecb87eb Mon Sep 17 00:00:00 2001
From: Amir Ayupov <aaupov at meta.com>
Date: Wed, 30 Aug 2023 18:59:48 -0700
Subject: [PATCH 30/35] [BOLT][NFC] Speedup YAML profile processing
Reduce YAML profile processing times:
- preprocessProfile: speed up buildNameMaps by replacing ProfileNameToProfile
mapping with ProfileFunctionNames set and ProfileBFs vector.
Pre-look up YamlBF->BF correspondence, memoize in ProfileBFs.
- readProfile: replace iteration over all functions in the binary by iteration
over profile functions (strict match and LTO name match).
On a large binary (1.9M functions) and large YAML profile (121MB, 30k functions)
reduces profile steps runtime:
pre-process profile data: 12.4953s -> 10.7123s
process profile data: 9.8195s -> 5.6639s
Compared to fdata profile reading:
pre-process profile data: 8.0268s
process profile data: 1.0265s
process profile data pre-CFG: 0.1644s
Reviewed By: #bolt, maksfb
Differential Revision: https://reviews.llvm.org/D159460
---
bolt/include/bolt/Profile/YAMLProfileReader.h | 11 +-
bolt/lib/Profile/YAMLProfileReader.cpp | 139 +++++++-----------
2 files changed, 64 insertions(+), 86 deletions(-)
diff --git a/bolt/include/bolt/Profile/YAMLProfileReader.h b/bolt/include/bolt/Profile/YAMLProfileReader.h
index f7cb52e151b606a..7a8aa176c30f1a2 100644
--- a/bolt/include/bolt/Profile/YAMLProfileReader.h
+++ b/bolt/include/bolt/Profile/YAMLProfileReader.h
@@ -61,10 +61,13 @@ class YAMLProfileReader : public ProfileReaderBase {
StringMap<std::vector<yaml::bolt::BinaryFunctionProfile *>> LTOCommonNameMap;
/// Map a common LTO prefix to a set of binary functions.
- StringMap<FunctionSet> LTOCommonNameFunctionMap;
+ StringMap<std::unordered_set<BinaryFunction *>> LTOCommonNameFunctionMap;
- /// Strict matching of a name in a profile to its contents.
- StringMap<yaml::bolt::BinaryFunctionProfile *> ProfileNameToProfile;
+ /// Function names in profile.
+ StringSet<> ProfileFunctionNames;
+
+ /// BinaryFunction pointers indexed by YamlBP functions.
+ std::vector<BinaryFunction *> ProfileBFs;
/// Populate \p Function profile with the one supplied in YAML format.
bool parseFunctionProfile(BinaryFunction &Function,
@@ -75,7 +78,7 @@ class YAMLProfileReader : public ProfileReaderBase {
const yaml::bolt::BinaryFunctionProfile &YamlBF);
/// Initialize maps for profile matching.
- void buildNameMaps(std::map<uint64_t, BinaryFunction> &Functions);
+ void buildNameMaps(BinaryContext &BC);
/// Update matched YAML -> BinaryFunction pair.
void matchProfileToFunction(yaml::bolt::BinaryFunctionProfile &YamlBF,
diff --git a/bolt/lib/Profile/YAMLProfileReader.cpp b/bolt/lib/Profile/YAMLProfileReader.cpp
index 07f32f61541dbd0..d20167bcc74205f 100644
--- a/bolt/lib/Profile/YAMLProfileReader.cpp
+++ b/bolt/lib/Profile/YAMLProfileReader.cpp
@@ -12,6 +12,7 @@
#include "bolt/Passes/MCF.h"
#include "bolt/Profile/ProfileYAMLMapping.h"
#include "bolt/Utils/Utils.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/CommandLine.h"
using namespace llvm;
@@ -45,27 +46,34 @@ bool YAMLProfileReader::isYAML(const StringRef Filename) {
return false;
}
-void YAMLProfileReader::buildNameMaps(
- std::map<uint64_t, BinaryFunction> &Functions) {
+void YAMLProfileReader::buildNameMaps(BinaryContext &BC) {
+ auto lookupFunction = [&](StringRef Name) -> BinaryFunction * {
+ if (BinaryData *BD = BC.getBinaryDataByName(Name))
+ return BC.getFunctionForSymbol(BD->getSymbol());
+ return nullptr;
+ };
+
+ ProfileBFs.reserve(YamlBP.Functions.size());
+
for (yaml::bolt::BinaryFunctionProfile &YamlBF : YamlBP.Functions) {
StringRef Name = YamlBF.Name;
const size_t Pos = Name.find("(*");
if (Pos != StringRef::npos)
Name = Name.substr(0, Pos);
- ProfileNameToProfile[Name] = &YamlBF;
+ ProfileFunctionNames.insert(Name);
+ ProfileBFs.push_back(lookupFunction(Name));
if (const std::optional<StringRef> CommonName = getLTOCommonName(Name))
LTOCommonNameMap[*CommonName].push_back(&YamlBF);
}
- for (auto &BFI : Functions) {
- const BinaryFunction &Function = BFI.second;
- for (StringRef Name : Function.getNames())
- if (const std::optional<StringRef> CommonName = getLTOCommonName(Name))
- LTOCommonNameFunctionMap[*CommonName].insert(&Function);
+ for (auto &[Symbol, BF] : BC.SymbolToFunctionMap) {
+ StringRef Name = Symbol->getName();
+ if (const std::optional<StringRef> CommonName = getLTOCommonName(Name))
+ LTOCommonNameFunctionMap[*CommonName].insert(BF);
}
}
bool YAMLProfileReader::hasLocalsWithFileName() const {
- return llvm::any_of(ProfileNameToProfile.keys(), [](StringRef FuncName) {
+ return llvm::any_of(ProfileFunctionNames.keys(), [](StringRef FuncName) {
return FuncName.count('/') == 2 && FuncName[0] != '/';
});
}
@@ -283,28 +291,21 @@ Error YAMLProfileReader::preprocessProfile(BinaryContext &BC) {
inconvertibleErrorCode());
// Match profile to function based on a function name.
- buildNameMaps(BC.getBinaryFunctions());
+ buildNameMaps(BC);
// Preliminary assign function execution count.
- for (auto &KV : BC.getBinaryFunctions()) {
- BinaryFunction &BF = KV.second;
- for (StringRef Name : BF.getNames()) {
- auto PI = ProfileNameToProfile.find(Name);
- if (PI != ProfileNameToProfile.end()) {
- yaml::bolt::BinaryFunctionProfile &YamlBF = *PI->getValue();
- BF.setExecutionCount(YamlBF.ExecCount);
- break;
- }
- }
- }
+ for (auto [YamlBF, BF] : llvm::zip_equal(YamlBP.Functions, ProfileBFs))
+ if (BF)
+ BF->setExecutionCount(YamlBF.ExecCount);
return Error::success();
}
bool YAMLProfileReader::mayHaveProfileData(const BinaryFunction &BF) {
- for (StringRef Name : BF.getNames()) {
- if (ProfileNameToProfile.contains(Name))
+ for (StringRef Name : BF.getNames())
+ if (ProfileFunctionNames.contains(Name))
return true;
+ for (StringRef Name : BF.getNames()) {
if (const std::optional<StringRef> CommonName = getLTOCommonName(Name)) {
if (LTOCommonNameMap.contains(*CommonName))
return true;
@@ -327,9 +328,10 @@ Error YAMLProfileReader::readProfile(BinaryContext &BC) {
// We have to do 2 passes since LTO introduces an ambiguity in function
// names. The first pass assigns profiles that match 100% by name and
// by hash. The second pass allows name ambiguity for LTO private functions.
- for (auto &BFI : BC.getBinaryFunctions()) {
- BinaryFunction &Function = BFI.second;
-
+ for (auto [YamlBF, BF] : llvm::zip_equal(YamlBP.Functions, ProfileBFs)) {
+ if (!BF)
+ continue;
+ BinaryFunction &Function = *BF;
// Clear function call count that may have been set while pre-processing
// the profile.
Function.setExecutionCount(BinaryFunction::COUNT_NO_PROFILE);
@@ -338,69 +340,42 @@ Error YAMLProfileReader::readProfile(BinaryContext &BC) {
if (!opts::IgnoreHash)
Function.computeHash(YamlBP.Header.IsDFSOrder);
- for (StringRef FunctionName : Function.getNames()) {
- auto PI = ProfileNameToProfile.find(FunctionName);
- if (PI == ProfileNameToProfile.end())
- continue;
-
- yaml::bolt::BinaryFunctionProfile &YamlBF = *PI->getValue();
- if (profileMatches(YamlBF, Function)) {
- matchProfileToFunction(YamlBF, Function);
- break;
- }
- }
+ if (profileMatches(YamlBF, Function))
+ matchProfileToFunction(YamlBF, Function);
}
- for (auto &BFI : BC.getBinaryFunctions()) {
- BinaryFunction &Function = BFI.second;
-
- if (ProfiledFunctions.count(&Function))
+ for (auto &[CommonName, LTOProfiles]: LTOCommonNameMap) {
+ if (!LTOCommonNameFunctionMap.contains(CommonName))
continue;
-
- for (StringRef FunctionName : Function.getNames()) {
- const std::optional<StringRef> CommonName =
- getLTOCommonName(FunctionName);
- if (CommonName) {
- auto I = LTOCommonNameMap.find(*CommonName);
- if (I == LTOCommonNameMap.end())
- continue;
-
- bool ProfileMatched = false;
- std::vector<yaml::bolt::BinaryFunctionProfile *> <OProfiles =
- I->getValue();
- for (yaml::bolt::BinaryFunctionProfile *YamlBF : LTOProfiles) {
- if (YamlBF->Used)
- continue;
- if ((ProfileMatched = profileMatches(*YamlBF, Function))) {
- matchProfileToFunction(*YamlBF, Function);
- break;
- }
- }
- if (ProfileMatched)
- break;
-
- // If there's only one function with a given name, try to
- // match it partially.
- if (LTOProfiles.size() == 1 &&
- LTOCommonNameFunctionMap[*CommonName].size() == 1 &&
- !LTOProfiles.front()->Used) {
- matchProfileToFunction(*LTOProfiles.front(), Function);
- break;
- }
- } else {
- auto PI = ProfileNameToProfile.find(FunctionName);
- if (PI == ProfileNameToProfile.end())
- continue;
-
- yaml::bolt::BinaryFunctionProfile &YamlBF = *PI->getValue();
- if (!YamlBF.Used) {
- matchProfileToFunction(YamlBF, Function);
- break;
+ std::unordered_set<BinaryFunction *> &Functions =
+ LTOCommonNameFunctionMap[CommonName];
+ // Return true if a given profile is matched to one of BinaryFunctions with
+ // matching LTO common name.
+ auto matchProfile = [&](yaml::bolt::BinaryFunctionProfile *YamlBF) {
+ if (YamlBF->Used)
+ return false;
+ for (BinaryFunction *BF : Functions) {
+ if (!ProfiledFunctions.count(BF) && profileMatches(*YamlBF, *BF)) {
+ matchProfileToFunction(*YamlBF, *BF);
+ return true;
}
}
- }
+ return false;
+ };
+ bool ProfileMatched = llvm::any_of(LTOProfiles, matchProfile);
+
+ // If there's only one function with a given name, try to match it
+ // partially.
+ if (!ProfileMatched && LTOProfiles.size() == 1 && Functions.size() == 1 &&
+ !LTOProfiles.front()->Used &&
+ !ProfiledFunctions.count(*Functions.begin()))
+ matchProfileToFunction(*LTOProfiles.front(), **Functions.begin());
}
+ for (auto [YamlBF, BF] : llvm::zip_equal(YamlBP.Functions, ProfileBFs))
+ if (!YamlBF.Used && BF && !ProfiledFunctions.count(BF))
+ matchProfileToFunction(YamlBF, *BF);
+
for (yaml::bolt::BinaryFunctionProfile &YamlBF : YamlBP.Functions)
if (!YamlBF.Used && opts::Verbosity >= 1)
errs() << "BOLT-WARNING: profile ignored for function " << YamlBF.Name
>From a6da9a9240cab8ac6daf98353404c9e699d3c932 Mon Sep 17 00:00:00 2001
From: yinying-lisa-li <107574043+yinying-lisa-li at users.noreply.github.com>
Date: Mon, 11 Sep 2023 23:13:15 +0000
Subject: [PATCH 31/35] [mlir][sparse] Fix bug in new syntax parser (#66024)
Currently, dimlvlmap with identity affine map will be treated as empty
affine map. But the new syntax would treat it as an actual identity
affine map such as {d0} -> {d0}. This mismatch could raise an error when
we are comparing sparse encodings.
---
mlir/lib/Dialect/SparseTensor/IR/Detail/DimLvlMap.cpp | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/mlir/lib/Dialect/SparseTensor/IR/Detail/DimLvlMap.cpp b/mlir/lib/Dialect/SparseTensor/IR/Detail/DimLvlMap.cpp
index 81302f200f686bb..05fce96043826f1 100644
--- a/mlir/lib/Dialect/SparseTensor/IR/Detail/DimLvlMap.cpp
+++ b/mlir/lib/Dialect/SparseTensor/IR/Detail/DimLvlMap.cpp
@@ -348,7 +348,9 @@ AffineMap DimLvlMap::getDimToLvlMap(MLIRContext *context) const {
lvlAffines.reserve(getLvlRank());
for (const auto &lvlSpec : lvlSpecs)
lvlAffines.push_back(lvlSpec.getExpr().getAffineExpr());
- return AffineMap::get(getDimRank(), getSymRank(), lvlAffines, context);
+ auto map = AffineMap::get(getDimRank(), getSymRank(), lvlAffines, context);
+ if (map.isIdentity()) return AffineMap();
+ return map;
}
AffineMap DimLvlMap::getLvlToDimMap(MLIRContext *context) const {
@@ -356,7 +358,9 @@ AffineMap DimLvlMap::getLvlToDimMap(MLIRContext *context) const {
dimAffines.reserve(getDimRank());
for (const auto &dimSpec : dimSpecs)
dimAffines.push_back(dimSpec.getExpr().getAffineExpr());
- return AffineMap::get(getLvlRank(), getSymRank(), dimAffines, context);
+ auto map = AffineMap::get(getLvlRank(), getSymRank(), dimAffines, context);
+ if (map.isIdentity()) return AffineMap();
+ return map;
}
void DimLvlMap::dump() const {
>From c38cc5423acb368a07de905a5733f8809e0d8703 Mon Sep 17 00:00:00 2001
From: Christopher Di Bella <cjdb.ns at gmail.com>
Date: Sat, 22 Oct 2022 22:54:38 -0700
Subject: [PATCH 32/35] adds `__reference_constructs_from_temporary`
This is information that the compiler already has, and should be exposed
so that the library doesn't need to reimplement the exact same
functionality.
Differential Revision: https://reviews.llvm.org/D135341
---
clang/docs/LanguageExtensions.rst | 4 +++
clang/include/clang/Basic/TokenKinds.def | 1 +
clang/lib/Lex/PPMacroExpansion.cpp | 1 +
clang/lib/Parse/ParseDeclCXX.cpp | 4 ++-
clang/lib/Parse/ParseExpr.cpp | 2 ++
clang/lib/Sema/SemaExprCXX.cpp | 24 ++++++++++---
clang/test/SemaCXX/type-traits.cpp | 45 ++++++++++++++++++++++++
clang/www/cxx_status.html | 7 ++--
8 files changed, 78 insertions(+), 10 deletions(-)
diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst
index 11cbdca7a268fc3..b9466b5a0bc2087 100644
--- a/clang/docs/LanguageExtensions.rst
+++ b/clang/docs/LanguageExtensions.rst
@@ -1621,6 +1621,10 @@ The following type trait primitives are supported by Clang. Those traits marked
materialized temporary object. If ``T`` is not a reference type the result
is false. Note this trait will also return false when the initialization of
``T`` from ``U`` is ill-formed.
+ Deprecated, use ``__reference_constructs_from_temporary``.
+* ``__reference_constructs_from_temporary(T, U)`` (C++)
+ Returns true if a reference ``T`` can be constructed from a temporary of type
+ a non-cv-qualified ``U``.
* ``__underlying_type`` (C++, GNU, Microsoft)
In addition, the following expression traits are supported:
diff --git a/clang/include/clang/Basic/TokenKinds.def b/clang/include/clang/Basic/TokenKinds.def
index 45ebc200b168986..72e8df8c793a7b6 100644
--- a/clang/include/clang/Basic/TokenKinds.def
+++ b/clang/include/clang/Basic/TokenKinds.def
@@ -531,6 +531,7 @@ TYPE_TRAIT_1(__is_scoped_enum, IsScopedEnum, KEYCXX)
TYPE_TRAIT_1(__is_referenceable, IsReferenceable, KEYCXX)
TYPE_TRAIT_1(__can_pass_in_regs, CanPassInRegs, KEYCXX)
TYPE_TRAIT_2(__reference_binds_to_temporary, ReferenceBindsToTemporary, KEYCXX)
+TYPE_TRAIT_2(__reference_constructs_from_temporary, ReferenceConstructsFromTemporary, KEYCXX)
// Embarcadero Expression Traits
EXPRESSION_TRAIT(__is_lvalue_expr, IsLValueExpr, KEYCXX)
diff --git a/clang/lib/Lex/PPMacroExpansion.cpp b/clang/lib/Lex/PPMacroExpansion.cpp
index 775cbfafa999602..ec6a084f228f32d 100644
--- a/clang/lib/Lex/PPMacroExpansion.cpp
+++ b/clang/lib/Lex/PPMacroExpansion.cpp
@@ -1695,6 +1695,7 @@ void Preprocessor::ExpandBuiltinMacro(Token &Tok) {
.Case("__array_rank", true)
.Case("__array_extent", true)
.Case("__reference_binds_to_temporary", true)
+ .Case("__reference_constructs_from_temporary", true)
#define TRANSFORM_TYPE_TRAIT_DEF(_, Trait) .Case("__" #Trait, true)
#include "clang/Basic/TransformTypeTraits.def"
.Default(false);
diff --git a/clang/lib/Parse/ParseDeclCXX.cpp b/clang/lib/Parse/ParseDeclCXX.cpp
index 730b6e55246d6b7..5fe9abb1fdcab30 100644
--- a/clang/lib/Parse/ParseDeclCXX.cpp
+++ b/clang/lib/Parse/ParseDeclCXX.cpp
@@ -1655,7 +1655,9 @@ void Parser::ParseClassSpecifier(tok::TokenKind TagTokKind,
tok::kw___is_union,
tok::kw___is_unsigned,
tok::kw___is_void,
- tok::kw___is_volatile))
+ tok::kw___is_volatile,
+ tok::kw___reference_binds_to_temporary,
+ tok::kw___reference_constructs_from_temporary))
// GNU libstdc++ 4.2 and libc++ use certain intrinsic names as the
// name of struct templates, but some are keywords in GCC >= 4.3
// and Clang. Therefore, when we see the token sequence "struct
diff --git a/clang/lib/Parse/ParseExpr.cpp b/clang/lib/Parse/ParseExpr.cpp
index f8bf785da2896a3..74664c34abdbd89 100644
--- a/clang/lib/Parse/ParseExpr.cpp
+++ b/clang/lib/Parse/ParseExpr.cpp
@@ -1128,6 +1128,8 @@ ExprResult Parser::ParseCastExpression(CastParseKind ParseKind,
REVERTIBLE_TYPE_TRAIT(__is_unsigned);
REVERTIBLE_TYPE_TRAIT(__is_void);
REVERTIBLE_TYPE_TRAIT(__is_volatile);
+ REVERTIBLE_TYPE_TRAIT(__reference_binds_to_temporary);
+ REVERTIBLE_TYPE_TRAIT(__reference_constructs_from_temporary);
#define TRANSFORM_TYPE_TRAIT_DEF(_, Trait) \
REVERTIBLE_TYPE_TRAIT(RTT_JOIN(__, Trait));
#include "clang/Basic/TransformTypeTraits.def"
diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp
index a7be01319a72393..65e8edc7806ecd8 100644
--- a/clang/lib/Sema/SemaExprCXX.cpp
+++ b/clang/lib/Sema/SemaExprCXX.cpp
@@ -30,6 +30,7 @@
#include "clang/Basic/TargetInfo.h"
#include "clang/Basic/TokenKinds.h"
#include "clang/Basic/TypeTraits.h"
+#include "clang/Basic/TokenKinds.h"
#include "clang/Lex/Preprocessor.h"
#include "clang/Sema/DeclSpec.h"
#include "clang/Sema/EnterExpressionEvaluationContext.h"
@@ -5410,14 +5411,15 @@ static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind,
if (Kind <= UTT_Last)
return EvaluateUnaryTypeTrait(S, Kind, KWLoc, Args[0]->getType());
- // Evaluate BTT_ReferenceBindsToTemporary alongside the IsConstructible
- // traits to avoid duplication.
- if (Kind <= BTT_Last && Kind != BTT_ReferenceBindsToTemporary)
+ // Evaluate ReferenceBindsToTemporary and ReferenceConstructsFromTemporary
+ // alongside the IsConstructible traits to avoid duplication.
+ if (Kind <= BTT_Last && Kind != BTT_ReferenceBindsToTemporary && Kind != BTT_ReferenceConstructsFromTemporary)
return EvaluateBinaryTypeTrait(S, Kind, Args[0]->getType(),
Args[1]->getType(), RParenLoc);
switch (Kind) {
case clang::BTT_ReferenceBindsToTemporary:
+ case clang::BTT_ReferenceConstructsFromTemporary:
case clang::TT_IsConstructible:
case clang::TT_IsNothrowConstructible:
case clang::TT_IsTriviallyConstructible: {
@@ -5494,11 +5496,23 @@ static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind,
if (Kind == clang::TT_IsConstructible)
return true;
- if (Kind == clang::BTT_ReferenceBindsToTemporary) {
+ if (Kind == clang::BTT_ReferenceBindsToTemporary || Kind == clang::BTT_ReferenceConstructsFromTemporary) {
if (!T->isReferenceType())
return false;
- return !Init.isDirectReferenceBinding();
+ if (!Init.isDirectReferenceBinding())
+ return true;
+
+ if (Kind == clang::BTT_ReferenceBindsToTemporary)
+ return false;
+
+ QualType U = Args[1]->getType();
+ if (U->isReferenceType())
+ return false;
+
+ QualType TPtr = S.BuiltinAddPointer(S.BuiltinRemoveReference(T, UnaryTransformType::RemoveCVRef, {}), {});
+ QualType UPtr = S.BuiltinAddPointer(S.BuiltinRemoveReference(U, UnaryTransformType::RemoveCVRef, {}), {});
+ return EvaluateBinaryTypeTrait(S, TypeTrait::BTT_IsConvertibleTo, UPtr, TPtr, RParenLoc);
}
if (Kind == clang::TT_IsNothrowConstructible)
diff --git a/clang/test/SemaCXX/type-traits.cpp b/clang/test/SemaCXX/type-traits.cpp
index 0fb364eaf362664..a35689d52978fcc 100644
--- a/clang/test/SemaCXX/type-traits.cpp
+++ b/clang/test/SemaCXX/type-traits.cpp
@@ -2542,6 +2542,51 @@ void reference_binds_to_temporary_checks() {
{ int arr[T((__reference_binds_to_temporary(const int &, long)))]; }
}
+void reference_constructs_from_temporary_checks() {
+ static_assert(!__reference_constructs_from_temporary(int &, int &), "");
+ static_assert(!__reference_constructs_from_temporary(int &, int &&), "");
+
+ static_assert(!__reference_constructs_from_temporary(int const &, int &), "");
+ static_assert(!__reference_constructs_from_temporary(int const &, int const &), "");
+ static_assert(!__reference_constructs_from_temporary(int const &, int &&), "");
+
+ static_assert(!__reference_constructs_from_temporary(int &, long &), ""); // doesn't construct
+
+ static_assert(__reference_constructs_from_temporary(int const &, long &), "");
+ static_assert(__reference_constructs_from_temporary(int const &, long &&), "");
+ static_assert(__reference_constructs_from_temporary(int &&, long &), "");
+
+ using LRef = ConvertsToRef<int, int &>;
+ using RRef = ConvertsToRef<int, int &&>;
+ using CLRef = ConvertsToRef<int, const int &>;
+ using LongRef = ConvertsToRef<long, long &>;
+ static_assert(__is_constructible(int &, LRef), "");
+ static_assert(!__reference_constructs_from_temporary(int &, LRef), "");
+
+ static_assert(__is_constructible(int &&, RRef), "");
+ static_assert(!__reference_constructs_from_temporary(int &&, RRef), "");
+
+ static_assert(__is_constructible(int const &, CLRef), "");
+ static_assert(!__reference_constructs_from_temporary(int &&, CLRef), "");
+
+ static_assert(__is_constructible(int const &, LongRef), "");
+ static_assert(__reference_constructs_from_temporary(int const &, LongRef), "");
+
+ // Test that it doesn't accept non-reference types as input.
+ static_assert(!__reference_constructs_from_temporary(int, long), "");
+
+ static_assert(__reference_constructs_from_temporary(const int &, long), "");
+
+ // Additional checks
+ static_assert(__reference_constructs_from_temporary(POD const&, Derives), "");
+ static_assert(__reference_constructs_from_temporary(int&&, int), "");
+ static_assert(__reference_constructs_from_temporary(const int&, int), "");
+ static_assert(!__reference_constructs_from_temporary(int&&, int&&), "");
+ static_assert(!__reference_constructs_from_temporary(const int&, int&&), "");
+ static_assert(__reference_constructs_from_temporary(int&&, long&&), "");
+ static_assert(__reference_constructs_from_temporary(int&&, long), "");
+}
+
void array_rank() {
int t01[T(__array_rank(IntAr) == 1)];
int t02[T(__array_rank(ConstIntArAr) == 2)];
diff --git a/clang/www/cxx_status.html b/clang/www/cxx_status.html
index da0a1c219c0ecc7..b0bae88fd5c33d4 100755
--- a/clang/www/cxx_status.html
+++ b/clang/www/cxx_status.html
@@ -292,10 +292,9 @@ <h2 id="cxx23">C++23 implementation status</h2>
<td><a href="https://wg21.link/P2255R2">P2255R2</a></td>
<td class="partial" align="center">
<details><summary>Partial</summary>
- Clang provides a <tt>__reference_binds_to_temporary</tt> type trait
- builtin, with which the library facility can be partially implemented.
- Both <tt>__reference_constructs_from_temporary</tt> and
- <tt>__reference_converts_from_temporary</tt> builtins should be
+ Clang provides <tt>__reference_constructs_from_temporary</tt> type
+ trait builtin, with which <tt>std::reference_constructs_from_temporary</tt>
+ implemented. <tt>__reference_converts_from_temporary</tt> needs to be
provided, following the normal cross-vendor convention to implement
traits requiring compiler support directly.
</details></td>
>From ed23c526675808227ac3435f2730d7447d90b286 Mon Sep 17 00:00:00 2001
From: Konstantin Varlamov <varconsteq at gmail.com>
Date: Mon, 11 Sep 2023 16:17:34 -0700
Subject: [PATCH 33/35] [libc++][ranges] Fix a `split_view` test accidentally
using `lazy_split`
---
.../std/ranges/range.adaptors/range.split/ctor.view.pass.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libcxx/test/std/ranges/range.adaptors/range.split/ctor.view.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.split/ctor.view.pass.cpp
index 963f85f8c478f88..27fc4b84c520659 100644
--- a/libcxx/test/std/ranges/range.adaptors/range.split/ctor.view.pass.cpp
+++ b/libcxx/test/std/ranges/range.adaptors/range.split/ctor.view.pass.cpp
@@ -61,7 +61,7 @@ static_assert( test_convertible<std::ranges::split_view<View, Pattern>, View, Pa
constexpr bool test() {
{
std::string_view input = "abc def";
- std::ranges::lazy_split_view<std::string_view, std::string_view> v(input, " ");
+ std::ranges::split_view<std::string_view, std::string_view> v(input, " ");
assert(v.base() == input);
assert(std::ranges::equal(*v.begin(), std::string_view{"abc"}));
}
>From ea98683abffdb746cb6410931d5ff3a54b7bbbb1 Mon Sep 17 00:00:00 2001
From: Alexey Bader <alexey.bader at intel.com>
Date: Mon, 11 Sep 2023 16:20:51 -0700
Subject: [PATCH 34/35] [Clang][Docs] Fix typo in clang-offload-packager
documentation
Fixed formatting of the section violating 80-char line limit.
---
clang/docs/ClangOffloadPackager.rst | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/clang/docs/ClangOffloadPackager.rst b/clang/docs/ClangOffloadPackager.rst
index 1d6ded952e8adfe..2b985e260e302de 100644
--- a/clang/docs/ClangOffloadPackager.rst
+++ b/clang/docs/ClangOffloadPackager.rst
@@ -124,7 +124,7 @@ array of the :ref:`string entry<table-binary_string>` format.
+----------+--------------+-------------------------------------------------------+
| Type | Identifier | Description |
+==========+==============+=======================================================+
- | uint64_t | key offset | Absolute byte offset of the key in th string table |
+ | uint64_t | key offset | Absolute byte offset of the key in the string table |
+----------+--------------+-------------------------------------------------------+
| uint64_t | value offset | Absolute byte offset of the value in the string table |
+----------+--------------+-------------------------------------------------------+
@@ -145,9 +145,9 @@ Usage
=====
This tool can be used with the following arguments. Generally information is
-passed as a key-value pair to the ``image=`` argument. The ``file`` and ``triple``,
-arguments are considered mandatory to make a valid image. The ``arch`` argument
-is suggested.
+passed as a key-value pair to the ``image=`` argument. The ``file`` and
+``triple``, arguments are considered mandatory to make a valid image.
+The ``arch`` argument is suggested.
.. code-block:: console
>From 5a851d8a972762423bd7e21fb7fec0a24daad187 Mon Sep 17 00:00:00 2001
From: Vitaly Buka <vitalybuka at google.com>
Date: Mon, 11 Sep 2023 16:24:43 -0700
Subject: [PATCH 35/35] [test][hwsasan] Invert enable_aliases check
For some reasons enable_aliases is not set when we
LLVM_ENABLE_RUNTIMES=compiler-rt instead of LLVM_ENABLE_PROJECTS.
---
compiler-rt/test/hwasan/lit.cfg.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/compiler-rt/test/hwasan/lit.cfg.py b/compiler-rt/test/hwasan/lit.cfg.py
index 71a7f96d652eeb7..594f3294a84ac17 100644
--- a/compiler-rt/test/hwasan/lit.cfg.py
+++ b/compiler-rt/test/hwasan/lit.cfg.py
@@ -13,7 +13,7 @@
clang_cxxflags = config.cxx_mode_flags + clang_cflags
clang_hwasan_common_cflags = clang_cflags + ["-fsanitize=hwaddress", "-fuse-ld=lld"]
-if config.target_arch == "x86_64" and config.enable_aliases == "1":
+if config.target_arch == "x86_64" and config.enable_aliases != "0":
clang_hwasan_common_cflags += ["-fsanitize-hwaddress-experimental-aliasing"]
else:
config.available_features.add("pointer-tagging")
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