[llvm] [GIsel][AArch64] Legalize <2 x i16> for G_INSERT_VECTOR_ELT (PR #65830)
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Mon Sep 11 05:02:35 PDT 2023
https://github.com/vfdff updated https://github.com/llvm/llvm-project/pull/65830:
>From 8176ec506e526f418ad55bf87efc9ee04045b87a Mon Sep 17 00:00:00 2001
From: zhongyunde 00443407 <zhongyunde at huawei.com>
Date: Thu, 7 Sep 2023 23:20:10 -0400
Subject: [PATCH] [GIsel][AArch64] Legalize <2 x i16> for G_INSERT_VECTOR_ELT
Widen the vector elements to 64 bits to make sure it legal instead by
clamping the number of elements. refer to commit ccffc27.
Fixes https://github.com/llvm/llvm-project/issues/63826
---
.../llvm/CodeGen/GlobalISel/LegalizerInfo.h | 9 ++-
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 5 +-
.../GlobalISel/insert-vector-elt-pr63826.ll | 42 ++++++++++
.../GlobalISel/legalize-insert-vector-elt.mir | 81 +++++++++++++++----
4 files changed, 115 insertions(+), 22 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/insert-vector-elt-pr63826.ll
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
index d38ff71b1589b56..8b1f5113cd71c20 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
@@ -943,21 +943,24 @@ class LegalizeRuleSet {
/// Ensure the vector size is at least as wide as VectorSize by promoting the
/// element.
- LegalizeRuleSet &widenVectorEltsToVectorMinSize(unsigned TypeIdx,
+ LegalizeRuleSet &widenVectorEltsToVectorMinSize(unsigned PredIdx,
+ unsigned TypeIdx,
unsigned VectorSize) {
using namespace LegalityPredicates;
using namespace LegalizeMutations;
return actionIf(
LegalizeAction::WidenScalar,
[=](const LegalityQuery &Query) {
- const LLT VecTy = Query.Types[TypeIdx];
+ const LLT VecTy = Query.Types[PredIdx];
return VecTy.isVector() && !VecTy.isScalable() &&
VecTy.getSizeInBits() < VectorSize;
},
[=](const LegalityQuery &Query) {
- const LLT VecTy = Query.Types[TypeIdx];
+ const LLT VecTy = Query.Types[PredIdx];
unsigned NumElts = VecTy.getNumElements();
unsigned MinSize = VectorSize / NumElts;
+ if (Query.Types[TypeIdx].isScalar())
+ return std::make_pair(TypeIdx, LLT::scalar(MinSize));
LLT NewTy = LLT::fixed_vector(NumElts, LLT::scalar(MinSize));
return std::make_pair(TypeIdx, NewTy);
});
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 00424f23e96d7d9..1d062b47aa7c8ce 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -718,8 +718,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
.legalIf(typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64}))
- .clampMinNumElements(0, s16, 4)
- .clampMaxNumElements(0, s16, 8);
+ .widenVectorEltsToVectorMinSize(0, 1, 64);
getActionDefinitionsBuilder(G_BUILD_VECTOR)
.legalFor({{v8s8, s8},
@@ -733,7 +732,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampNumElements(0, v4s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
.minScalarOrElt(0, s8)
- .widenVectorEltsToVectorMinSize(0, 64)
+ .widenVectorEltsToVectorMinSize(0, 0, 64)
.minScalarSameAs(1, 0);
getActionDefinitionsBuilder(G_BUILD_VECTOR_TRUNC).lower();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/insert-vector-elt-pr63826.ll b/llvm/test/CodeGen/AArch64/GlobalISel/insert-vector-elt-pr63826.ll
new file mode 100644
index 000000000000000..e41b25fb2b88f14
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/insert-vector-elt-pr63826.ll
@@ -0,0 +1,42 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -o - -verify-machineinstrs -global-isel=1 -global-isel-abort=1 | FileCheck %s --check-prefixes=CHECK
+; RUN: llc < %s -o - -verify-machineinstrs -global-isel=0 | FileCheck %s --check-prefixes=CHECK
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-apple-ios14.5.0"
+
+define <2 x i16> @pr63826_v2s16(<2 x i16> %vec) {
+; CHECK-LABEL: pr63826_v2s16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov w8, #1 ; =0x1
+; CHECK-NEXT: mov.s v0[0], w8
+; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
+ %vec1 = insertelement <2 x i16> %vec, i16 1, i32 0
+ ret <2 x i16> %vec1
+}
+
+define <2 x i8> @pr63826_v2s8(<2 x i8> %vec) {
+; CHECK-LABEL: pr63826_v2s8:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov w8, #1 ; =0x1
+; CHECK-NEXT: mov.s v0[0], w8
+; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
+ %vec1 = insertelement <2 x i8> %vec, i8 1, i32 0
+ ret <2 x i8> %vec1
+}
+
+define <4 x i8> @pr63826_v4s8(<4 x i8> %vec) {
+; CHECK-LABEL: pr63826_v4s8:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov w8, #1 ; =0x1
+; CHECK-NEXT: mov.h v0[0], w8
+; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
+ %vec1 = insertelement <4 x i8> %vec, i8 1, i32 0
+ ret <4 x i8> %vec1
+}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
index 26db18bd611a57c..6f6cf2cc165b9f1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
@@ -1,24 +1,73 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -o - -global-isel-abort=1 | FileCheck %s
---
-name: pr63826
+name: pr63826_v2s16
body: |
bb.0:
- ; CHECK-LABEL: name: pr63826
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $w0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[DEF]](s16), [[DEF]](s16)
- ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[C]](s16), [[C1]](s32)
- ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[IVEC]](<4 x s16>)
- ; CHECK-NEXT: $w0 = COPY [[UV2]](<2 x s16>)
- %0:_(<2 x s16>) = COPY $w0
- %1:_(s16) = G_CONSTANT i16 1
- %2:_(s32) = G_CONSTANT i32 42
- %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %0(<2 x s16>), %1(s16), %2(s32)
- $w0 = COPY %4(<2 x s16>)
+ liveins: $d0
+ ; CHECK-LABEL: name: pr63826_v2s16
+ ; CHECK: liveins: $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s32), [[C]](s32)
+ ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %1:_(<2 x s32>) = COPY $d0
+ %0:_(<2 x s16>) = G_TRUNC %1(<2 x s32>)
+ %4:_(s32) = G_CONSTANT i32 0
+ %3:_(s16) = G_CONSTANT i16 1
+ %2:_(<2 x s16>) = G_INSERT_VECTOR_ELT %0, %3(s16), %4(s32)
+ %5:_(<2 x s32>) = G_ANYEXT %2(<2 x s16>)
+ $d0 = COPY %5(<2 x s32>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: pr63826_v2s8
+body: |
+ bb.0:
+ liveins: $d0
+ ; CHECK-LABEL: name: pr63826_v2s8
+ ; CHECK: liveins: $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s32), [[C]](s32)
+ ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %1:_(<2 x s32>) = COPY $d0
+ %0:_(<2 x s8>) = G_TRUNC %1(<2 x s32>)
+ %4:_(s32) = G_CONSTANT i32 0
+ %3:_(s8) = G_CONSTANT i8 1
+ %2:_(<2 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s32)
+ %5:_(<2 x s32>) = G_ANYEXT %2(<2 x s8>)
+ $d0 = COPY %5(<2 x s32>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: pr63826_v4s8
+body: |
+ bb.0:
+ liveins: $d0
+ ; CHECK-LABEL: name: pr63826_v4s8
+ ; CHECK: liveins: $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s16), [[C]](s32)
+ ; CHECK-NEXT: $d0 = COPY [[IVEC]](<4 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %1:_(<4 x s16>) = COPY $d0
+ %0:_(<4 x s8>) = G_TRUNC %1(<4 x s16>)
+ %4:_(s32) = G_CONSTANT i32 0
+ %3:_(s8) = G_CONSTANT i8 1
+ %2:_(<4 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s32)
+ %5:_(<4 x s16>) = G_ANYEXT %2(<4 x s8>)
+ $d0 = COPY %5(<4 x s16>)
+ RET_ReallyLR implicit $d0
...
---
name: v8s8
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