[llvm] [MC][RISCV] Add assembly syntax highlighting for RISCV (PR #65853)

[Yingwei Zheng via llvm-commits]

https://github.com/dtcxzyw updated https://github.com/llvm/llvm-project/pull/65853:

>From f80801b8d6c387c256504fb6b19a4a9d94572dac Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Sun, 10 Sep 2023 01:40:05 +0800
Subject: [PATCH 1/3] [MC][RISCV] Add assembly syntax highlighting for RISCV

---
 .../RISCV/MCTargetDesc/RISCVInstPrinter.cpp   | 45 ++++++++++---------
 llvm/test/MC/Disassembler/RISCV/colored.txt   | 23 ++++++++++
 2 files changed, 47 insertions(+), 21 deletions(-)
 create mode 100644 llvm/test/MC/Disassembler/RISCV/colored.txt

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index 8e98abd65aab7b9..d0a77b1248d8c99 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -16,6 +16,7 @@
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCSymbol.h"
@@ -75,7 +76,7 @@ void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
 }
 
 void RISCVInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const {
-  O << getRegisterName(Reg);
+  markup(O, Markup::Register) << getRegisterName(Reg);
 }
 
 void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
@@ -90,7 +91,7 @@ void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
   }
 
   if (MO.isImm()) {
-    O << MO.getImm();
+    markup(O, Markup::Immediate) << MO.getImm();
     return;
   }
 
@@ -110,9 +111,9 @@ void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
     uint64_t Target = Address + MO.getImm();
     if (!STI.hasFeature(RISCV::Feature64Bit))
       Target &= 0xffffffff;
-    O << formatHex(Target);
+    markup(O, Markup::Target) << formatHex(Target);
   } else {
-    O << MO.getImm();
+    markup(O, Markup::Target) << MO.getImm();
   }
 }
 
@@ -123,11 +124,11 @@ void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
   auto SiFiveReg = RISCVSysReg::lookupSiFiveRegByEncoding(Imm);
   auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
   if (SiFiveReg && SiFiveReg->haveVendorRequiredFeatures(STI.getFeatureBits()))
-    O << SiFiveReg->Name;
+    markup(O, Markup::Register) << SiFiveReg->Name;
   else if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits()))
-    O << SysReg->Name;
+    markup(O, Markup::Register) << SysReg->Name;
   else
-    O << Imm;
+    markup(O, Markup::Register) << Imm;
 }
 
 void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
@@ -162,11 +163,11 @@ void RISCVInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNo,
                                          raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
   if (Imm == 1) {
-    O << "min";
+    markup(O, Markup::Immediate) << "min";
   } else if (Imm == 30) {
-    O << "inf";
+    markup(O, Markup::Immediate) << "inf";
   } else if (Imm == 31) {
-    O << "nan";
+    markup(O, Markup::Immediate) << "nan";
   } else {
     float FPVal = RISCVLoadFPImm::getFPImm(Imm);
     // If the value is an integer, print a .0 fraction. Otherwise, use %g to
@@ -174,9 +175,9 @@ void RISCVInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNo,
     // if it is shorter than printing as a decimal. The smallest value requires
     // 12 digits of precision including the decimal.
     if (FPVal == (int)(FPVal))
-      O << format("%.1f", FPVal);
+      markup(O, Markup::Immediate) << format("%.1f", FPVal);
     else
-      O << format("%.12g", FPVal);
+      markup(O, Markup::Immediate) << format("%.12g", FPVal);
   }
 }
 
@@ -208,19 +209,20 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
 void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
                                   const MCSubtargetInfo &STI, raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
-  O << "{";
+  auto OS = markup(O, Markup::Register);
+  OS << "{";
   switch (Imm) {
   case RISCVZC::RLISTENCODE::RA:
-    O << (ArchRegNames ? "x1" : "ra");
+    OS << (ArchRegNames ? "x1" : "ra");
     break;
   case RISCVZC::RLISTENCODE::RA_S0:
-    O << (ArchRegNames ? "x1, x8" : "ra, s0");
+    OS << (ArchRegNames ? "x1, x8" : "ra, s0");
     break;
   case RISCVZC::RLISTENCODE::RA_S0_S1:
-    O << (ArchRegNames ? "x1, x8-x9" : "ra, s0-s1");
+    OS << (ArchRegNames ? "x1, x8-x9" : "ra, s0-s1");
     break;
   case RISCVZC::RLISTENCODE::RA_S0_S2:
-    O << (ArchRegNames ? "x1, x8-x9, x18" : "ra, s0-s2");
+    OS << (ArchRegNames ? "x1, x8-x9, x18" : "ra, s0-s2");
     break;
   case RISCVZC::RLISTENCODE::RA_S0_S3:
   case RISCVZC::RLISTENCODE::RA_S0_S4:
@@ -229,16 +231,16 @@ void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
   case RISCVZC::RLISTENCODE::RA_S0_S7:
   case RISCVZC::RLISTENCODE::RA_S0_S8:
   case RISCVZC::RLISTENCODE::RA_S0_S9:
-    O << (ArchRegNames ? "x1, x8-x9, x18-" : "ra, s0-")
-      << getRegisterName(RISCV::X19 + (Imm - RISCVZC::RLISTENCODE::RA_S0_S3));
+    OS << (ArchRegNames ? "x1, x8-x9, x18-" : "ra, s0-")
+       << getRegisterName(RISCV::X19 + (Imm - RISCVZC::RLISTENCODE::RA_S0_S3));
     break;
   case RISCVZC::RLISTENCODE::RA_S0_S11:
-    O << (ArchRegNames ? "x1, x8-x9, x18-x27" : "ra, s0-s11");
+    OS << (ArchRegNames ? "x1, x8-x9, x18-x27" : "ra, s0-s11");
     break;
   default:
     llvm_unreachable("invalid register list");
   }
-  O << "}";
+  OS << "}";
 }
 
 void RISCVInstPrinter::printSpimm(const MCInst *MI, unsigned OpNo,
@@ -256,6 +258,7 @@ void RISCVInstPrinter::printSpimm(const MCInst *MI, unsigned OpNo,
   if (Opcode == RISCV::CM_PUSH)
     Spimm = -Spimm;
 
+  auto OS = markup(O, Markup::Immediate);
   RISCVZC::printSpimm(Spimm, O);
 }
 
diff --git a/llvm/test/MC/Disassembler/RISCV/colored.txt b/llvm/test/MC/Disassembler/RISCV/colored.txt
new file mode 100644
index 000000000000000..10d52b525cd90c9
--- /dev/null
+++ b/llvm/test/MC/Disassembler/RISCV/colored.txt
@@ -0,0 +1,23 @@
+# RUN: llvm-mc -triple=riscv64 -mattr=+zcmp,+experimental-zfa --cdis %s | FileCheck %s --strict-whitespace --match-full-lines
+
+# Registers and immediates
+0x03 0xe0 0x40 0x00
+# CHECK:	lwu	zero, 4(ra)
+
+# Branch targets
+0x63 0x00 0xb5 0x04
+# CHECK-NEXT:	beq	a0, a1, 64
+
+# CSRs
+0xf3 0x23 0x10 0xf1
+# CHECK-NEXT:	csrr	t2, mvendorid
+
+# FP immediates
+0xd3 0x00 0x1f 0xf0
+# CHECK-NEXT:	fli.s	ft1, inf
+0xd3 0x80 0x1e 0xf0
+# CHECK-NEXT:	fli.s	ft1, 65536.0
+
+# Rlist and spimm
+0x62 0xbe
+# CHECK-NEXT:	cm.popret	{ra, s0-s1}, 32

>From c9f0b0eaac1fe6381c97fb7f8d5d78b9f6e53ab6 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Mon, 11 Sep 2023 05:39:57 +0800
Subject: [PATCH 2/3] [MC][RISCV] Only mark up register part of Rlist

---
 .../RISCV/MCTargetDesc/RISCVInstPrinter.cpp   | 48 ++++++++++++++-----
 llvm/test/MC/Disassembler/RISCV/colored.txt   | 39 ++++++++++++---
 2 files changed, 68 insertions(+), 19 deletions(-)

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index d0a77b1248d8c99..d1329214f021bcd 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -209,20 +209,33 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
 void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
                                   const MCSubtargetInfo &STI, raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
-  auto OS = markup(O, Markup::Register);
-  OS << "{";
+  O << "{";
   switch (Imm) {
   case RISCVZC::RLISTENCODE::RA:
-    OS << (ArchRegNames ? "x1" : "ra");
+    markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
     break;
   case RISCVZC::RLISTENCODE::RA_S0:
-    OS << (ArchRegNames ? "x1, x8" : "ra, s0");
+    markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
+    O << ", ";
+    markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
     break;
   case RISCVZC::RLISTENCODE::RA_S0_S1:
-    OS << (ArchRegNames ? "x1, x8-x9" : "ra, s0-s1");
+    markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
+    O << ", ";
+    markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
+    O << '-';
+    markup(O, Markup::Register) << (ArchRegNames ? "x9" : "s1");
     break;
   case RISCVZC::RLISTENCODE::RA_S0_S2:
-    OS << (ArchRegNames ? "x1, x8-x9, x18" : "ra, s0-s2");
+    markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
+    O << ", ";
+    markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
+    O << '-';
+    markup(O, Markup::Register) << (ArchRegNames ? "x9" : "s2");
+    if (ArchRegNames) {
+      O << ", ";
+      markup(O, Markup::Register) << "x18";
+    }
     break;
   case RISCVZC::RLISTENCODE::RA_S0_S3:
   case RISCVZC::RLISTENCODE::RA_S0_S4:
@@ -231,16 +244,26 @@ void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
   case RISCVZC::RLISTENCODE::RA_S0_S7:
   case RISCVZC::RLISTENCODE::RA_S0_S8:
   case RISCVZC::RLISTENCODE::RA_S0_S9:
-    OS << (ArchRegNames ? "x1, x8-x9, x18-" : "ra, s0-")
-       << getRegisterName(RISCV::X19 + (Imm - RISCVZC::RLISTENCODE::RA_S0_S3));
-    break;
   case RISCVZC::RLISTENCODE::RA_S0_S11:
-    OS << (ArchRegNames ? "x1, x8-x9, x18-x27" : "ra, s0-s11");
+    markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
+    O << ", ";
+    markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
+    O << '-';
+    if (ArchRegNames) {
+      markup(O, Markup::Register) << "x9";
+      O << ", ";
+      markup(O, Markup::Register) << "x18";
+      O << '-';
+    }
+    markup(O, Markup::Register) << getRegisterName(
+        RISCV::X19 + (Imm == RISCVZC::RLISTENCODE::RA_S0_S11
+                          ? 8
+                          : Imm - RISCVZC::RLISTENCODE::RA_S0_S3));
     break;
   default:
     llvm_unreachable("invalid register list");
   }
-  OS << "}";
+  O << "}";
 }
 
 void RISCVInstPrinter::printSpimm(const MCInst *MI, unsigned OpNo,
@@ -258,6 +281,7 @@ void RISCVInstPrinter::printSpimm(const MCInst *MI, unsigned OpNo,
   if (Opcode == RISCV::CM_PUSH)
     Spimm = -Spimm;
 
+  // RAII guard for ANSI color escape sequences
   auto OS = markup(O, Markup::Immediate);
   RISCVZC::printSpimm(Spimm, O);
 }
@@ -272,7 +296,7 @@ void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
     return;
   O << ", ";
   printRegName(O, MO.getReg());
-  O << ".t";
+  markup(O, Markup::Register) << ".t";
 }
 
 const char *RISCVInstPrinter::getRegisterName(MCRegister Reg) {
diff --git a/llvm/test/MC/Disassembler/RISCV/colored.txt b/llvm/test/MC/Disassembler/RISCV/colored.txt
index 10d52b525cd90c9..94d2f8170ee1289 100644
--- a/llvm/test/MC/Disassembler/RISCV/colored.txt
+++ b/llvm/test/MC/Disassembler/RISCV/colored.txt
@@ -1,23 +1,48 @@
-# RUN: llvm-mc -triple=riscv64 -mattr=+zcmp,+experimental-zfa --cdis %s | FileCheck %s --strict-whitespace --match-full-lines
+# UNSUPPORTED: system-windows
+# RUN: llvm-mc -triple=riscv64 -mattr=+zcmp,+experimental-zfa,+v --cdis %s | FileCheck %s --strict-whitespace --match-full-lines -check-prefixes=CHECK,ASM,ABINAME
+# RUN: llvm-mc -triple=riscv64 -mattr=+zcmp,+experimental-zfa,+v -M numeric --cdis %s | FileCheck %s --strict-whitespace --match-full-lines -check-prefixes=CHECK,ASM,ARCHNAME
 
+# CHECK:	.text
 # Registers and immediates
 0x03 0xe0 0x40 0x00
-# CHECK:	lwu	zero, 4(ra)
+# ABINAME-NEXT:	lwu	zero, 4(ra)
+# ARCHNAME-NEXT:	lwu	x0, 4(x1)
 
 # Branch targets
 0x63 0x00 0xb5 0x04
-# CHECK-NEXT:	beq	a0, a1, 64
+# ABINAME-NEXT:	beq	a0, a1, 64
+# ARCHNAME-NEXT:	beq	x10, x11, 64
 
 # CSRs
 0xf3 0x23 0x10 0xf1
-# CHECK-NEXT:	csrr	t2, mvendorid
+# ABINAME-NEXT:	csrr	t2, mvendorid
+# ARCHNAME-NEXT:	csrr	x7, mvendorid
 
 # FP immediates
 0xd3 0x00 0x1f 0xf0
-# CHECK-NEXT:	fli.s	ft1, inf
+# ABINAME-NEXT:	fli.s	ft1, inf
+# ARCHNAME-NEXT:	fli.s	f1, inf
 0xd3 0x80 0x1e 0xf0
-# CHECK-NEXT:	fli.s	ft1, 65536.0
+# ABINAME-NEXT:	fli.s	ft1, 65536.0
+# ARCHNAME-NEXT:	fli.s	f1, 65536.0
 
 # Rlist and spimm
+0x42 0xbe
+# ABINAME-NEXT:	cm.popret	{ra}, 16
+# ARCHNAME-NEXT:	cm.popret	{x1}, 16
+0x5e 0xbe
+# ABINAME-NEXT:	cm.popret	{ra, s0}, 64
+# ARCHNAME-NEXT:	cm.popret	{x1, x8}, 64
 0x62 0xbe
-# CHECK-NEXT:	cm.popret	{ra, s0-s1}, 32
+# ABINAME-NEXT:	cm.popret	{ra, s0-s1}, 32
+# ARCHNAME-NEXT:	cm.popret	{x1, x8-x9}, 32
+0x76 0xbe
+# ABINAME-NEXT:	cm.popret	{ra, s0-s2}, 48
+# ARCHNAME-NEXT:	cm.popret	{x1, x8-x9, x18}, 48
+0xfe 0xbe
+# ABINAME-NEXT:	cm.popret	{ra, s0-s11}, 160
+# ARCHNAME-NEXT:	cm.popret	{x1, x8-x9, x18-x27}, 160
+
+# mask registers
+0x57 0x04 0x4a 0x00
+# ASM-NEXT:	vadd.vv	v8, v4, v20, v0.t

>From d35b9ea895034994d107357b56c1a8b7669dc6c9 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Mon, 11 Sep 2023 06:02:42 +0800
Subject: [PATCH 3/3] [MC][RISCV] Merge adjacent colored seqs

---
 llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp | 3 +--
 llvm/test/MC/Disassembler/RISCV/colored.txt             | 2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index d1329214f021bcd..e3c58b618d1295f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -295,8 +295,7 @@ void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
   if (MO.getReg() == RISCV::NoRegister)
     return;
   O << ", ";
-  printRegName(O, MO.getReg());
-  markup(O, Markup::Register) << ".t";
+  markup(O, Markup::Register) << getRegisterName(MO.getReg()) << ".t";
 }
 
 const char *RISCVInstPrinter::getRegisterName(MCRegister Reg) {
diff --git a/llvm/test/MC/Disassembler/RISCV/colored.txt b/llvm/test/MC/Disassembler/RISCV/colored.txt
index 94d2f8170ee1289..e7b028dfc94dd16 100644
--- a/llvm/test/MC/Disassembler/RISCV/colored.txt
+++ b/llvm/test/MC/Disassembler/RISCV/colored.txt
@@ -45,4 +45,4 @@
 
 # mask registers
 0x57 0x04 0x4a 0x00
-# ASM-NEXT:	vadd.vv	v8, v4, v20, v0.t
+# ASM-NEXT:	vadd.vv	v8, v4, v20, v0.t