[llvm] [Sparc] Replace some CAS instructions with InstAlias (PR #65588)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 7 05:21:06 PDT 2023
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/65588:
>From 8c97558a4dfba1c3f9db864fea8b7d9e304ad597 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Thu, 7 Sep 2023 12:37:01 +0300
Subject: [PATCH 1/3] [Sparc] Replace some CAS instructions with InstAlias
According to the manual, cas, casl, casx and casxl are synthetic
instructions. They map to casa and casxa with certain ASI tags.
---
llvm/lib/Target/Sparc/SparcInstr64Bit.td | 18 ++------
llvm/lib/Target/Sparc/SparcInstrAliases.td | 18 ++++++++
llvm/lib/Target/Sparc/SparcInstrInfo.td | 43 ++++---------------
llvm/test/CodeGen/SPARC/64atomics.ll | 8 ++--
.../CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll | 12 +++---
llvm/test/CodeGen/SPARC/atomics.ll | 40 ++++++++---------
llvm/test/MC/Sparc/sparc-cas-instructions.s | 8 ++--
7 files changed, 64 insertions(+), 83 deletions(-)
diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
index 6ddb1cc3afb0da8..45028f156166daf 100644
--- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td
+++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
@@ -476,21 +476,6 @@ def SETHIXi : F2_1<0b100,
// ATOMICS.
let Predicates = [Is64Bit, HasV9], Constraints = "$swap = $rd" in {
- let asi = 0b10000000 in
- def CASXrr: F3_1_asi<3, 0b111110,
- (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
- I64Regs:$swap),
- "casx [$rs1], $rs2, $rd",
- [(set i64:$rd,
- (atomic_cmp_swap_64 i64:$rs1, i64:$rs2, i64:$swap))]>;
-
- let asi = 0b10001000 in
- def CASXLrr: F3_1_asi<3, 0b111110,
- (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
- I64Regs:$swap),
- "casxl [$rs1], $rs2, $rd",
- []>;
-
def CASXArr: F3_1_asi<3, 0b111110,
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
I64Regs:$swap, ASITag:$asi),
@@ -515,6 +500,9 @@ def : Pat<(i64 (atomic_load_64 ADDRri:$src)), (LDXri ADDRri:$src)>;
def : Pat<(atomic_store_64 i64:$val, ADDRrr:$dst), (STXrr ADDRrr:$dst, $val)>;
def : Pat<(atomic_store_64 i64:$val, ADDRri:$dst), (STXri ADDRri:$dst, $val)>;
+def : Pat<(atomic_cmp_swap_64 i64:$rs1, i64:$rs2, i64:$swap),
+ (CASXArr $rs1, $rs2, $swap, 0x80)>;
+
} // Predicates = [Is64Bit]
let Predicates = [Is64Bit], hasSideEffects = 1, Uses = [ICC], cc = 0b10 in
diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td b/llvm/lib/Target/Sparc/SparcInstrAliases.td
index dcc6ec3c971458c..713d031cbc05df1 100644
--- a/llvm/lib/Target/Sparc/SparcInstrAliases.td
+++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td
@@ -464,6 +464,24 @@ def : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>;
// neg reg, rd -> sub %g0, reg, rd
def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>;
+let Predicates = [HasV9] in {
+ // cas [rs1], rs2, rd -> casa [rs1] #ASI_P, rs2, rd
+ def : InstAlias<"cas [$rs1], $rs2, $rd",
+ (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x80), 0>;
+
+ // casl [rs1], rs2, rd -> casa [rs1] #ASI_P_L, rs2, rd
+ def : InstAlias<"casl [$rs1], $rs2, $rd",
+ (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x88), 0>;
+
+ // casx [rs1], rs2, rd -> casxa [rs1] #ASI_P, rs2, rd
+ def : InstAlias<"casx [$rs1], $rs2, $rd",
+ (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x80), 0>;
+
+ // casxl [rs1], rs2, rd -> casxa [rs1] #ASI_P_L, rs2, rd
+ def : InstAlias<"casxl [$rs1], $rs2, $rd",
+ (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x88), 0>;
+}
+
// inc rd -> add rd, 1, rd
def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 1d625b608a2b5e2..0ae0dfbb00503e6 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -1703,41 +1703,7 @@ let Predicates = [HasV9], rd = 15, rs1 = 0b00000 in
(ins simm13Op:$simm13),
"sir $simm13", []>;
-// The CAS instruction, unlike other instructions, only comes in a
-// form which requires an ASI be provided.
-let Predicates = [HasV9], Constraints = "$swap = $rd" in {
- // The ASI value hardcoded here is ASI_PRIMARY, the default
- // unprivileged ASI for SparcV9.
- let asi = 0b10000000 in
- def CASrr: F3_1_asi<3, 0b111100,
- (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
- IntRegs:$swap),
- "cas [$rs1], $rs2, $rd",
- [(set i32:$rd,
- (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
-
- // SparcV9 also specifies a CASL alias, which uses ASI_PRIMARY_LITTLE.
- let asi = 0b10001000 in
- def CASLrr: F3_1_asi<3, 0b111100,
- (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
- IntRegs:$swap),
- "casl [$rs1], $rs2, $rd",
- []>;
-}
-
-// CASA is supported as an instruction on some LEON3 and all LEON4 processors.
-// This version can be automatically lowered from C code, selecting ASI 10
-let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in
- def CASAasi10: F3_1_asi<3, 0b111100,
- (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
- IntRegs:$swap),
- "casa [$rs1] 10, $rs2, $rd",
- [(set i32:$rd,
- (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
-
// CASA supported on all V9, some LEON3 and all LEON4 processors.
-// Same pattern as CASrr above, but with a different ASI.
-// This version is supported for inline assembly lowering only.
let Predicates = [HasCASA], Constraints = "$swap = $rd" in
def CASArr: F3_1_asi<3, 0b111100,
(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
@@ -1938,6 +1904,15 @@ def : Pat<(atomic_store_16 i32:$val, ADDRri:$dst), (STHri ADDRri:$dst, $val)>;
def : Pat<(atomic_store_32 i32:$val, ADDRrr:$dst), (STrr ADDRrr:$dst, $val)>;
def : Pat<(atomic_store_32 i32:$val, ADDRri:$dst), (STri ADDRri:$dst, $val)>;
+let Predicates = [HasV9] in
+def : Pat<(atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap),
+ (CASArr $rs1, $rs2, $swap, 0x80)>;
+
+// Same pattern as CASArr above, but with a different ASI.
+let Predicates = [HasLeonCASA] in
+def : Pat<(atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap),
+ (CASArr $rs1, $rs2, $swap, 0x0A)>;
+
// A register pair with zero upper half.
// The upper part is done with ORrr instead of `COPY G0`
// or a normal register copy, since `COPY G0`s in that place
diff --git a/llvm/test/CodeGen/SPARC/64atomics.ll b/llvm/test/CodeGen/SPARC/64atomics.ll
index 89175b6242e639e..84c3a5d8740c5fd 100644
--- a/llvm/test/CodeGen/SPARC/64atomics.ll
+++ b/llvm/test/CodeGen/SPARC/64atomics.ll
@@ -18,7 +18,7 @@ entry:
; CHECK-LABEL: test_cmpxchg_i64
; CHECK: mov 123, [[R:%[gilo][0-7]]]
-; CHECK: casx [%o1], %o0, [[R]]
+; CHECK: casxa [%o1] #ASI_P, %o0, [[R]]
define i64 @test_cmpxchg_i64(i64 %a, i64* %ptr) {
entry:
@@ -28,7 +28,7 @@ entry:
}
; CHECK-LABEL: test_swap_i64
-; CHECK: casx [%o1],
+; CHECK: casxa [%o1] #ASI_P,
define i64 @test_swap_i64(i64 %a, i64* %ptr) {
entry:
@@ -39,7 +39,7 @@ entry:
; CHECK-LABEL: test_load_sub_64
; CHECK: membar
; CHECK: sub
-; CHECK: casx [%o0]
+; CHECK: casxa [%o0] #ASI_P
; CHECK: membar
define zeroext i64 @test_load_sub_64(i64* %p, i64 zeroext %v) {
entry:
@@ -51,7 +51,7 @@ entry:
; CHECK: membar
; CHECK: cmp
; CHECK: movg %xcc
-; CHECK: casx [%o0]
+; CHECK: casxa [%o0] #ASI_P
; CHECK: membar
define zeroext i64 @test_load_max_64(i64* %p, i64 zeroext %v) {
entry:
diff --git a/llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll
index 9b49035c4604071..27ae6af8372aef4 100644
--- a/llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll
+++ b/llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll
@@ -27,7 +27,7 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
; CHECK-NEXT: sll %o4, %o0, %o4
; CHECK-NEXT: and %o5, %o3, %g2
; CHECK-NEXT: or %g2, %o4, %o4
-; CHECK-NEXT: cas [%o2], %o5, %o4
+; CHECK-NEXT: casa [%o2] #ASI_P, %o5, %o4
; CHECK-NEXT: mov %g0, %g2
; CHECK-NEXT: cmp %o4, %o5
; CHECK-NEXT: move %icc, 1, %g2
@@ -70,7 +70,7 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) {
; CHECK-NEXT: sll %o5, %o0, %o5
; CHECK-NEXT: and %g2, %o4, %g3
; CHECK-NEXT: or %g3, %o5, %o5
-; CHECK-NEXT: cas [%o2], %g2, %o5
+; CHECK-NEXT: casa [%o2] #ASI_P, %g2, %o5
; CHECK-NEXT: mov %g0, %g3
; CHECK-NEXT: cmp %o5, %g2
; CHECK-NEXT: move %icc, 1, %g3
@@ -98,7 +98,7 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) {
; CHECK-NEXT: add %o2, 1, %o2
; CHECK-NEXT: cmp %o3, %o1
; CHECK-NEXT: movcc %icc, 0, %o2
-; CHECK-NEXT: cas [%o0], %o3, %o2
+; CHECK-NEXT: casa [%o0] #ASI_P, %o3, %o2
; CHECK-NEXT: mov %g0, %o4
; CHECK-NEXT: cmp %o2, %o3
; CHECK-NEXT: move %icc, 1, %o4
@@ -186,7 +186,7 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) {
; CHECK-NEXT: sll %o5, %o0, %o5
; CHECK-NEXT: and %g2, %o3, %g3
; CHECK-NEXT: or %g3, %o5, %o5
-; CHECK-NEXT: cas [%o2], %g2, %o5
+; CHECK-NEXT: casa [%o2] #ASI_P, %g2, %o5
; CHECK-NEXT: mov %g0, %g3
; CHECK-NEXT: cmp %o5, %g2
; CHECK-NEXT: move %icc, 1, %g3
@@ -231,7 +231,7 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) {
; CHECK-NEXT: sll %g2, %o0, %g2
; CHECK-NEXT: and %g3, %o4, %g4
; CHECK-NEXT: or %g4, %g2, %g2
-; CHECK-NEXT: cas [%o2], %g3, %g2
+; CHECK-NEXT: casa [%o2] #ASI_P, %g3, %g2
; CHECK-NEXT: mov %g0, %g4
; CHECK-NEXT: cmp %g2, %g3
; CHECK-NEXT: move %icc, 1, %g4
@@ -261,7 +261,7 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) {
; CHECK-NEXT: movgu %icc, %o1, %o2
; CHECK-NEXT: cmp %o3, 0
; CHECK-NEXT: move %icc, %o1, %o2
-; CHECK-NEXT: cas [%o0], %o3, %o2
+; CHECK-NEXT: casa [%o0] #ASI_P, %o3, %o2
; CHECK-NEXT: mov %g0, %o4
; CHECK-NEXT: cmp %o2, %o3
; CHECK-NEXT: move %icc, 1, %o4
diff --git a/llvm/test/CodeGen/SPARC/atomics.ll b/llvm/test/CodeGen/SPARC/atomics.ll
index 715202f5977db81..707534e0e1dca47 100644
--- a/llvm/test/CodeGen/SPARC/atomics.ll
+++ b/llvm/test/CodeGen/SPARC/atomics.ll
@@ -91,7 +91,7 @@ entry:
; SPARC: [[LABEL1:\.L.*]]:
; SPARC: or %o5, %o4, %g2
; SPARC: or %o5, %o0, %g3
-; SPARC: cas [%o2], %g3, %g2
+; SPARC: casa [%o2] #ASI_P, %g3, %g2
; SPARC: mov %g0, %g4
; SPARC: cmp %g2, %g3
; SPARC: move %icc, 1, %g4
@@ -122,7 +122,7 @@ entry:
; SPARC64: [[LABEL1:\.L.*]]:
; SPARC64: or %o5, %o4, %g2
; SPARC64: or %o5, %o0, %g3
-; SPARC64: cas [%o2], %g3, %g2
+; SPARC64: casa [%o2] #ASI_P, %g3, %g2
; SPARC64: mov %g0, %g4
; SPARC64: cmp %g2, %g3
; SPARC64: move %icc, 1, %g4
@@ -162,7 +162,7 @@ entry:
; SPARC: [[LABEL1:\.L.*]]:
; SPARC: or %o5, %o0, %g2
; SPARC: or %o5, %o4, %g3
-; SPARC: cas [%o2], %g3, %g2
+; SPARC: casa [%o2] #ASI_P, %g3, %g2
; SPARC: mov %g0, %g4
; SPARC: cmp %g2, %g3
; SPARC: move %icc, 1, %g4
@@ -193,7 +193,7 @@ entry:
; SPARC64: [[LABEL1:\.L.*]]:
; SPARC64: or %o5, %o0, %g2
; SPARC64: or %o5, %o4, %g3
-; SPARC64: cas [%o2], %g3, %g2
+; SPARC64: casa [%o2] #ASI_P, %g3, %g2
; SPARC64: mov %g0, %g4
; SPARC64: cmp %g2, %g3
; SPARC64: move %icc, 1, %g4
@@ -216,10 +216,10 @@ entry:
; SPARC-LABEL: test_cmpxchg_i32
; SPARC: mov 123, [[R:%[gilo][0-7]]]
-; SPARC: cas [%o1], %o0, [[R]]
+; SPARC: casa [%o1] #ASI_P, %o0, [[R]]
; SPARC64-LABEL: test_cmpxchg_i32
; SPARC64: mov 123, [[R:%[gilo][0-7]]]
-; SPARC64: cas [%o1], %o0, [[R]]
+; SPARC64: casa [%o1] #ASI_P, %o0, [[R]]
define i32 @test_cmpxchg_i32(i32 %a, i32* %ptr) {
entry:
%pair = cmpxchg i32* %ptr, i32 %a, i32 123 monotonic monotonic
@@ -267,13 +267,13 @@ entry:
; SPARC: membar
; SPARC: .L{{.*}}:
; SPARC: sub
-; SPARC: cas [{{%[gilo][0-7]}}]
+; SPARC: casa [{{%[gilo][0-7]}}] #ASI_P
; SPARC: membar
; SPARC64-LABEL: test_load_sub_i8
; SPARC64: membar
; SPARC64: .L{{.*}}:
; SPARC64: sub
-; SPARC64: cas [{{%[gilo][0-7]}}]
+; SPARC64: casa [{{%[gilo][0-7]}}] #ASI_P
; SPARC64: membar
define zeroext i8 @test_load_sub_i8(i8* %p, i8 zeroext %v) {
entry:
@@ -285,13 +285,13 @@ entry:
; SPARC: membar
; SPARC: .L{{.*}}:
; SPARC: sub
-; SPARC: cas [{{%[gilo][0-7]}}]
+; SPARC: casa [{{%[gilo][0-7]}}] #ASI_P
; SPARC: membar
; SPARC64-LABEL: test_load_sub_i16
; SPARC64: membar
; SPARC64: .L{{.*}}:
; SPARC64: sub
-; SPARC64: cas [{{%[gilo][0-7]}}]
+; SPARC64: casa [{{%[gilo][0-7]}}] #ASI_P
; SPARC64: membar
define zeroext i16 @test_load_sub_i16(i16* %p, i16 zeroext %v) {
entry:
@@ -303,13 +303,13 @@ entry:
; SPARC: membar
; SPARC: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
; SPARC: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
-; SPARC: cas [%o0], [[V]], [[V2]]
+; SPARC: casa [%o0] #ASI_P, [[V]], [[V2]]
; SPARC: membar
; SPARC64-LABEL: test_load_add_i32
; SPARC64: membar
; SPARC64: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
; SPARC64: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
-; SPARC64: cas [%o0], [[V]], [[V2]]
+; SPARC64: casa [%o0] #ASI_P, [[V]], [[V2]]
; SPARC64: membar
define zeroext i32 @test_load_add_i32(i32* %p, i32 zeroext %v) {
entry:
@@ -320,12 +320,12 @@ entry:
; SPARC-LABEL: test_load_xor_32
; SPARC: membar
; SPARC: xor
-; SPARC: cas [%o0]
+; SPARC: casa [%o0] #ASI_P
; SPARC: membar
; SPARC64-LABEL: test_load_xor_32
; SPARC64: membar
; SPARC64: xor
-; SPARC64: cas [%o0]
+; SPARC64: casa [%o0] #ASI_P
; SPARC64: membar
define zeroext i32 @test_load_xor_32(i32* %p, i32 zeroext %v) {
entry:
@@ -337,13 +337,13 @@ entry:
; SPARC: membar
; SPARC: and
; SPARC-NOT: xor
-; SPARC: cas [%o0]
+; SPARC: casa [%o0] #ASI_P
; SPARC: membar
; SPARC64-LABEL: test_load_and_32
; SPARC64: membar
; SPARC64: and
; SPARC64-NOT: xor
-; SPARC64: cas [%o0]
+; SPARC64: casa [%o0] #ASI_P
; SPARC64: membar
define zeroext i32 @test_load_and_32(i32* %p, i32 zeroext %v) {
entry:
@@ -355,13 +355,13 @@ entry:
; SPARC: membar
; SPARC: and
; SPARC: xor
-; SPARC: cas [%o0]
+; SPARC: casa [%o0] #ASI_P
; SPARC: membar
; SPARC64-LABEL: test_load_nand_32
; SPARC64: membar
; SPARC64: and
; SPARC64: xor
-; SPARC64: cas [%o0]
+; SPARC64: casa [%o0] #ASI_P
; SPARC64: membar
define zeroext i32 @test_load_nand_32(i32* %p, i32 zeroext %v) {
entry:
@@ -373,13 +373,13 @@ entry:
; SPARC: membar
; SPARC: cmp
; SPARC: movleu %icc
-; SPARC: cas [%o0]
+; SPARC: casa [%o0] #ASI_P
; SPARC: membar
; SPARC64-LABEL: test_load_umin_32
; SPARC64: membar
; SPARC64: cmp
; SPARC64: movleu %icc
-; SPARC64: cas [%o0]
+; SPARC64: casa [%o0] #ASI_P
; SPARC64: membar
define zeroext i32 @test_load_umin_32(i32* %p, i32 zeroext %v) {
entry:
diff --git a/llvm/test/MC/Sparc/sparc-cas-instructions.s b/llvm/test/MC/Sparc/sparc-cas-instructions.s
index c0cf72dda208b11..763eb29e1bd1b8f 100644
--- a/llvm/test/MC/Sparc/sparc-cas-instructions.s
+++ b/llvm/test/MC/Sparc/sparc-cas-instructions.s
@@ -3,22 +3,22 @@
! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
! V8: error: instruction requires a CPU feature not currently enabled
-! V9: cas [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
+! V9: casa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
! LEON: error: instruction requires a CPU feature not currently enabled
cas [%i0], %l6, %o2
! V8: error: instruction requires a CPU feature not currently enabled
-! V9: casl [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x11,0x16]
+! V9: casa [%i0] #ASI_P_L, %l6, %o2 ! encoding: [0xd5,0xe6,0x11,0x16]
! LEON: error: instruction requires a CPU feature not currently enabled
casl [%i0], %l6, %o2
! V8: error: instruction requires a CPU feature not currently enabled
-! V9: casx [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
+! V9: casxa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
! LEON: error: instruction requires a CPU feature not currently enabled
casx [%i0], %l6, %o2
! V8: error: instruction requires a CPU feature not currently enabled
-! V9: casxl [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x16]
+! V9: casxa [%i0] #ASI_P_L, %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x16]
! LEON: error: instruction requires a CPU feature not currently enabled
casxl [%i0], %l6, %o2
>From 7a3b787e80f7e8eb4ffdfb171d9750b2ce70b560 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Thu, 7 Sep 2023 14:51:31 +0300
Subject: [PATCH 2/3] Update disassembler tests
---
llvm/test/MC/Disassembler/Sparc/sparc-atomics.txt | 8 ++++----
llvm/test/MC/Disassembler/Sparc/sparc-v9-asi.txt | 6 ++----
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-atomics.txt b/llvm/test/MC/Disassembler/Sparc/sparc-atomics.txt
index 289eed0e83a1d1f..a51a1a9470f5c5c 100644
--- a/llvm/test/MC/Disassembler/Sparc/sparc-atomics.txt
+++ b/llvm/test/MC/Disassembler/Sparc/sparc-atomics.txt
@@ -1,9 +1,9 @@
# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux | FileCheck %s
-# CHECK: cas [%i0], %l6, %o2
+# CHECK: casa [%i0] #ASI_P, %l6, %o2
0xd5,0xe6,0x10,0x16
-# CHECK: casl [%i0], %l6, %o2
+# CHECK: casa [%i0] #ASI_P_L, %l6, %o2
0xd5,0xe6,0x11,0x16
# CHECK: casa [%i0] 255, %l6, %o2
@@ -12,10 +12,10 @@
# CHECK: casa [%i0] %asi, %l6, %o2
0xd5,0xe6,0x20,0x16
-# CHECK: casx [%i0], %l6, %o2
+# CHECK: casxa [%i0] #ASI_P, %l6, %o2
0xd5,0xf6,0x10,0x16
-# CHECK: casxl [%i0], %l6, %o2
+# CHECK: casxa [%i0] #ASI_P_L, %l6, %o2
0xd5,0xf6,0x11,0x16
# CHECK: casxa [%i0] 255, %l6, %o2
diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-v9-asi.txt b/llvm/test/MC/Disassembler/Sparc/sparc-v9-asi.txt
index 9286814552cf5f6..8cf30ecdd2bb680 100644
--- a/llvm/test/MC/Disassembler/Sparc/sparc-v9-asi.txt
+++ b/llvm/test/MC/Disassembler/Sparc/sparc-v9-asi.txt
@@ -14,8 +14,7 @@
0xd5 0xf6 0x03 0x16
# V9: casxa [%i0] #ASI_AIUS_L, %l6, %o2
0xd5 0xf6 0x03 0x36
-## casx == casxa #ASI_P
-# V9: casx [%i0], %l6, %o2
+# V9: casxa [%i0] #ASI_P, %l6, %o2
0xd5 0xf6 0x10 0x16
# V9: casxa [%i0] #ASI_S, %l6, %o2
0xd5 0xf6 0x10 0x36
@@ -23,8 +22,7 @@
0xd5 0xf6 0x10 0x56
# V9: casxa [%i0] #ASI_SNF, %l6, %o2
0xd5 0xf6 0x10 0x76
-## casxl == casxa #ASI_L
-# V9: casxl [%i0], %l6, %o2
+# V9: casxa [%i0] #ASI_P_L, %l6, %o2
0xd5 0xf6 0x11 0x16
# V9: casxa [%i0] #ASI_S_L, %l6, %o2
0xd5 0xf6 0x11 0x36
>From 89bcd1f7a0be07cde8e10ae56a036999ad816ef9 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Thu, 7 Sep 2023 15:17:35 +0300
Subject: [PATCH 3/3] Print aliases by default
---
llvm/lib/Target/Sparc/SparcInstrAliases.td | 8 ++--
llvm/test/CodeGen/SPARC/64atomics.ll | 8 ++--
.../CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll | 12 +++---
llvm/test/CodeGen/SPARC/atomics.ll | 40 +++++++++----------
.../MC/Disassembler/Sparc/sparc-atomics.txt | 8 ++--
.../MC/Disassembler/Sparc/sparc-v9-asi.txt | 6 ++-
llvm/test/MC/Sparc/sparc-cas-instructions.s | 16 ++++----
llvm/test/MC/Sparc/sparcv9-asi-names.s | 8 ++--
8 files changed, 54 insertions(+), 52 deletions(-)
diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td b/llvm/lib/Target/Sparc/SparcInstrAliases.td
index 713d031cbc05df1..5ee8ff978a242fe 100644
--- a/llvm/lib/Target/Sparc/SparcInstrAliases.td
+++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td
@@ -467,19 +467,19 @@ def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>;
let Predicates = [HasV9] in {
// cas [rs1], rs2, rd -> casa [rs1] #ASI_P, rs2, rd
def : InstAlias<"cas [$rs1], $rs2, $rd",
- (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x80), 0>;
+ (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x80)>;
// casl [rs1], rs2, rd -> casa [rs1] #ASI_P_L, rs2, rd
def : InstAlias<"casl [$rs1], $rs2, $rd",
- (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x88), 0>;
+ (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x88)>;
// casx [rs1], rs2, rd -> casxa [rs1] #ASI_P, rs2, rd
def : InstAlias<"casx [$rs1], $rs2, $rd",
- (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x80), 0>;
+ (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x80)>;
// casxl [rs1], rs2, rd -> casxa [rs1] #ASI_P_L, rs2, rd
def : InstAlias<"casxl [$rs1], $rs2, $rd",
- (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x88), 0>;
+ (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x88)>;
}
// inc rd -> add rd, 1, rd
diff --git a/llvm/test/CodeGen/SPARC/64atomics.ll b/llvm/test/CodeGen/SPARC/64atomics.ll
index 84c3a5d8740c5fd..89175b6242e639e 100644
--- a/llvm/test/CodeGen/SPARC/64atomics.ll
+++ b/llvm/test/CodeGen/SPARC/64atomics.ll
@@ -18,7 +18,7 @@ entry:
; CHECK-LABEL: test_cmpxchg_i64
; CHECK: mov 123, [[R:%[gilo][0-7]]]
-; CHECK: casxa [%o1] #ASI_P, %o0, [[R]]
+; CHECK: casx [%o1], %o0, [[R]]
define i64 @test_cmpxchg_i64(i64 %a, i64* %ptr) {
entry:
@@ -28,7 +28,7 @@ entry:
}
; CHECK-LABEL: test_swap_i64
-; CHECK: casxa [%o1] #ASI_P,
+; CHECK: casx [%o1],
define i64 @test_swap_i64(i64 %a, i64* %ptr) {
entry:
@@ -39,7 +39,7 @@ entry:
; CHECK-LABEL: test_load_sub_64
; CHECK: membar
; CHECK: sub
-; CHECK: casxa [%o0] #ASI_P
+; CHECK: casx [%o0]
; CHECK: membar
define zeroext i64 @test_load_sub_64(i64* %p, i64 zeroext %v) {
entry:
@@ -51,7 +51,7 @@ entry:
; CHECK: membar
; CHECK: cmp
; CHECK: movg %xcc
-; CHECK: casxa [%o0] #ASI_P
+; CHECK: casx [%o0]
; CHECK: membar
define zeroext i64 @test_load_max_64(i64* %p, i64 zeroext %v) {
entry:
diff --git a/llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll
index 27ae6af8372aef4..9b49035c4604071 100644
--- a/llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll
+++ b/llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll
@@ -27,7 +27,7 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
; CHECK-NEXT: sll %o4, %o0, %o4
; CHECK-NEXT: and %o5, %o3, %g2
; CHECK-NEXT: or %g2, %o4, %o4
-; CHECK-NEXT: casa [%o2] #ASI_P, %o5, %o4
+; CHECK-NEXT: cas [%o2], %o5, %o4
; CHECK-NEXT: mov %g0, %g2
; CHECK-NEXT: cmp %o4, %o5
; CHECK-NEXT: move %icc, 1, %g2
@@ -70,7 +70,7 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) {
; CHECK-NEXT: sll %o5, %o0, %o5
; CHECK-NEXT: and %g2, %o4, %g3
; CHECK-NEXT: or %g3, %o5, %o5
-; CHECK-NEXT: casa [%o2] #ASI_P, %g2, %o5
+; CHECK-NEXT: cas [%o2], %g2, %o5
; CHECK-NEXT: mov %g0, %g3
; CHECK-NEXT: cmp %o5, %g2
; CHECK-NEXT: move %icc, 1, %g3
@@ -98,7 +98,7 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) {
; CHECK-NEXT: add %o2, 1, %o2
; CHECK-NEXT: cmp %o3, %o1
; CHECK-NEXT: movcc %icc, 0, %o2
-; CHECK-NEXT: casa [%o0] #ASI_P, %o3, %o2
+; CHECK-NEXT: cas [%o0], %o3, %o2
; CHECK-NEXT: mov %g0, %o4
; CHECK-NEXT: cmp %o2, %o3
; CHECK-NEXT: move %icc, 1, %o4
@@ -186,7 +186,7 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) {
; CHECK-NEXT: sll %o5, %o0, %o5
; CHECK-NEXT: and %g2, %o3, %g3
; CHECK-NEXT: or %g3, %o5, %o5
-; CHECK-NEXT: casa [%o2] #ASI_P, %g2, %o5
+; CHECK-NEXT: cas [%o2], %g2, %o5
; CHECK-NEXT: mov %g0, %g3
; CHECK-NEXT: cmp %o5, %g2
; CHECK-NEXT: move %icc, 1, %g3
@@ -231,7 +231,7 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) {
; CHECK-NEXT: sll %g2, %o0, %g2
; CHECK-NEXT: and %g3, %o4, %g4
; CHECK-NEXT: or %g4, %g2, %g2
-; CHECK-NEXT: casa [%o2] #ASI_P, %g3, %g2
+; CHECK-NEXT: cas [%o2], %g3, %g2
; CHECK-NEXT: mov %g0, %g4
; CHECK-NEXT: cmp %g2, %g3
; CHECK-NEXT: move %icc, 1, %g4
@@ -261,7 +261,7 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) {
; CHECK-NEXT: movgu %icc, %o1, %o2
; CHECK-NEXT: cmp %o3, 0
; CHECK-NEXT: move %icc, %o1, %o2
-; CHECK-NEXT: casa [%o0] #ASI_P, %o3, %o2
+; CHECK-NEXT: cas [%o0], %o3, %o2
; CHECK-NEXT: mov %g0, %o4
; CHECK-NEXT: cmp %o2, %o3
; CHECK-NEXT: move %icc, 1, %o4
diff --git a/llvm/test/CodeGen/SPARC/atomics.ll b/llvm/test/CodeGen/SPARC/atomics.ll
index 707534e0e1dca47..715202f5977db81 100644
--- a/llvm/test/CodeGen/SPARC/atomics.ll
+++ b/llvm/test/CodeGen/SPARC/atomics.ll
@@ -91,7 +91,7 @@ entry:
; SPARC: [[LABEL1:\.L.*]]:
; SPARC: or %o5, %o4, %g2
; SPARC: or %o5, %o0, %g3
-; SPARC: casa [%o2] #ASI_P, %g3, %g2
+; SPARC: cas [%o2], %g3, %g2
; SPARC: mov %g0, %g4
; SPARC: cmp %g2, %g3
; SPARC: move %icc, 1, %g4
@@ -122,7 +122,7 @@ entry:
; SPARC64: [[LABEL1:\.L.*]]:
; SPARC64: or %o5, %o4, %g2
; SPARC64: or %o5, %o0, %g3
-; SPARC64: casa [%o2] #ASI_P, %g3, %g2
+; SPARC64: cas [%o2], %g3, %g2
; SPARC64: mov %g0, %g4
; SPARC64: cmp %g2, %g3
; SPARC64: move %icc, 1, %g4
@@ -162,7 +162,7 @@ entry:
; SPARC: [[LABEL1:\.L.*]]:
; SPARC: or %o5, %o0, %g2
; SPARC: or %o5, %o4, %g3
-; SPARC: casa [%o2] #ASI_P, %g3, %g2
+; SPARC: cas [%o2], %g3, %g2
; SPARC: mov %g0, %g4
; SPARC: cmp %g2, %g3
; SPARC: move %icc, 1, %g4
@@ -193,7 +193,7 @@ entry:
; SPARC64: [[LABEL1:\.L.*]]:
; SPARC64: or %o5, %o0, %g2
; SPARC64: or %o5, %o4, %g3
-; SPARC64: casa [%o2] #ASI_P, %g3, %g2
+; SPARC64: cas [%o2], %g3, %g2
; SPARC64: mov %g0, %g4
; SPARC64: cmp %g2, %g3
; SPARC64: move %icc, 1, %g4
@@ -216,10 +216,10 @@ entry:
; SPARC-LABEL: test_cmpxchg_i32
; SPARC: mov 123, [[R:%[gilo][0-7]]]
-; SPARC: casa [%o1] #ASI_P, %o0, [[R]]
+; SPARC: cas [%o1], %o0, [[R]]
; SPARC64-LABEL: test_cmpxchg_i32
; SPARC64: mov 123, [[R:%[gilo][0-7]]]
-; SPARC64: casa [%o1] #ASI_P, %o0, [[R]]
+; SPARC64: cas [%o1], %o0, [[R]]
define i32 @test_cmpxchg_i32(i32 %a, i32* %ptr) {
entry:
%pair = cmpxchg i32* %ptr, i32 %a, i32 123 monotonic monotonic
@@ -267,13 +267,13 @@ entry:
; SPARC: membar
; SPARC: .L{{.*}}:
; SPARC: sub
-; SPARC: casa [{{%[gilo][0-7]}}] #ASI_P
+; SPARC: cas [{{%[gilo][0-7]}}]
; SPARC: membar
; SPARC64-LABEL: test_load_sub_i8
; SPARC64: membar
; SPARC64: .L{{.*}}:
; SPARC64: sub
-; SPARC64: casa [{{%[gilo][0-7]}}] #ASI_P
+; SPARC64: cas [{{%[gilo][0-7]}}]
; SPARC64: membar
define zeroext i8 @test_load_sub_i8(i8* %p, i8 zeroext %v) {
entry:
@@ -285,13 +285,13 @@ entry:
; SPARC: membar
; SPARC: .L{{.*}}:
; SPARC: sub
-; SPARC: casa [{{%[gilo][0-7]}}] #ASI_P
+; SPARC: cas [{{%[gilo][0-7]}}]
; SPARC: membar
; SPARC64-LABEL: test_load_sub_i16
; SPARC64: membar
; SPARC64: .L{{.*}}:
; SPARC64: sub
-; SPARC64: casa [{{%[gilo][0-7]}}] #ASI_P
+; SPARC64: cas [{{%[gilo][0-7]}}]
; SPARC64: membar
define zeroext i16 @test_load_sub_i16(i16* %p, i16 zeroext %v) {
entry:
@@ -303,13 +303,13 @@ entry:
; SPARC: membar
; SPARC: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
; SPARC: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
-; SPARC: casa [%o0] #ASI_P, [[V]], [[V2]]
+; SPARC: cas [%o0], [[V]], [[V2]]
; SPARC: membar
; SPARC64-LABEL: test_load_add_i32
; SPARC64: membar
; SPARC64: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
; SPARC64: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
-; SPARC64: casa [%o0] #ASI_P, [[V]], [[V2]]
+; SPARC64: cas [%o0], [[V]], [[V2]]
; SPARC64: membar
define zeroext i32 @test_load_add_i32(i32* %p, i32 zeroext %v) {
entry:
@@ -320,12 +320,12 @@ entry:
; SPARC-LABEL: test_load_xor_32
; SPARC: membar
; SPARC: xor
-; SPARC: casa [%o0] #ASI_P
+; SPARC: cas [%o0]
; SPARC: membar
; SPARC64-LABEL: test_load_xor_32
; SPARC64: membar
; SPARC64: xor
-; SPARC64: casa [%o0] #ASI_P
+; SPARC64: cas [%o0]
; SPARC64: membar
define zeroext i32 @test_load_xor_32(i32* %p, i32 zeroext %v) {
entry:
@@ -337,13 +337,13 @@ entry:
; SPARC: membar
; SPARC: and
; SPARC-NOT: xor
-; SPARC: casa [%o0] #ASI_P
+; SPARC: cas [%o0]
; SPARC: membar
; SPARC64-LABEL: test_load_and_32
; SPARC64: membar
; SPARC64: and
; SPARC64-NOT: xor
-; SPARC64: casa [%o0] #ASI_P
+; SPARC64: cas [%o0]
; SPARC64: membar
define zeroext i32 @test_load_and_32(i32* %p, i32 zeroext %v) {
entry:
@@ -355,13 +355,13 @@ entry:
; SPARC: membar
; SPARC: and
; SPARC: xor
-; SPARC: casa [%o0] #ASI_P
+; SPARC: cas [%o0]
; SPARC: membar
; SPARC64-LABEL: test_load_nand_32
; SPARC64: membar
; SPARC64: and
; SPARC64: xor
-; SPARC64: casa [%o0] #ASI_P
+; SPARC64: cas [%o0]
; SPARC64: membar
define zeroext i32 @test_load_nand_32(i32* %p, i32 zeroext %v) {
entry:
@@ -373,13 +373,13 @@ entry:
; SPARC: membar
; SPARC: cmp
; SPARC: movleu %icc
-; SPARC: casa [%o0] #ASI_P
+; SPARC: cas [%o0]
; SPARC: membar
; SPARC64-LABEL: test_load_umin_32
; SPARC64: membar
; SPARC64: cmp
; SPARC64: movleu %icc
-; SPARC64: casa [%o0] #ASI_P
+; SPARC64: cas [%o0]
; SPARC64: membar
define zeroext i32 @test_load_umin_32(i32* %p, i32 zeroext %v) {
entry:
diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-atomics.txt b/llvm/test/MC/Disassembler/Sparc/sparc-atomics.txt
index a51a1a9470f5c5c..289eed0e83a1d1f 100644
--- a/llvm/test/MC/Disassembler/Sparc/sparc-atomics.txt
+++ b/llvm/test/MC/Disassembler/Sparc/sparc-atomics.txt
@@ -1,9 +1,9 @@
# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux | FileCheck %s
-# CHECK: casa [%i0] #ASI_P, %l6, %o2
+# CHECK: cas [%i0], %l6, %o2
0xd5,0xe6,0x10,0x16
-# CHECK: casa [%i0] #ASI_P_L, %l6, %o2
+# CHECK: casl [%i0], %l6, %o2
0xd5,0xe6,0x11,0x16
# CHECK: casa [%i0] 255, %l6, %o2
@@ -12,10 +12,10 @@
# CHECK: casa [%i0] %asi, %l6, %o2
0xd5,0xe6,0x20,0x16
-# CHECK: casxa [%i0] #ASI_P, %l6, %o2
+# CHECK: casx [%i0], %l6, %o2
0xd5,0xf6,0x10,0x16
-# CHECK: casxa [%i0] #ASI_P_L, %l6, %o2
+# CHECK: casxl [%i0], %l6, %o2
0xd5,0xf6,0x11,0x16
# CHECK: casxa [%i0] 255, %l6, %o2
diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-v9-asi.txt b/llvm/test/MC/Disassembler/Sparc/sparc-v9-asi.txt
index 8cf30ecdd2bb680..9286814552cf5f6 100644
--- a/llvm/test/MC/Disassembler/Sparc/sparc-v9-asi.txt
+++ b/llvm/test/MC/Disassembler/Sparc/sparc-v9-asi.txt
@@ -14,7 +14,8 @@
0xd5 0xf6 0x03 0x16
# V9: casxa [%i0] #ASI_AIUS_L, %l6, %o2
0xd5 0xf6 0x03 0x36
-# V9: casxa [%i0] #ASI_P, %l6, %o2
+## casx == casxa #ASI_P
+# V9: casx [%i0], %l6, %o2
0xd5 0xf6 0x10 0x16
# V9: casxa [%i0] #ASI_S, %l6, %o2
0xd5 0xf6 0x10 0x36
@@ -22,7 +23,8 @@
0xd5 0xf6 0x10 0x56
# V9: casxa [%i0] #ASI_SNF, %l6, %o2
0xd5 0xf6 0x10 0x76
-# V9: casxa [%i0] #ASI_P_L, %l6, %o2
+## casxl == casxa #ASI_L
+# V9: casxl [%i0], %l6, %o2
0xd5 0xf6 0x11 0x16
# V9: casxa [%i0] #ASI_S_L, %l6, %o2
0xd5 0xf6 0x11 0x36
diff --git a/llvm/test/MC/Sparc/sparc-cas-instructions.s b/llvm/test/MC/Sparc/sparc-cas-instructions.s
index 763eb29e1bd1b8f..4e30fed378beb80 100644
--- a/llvm/test/MC/Sparc/sparc-cas-instructions.s
+++ b/llvm/test/MC/Sparc/sparc-cas-instructions.s
@@ -3,22 +3,22 @@
! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
! V8: error: instruction requires a CPU feature not currently enabled
-! V9: casa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
+! V9: cas [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
! LEON: error: instruction requires a CPU feature not currently enabled
cas [%i0], %l6, %o2
! V8: error: instruction requires a CPU feature not currently enabled
-! V9: casa [%i0] #ASI_P_L, %l6, %o2 ! encoding: [0xd5,0xe6,0x11,0x16]
+! V9: casl [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x11,0x16]
! LEON: error: instruction requires a CPU feature not currently enabled
casl [%i0], %l6, %o2
! V8: error: instruction requires a CPU feature not currently enabled
-! V9: casxa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
+! V9: casx [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
! LEON: error: instruction requires a CPU feature not currently enabled
casx [%i0], %l6, %o2
! V8: error: instruction requires a CPU feature not currently enabled
-! V9: casxa [%i0] #ASI_P_L, %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x16]
+! V9: casxl [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x16]
! LEON: error: instruction requires a CPU feature not currently enabled
casxl [%i0], %l6, %o2
@@ -28,12 +28,12 @@ casxl [%i0], %l6, %o2
casxa [%i0] %asi, %l6, %o2
! V8: error: instruction requires a CPU feature not currently enabled
-! V9: casxa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
+! V9: casx [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
! LEON: error: instruction requires a CPU feature not currently enabled
casxa [%i0] 0x80, %l6, %o2
! V8: error: instruction requires a CPU feature not currently enabled
-! V9: casxa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
+! V9: casx [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
! LEON: error: instruction requires a CPU feature not currently enabled
casxa [%i0] (0x40+0x40), %l6, %o2
@@ -43,11 +43,11 @@ casxa [%i0] (0x40+0x40), %l6, %o2
casa [%i0] %asi, %l6, %o2
! V8: error: instruction requires a CPU feature not currently enabled
-! V9: casa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
+! V9: cas [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
! LEON: casa [%i0] 128, %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
casa [%i0] 0x80, %l6, %o2
! V8: error: instruction requires a CPU feature not currently enabled
-! V9: casa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
+! V9: cas [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
! LEON: casa [%i0] 128, %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16]
casa [%i0] (0x40+0x40), %l6, %o2
diff --git a/llvm/test/MC/Sparc/sparcv9-asi-names.s b/llvm/test/MC/Sparc/sparcv9-asi-names.s
index 042d62380b03ad0..a27d1a0c30d8d61 100644
--- a/llvm/test/MC/Sparc/sparcv9-asi-names.s
+++ b/llvm/test/MC/Sparc/sparcv9-asi-names.s
@@ -13,7 +13,7 @@ casxa [%i0] #ASI_AIUS, %l6, %o2
casxa [%i0] #ASI_AIUP_L, %l6, %o2
! V9: casxa [%i0] #ASI_AIUS_L, %l6, %o2 ! encoding: [0xd5,0xf6,0x03,0x36]
casxa [%i0] #ASI_AIUS_L, %l6, %o2
-! V9: casxa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
+! V9: casx [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
casxa [%i0] #ASI_P, %l6, %o2
! V9: casxa [%i0] #ASI_S, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x36]
casxa [%i0] #ASI_S, %l6, %o2
@@ -21,7 +21,7 @@ casxa [%i0] #ASI_S, %l6, %o2
casxa [%i0] #ASI_PNF, %l6, %o2
! V9: casxa [%i0] #ASI_SNF, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x76]
casxa [%i0] #ASI_SNF, %l6, %o2
-! V9: casxa [%i0] #ASI_P_L, %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x16]
+! V9: casxl [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x16]
casxa [%i0] #ASI_P_L, %l6, %o2
! V9: casxa [%i0] #ASI_S_L, %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x36]
casxa [%i0] #ASI_S_L, %l6, %o2
@@ -43,7 +43,7 @@ casxa [%i0] #ASI_AS_IF_USER_SECONDARY, %l6, %o2
casxa [%i0] #ASI_AS_IF_USER_PRIMARY_LITTLE, %l6, %o2
! V9: casxa [%i0] #ASI_AIUS_L, %l6, %o2 ! encoding: [0xd5,0xf6,0x03,0x36]
casxa [%i0] #ASI_AS_IF_USER_SECONDARY_LITTLE, %l6, %o2
-! V9: casxa [%i0] #ASI_P, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
+! V9: casx [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16]
casxa [%i0] #ASI_PRIMARY, %l6, %o2
! V9: casxa [%i0] #ASI_S, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x36]
casxa [%i0] #ASI_SECONDARY, %l6, %o2
@@ -51,7 +51,7 @@ casxa [%i0] #ASI_SECONDARY, %l6, %o2
casxa [%i0] #ASI_PRIMARY_NOFAULT, %l6, %o2
! V9: casxa [%i0] #ASI_SNF, %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x76]
casxa [%i0] #ASI_SECONDARY_NOFAULT, %l6, %o2
-! V9: casxa [%i0] #ASI_P_L, %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x16]
+! V9: casxl [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x16]
casxa [%i0] #ASI_PRIMARY_LITTLE, %l6, %o2
! V9: casxa [%i0] #ASI_S_L, %l6, %o2 ! encoding: [0xd5,0xf6,0x11,0x36]
casxa [%i0] #ASI_SECONDARY_LITTLE, %l6, %o2
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